Display control method and circuit, electronic equipment and computer readable storage medium

Abstract

The invention provides a display control method and circuit, electronic equipment and a computer readable medium, and relates to the technical field of digital image processing. The method comprises the following steps: storing to-be-converted data into a first storage unit, and converting the to-be-converted data into first grouped data and second grouped data in the first storage unit; the storage signal controls the grouped data to be stored in the second storage unit; the transmission signal controls packet data to be transmitted to the primary circuit; the storage signal comprises a first storage sub-signal and a second storage sub-signal; the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal; when the first storage sub-signal ends, the second storage sub-signal is triggered by delaying a preset time period; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent. By optimizing the time sequence configuration of the control signal, the data flipping and waiting time is reduced, the invalid working time can be effectively reduced, and the chip power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of digital image processing, and in particular to a display control method, circuit, electronic device and computer-readable storage medium. Background Art

[0002] With the continuous development of display technology, AMOLED displays have been widely used in electronic devices such as smartphones and tablets due to their advantages such as high contrast, wide color gamut and low power consumption. In order to improve the resolution of AMOLED displays, PenTile technology is usually used. PenTile technology achieves higher pixel density through a special sub-pixel arrangement, thereby improving the display effect.

[0003] In an AMOLED display, the driver chip needs to process a large amount of image data. Usually, the image data sent by the host is real image data, and the driver chip processes the real image data into sub-pixel data arranged in Pentiles through subpixel rendering (SPR). Although this processing method improves the display resolution, it also increases the complexity of data processing.

[0004] However, this design has certain problems in the data transmission process. The driver chip needs to transmit sub-pixel 1 data or sub-pixel 2 data to the grayscale voltage conversion circuit in time periods within a line of display time. The conventional practice is to select the sub-pixel data to be transmitted in the current time period through a control signal. When the control signal is high, the sub-pixel 1 data is transmitted, and when it is low, the sub-pixel 2 data is transmitted. When the sub-pixel 1 data and the sub-pixel 2 data are switched, there is invalid data flipping for a period of time, causing the grayscale voltage conversion circuit to work invalidly for a period of time, which is manifested as an increase in the power consumption of the driver chip for a period of time. Summary of the invention

[0005] In view of this, the purpose of the embodiment of the present application is to provide a display control method, which can effectively reduce the invalid working time and the chip power consumption by optimizing the timing configuration of the control signal, reducing the data flipping and waiting time, so as to improve the problem of much invalid working time of the circuit and high chip power consumption in the prior art.

[0006] The display control method includes: storing the data to be converted into a first storage unit, and converting the data to be converted into first grouped data and second grouped data in the first storage unit; controlling the first grouped data and the second grouped data to be stored in the second storage unit through a storage signal; wherein the storage signal includes: a first storage sub-signal and a second storage sub-signal; controlling the first grouped data and the second grouped data to be transmitted to a primary circuit through a transmission signal; wherein the transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; wherein the second storage sub-signal is triggered by delaying a preset period of time when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; and the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0007] In the above implementation process, the preliminary storage and grouping operations are first completed in the first storage unit. The data to be converted is stored in the first storage unit. When the first storage unit completely receives the data to be converted in the first storage unit and converts it into the first grouped data and the second grouped data, it is used to control the first grouped data and the second grouped data to be stored in the second storage unit respectively, and then the first grouped data and the second grouped data are transmitted to the first-level circuit through the transmission signal, and the transmission signal includes the first transmission sub-signal and the second transmission sub-signal. And the triggering of the second storage sub-signal needs to be delayed for a preset period of time after the end of the first storage sub-signal, the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent, and the triggering time points of the second storage sub-signal and the second transmission sub-signal are also consistent, thereby realizing the orderly storage and transmission of data, improving the stability and reliability of the overall display control method, and then the timing of each signal can be allocated, so that the invalid working time of the circuit is reduced, and the power consumption of the chip is reduced.

[0008] Optionally, the display control method further includes: the transmission signal controls the first grouped data and the second grouped data to be transmitted to the secondary circuit after passing through the primary circuit; and the secondary circuit converts the first grouped data and the second grouped data and outputs a display voltage.

[0009] In the above implementation process, the first group data and the second group data processed by the primary circuit are transmitted to the secondary circuit. In the secondary circuit, the two parts of data are further converted and processed, and finally a voltage signal for display is output. The complete conversion process of data from the original state to a voltage signal that can be directly used for display is realized, which improves the flexibility and adaptability of the display control method, can better meet the diverse needs of data processing and display effects in different display scenarios, and also enhances the performance and stability of the entire display system.

[0010] Optionally, the first grouped data includes first category data and second category data, and the second grouped data includes third category data and fourth category data; controlling the first grouped data and the second grouped data to be transmitted to the primary circuit through a transmission signal, further comprising: when the transmission signal is at a high level, transmitting the first category data and / or the third category data to the secondary circuit; when the transmission signal is at a low level, transmitting the second category data and / or the fourth category data to the secondary circuit.

[0011] In the above implementation process, by subdividing the first grouped data into the first category data and the second category data, and subdividing the second grouped data into the third category data and the fourth category data, the flexibility and refinement of data processing are further enhanced. When the transmission signal is at a high level, the first category data and / or the third category data are transmitted to the secondary circuit, and when the transmission signal is at a low level, the second category data and / or the fourth category data are transmitted to the secondary circuit. By utilizing the high and low level characteristics of the transmission signal, time-sharing transmission of different categories of data is realized, conflicts and interferences in the data transmission process are reduced, and the stability and reliability of data transmission are improved. At the same time, the processing efficiency of the secondary circuit for data is optimized. By adjusting the timing of each signal, the invalid working time of the circuit is reduced, and the power consumption of the chip is reduced. The performance of the entire display control method is further improved, and the high requirements for data processing and display effects in complex display scenarios are better met.

[0012] Optionally, controlling the first packet data and the second packet data to be stored in a second storage unit by means of a storage signal comprises: controlling the first packet data to be stored from the first storage unit to the second storage unit by means of the first storage sub-signal; and controlling the second packet data to be stored from the first storage unit to the second storage unit by means of the second storage sub-signal.

[0013] In the above implementation process, by subdividing the storage signal into the first storage sub-signal and the second storage sub-signal, the first grouped data and the second grouped data are controlled separately. Specifically, the first storage sub-signal is used to control the storage operation of the first grouped data from the first storage unit to the second storage unit, so that the first grouped data is accurately stored; at the same time, the second storage sub-signal is used to control the storage process of the second grouped data from the first storage unit to the second storage unit, so as to ensure the reliable storage of the second grouped data. The method of controlling the storage of different grouped data by different storage sub-signals not only improves the flexibility and controllability of data storage, but also reduces the conflict and confusion of data during the storage process. By adjusting the timing of each signal, the invalid working time of the circuit is reduced, and the power consumption of the chip is reduced.

[0014] Optionally, controlling the transmission of the first packet data and the second packet data to the primary circuit through the transmission signal includes: controlling the first packet data to be transmitted from the second storage unit to the primary circuit through the first transmission sub-signal; and controlling the second packet data to be transmitted from the second storage unit to the primary circuit through the second transmission sub-signal.

[0015] In the above implementation process, by subdividing the transmission signal into a first transmission sub-signal and a second transmission sub-signal, the first packet data and the second packet data are controlled and transmitted separately. Specifically, the first transmission sub-signal is used to accurately control the transmission process of the first packet data from the second storage unit to the primary circuit, so that the first packet data is accurately transmitted; at the same time, the second transmission sub-signal is used to control the transmission operation of the second packet data from the second storage unit to the primary circuit, so as to ensure the reliable transmission of the second packet data. The method of controlling the transmission of different packet data by different transmission sub-signals not only improves the flexibility and controllability of data transmission, but also effectively reduces the conflict and interference of data during the transmission process. By adjusting the timing of each signal, the invalid working time of the circuit is reduced, and the power consumption of the chip is reduced.

[0016] Optionally, storing the data to be converted into a first storage unit, and converting the data to be converted into first grouped data and second grouped data in the first storage unit, includes: obtaining the data to be converted by preprocessing the original data; temporarily storing the data to be converted in the first storage unit; and when the first storage unit has received all the data to be converted, dividing the data to be converted into the first grouped data and the second grouped data through the first storage unit.

[0017] In the above implementation process, the original data is first preprocessed so that the data to be converted meets the requirements of subsequent processing. The preprocessed data to be converted is temporarily stored in the first storage unit. When the first storage unit completes the reception of all the data to be converted, the data to be converted is divided into first group data and second group data using the storage and processing capabilities of the first storage unit. The grouping helps to process and transmit different types of data separately, thereby improving the efficiency and accuracy of the entire display control method, so that the data maintains its orderliness during storage and transmission.

[0018] An embodiment of the present application also provides a display control circuit, which includes: a first storage unit, a second storage unit and a primary circuit; the first storage unit is configured to store data to be converted, and receive a storage signal to perform a corresponding operation; wherein the storage signal includes: a first storage sub-signal and a second storage sub-signal; wherein the first storage unit receives the first storage sub-signal to divide the data to be converted into a first group data and a second group data; the second storage unit is configured to transmit the first group data and the second group data to the primary circuit after receiving a transmission signal; wherein the transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; wherein the second storage sub-signal is triggered with a delay of a preset time period when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0019] In the above implementation process, the display control circuit realizes effective storage, grouping and transmission of data through the coordinated work of the first storage unit, the second storage unit and the primary circuit. After receiving the first storage sub-signal, the first storage unit divides the data to be converted into the first group data and the second group data. Subsequently, after receiving the transmission signal, the second storage unit sequentially transmits the two parts of the group data to the primary circuit. The first transmission sub-signal and the second transmission sub-signal in the transmission signal respectively control the transmission process of the first group data and the second group data, so that the data transmission maintains orderliness and accuracy. In addition, the second storage sub-signal is triggered by a preset time delay after the first storage sub-signal ends, which further optimizes the timing relationship between data storage and transmission, reduces conflicts and confusion in the data processing process, and reduces the invalid working time of the circuit by adjusting the timing of each signal, thereby reducing the power consumption of the chip. Not only the flexibility and controllability of data storage and transmission are improved, but also the stability and reliability of the entire display control circuit are enhanced, providing strong support for realizing efficient display control functions.

[0020] Optionally, the display control circuit further includes: a secondary circuit; the secondary circuit is configured to receive and convert the first group data and the second group data and then output a display voltage.

[0021] In the above implementation process, after the primary circuit completes the preliminary processing of the first group data and the second group data, the secondary circuit receives the processed data, performs further conversion processing on it, and finally outputs a voltage signal for display. The complete conversion process of data from the original state to a voltage signal that can be directly used for display is realized, and the timing relationship between data storage and transmission is optimized in conjunction with the previous circuit module for data group processing and transmission, reducing conflicts and confusion in the data processing process. By adjusting the timing of each signal, the circuit's invalid working time is reduced, and the chip power consumption is reduced.

[0022] An embodiment of the present application further provides an electronic device, which includes a memory and a processor, wherein the memory stores program instructions, and when the processor reads and runs the program instructions, the steps in any of the above implementation methods are executed.

[0023] In the above implementation process, the electronic device realizes the effective execution of the display control method through its internal memory and processor. The program instructions stored in the memory include the various steps of the above display control method. When the processor reads and runs these program instructions, the electronic device can complete the data storage, grouping, transmission and final display control operation according to the predetermined process.

[0024] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer program instructions, and when the computer program instructions are read and executed by a processor, the steps in any of the above implementation methods are executed.

[0025] In the above implementation process, the computer-readable storage medium is a key storage component that stores computer program instructions related to the display control method. When these program instructions are read and executed by the processor, the steps in any of the above implementations can be executed, thereby effectively deploying and running the display control method. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A simple schematic diagram of a display control method provided in an embodiment of the present application;

[0028] Figure 2 A detailed schematic diagram of a display control method provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of data transmission to a secondary circuit provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a display control circuit provided in an embodiment of the present application;

[0031] Figure 5 A block diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of data transmission in an embodiment provided in the present application;

[0033] Figure 7 A timing diagram of data transmission in an embodiment provided in the present application;

[0034] Figure 8 A timing diagram of a conventional method provided in an embodiment of the present application.

[0035] Icon: 001-preprocessing module; 010-first storage unit; 020-second storage unit; 030-primary circuit; 040-secondary circuit; 100-electronic device; 111-memory; 112-storage controller; 113-processor; 114-peripheral interface; 115-input and output unit; 116-display unit. DETAILED DESCRIPTION

[0036] The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.

[0037] The embodiment of the present application provides a display control method, which is applied to the data display control of a driver chip. By generating signals of the same type but different categories, the data to be displayed is transmitted to the output circuit (secondary circuit 040) according to the configured timing, thereby reducing invalid flipping during data switching, thereby reducing the circuit working power consumption.

[0038] Optionally, see Figure 1 , Figure 1 A simple schematic diagram of a display control method provided in an embodiment of the present application.

[0039] The display control method includes: storing the data to be converted into the first storage unit 010, and converting the data to be converted into the first group data and the second group data in the first storage unit 010; controlling the first group data and the second group data to be stored in the second storage unit 020 through a storage signal; wherein the storage signal includes: a first storage sub-signal and a second storage sub-signal; controlling the first group data and the second group data to be transmitted to the primary circuit 030 through a transmission signal; wherein the transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; wherein the second storage sub-signal is triggered by delaying a preset period of time when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0040] In the above implementation process, the display control method realizes the preliminary processing and grouping of data by storing the data to be converted into the first storage unit 010, and converting the data to be converted into the first group data and the second group data in the first storage unit 010. Subsequently, the first group data and the second group data are stored in the second storage unit 020 by controlling the storage signal, wherein the storage signal includes the first storage sub-signal and the second storage sub-signal. Further, the first group data and the second group data are transmitted to the primary circuit 030 by controlling the transmission signal, wherein the transmission signal includes the first transmission sub-signal and the second transmission sub-signal. The triggering time point of the transmission signal is consistent with the triggering time point of the storage signal, so as to maintain the orderliness and accuracy of the data transmission. In addition, the second storage sub-signal is triggered by delaying the preset period of time when the first storage sub-signal ends, which further optimizes the timing relationship between data storage and transmission, avoids conflicts and confusions in the data processing process, reduces the invalid working time of the circuit, and reduces the power consumption of the chip.

[0041] Optionally, combine Figure 1 , see Figure 2 , Figure 2 A detailed schematic diagram of a display control method provided in an embodiment of the present application.

[0042] The original data is preprocessed to obtain data to be converted; the data to be converted is temporarily stored in the first storage unit 010; when the first storage unit 010 has received all the data to be converted, the data to be converted is divided into first grouped data and second grouped data through the first storage unit 010, wherein the first grouped data includes first category data and second category data, and the second grouped data includes third category data and fourth category data.

[0043] In the above implementation process, the original data is preprocessed to obtain the data to be converted, and the preprocessing may include operations such as data cleaning and format conversion, so that the data meets the requirements of subsequent processing. Then, the data to be converted is temporarily stored in the first storage unit 010, waiting for further processing. When the first storage unit 010 receives all the data to be converted, the data to be converted is divided into a first group data and a second group data by the first storage unit 010. The first group data includes the first category data and the second category data, and the second group data includes the third category data and the fourth category data.

[0044] Optionally, the grouped data here can also be expanded to more groups or categories. The finer the grouping, the better the data transmission effect, but the more time it takes and the more complex the circuit. Selecting the appropriate grouping can ensure output efficiency while reducing chip power consumption. Similarly, each category has its own control signal, and the timing between the various control signals is configurable.

[0045] Please combine Figure 2 Based on Figure 3 , Figure 3 A schematic diagram of data transmission to the secondary circuit 040 provided in an embodiment of the present application.

[0046] The first group data and the second group data are controlled to be stored in the second storage unit 020 through the storage signal. The first group data and the second group data are controlled to be transmitted to the secondary circuit 040 after passing through the primary circuit 030 through the transmission signal. When the transmission signal is at a high level, the first type of data and / or the third type of data are transmitted to the secondary circuit 040; when the transmission signal is at a low level, the second type of data and / or the fourth type of data are transmitted to the secondary circuit 040. The secondary circuit 040 converts the first group data and the second group data and outputs a display voltage.

[0047] In the above implementation process, the first grouped data and the second grouped data are stored in the second storage unit 020 through the storage signal. The storage signal includes a first storage sub-signal and a second storage sub-signal, which are respectively used to control the storage operation of the first grouped data and the second grouped data. Then, the first grouped data and the second grouped data are transmitted to the secondary circuit 040 after passing through the primary circuit 030 through the transmission signal. The transmission signal includes a first transmission sub-signal and a second transmission sub-signal. When the transmission signal is at a high level, the first type of data and / or the third type of data are transmitted to the secondary circuit 040; when the transmission signal is at a low level, the second type of data and / or the fourth type of data are transmitted to the secondary circuit 040. After the secondary circuit 040 converts the first grouped data and the second grouped data, it outputs a voltage signal for display. The use of grouping and timing configuration not only improves the flexibility and efficiency of data processing, but also effectively reduces the time of invalid data flipping, reduces the power consumption of the driver chip, and improves the performance and stability of the entire display control method.

[0048] In one embodiment of the present application, the method is applied to the field of digital image processing. The original data is processed into sub-pixel data arranged in Pentile by sub-pixel rendering technology (SPR for short). If the original data has a resolution of 1080, that is, 1080 pixels are arranged in 3 columns, 2160 sub-pixel data are obtained after SPR processing, that is, each pixel has two sub-pixels. When all pixel data are stored in the first storage unit 010, the pixel data are divided into a first grouping data and a second grouping data, and the first grouping data includes a first category data and a second category data, and the second grouping data includes a third category data and a fourth category data. The grouped pixel data is controlled by a storage signal to be stored in a second storage unit 020, wherein the storage signal includes a first storage sub-signal and a second storage sub-signal, which are respectively used to control the storage operation of the first grouping data and the second grouping data. The transmission signal is used to control the transmission of the first group data and the second group data to the primary circuit 030. The transmission signal includes a first transmission sub-signal and a second transmission sub-signal. When the transmission signal is at a high level, the first type of pixel data and / or the third type of pixel data are transmitted to the secondary circuit 040; when the transmission signal is at a low level, the second type of pixel data and / or the fourth type of pixel data are transmitted to the secondary circuit 040. It should be further explained that when the storage signal is at a high level, the corresponding transmission signal changes from a low level to a high level. When each transmission signal changes from a high level to a low level, it also needs to change in sequence. The secondary circuit 040 converts the first group data and the second group data and outputs a display voltage. By means of grouping and timing configuration, not only the flexibility and efficiency of data processing are improved, but also the time of invalid data flipping is effectively reduced, the power consumption of the driver chip is reduced, and the performance and stability of the entire display control method are improved.

[0049] See also Figure 4 , Figure 4 A schematic diagram of a display control circuit provided in an embodiment of the present application.

[0050] The display control circuit includes: a preprocessing module 001, a first storage unit 010, a second storage unit 020, a primary circuit 030 and a secondary circuit 040; the first storage unit 010 is configured to store data to be converted, and receive a storage signal to perform a corresponding operation; wherein the storage signal includes: a first storage sub-signal and a second storage sub-signal; wherein the first storage unit 010 receives the first storage sub-signal to divide the data to be converted into a first group of data and a second group of data; the second storage unit 020 is configured to receive the transmission signal and transmit the first group of data and the second group of data to the primary circuit 030; the secondary circuit 040 is configured to receive and convert the first group of data and the second group of data and then output a display voltage. wherein the transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; wherein the second storage sub-signal is triggered by delaying a preset period of time when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0051] In one embodiment of the present application, the preprocessing module 001 may be a data format conversion module, a data cleaning module, a data compression module, a data enhancement module, a color correction module, or a data sorting module. The first storage unit 010 and the second storage unit 020 may be a data buffer or a data buffer; used to store original pixel data or preprocessed data to be converted, or first packet data and second packet data. The primary circuit 030 may be a MUX2:1 circuit, a data selector, or a multiplexer; used to select and transmit packet data to the secondary circuit 040. The secondary circuit 040 may be a grayscale conversion circuit, a display drive circuit, or a display signal conversion circuit; used to convert packet data into a display voltage.

[0052] In one embodiment of the present application, the raw pixel data usually comes from a host or other external device, and its input speed and format may not be completely suitable for direct subsequent data processing. The preprocessing module 001 converts the raw pixel data from one format to another format to meet the requirements of subsequent processing. For example, the data in RGB format is converted into data in Pentile format. The first storage unit 010, as the first storage unit 010, plays a buffering role, can receive a single data sent by the input end, and temporarily store the raw pixel data after receiving it, to ensure that the data is complete and continuous before processing. The second storage unit 020 is used to store the first packet data and the second packet data updated by the storage signal from the first storage unit 010, to ensure that the data is complete and orderly in the form of packets before being transmitted to the first circuit 030. As the MUX2:1 circuit of the first circuit 030, it is responsible for selecting and transmitting sub-pixel data to the second circuit 040. Through the control of the transmission signal, the MUX2:1 circuit can select the first type of pixel data and / or the third type of pixel data or the second type of pixel data and / or the fourth type of pixel data as needed to ensure the flexibility and controllability of data transmission. At the same time, by optimizing the timing configuration of the control signal, the invalid flipping time in the data transmission process is reduced, and the efficiency of data transmission is improved. The secondary circuit 040 converts the received sub-pixel data into a display voltage and outputs it to the AMOLED display screen. Its main function is to convert the sub-pixel data in digital form into a display voltage in analog form to ensure that the display device can correctly display the image. In addition, the grayscale conversion circuit can also reduce the invalid working time and the power consumption of the driver chip by optimizing the data transmission and conversion process, thereby achieving high-quality display effects and excellent performance.

[0053] Figure 5 The block diagram of an electronic device provided in an embodiment of the present application. The electronic device 100 may include a memory 111, a storage controller 112, a processor 113, a peripheral interface 114, an input and output unit 115, and a display unit 116. A person skilled in the art may understand that Figure 5 The structure shown is only for illustration and does not limit the structure of the electronic device 100. For example, the electronic device 100 may further include Figure 5 More or fewer components as shown, or with Figure 5 Different configurations are shown.

[0054] The memory 111, storage controller 112, processor 113, peripheral interface 114, input / output unit 115 and display unit 116 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The processor 113 is used to execute the executable module stored in the memory.

[0055] The memory 111 may be, but not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory 111 is used to store programs, and the processor 113 executes the program after receiving the execution instruction. The method executed by the electronic device 100 defined by the process disclosed in any embodiment of the present application can be applied to the processor 113, or implemented by the processor 113.

[0056] The processor 113 may be an integrated circuit chip with signal processing capability. The processor 113 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor.

[0057] The peripheral interface 114 couples various input / output devices to the processor 113 and the memory 111. In some embodiments, the peripheral interface 114, the processor 113 and the memory controller 112 can be implemented in a single chip. In other embodiments, they can be implemented by separate chips.

[0058] The input and output unit 115 is used to provide input data to the user. The input and output unit 115 can be, but is not limited to, a mouse and a keyboard.

[0059] The display unit 116 provides an interactive interface (e.g., a user operation interface) between the electronic device 100 and the user or is used to display image data for the user's reference. In this embodiment, the display unit may be a liquid crystal display or a touch display. If it is a touch display, it may be a capacitive touch screen or a resistive touch screen that supports single-point and multi-point touch operations. Supporting single-point and multi-point touch operations means that the touch display can sense touch operations generated simultaneously from one or more positions on the touch display, and the sensed touch operations are handed over to the processor for calculation and processing.

[0060] See also Figure 6 , Figure 6 A schematic diagram of data transmission in an embodiment provided for an embodiment of the present application.

[0061] In one embodiment of the present application, taking 1080 source PADs of a driver chip as an example, 1080 grayscale conversion paths, i.e., 1080 data of S1-S1080 are divided into two groups, high and low, of which S1-S540 is a low group and S541-S1080 is a high group. Each group contains 4 types of data, odd 1, even 1, odd 2, and even 2. In this way, 1080 grayscale conversion paths, i.e., 2160 data are divided into 8 categories, specifically low group odd 1, low group even 1, low group odd 2, low group even 2, high group odd 1, high group even 1, high group odd 2, and high group even 2. When the grouped data is updated from LA1 (the first storage unit) to LA2 (the second storage unit), the data update is controlled by the UPD signal (storage signal). Since the data is divided into 8 categories, each type of data has its own control signal, namely UPD_O1_L, UPD_E1_L, UPD_O2_L, UPD_E2_L, UPD_O1_H, UPD_E1_H, UPD_O2_H, UPD_E2_H. When the sub-pixel data is transmitted from LA2 to the grayscale conversion circuit through the MUX2:1 circuit, the sub-pixel 1 data or the sub-pixel 2 data is controlled by the SEL signal (transmission signal). Among them, the high level selects the sub-pixel 1 data to be transmitted to the grayscale conversion circuit, and the low level selects the sub-pixel 2 data to be transmitted to the grayscale conversion circuit. Since LA2 and the grayscale conversion circuit are divided into 8 categories, each type of data has its own control signal, namely SEL_O1_L, SEL_E1_L, SEL_O2_L, SEL_E2_L, SEL_O1_H, SEL_E1_H, SEL_O2_H, SEL_E2_H. Figure 6The control signals and data transmission diagram of high group odd 1, high group even 1, high group odd 2, and high group even 2 are shown. The processing method of low group is the same. When the sub-pixel data is updated from LA1 to LA2, the control signals are UPD_O1_L, UPD_E1_L, UPD_O2_L, and UPD_E2_L. When the sub-pixel data is transmitted from LA2 to the grayscale conversion circuit through the MUX2:1 circuit, the control signals are SEL_O1_L, SEL_E1_L, SEL_O2_L, and SEL_E2_L. The timing of each similar signal is different and can be configured through registers.

[0062] See also Figure 7 and Figure 8 , Figure 7 A timing diagram of data transmission in an embodiment provided in the present application; Figure 8 A timing diagram of a conventional method provided in an embodiment of the present application.

[0063] first, Figure 7 In the figure, T0 represents the display time of a row, and T1 represents the time interval between each type of control signal, which can be configured by registers to achieve different timings. T2 represents the invalid flipping time of the sub-pixel data output by the MUX2:1 circuit to the grayscale conversion circuit before stabilization. Through 8 UPD signals, 2160 sub-pixel data can be divided into 8 different timing points and updated from LA1 to LA2. Then, through the coordination of the corresponding SEL control signal timing, the sub-pixel data output by the MUX2:1 circuit to the grayscale conversion circuit is switched from the previous row of sub-pixel 2 to the current row of sub-pixel 1. The invalid time T2 is shortened and the number of data is reduced. Similarly, within the T3 time, the number of invalid data is also reduced. The T1 time is equal to the high level time of the UPD signal multiplied by 7, plus the spacing between the UPD signals multiplied by 7. The spacing between the UPD signals is shown in the figure, which can be configured by registers to achieve different timings. It should be noted that when the UPD signal is high, the corresponding SEL signal changes from low to high. When each SEL signal changes from a high level to a low level, it also changes in sequence. T2 represents the invalid data time before the MUX2:1 circuit outputs the data of the sub-pixel 2 in the previous row to the data of the sub-pixel 1 in the current row, because the sub-pixel data is multi-bit, and the circuit delay of each bit is different. T3 represents the invalid data time before the MUX2:1 circuit outputs the data of the sub-pixel 1 in the current row and switches to the data of the sub-pixel 2 in the current row. Each of the 8 types of data has T2 and T3 time, but the time point at which the T2 and T3 time periods appear in each type is different. For example, the time point at which T2 of the low group odd number 1 appears is before T2 of the high group odd number 1.

[0064] contrast Figure 8In conventional schemes, grayscale conversion circuits are usually divided into two categories, namely low-level groups and high-level groups. Taking the resolution of the original image as 1080 as an example, when the MUX2:1 circuit outputs sub-pixel data 1 and switches to sub-pixel data 2, a total of 1080 sub-pixel data are switched within the T3 time, and the number of invalid data is 8 times that of this scheme. Similarly, when the sub-pixel data 2 of the previous row is switched to the sub-pixel data 1 of the current row, the number of invalid data is also 8 times that of this scheme within the T2 time. In addition, since the control signal UPD and the corresponding control signal SEL in this scheme have the same timing switching point, this scheme greatly reduces the T2 time, thereby reducing the invalid data flipping time.

[0065] In summary, the present application provides a display control method, circuit, electronic device and computer-readable medium, which ensures the integrity and orderliness of the data by temporarily storing the original pixel data in the first storage unit 010, preprocessing and grouping, and then storing it in the second storage unit 020. The second storage unit 020 temporarily stores the grouped data, providing a stable basis for subsequent data selection and transmission. The primary circuit 030 selects and transmits the grouped data through the transmission signal, ensuring the flexibility and controllability of data transmission. The secondary circuit 040 converts the sub-pixel data into a display voltage output, achieving a high-quality display effect. In the whole process, by optimizing the timing configuration of data storage, transmission and conversion, the invalid data flipping time is reduced, the power consumption of the driver chip is reduced, and the performance and stability of the display control method are improved.

[0066] In several embodiments provided in the present application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely schematic, for example, the block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices according to the multiple embodiments of the present application. In this regard, each box in the block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram, and the combination of the block diagrams, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0067] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0068] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0069] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

[0070] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A display control method, characterized in that: The display control method comprises: storing the data to be converted into a first storage unit, and converting the data to be converted into first group data and second group data in the first storage unit; Controlling the first group data and the second group data to be stored in a second storage unit through a storage signal; wherein the storage signal comprises: a first storage sub-signal and a second storage sub-signal; Controlling the transmission of the first packet data and the second packet data to the primary circuit through a transmission signal; wherein the transmission signal comprises: a first transmission sub-signal and a second transmission sub-signal; Among them, when the first storage sub-signal ends, the second storage sub-signal is triggered with a delay of a preset period; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; and the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

2. The display control method according to claim 1, characterized in that: The display control method further includes: The transmission signal controls the first group data and the second group data to be transmitted to the secondary circuit after passing through the primary circuit; the secondary circuit converts the first group data and the second group data and outputs a display voltage.

3. The display control method according to claim 2, characterized in that: in, The first grouped data includes first-category data and second-category data, and the second grouped data includes third-category data and fourth-category data; Controlling the transmission of the first packet data and the second packet data to a primary circuit by a transmission signal, further comprising: When the transmission signal is at a high level, transmitting the first category data and / or the third category data to the secondary circuit; When the transmission signal is at a low level, the second type of data and / or the fourth type of data are transmitted to the secondary circuit.

4. The display control method according to claim 1, characterized in that: The step of controlling the first grouped data and the second grouped data to be stored in a second storage unit by storing a signal comprises: The first storage sub-signal is used to control the first packet data to be stored from the first storage unit to the second storage unit; and the second storage sub-signal is used to control the second packet data to be stored from the first storage unit to the second storage unit.

5. The display control method according to claim 1, characterized in that: The step of controlling the first packet data and the second packet data to be transmitted to a primary circuit by transmitting a signal comprises: The first transmission sub-signal is used to control the first packet data to be transmitted from the second storage unit to the primary circuit; the second transmission sub-signal is used to control the second packet data to be transmitted from the second storage unit to the primary circuit.

6. The display control method according to claim 1, characterized in that: The step of storing the data to be converted into a first storage unit, and converting the data to be converted into first group data and second group data in the first storage unit includes: Preprocessing the original data to obtain the data to be converted; Temporarily storing the data to be converted in the first storage unit; When the first storage unit has received all the data to be converted, the data to be converted is divided into the first grouped data and the second grouped data by the first storage unit.

7. A display control circuit, characterized in that: The display control circuit comprises: a first storage unit, a second storage unit and a primary circuit; The first storage unit is configured to store the data to be converted and receive a storage signal to perform a corresponding operation; wherein the storage signal includes: a first storage sub-signal and a second storage sub-signal; Wherein, the first storage unit receives the first storage sub-signal to divide the data to be converted into first group data and second group data; The second storage unit is configured to transfer the first packet data and the second packet data to a primary circuit after receiving a transmission signal; Wherein, the transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; Among them, when the first storage sub-signal ends, the second storage sub-signal is triggered with a delay of a preset period; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; and the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

8. The display control circuit according to claim 7, characterized in that: The display control circuit further includes: a secondary circuit; The secondary circuit is configured to receive and convert the first group data and the second group data and then output a display voltage.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores program instructions, and when the processor runs the program instructions, the steps in the method according to any one of claims 1 to 6 are executed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the steps in the method according to any one of claims 1 to 6 are executed.

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