Offset cancellation

Abstract

The invention relates to offset cancellation. A memory device may determine that a channel is in a state that interrupts active termination of the channel and enable calibration of a reference voltage (e.g., by the memory device). For example, a channel for data transfer for a second device (e.g., a controller) may initially be in an actively terminated state. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting a calibration signal on the channel and detecting an offset associated with the reference voltage. The memory device may identify a signal transmitted to the memory device on the channel using the detected offset and the reference voltage.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of the invention patent with application date of October 15, 2019, application number 201980074401.2, and invention name “Offset Elimination”.

[0003] Cross-references

[0004] This patent application claims priority to PCT application No. PCT / US2019 / 056285, entitled “OFFSET CANCELLATION,” filed by Brox et al. on October 15, 2019, which claims priority to U.S. patent application No. 16 / 601,439, entitled “OFFSET CANCELLATION,” filed by Brox et al. on October 14, 2019, and U.S. provisional patent application No. 62 / 746,250, entitled “OFFSET CANCELLATION,” filed by Brox et al. on October 16, 2018, each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to offset cancellation. Background Art

[0006] The following relates generally to systems including at least one memory device, and more specifically, to offset cancellation.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device can store one of two states, often represented by a logical 1 or a logical 0. In other devices, more than two states can be stored. To access the stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0008] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even when no external power is present. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless they are periodically refreshed by an external power source.

[0009] The memory device may include various channels for communicating information with other devices (eg, controllers) within the system. Procedures to configure the receiver of the memory device to ensure effective and efficient reception of data from other devices are desirable. Summary of the invention

[0010] A method is described. The method may include identifying a first state of a channel for transmitting data to a controller, the first state corresponding to active termination of the channel; determining that the channel transitions from the first state to a second state corresponding to interrupting the active termination; and for a receiver coupled to the channel and while the channel is in the second state, calibrating an offset associated with a reference voltage for identifying a signal received on the channel.

[0011] A method is described. The method may include driving a channel for transmitting data in a first state, the first state corresponding to active termination of the channel; enabling a second state that interrupts the active termination by refraining from driving the channel, the second state corresponding to offset calibration for the channel; after the offset calibration, transitioning the channel out of the second state; and performing an access operation for a memory device on the channel based at least in part on transitioning the channel out of the second state.

[0012] An apparatus is described. The apparatus may include a receiver coupled to a channel for transmitting data, the channel being configured to operate in a first state corresponding to active termination of the channel and a second state that interrupts the active termination; a processor configured to determine that the channel transitions from the first state to the second state; and an output driver configured to drive a set of calibration signals on the channel when the channel is in the second state, wherein the receiver is configured to detect an offset associated with a reference voltage based at least in part on the set of calibration signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a system supporting offset cancellation as described herein is described.

[0014] Figure 2 An example of a memory die supporting offset cancellation as described herein is illustrated.

[0015] Figure 3 An example of an eye diagram supporting offset cancellation as described herein is illustrated.

[0016] Figure 4A An example of a system supporting offset cancellation as described herein is described.

[0017] Figure 4B Examples of state transitions that support offset cancellation as described herein are illustrated.

[0018] Figure 5 An example of a process flow in a system supporting offset cancellation as described herein is illustrated.

[0019] Figure 6 and 7 A flow chart illustrating one or more methods of supporting offset cancellation as described herein is shown. DETAILED DESCRIPTION

[0020] In some memory systems, a procedure may be used to tune a receiver that transmits data between two devices (e.g., a host device and a memory device). For example, a calibration procedure for a receiver may reduce errors that may occur during one or more access operations (e.g., read and write operations). In some cases, the ability of a receiver to efficiently detect an input signal may be affected by the type of signaling transmitted on a channel. For example, a data eye for a signal modulated according to a scheme including three or more levels (e.g., multi-level signaling, signaling having at least four voltage levels) may become relatively small due to intermediate voltage levels between a lowest voltage and a highest voltage.

[0021] In such cases, the voltage resolution used by the receiver to distinguish the levels of these signals (e.g., distinguishing between '01' and '00') may need to be greater than the resolution of a signal having, for example, two levels. In addition, the inherent characteristics of the receiver may also cause random variations in the local voltage experienced at the receiver (e.g., caused by variations in the input transistors). Such unpredictable variations may result in input offsets that affect the receiver's ability to accurately detect the value of the signal. Thus, a calibration procedure may be used to eliminate such offsets caused by the receiver circuitry.

[0022] Some memory systems may utilize termination lines to reduce interference from signals transmitted on a channel. For example, a channel may include components that match the characteristic impedance of a conductive line corresponding to the channel, which may prevent the signal from reflecting back toward the transmitting device and causing interference. In some cases, when not used for access operations between a memory device and a host device, the channel may be continuously maintained at a terminated voltage level and actively driven, for example, at a low level ('0') or a high level ('1').

[0023] However, a device (such as a memory device) may require a non-terminated (e.g., tri-stated) condition of a channel to perform a procedure of calibrating a receiver to compensate for input offsets. To enable such a procedure, a period of time during which the channel is not actively terminated may be inserted into the communication protocol. As described herein, an additional state of a channel may be utilized that allows a memory device to perform operations while the channel is not actively terminated. In this state, as an example, a host device may tri-state its transmitter (e.g., refrain from driving a signal that causes the channel to be actively terminated) so that the memory device may gain full control of the channel for a period of time. While the channel is in this state, the memory device may perform one or more desired operations.

[0024] The channel may enter the non-terminated state in a variety of ways. For example, a command may trigger a transition from a first state (e.g., where the termination is active) to a second state (e.g., where the termination is not active). In such cases, a device (e.g., a host device) may determine to transition the channel to the second state and transmit a signal to the memory device that may indicate the transition. Once the second state is identified (e.g., by the memory device), the device may have the ability to drive certain voltage levels on the channel to perform a calibration procedure (e.g., an offset calibration procedure to eliminate offsets that may be inherent to one or more receivers). In some cases, the command may be issued before performing an access operation (e.g., a high-speed access operation). For example, a command may be issued before an access operation so that a calibration procedure may be performed on the channel before the access operation begins.

[0025] Additionally or alternatively, the second state of the channel may be entered (e.g., automatically) at a specific time. For example, the second state of the channel may be entered during a power-on sequence (e.g., after the memory device exits a reset state) or at a specific time (e.g., a defined time) after the power-on sequence. After a defined number of clock cycles (e.g., long enough to allow calibration of the receiver), the channel may enter the second state (e.g., automatically). In some cases, the second state may also be automatically exited (e.g., after a determined number of clock cycles), for example. In other examples, a signal sent from the controller to the memory device may indicate the transition of the channel from the second state.

[0026] In this article Figure 1The features of the present disclosure are described with respect to an exemplary memory system hierarchy in the context of Figure 2 Features of the present disclosure are further described in the context of an exemplary memory device. Figure 4A and 4B Specific examples of state transitions of the system and the channel are described in the context of FIG. Figure 5 The process flow and Figure 6 and 7 The flowcharts of FIG. 5 further illustrate and describe these and other features of the present disclosure.

[0027] Figure 1 An example of a system 100 utilizing one or more memory devices according to aspects disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0028] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a handheld computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, and the like. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some examples, system 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0029] At least a portion of the system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a handheld computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host or a host device. In some examples, the system 100 is a graphics card.

[0030] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / space that may be used or referenced by system 100. In some instances, memory device 110 may be configured to cooperate with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be used to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0031] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0032] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may electronically communicate with each other using a bus 140.

[0033] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other instances.

[0034] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0035] Peripheral component 130 may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0036] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0037] Input device 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input device 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0038] Output device 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output device 150 may include a display, an audio speaker, another processor on a printed device or printed circuit board, etc. In some cases, output device 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0039] The components of system 100 may be composed of general or special purpose circuits designed to perform their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

[0040] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0041] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., a memory die 160-a, a memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, a plurality of memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, a level, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This can increase the number of memory cells that can be located on the substrate compared to a single 2D memory device, which in turn can reduce production costs or increase performance of the memory array 170, or both. In some 3D memory devices, different stacks can share at least one common access line, such that some stacks can share at least one of a word line, a digit line, and / or a plate line.

[0042] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command or a read command, wherein the write command instructs the memory device 110 to store certain data on behalf of a component of the system 100 (e.g., the processor 120) and the read command instructs the memory device 110 to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, and the like.

[0043] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0044] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the operating details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0045] In some cases, the external memory controller 105 or other components of the system 100, or the functions thereof described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functions thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120 ).

[0046] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to act as part of a channel. In some cases, a reference voltage of a receiver may be tuned to improve communication on a conductive line. For example, a receiver may be calibrated to account for (e.g., eliminate) an offset from a reference voltage, where the offset may be caused by variations of components of system 100 (e.g., Monte Carlo variations of transistors). In such cases, by accounting for the offset, the receiver may be tuned to more efficiently detect signals received at the memory device.

[0047] In some cases, the pins or pads of the terminals may be part of a signal path of channel 115. Additional signal paths may be coupled with the terminals of the channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., internal to memory device 110 or a component thereof, such as a signal path internal to memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0048] In some cases, channel 115 may include electrically terminated conductive lines. For example, a device (e.g., memory device 110, external memory controller 105) coupled to channel 115 may include a component that matches the characteristic impedance of the conductive line corresponding to the channel. As an example, a component (e.g., at the end of the conductive line) may include a set of resistors (e.g., termination resistors) to match the impedance of the line, thereby preventing the signal from reflecting back toward the transmitting device and causing interference. In some cases, the voltage of the component may be maintained at a constant value to achieve active electrical termination of the conductive line. In some cases, external memory controller 105 may control active termination of one or more channels 115 within system 100. As described herein, external memory controller 105 may refrain from driving channel 115 to cause an active termination interruption, thereby enabling a device (e.g., memory device 110) to control channel 115 when channel 115 is not terminated (e.g., tri-stated).

[0049] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting a specific type of information. In some cases, channel 115 may be an aggregate channel and may therefore include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc.

[0050] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command regarding the address of the desired data. In some cases, CA channel 186 may register on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channel 186 may include eight or nine signal paths.

[0051] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channel 188 may be configured to communicate one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to adjust (e.g., oscillate) between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. In some cases, the clock signal may be a 1.5 GHz signal. CK channel 188 may include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signal CK may therefore be variously referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0052] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110. Data channels 190 may transfer signals that may be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

[0053] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths. In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference (e.g., a timing reference for both read and write operations) that is commonly used for access operations of the memory device 110. Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate the access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths.The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0054] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels may be configured to convey error detection signals, such as checksums, to improve system reliability. EDC channels may include any number of signal paths.

[0055] The channel 115 may couple the external memory controller 105 with the memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0056] A variety of different modulation schemes may be used to modulate signals transmitted over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and the like.

[0057] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal or PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0058] System 100 may support techniques for achieving optimization of reference voltages for use by a receiver of memory device 110. For example, channel 115 may be actively terminated and a state that interrupts active termination may be used, thereby allowing memory device 110 to control the channel. In such cases, memory device 110 may actively drive a calibration signal (e.g., a signal that sweeps through a set of reference voltages) that identifies an offset associated with each reference voltage at the receiver. By doing so, the memory device may compensate (e.g., eliminate) detected offsets for the receiver, which may enhance detection of signals received by memory device 110.

[0059] In some cases, a state of the channel (e.g., a state in which the influence of the external memory controller 105 is removed from the channel) may be enabled (e.g., automatically, by one or more commands sent, for example, by the external memory controller 105). For example, the channel may be tri-stated a defined time after the memory device 110 exits the reset state (e.g., during power-up). Additionally or alternatively, the external memory controller may recognize the access operation and may signal that the channel is to be transitioned to tri-stated prior to the access operation. The memory device 110 may thus perform an offset calibration while the channel is tri-stated prior to the access operation. In any case, the channel may be transitioned out of tri-stated automatically or based on one or more commands (e.g., from the external memory controller 105).

[0060] Using a state that interrupts active termination of a channel can enable durations when the channel is not actively driven (e.g., for termination or for access operations) during which the memory device 110 can transmit signals on the channel. Such signals can enable calibration of a receiver to account for offsets associated with reference voltage levels and improve the resolution with which the receiver detects signals received at the memory device (e.g., during write operations). Such techniques can improve communication efficiency in the system 100 by reducing the number of errors in received data.

[0061] Figure 2 An example of a memory device 200 according to various examples of the present disclosure is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0062] Memory cell 205 can store a charge representing a programmable state in capacitor 230. In a DRAM architecture, a memory cell (e.g., memory cell 205) can include a capacitor 230 having a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are also possible. For example, a nonlinear dielectric material can be used.

[0063] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digit line 215. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, and digit lines, or the like, are interchangeable and do not affect understanding or operation. Activating or selecting word line 210 or digit line 215 may include applying a voltage to the corresponding line.

[0064] The memory die 200 may arrange access lines (e.g., word lines 210 and digit lines 215) in a grid-like pattern. Memory cells 205 may be located at intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections.

[0065] Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from a local memory controller 260 and activate a word line 210 based on the received row address. The column decoder 225 may receive a column address from a local memory controller 260 and may activate a digit line 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, such as WL_1 and DL_3, a memory cell 205 at the intersection thereof may be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0066] Memory cell 205 may include a logic storage component, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell board reference voltage, such as Vpl, or may be grounded, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0067] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch component 235. Capacitor 230 can be in electronic communication with digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 can be coupled to digit line 215. In some cases, switch component 235 can be or include a transistor and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, switch component 235 can be or include a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switch component 235, and switch component 235 can be activated / deactivated based on the voltage applied to word line 210.

[0068] The word line 210 may be a conductive line that may be used to electronically communicate with the memory cell 205 for performing an access operation on the memory cell 205. In some architectures, the word line 210 may electronically communicate with a gate of a switch component 235 of the memory cell 205 and may be configured to control the switch component 235 of the memory cell 205. In some architectures, the word line 210 may electronically communicate with a node of a capacitor 230 of the memory cell 205 and the memory cell 205 may not include a switch component 235.

[0069] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0070] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205, and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be extremely small. Therefore, the sensing component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., release charge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 0. The sensing component 245 can include various transistors or amplifiers to detect and amplify the difference in signals. The detected logic state of the memory cell 205 can be output as an output 255 via the column decoder 225. In some cases, the sensing component 245 can be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 can be in electronic communication with the row decoder 220 or the column decoder 225.

[0071] The local memory controller 260 may control the operation of the memory cell 205 via various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 220, column decoder 225, and sense component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to receive data from the external memory controller 105 (or reference 105). Figure 1The device memory controller 155 described herein receives commands and / or data, translates the commands and / or data into information that can be used by the memory die 200, performs one or more operations on the memory die 200, and communicates data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 260 can generate row and column address signals to activate the target word lines 210 and the target digital lines 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or varied and can be different for the various operations discussed when operating the memory system 200. In some cases, the local memory controller 260 can control the calibration of one or more components of the memory die 200. For example, the local memory controller 260 can trigger the transmission of a signal for calibration of a group of receivers. In such cases, the signal may be transmitted during time periods when the data channel is not actively being driven (eg, by an external memory controller).

[0072] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. Local memory controller 260 may apply a specific signal (eg, voltage) to digit line 215 during a write operation to store a specific state (eg, charge) in capacitor 230 of memory cell 205 that may indicate a desired logic state.

[0073] In some cases, the local memory controller 260 can be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cell 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 260 can identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 260 can identify the target word line 210 and the target digit line 215 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can pass a signal to the sensing component 245 in response to the biased access line. The sensing component 245 can amplify the signal. The local memory controller 260 may trigger the sensing component 245 (e.g., latch the sensing component) and, in turn, compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. As part of a read operation, the local memory controller 260 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0074] In some memory architectures, accessing a memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor 230 of the target memory cell 205. The local memory controller 260 may perform a rewrite operation or a refresh operation to restore the memory cell 205 to its original logic state. The local memory controller 260 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line (e.g., word line 210) may disturb the state stored in some memory cells 205 that are in electronic communication with the access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells 205 that may not have been accessed.

[0075] Figure 3 An example of an eye diagram 300 supporting offset cancellation as described herein is illustrated. The eye diagram 300 may depict overlapping data transmissions and may illustrate reference Figure 1 and 2Implementations of aspects of system 100 and memory die 200 are described. In some examples, eye diagram 300 can represent a signal modulated according to a signal including three or more levels 305 (eg, a multi-level signal).

[0076] Eye diagram 300 may be used to indicate the quality of a signal in a high-speed transmission and may represent four symbols of a signal (e.g., '00', '01', '10', and '11'). In some examples, each of the four symbols may be represented by a different voltage amplitude (e.g., voltage levels 305-a, 305-b, 305-c, and 305-d). In other examples, eye diagram 300 may represent a signal that may be used to transmit a memory device (e.g., reference numeral 305). Figure 1 300. The eye diagram 300 may be used to provide a visual indication of signal health and integrity, and may further indicate the noise margin of the data signal. The noise margin may, for example, refer to the amount by which the signal exceeds the ideal boundaries of the level 305. In the present example, the eye diagram 300 illustrates four distinct voltage levels 305 (e.g., a first voltage level 305-a, a second voltage level 305-b, a third voltage level 305-c, and a fourth voltage level 305-d) or symbols that may be transmitted, for example, using PAM4 signaling (e.g., across conductors).

[0077] To generate the eye diagram 300, an oscilloscope or other computing device may sample a digital signal according to a sampling period 310 (e.g., a unit time interval or a bit period). The sampling period 310 may be defined by a clock associated with the transmission of the measured signal. In some examples, the oscilloscope or other computing device may measure the voltage level of the signal during the sampling period 310 to form a trace 315. Noise and other factors may cause the trace 315 measured from the signal to deviate from the ideal step function set. By overlapping multiple traces 315, various characteristics about the measured signal may be determined. For example, the eye diagram 300 may be used to identify different characteristics of a communication signal, such as jitter, crosstalk, distortion, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. A closed eye may indicate a noisy and / or unpredictable signal.

[0078] The 'eye' of the eye diagram 300 may refer to the space between the traces 315 and may include a width, such as width 320, and an opening, such as opening 330. As the signal converges toward one of the plurality of voltage levels 305-a to 305-d, the area between the levels 305-a to 305-d without the traces 315 may therefore be referred to as the eye of the eye diagram 300. Each eye in the eye diagram 300 may have a unique width 320 based on the characteristics of the measured signal. The width 320 of the measured signal may be modified using various encoding and decoding techniques.

[0079] In order to distinguish between different voltage levels 305 when decoding a signal, a corresponding reference voltage 340 may be located between the different levels 305 represented by trace 315. For example, a low level reference voltage 340-a may be located between a first voltage level 305-a and a second voltage level 305-b; a mid level reference voltage 340-b may be located between a second voltage level 305-b and a third voltage level 305-c; and a high level reference voltage 340-c may be located between a third voltage level 305-c and a fourth voltage level 305-d. When decoding, the signal represented by trace 315 may be compared to reference voltage 340 at a sampling time that may be near the middle of sampling period 310. The smaller the eye associated with reference voltage 340, the more likely it is that errors will be introduced into detection. Thus, a receiver may ideally use a minimum voltage difference (relative to reference voltage 340) to distinguish whether a particular signal is higher or lower than reference voltage 340. In practice, however, the data eye may be smaller, for example, due to cross-coupling, noise, unstable voltages, and the like. Thus, an error (e.g., an incorrect value) may be detected if a signal intended to transmit the first voltage level 305-a settles on the low-level reference voltage 340-a or inadvertently exceeds the low-level reference voltage 340-a when a sampling event occurs. Thus, the receiver may determine that the second voltage level 305-b was signaled when the first voltage level 305-a was actually signaled.

[0080] For high speed data transmissions (e.g., transmissions with a data transfer rate that meets a threshold), it may become increasingly difficult for a receiver to distinguish whether a signal is below or above a corresponding reference voltage 340. Additionally, some receivers may experience a variable offset 350 when sensing a received signal. The offset 350 may be caused by certain inherent characteristics of the receiver itself (e.g., due to a manufacturing process that may result in local voltage variations from random dopant placement). For example, the circuitry of a receiver may include a complementary metal oxide semiconductor (CMOS) transistor (e.g., similar to a differential amplifier) ​​that compares a received signal to a reference voltage 340. Although CMOS transistors may be manufactured to be identical, the inherent characteristics and behavior of individual CMOS transistors may vary (an effect that may be referred to as Monte Carlo variations). Thus, a receiver may experience variations in the sensed voltage level of a received signal, which may be based on the area of ​​the CMOS transistor. This variation may result in an offset 350 from the reference voltage 340, affecting the receiver's ability to correctly determine whether a signal is above or below the reference voltage 340. These receiver characteristics that result in voltage variations, as well as a small data eye, may make it difficult to effectively receive data without errors in high speed transmission scenarios.

[0081] However, as disclosed herein, a state of a channel may be enabled to perform a calibration procedure that compensates for an offset 350 caused by inherent variations produced by the receiver circuitry. For example, a state on a channel (e.g., a channel that is normally actively terminated) may be enabled during a time period that provides an opportunity for a device, such as a receiving device, to drive calibration signals on the channel. These calibration signals may enable the device to detect an offset 350 associated with a reference voltage 340 and compensate (e.g., eliminate) the offset 350 (e.g., by modifying the associated reference voltage 340, or modifying some other characteristic of the receiver circuitry). Thus, the offset 350 may be compensated for to improve the resolution and reliability of detecting the value of the received signal. In cases where the offset 350 is not dependent on time or temperature, the offset elimination may be performed once before an access operation (e.g., a read operation or a write operation), thereby ensuring accurate identification of the received data.

[0082] Figure 4A and 4B One or more examples of a system 401 and state transitions 402 for supporting a channel with offset cancellation as described herein are illustrated, respectively. System 401 may include a controller 405 and a memory device 410, each of which may implement aspects of the described techniques. The disclosure herein is not limited to examples including a controller or a memory device or both. The operations and aspects described herein are not limited to the use of these components, and other alternatives are contemplated.

[0083] The controller 405 may be as described herein with reference to Figure 1 The examples of external memory controller 105 described herein (eg, CPU, GPU, GPGPU, etc.) Additionally or alternatively, the memory device 410 may be as described in reference Figures 1 to 3 Examples of memory device 110 are depicted (eg, a graphics double data rate (GDDR) memory device).

[0084] The memory device 410 can communicate with the controller 405 over one or more channels 415. Such channels 415 (e.g., conductive lines) can couple pins of the memory device 410 with pins of other devices. For example, the channel 415 can couple a data (DQ) pin of the memory device 410 with a corresponding pin of the controller 405, and data can be transferred between the memory device 410 and the controller 405. The controller 405 can perform access operations with the memory device 410, wherein data is transmitted to the memory device 410 during a write operation, and the memory device 410 can accordingly receive the data using one or more receivers 420.

[0085] A receiver, such as receiver 420, may be affected by the type of signaling transmitted on channel 415. For example, a data eye for multi-level signaling may be attributed to a signal between a lowest amplitude and a highest amplitude (e.g., between first voltage level 305-a and fourth voltage level 305-d, as shown in FIG. Figure 3 4. As a result, the voltage resolution used by receiver 420 to distinguish multi-level signals (e.g., distinguishing between '01' and '00') may need to be greater than the resolution of a signal having two levels. In addition, the characteristics of receiver 420 may cause random variations in the local voltage experienced at receiver 420 (e.g., caused by Monte Carlo variations of the input transistors), resulting in an input offset that affects the ability of receiver 420 to accurately detect the value of the signal.

[0086] System 401 may implement termination lines to reduce interference from signals transmitted on channel 415. In such examples, channel 415 may include components that match the characteristic impedance of the conductive line corresponding to channel 415, which may prevent the signal from reflecting back toward the transmitting device and causing interference. Channel 415 may be maintained at a terminated voltage level and actively driven, for example, at a low level ('0') or a high level ('1').

[0087] However, if the memory device 410 is to perform the procedure of calibrating the receiver 420 to compensate for the input offset described above, then a non-terminated (e.g., tri-stated) condition of the channel 415 may be desired. Specifically, in other systems, the memory device 410 may not have control of the channel 415 because the memory device 410 may only react to instructions for access operations received from the controller 405. When access operations are not being performed, the controller 405 may drive the channel 415 in an actively terminated state, and the channel 415 may not be available to the memory device 410 at any time. For example, the offset calibration procedure may include driving the receiver 420 to a voltage that is equal to a reference voltage (e.g., equal to a reference voltage) by the memory device 410. Figure 3 4. However, in other termination systems, if the memory device 410 does not have the opportunity to control the channel 415 and drive such a signal, then offset calibration may not be possible.

[0088] To enable such operations, a time period during which the channel 415 is not actively terminated may be inserted into the communication protocol. As described herein, an additional state of the channel 415 may be introduced to allow operations performed by the memory device 410. In this state, the controller 405 may tri-state its transmitter (e.g., refrain from driving a signal that causes the channel 415 to be actively terminated) so that the memory device 410 can obtain full control of the channel 415. When the channel 415 is in this state, the memory device 410 may perform its desired operations when independent control of the channel 415 is required. As an example, an offset calibration for the receiver 420 may be performed. In such a case, the processor 425 of the memory device 410 may recognize that the channel has entered a state in which the termination is no longer active, and the driver 430 may drive a voltage within the range of the reference voltage of the receiver 420 onto the channel 415. The voltage driven by the memory device 410 on the channel 415 may not be modified by the termination on the controller side, thereby enabling the processor 425 to sweep through a set of voltages to identify any input offset from the receiver 420.

[0089] like Figure 4B As illustrated in the state transition 402 of , the channel 415 may transition between different states corresponding to active termination enabled, no termination (e.g., tri-state), and data transfer, respectively. For example, the channel 415 may initially be in a first state in which the termination is active, and at time T0, the channel may transition to a second state corresponding to the tri-state. While in the tri-state, the memory device 410 may use the channel 415 to perform an operation, which may include transmitting a signal on the channel 415. After a period of time, the channel 415 may transition out of the second state at time T1 to perform an access operation, in which data may be transferred between the controller 405 and the memory device 410 on the channel 415. At time T3, after the access operation is completed, the channel 415 may transition back to the first state in which the termination is active. It should be noted that the state transition 402 is only one illustrative example of different states that the channel 415 may assume, and additional or different states may be used. For example, at time T1, the channel 415 may transition from the second state back to the first state (with active termination). Additionally, while state transition 402 illustrates active termination at a high level, it should be understood that channel 415 may also be actively terminated at a low level, as described herein.

[0090] The channel 415 may enter the non-terminated state in a variety of ways. For example, a command may trigger a transition from a first state (e.g., where the termination is active) to a second state (e.g., where the termination is not active). In such cases, a device (e.g., controller 405) may determine to transition the channel 415 to the second state and transmit a signal to the memory device 410 that may indicate the transition. The processor 425 may identify that the state of the channel 415 will transition (and may further identify a time period during which the channel 415 will be tri-stated), and may cause the driver 430 to drive the signal on the channel 415 while in the second state. That is, once the memory device 410 identifies the second state, the memory device 410 may have the ability to drive certain voltage levels on the channel 415 to perform a calibration procedure (e.g., offset calibration to eliminate offsets that may be inherent to one or more receivers 420). In some cases, the channel 415 may transition out of the second state after a period of time (e.g., automatically) or may send a signal indicating that the channel 415 is transitioning from the second state. Signaling indicating a state transition of channel 415 may be transmitted to memory device 410 on channel 415 itself or using a different channel.

[0091] In some cases, a command may be issued before an access operation, such as a high-speed access operation. That is, the system 401 may initially start in a first mode, such as a low-speed mode (e.g., one or more access operations have a data transfer rate below a threshold), and offset calibration may not be required in such a mode. For example, under normal operation, the controller 405 may be configured to perform limited operations. However, when entering a second mode, such as a high-speed mode (e.g., for 3D gaming, complex graphics visualization or manipulation), the system 401 and the memory device 410 may enter a different mode. In such cases, a command may be issued to transition the channel 415 to a tri-state before entering the high-speed mode. Therefore, the receiver 420 of the memory device 410 may be fully calibrated to achieve efficient data transfer during subsequent access operations.

[0092] Additionally or alternatively, the second state may be automatically entered at a specific time. For example, the tri-state of channel 415 may be entered during a power-on sequence (e.g., after the memory device exits the reset state) or at a defined time after the power-on sequence. Channel 415 may automatically enter the second state after a defined number of clock cycles (e.g., corresponding to time T0). As an illustrative example, the clock cycles after exiting the reset state may be counted, and memory device 410 may control channel 415 from 2000 clock cycles after the reset exit to 3000 clock cycles after the reset exit. Different values ​​of clock cycles may be possible, and those clock cycle values ​​are given only for ease of description. Processor 425 may know the number of clock cycles and cause driver 430 to perform offset calibration on channel 415 (e.g., after time T0).

[0093] In some cases, the second state may be exited automatically (e.g., after a determined number of clock cycles). In other examples, the controller 405 may transmit a signal or command indicating the transition of the channel 415 from the second state. By automatically entering (and / or exiting) the tri-state of the channel 415, command entry and associated overhead may be avoided within the system 401. Additionally, the tri-state of the channel 415 may be automatically entered before performing an access operation, and the offset calibration performed while the channel 415 is in the second state may enable efficient data transfer as long as the memory device 410 is powered on (e.g., when the offset is not dependent on time and / or temperature, multiple offset calibrations may not be required).

[0094] Figure 5 An example of a process flow 500 in a system supporting offset cancellation as described herein is illustrated. In some examples, aspects of the process flow 500 may be implemented by a controller 505 and a memory device 510, which may be reference Figure 1-3 , 4A and 4B. The disclosure herein is not limited to examples including controllers or memory devices or both. The operations and aspects described herein are not limited to the use of these components, and other alternatives are contemplated.

[0095] For example, the controller 505 may be a reference Figure 1 The example of the external memory controller 105 described above (eg, a GPU). In addition, the memory device 510 may be a reference Figure 1 The process flow 500 may illustrate using different states of a channel to interrupt the active termination state, thereby enabling the memory device 510 to perform offset calibration. Such techniques may improve the reliability of the receiver of the memory device 510 and increase communication efficiency (e.g., fewer errors may occur when identifying received signals).

[0096] At 515, the controller 505 may drive the channel for transmitting data in a first state that causes the channel to be actively terminated. For example, the channel may be driven at a low level ('0') or at a high level ('1') to achieve active termination. At 520, the memory device 510 may recognize that the channel is in the first state and is actively terminated.

[0097] At 525, the controller 505 may enable a second state that interrupts active termination, which may cause the memory device 510 to perform offset calibration on the channel. In such cases, the controller 505 may stop driving the channel. In some cases, the controller 505 may cause its transmitter to enter a tri-state, which may remove the influence of the controller 505 on the channel. In some cases, the controller 505 may identify a first time period, a second time period, or both after the memory device 510 exits the reset state and may enable the second state by stopping driving the channel between the first time period and the second time period. Alternatively, the controller may manage or drive the channel during either or both of the first or second time periods. The first and second time periods may be determined or preconfigured, and the channel may transition (e.g., automatically transition) to the second state based on these determined time periods. In other examples, the controller 505 may identify a command to perform an access operation on the channel. The controller 505 may then transmit a signal indicating that the channel is transitioning to the second state before the access operation begins.

[0098] At 530, memory device 510 may determine that the channel transitions from the first state to the second state and may therefore identify that the active termination is interrupted. Thus, at 535, memory device 510 may calibrate an offset associated with a reference voltage for identifying signals received on the channel for a receiver coupled to the channel and when the channel is in the second state. In such cases, the offset calibration may include transmitting various calibration signals on the channel.

[0099] As an illustrative example, once the controller 505 turns off its driver to put the channel into a tri-state, the memory device can determine that it controls the channel. When performing offset calibration on a non-terminated channel, the memory device 510 can drive a voltage on the channel that will not be modified by the termination on the controller side. For example, the memory device 510 can determine a reference voltage level, and then the driver of the memory device 510 can drive the determined reference voltage level on the channel. The memory device 510 can sweep through various unmodified voltages (for example, because the termination is interrupted), and the receiver of the memory device 510 can detect these voltages. Therefore, the memory device 510 can identify the voltage level where there is a transition from 0 to 1. That is, the memory device 510 can identify that the receiver is transitioning from one level to another. These levels can ideally be at the determined reference voltage level, but there can be a certain offset based on the characteristics of the receiver.

[0100] In the case where an offset of a receiver is identified, the receiver can be modified based on the offset. For example, a memory device can modify the level at which a signal is received (e.g., where a transition from 0 to 1 can be identified), or modify some other characteristic of the receiver. For example, the receiver can perform in a manner similar to a differential amplifier, where a reference voltage is compared to the input on the channel. By turning on additional transistors, a programmable imbalance can be created, which can offset any identified offset.

[0101] At 545, after completing the offset calibration, the controller 505 can cause the channel to transition out of the second state. In some cases, the transition out of the second state can be automatic. Additionally or alternatively, the transition can be based on a command from the controller 505. In some cases, the channel can transition back to the first state associated with active termination of the channel. At 550, the controller 505 and the memory device 510 can perform an access operation on the channel based on transitioning the channel out of the second state.

[0102] Figure 6 A flow chart illustrating a method 600 for supporting a transmit failure feedback scheme for reducing crosstalk according to aspects disclosed herein is shown. The operations of the method 600 may be referred to as Figure 1-5 For example, the operations of method 600 may be implemented by the memory device 410 described with reference to FIG. 4 or by the memory device 410 described with reference to FIG. Figure 5 The described memory device 510 performs. In some examples, the memory device may execute instructions or sets of codes to control the functional elements of the memory device to perform the functions described herein.

[0103] At 605, the memory device may identify a first state of a channel for communicating data with a controller. The first state may correspond to active termination of the channel. That is, the channel may be actively terminated to prevent a transmitted signal from reflecting off a receiving end of the conductive line. Figure 1-5 The described method performs the operation of 605 .

[0104] At 610, the memory device may determine that the channel has transitioned from the first state to a second state corresponding to interrupting active termination. For example, the second state may be a tri-state of the channel (e.g., according to tri-state logic). In the case where the channel is no longer actively driven by the controller, the memory device may transmit a signal when the channel is tri-stated. In some cases, the transition of the channel from the first state to the second state may be based on a determined time period (e.g., after exiting a restart state). The memory device may determine that the channel has transitioned from the first state to the second state according to a reference period. Figure 1-5 The described method performs the operation of 610 .

[0105] At 615, the memory device may calibrate an offset associated with a reference voltage for identifying a signal received on the channel for a receiver coupled to the channel and when the channel is in a second state. In some cases, the duration that the channel is in the second state may be at least equal to the duration of the offset calibration. Figure 1-5 The described method performs the operation of 615 .

[0106] In some examples, an apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: identifying a first state of a channel for transmitting data to a controller, the first state corresponding to active termination of the channel; determining that the channel transitions from the first state to a second state corresponding to interrupting the active termination; and for a receiver coupled to the channel and when the channel is in the second state, calibrating an offset associated with a reference voltage for identifying a signal received on the channel.

[0107] Some instances of the method 600, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for determining that the channel transitions from the first state to the second state during a first time period after exiting a reset state; calibrating the offset during a second time period after the channel transitions from the first state to the second state based on determining that the channel transitions from the first state to the second state; determining that the channel transitions out of the second state after the second time period may have passed; and performing an access operation based on determining that the channel transitions from the second state.

[0108] In some examples of the method 600, apparatus, and non-transitory computer-readable media described herein, the first time period includes a first number of clock cycles and the second time period includes a second number of clock cycles. Some examples of the method 600, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: receiving a signal indicating that the channel transitions from the first state to the second state, wherein the calibration may be performed based on the signal.

[0109] Some examples of the method 600, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: determining that the channel transitions out of the second state after a first number of clock cycles have elapsed; and performing an access operation for the controller on the channel based on determining that the channel transitions from the second state.

[0110] Some examples of the methods 600, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for: receiving a second signal from the controller indicating that the channel is transitioning out of the second state. In some examples of the methods 600, apparatus, and non-transitory computer-readable media described herein, the signal may be received on a second channel different from the channel.

[0111] In some examples of the methods 600, devices, and non-transitory computer-readable media described herein, the channel transitions from the first state to the second state prior to an access operation having a data transfer rate that satisfies a threshold. In some examples of the methods 600, devices, and non-transitory computer-readable media described herein, the second state corresponds to a bus having an impedance that satisfies a threshold.

[0112] Figure 7 A flowchart illustrating a method 700 for supporting offset cancellation according to aspects disclosed herein is shown. The operations of the method 700 may be referred to as Figure 1-5 For example, the operations of method 700 may be performed by controller 405 described with reference to FIG. 4 or by controller 406 described with reference to FIG. Figure 5 The controller 505 described here performs. In some examples, the controller may execute a set of codes to control functional elements of a device (eg, memory device 410, which may include memory device 110) to perform the functions described herein.

[0113] At 705, the controller may drive a channel for transmitting data in a first state, the first state corresponding to active termination of the channel. For example, the channel may be actively driven so that a voltage used by a set of termination resistors is maintained at a constant value (e.g., low (0) or high (1)). Figure 1-5 The described method performs the operation of 705 .

[0114] At 710, the controller may enable a second state that interrupts active termination by refraining from driving the channel, wherein the second state may correspond to offset calibration for the channel. For example, the second state may be tri-stating of the channel (e.g., according to tri-state logic) such that the controller is no longer actively driving the channel. When the channel is tri-stated, for example, to transmit a calibration signal on the channel that is no longer driven by the controller, the memory device may accordingly gain control of the channel. The second state may correspond to an offset calibration for the channel. Figure 1-5 The described method performs the operation of 710 .

[0115] At 715, the controller may transition the channel out of the second state after the offset calibration. In such cases, there may be a defined duration of offset calibration to be performed, and the controller may transition the channel out of the tri-state after the defined duration. In some cases, the channel may return to the first state (e.g., the active termination state) after the offset calibration. The controller may transition the channel out of the tri-state according to the reference. Figure 1-5 The described method performs the operation of 715 .

[0116] At 720, the controller may perform an access operation for the memory device on the channel based on transitioning the channel out of the second state. For example, write data may be transmitted from the controller to the memory device on the channel. In such cases, the memory device may operate its receiver using a reference voltage that has been calibrated based on an offset calibration performed when the channel was tri-stated. Figure 1-5 The described method performs the operation of 720 .

[0117] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., instructions executable by a processor stored by a non-transitory computer-readable medium) for: driving a channel for transmitting data in a first state, the first state corresponding to active termination of the channel; enabling a second state that interrupts the active termination by refraining from driving the channel, the second state corresponding to offset calibration for the channel; and after the offset calibration, transitioning the channel out of the second state; and performing an access operation for a memory device on the channel based on transitioning the channel out of the second state.

[0118] Some instances of the method 700, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: identifying a first time period after exiting a reset state and a second time period after exiting the reset state; and enabling the second state by refraining from driving the channel between the first time period and the second time period.

[0119] In some examples of the methods 700, apparatus, and non-transitory computer-readable media described herein, the first time period includes a first number of clock cycles and the second time period includes a second number of clock cycles. Some examples of the methods 700, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for transmitting a first signal indicating that the channel transitions from the first state to the second state to a receiver coupled to the channel.

[0120] Some instances of the method 700, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: enabling the second state within a time period after transmitting the first signal, the time period corresponding to the duration of the offset calibration; and causing the channel to transition from the second state after expiration of the time period.

[0121] Some examples of the method 700, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for transmitting a second signal to the receiver indicating that the channel transitioned out of the second state.

[0122] Some examples of the method 700, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: identifying a command to perform the access operation on the channel; and transmitting the first signal prior to the access operation, wherein the offset calibration may be performed prior to the access operation starting.

[0123] Some examples of the method 700, apparatus, and non-transitory computer-readable media described herein may additionally include operations, features, means, or instructions for enabling the second state of the channel by deactivating an output driver coupled to the channel.

[0124] It should be noted that the methods described herein describe possible embodiments, and that operations and steps may be rearranged or otherwise modified, and other embodiments are possible. In addition, aspects from two or more than two of the methods may be combined.

[0125] In some examples, an apparatus or device may use general or special purpose hardware to perform aspects of the functionality described herein. The apparatus or device may include a receiver coupled to a channel for transmitting data, the channel being configured to operate in a first state corresponding to active termination of the channel and a second state interrupting the active termination; a processor configured to determine that the channel transitions from the first state to the second state; and an output driver configured to drive a set of calibration signals on the channel when the channel is in the second state, wherein the receiver is configured to detect an offset associated with a reference voltage based on the set of calibration signals.

[0126] In some examples, the processor may be configured to identify a time period after the device exits a reset state, and wherein the processor may be configured to determine that the channel transitions from the first state to the second state during the time period.

[0127] In some examples, the apparatus or device may include a counter configured to count a number of clock cycles after the apparatus exits a reset state, wherein the processor may be configured to determine that the channel transitions from the first state to the second state based on a first number of clock cycles counted by the counter, and wherein the output driver may be configured to drive the set of calibration signals until the counter counts a second number of clock cycles.

[0128] In some instances, the receiver is configured to receive a signal from a controller indicating that the channel transitions from the first state to the second state. In some cases, the receiver is configured to receive a second signal indicating that the channel transitions from the second state to a third state corresponding to performing an access operation on the channel. In some instances, the receiver is configured to detect the offset before performing an access operation with a data transfer rate that satisfies a threshold. In some cases, the processor is configured to determine that the channel transitions from the second state to a third state corresponding to communicating on the channel after a period of time.

[0129] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0130] As used herein, the term "virtual ground" refers to a node of a circuit being maintained at a voltage of approximately zero volts (0V) but not directly coupled to the ground. Thus, the voltage of the virtual ground may fluctuate over time and return to approximately 0V in a steady state. Virtual ground may be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" refers to a connection to approximately 0V.

[0131] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0132] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components, in which signals are able to communicate between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0133] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0134] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to obtain the advantage of the characteristic.

[0135] As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, etc., that provides an electrically conductive path between elements or components of a memory array.

[0136] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0137] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material (e.g., a metal). The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0138] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0139] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0140] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0141] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0142] The functions described herein may be implemented in hardware, software, firmware executed by a processor, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0143] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special-purpose computer or a general or special-purpose processor. And, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0144] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operation, comprising: operating according to a first data communication mode associated with a first data rate; calibrating one or more data eyes based at least in part on transmitting one or more calibration signals, the one or more data eyes associated with communications according to a multi-level modulation scheme, wherein the multi-level modulation scheme is associated with a second data communication mode associated with a second data rate greater than the first data rate; as well as Signals are transmitted via one or more channels and in accordance with the second data communication mode in accordance with the multi-level modulation scheme and based at least in part on calibrating the one or more data eyes.

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