Non-volatile memory architecture

Abstract

The invention relates to a non-volatile memory architecture. A non-volatile memory includes a first region having a first storage element configured to store a value associated with a first neuron of a network and a second region having a second storage element. The control circuit applies one or more first input values to first read paths, each first read path including one of the first storage elements. A calculation circuit adds the current supplied by the first read path to generate an output current. The programming circuit converts the output current into a programming current, and programs the second memory element using the programming current.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French Patent Application No. 2310039, filed on September 22, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure generally relates to non-volatile memory configured to perform computational operations. In particular, the present disclosure relates to non-volatile memory configured to perform computational operations between multiple layers of an artificial neural network. Background Art

[0004] The operation of a neural network usually means the execution of a high-level algorithm by a processor. The computational operations (such as convolution and / or matrix computation operations) controlled during the execution of the algorithm then mean the transfer of data between a non-volatile and / or volatile memory and the processor. The transferred data are, for example, parameters of the neural network, such as weights. Intermediate results between successive computational operations are, for example, temporarily stored in a volatile memory.

[0005] Each data transfer between the non-volatile memory and / or the volatile memory and the processor is very time-consuming and energy-consuming. This can lead to time delays in data processing of, for example, neural networks, and a decrease in data processing performance.

[0006] There is a need to improve the execution of computational operations controlled by artificial neural networks during data processing. Summary of the invention

[0007] An embodiment provides a non-volatile memory comprising: a first memory area including a first plurality of storage elements configured to store values ​​of weights associated with a first plurality of neurons of a neural network; a second memory area including a second plurality of storage elements; a control circuit configured to apply one or more first input values ​​to a plurality of first read paths, each first read path including one of the first plurality of storage elements; a first computing circuit configured to add currents supplied by the first read paths to generate a first output current; and a programming circuit configured to convert the first output current into a first programming current and to program a first storage element of the second plurality of storage elements using the first programming current.

[0008] According to an embodiment, the one or more first input values ​​are applied to the plurality of first read paths simultaneously.

[0009] According to one embodiment, the control circuit is also configured to apply one or more second input values ​​generated by reading a first storage element among a second plurality of storage elements to a plurality of second read paths, each second read path including one of the first plurality of storage elements, and the non-volatile memory further includes: a second calculation circuit configured to add currents supplied by the second read paths to generate a second output current, the programming circuit configured to convert the second output current into a second programming current, and use the second programming current to program another storage element of the first region of the memory.

[0010] According to one embodiment, the control circuit is also configured to apply one or more third input values ​​generated by reading the other storage elements of the first memory area to multiple third read paths, each third read path includes one of the storage elements in the first plurality of storage elements, and the first calculation circuit is also configured to add the currents supplied by the third read paths to generate a third output current, and the programming circuit is also configured to convert the third output current into a third programming current, and use the third programming current to reprogram the first storage element in the second plurality of storage elements.

[0011] According to one embodiment, the storage elements included in the first read path define weights associated with an input layer of the neural network, and the storage elements included in the third read path define weights associated with another layer or an output layer of the neural network.

[0012] According to one embodiment, the weights stored by the first plurality of storage elements define the weights of neurons belonging to the odd-check layer and the even-check layer of the neural network, respectively, and the weights stored by the second plurality of storage elements define the weights of neurons belonging to the even-check layer and the odd-check layer of the neural network, respectively.

[0013] According to an embodiment, each storage element of the first and second plurality of storage elements belongs to a memory cell, each memory cell being coupled via a word line and a bit line to a control circuit configured to activate or deactivate the word line and the bit line.

[0014] According to an embodiment, the first calculation circuit is configured to generate a first output value based on a current supplied by a memory cell included in a read path among the first read paths.

[0015] According to an embodiment, the calculation circuit is further configured to apply compensation and / or threshold and / or offset and / or scaling effects based on currents supplied by memory cells comprised in a read path among the first read paths.

[0016] According to an embodiment, the memory element and the further memory elements are programmable resistive elements.

[0017] According to an embodiment, the memory further includes a third calculation circuit configured to generate another output value based on current supplied by one or more memory cells included in a read path among the first read paths and one or more first input values.

[0018] According to an embodiment, the first and third calculation circuits are configured to generate output values ​​based on one or more cells common to the plurality of first read paths, the common cells being replicated in at least two sub-regions in the first region.

[0019] An embodiment provides a method, comprising: applying one or more first input values ​​to multiple first read paths through a control circuit, each first read path comprising one of a first plurality of storage elements in a first region of a non-volatile memory, the first plurality of storage elements being configured to store weight values ​​associated with a first plurality of neurons of a neural network; adding currents supplied by the first read paths to generate a first output current through a first computing circuit; converting the first output current into a first programming current through a programming circuit, and programming a first storage element of a second plurality of storage elements in a second region of the non-volatile memory using the first programming current through the programming circuit.

[0020] According to one embodiment, the above method also includes: applying one or more second input values ​​generated by reading a first storage element among a second plurality of storage elements to a plurality of second read paths through a control circuit, each second read path including one of the first plurality of storage elements; adding currents supplied by the second read paths to generate a second output current through a second calculation circuit; converting the second output current into a second programming current through a programming circuit, and programming another storage element of the first area of ​​the memory using the second programming current through the programming circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above features and advantages and other features and advantages will be described in detail in the following disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0022] Figure 1 An artificial neural network is schematically illustrated, and examples of operations performed by the artificial neural network are shown;

[0023] Figure 2 is a block diagram illustrating a non-volatile memory;

[0024] Figure 3 A portion of a non-volatile memory is illustrated;

[0025] Figure 4is a diagram illustrating a plurality of neurons implemented directly in non-volatile memory;

[0026] Figure 5A illustrates the computational operations performed between the first and second layers of a neural network;

[0027] Figure 5B illustrates the computational operations performed between the second and third layers of a neural network;

[0028] Figure 6 is a block diagram illustrating another non-volatile memory;

[0029] Fig. 7A illustrates computational operations performed between a first layer and a second layer of a neural network; and

[0030] Figure 7B Illustration of the computational operations performed between the second and third layers of a neural network. DETAILED DESCRIPTION

[0031] The same features in the various figures are indicated by the same reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may have the same structure, size and material properties.

[0032] For the sake of clarity, only the steps and elements that are helpful for understanding the described embodiments are explained and described in detail.In particular, the programming of resistive elements is known and within the capabilities of those skilled in the art.

[0033] Unless otherwise specified, when two elements are referred to as being connected together, this means being directly connected without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0034] In the following description, when referring to terms defining absolute positions, such as terms "edge", "back", "top", "bottom", "left", "right", etc., or relative positions, such as terms "above", "below", "upper", "lower", etc., or terms defining directions, such as terms "horizontal", "vertical", etc., unless otherwise specified, reference is made to the orientation of the accompanying drawings.

[0035] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0036] Figure 1 An artificial neural network 100 is schematically illustrated, and examples of operations performed by the artificial neural network 100 are shown.

[0037] Artificial neural network 100 includes, for example, layer 102 (layer A), layer 104 (layer B), and layer 106 (layer C). As an example, layers 102 and 106 are the input layer and output layer of neural network 100, respectively. In the illustrated example, layer 102 includes four artificial neurons 108, 110, 112, and 114 associated with weights A1, A2, A3, and A4, respectively. Layer 104 includes three artificial neurons 116, 118, and 120 associated with weights B1, B2, and B3, respectively. Layer 106 includes three neurons 122, 124, and 126 associated with weights C1, C2, and C3, respectively.

[0038] As an example, an input vector 128 is supplied to a layer 102 of a neural network 100. The neural network 100 is then configured to generate an output vector 130 based on the input vector 128. As an example, the input vector 128 includes data related to an image, video, or audio band. As an example, the output vector 130 includes, for example, a probability of belonging to a member of a target pair class, etc. of the image or video. In another example, the neural network 100 is configured to perform speech recognition, language processing, speech to text or text to speech conversion, translation, etc. based on the audio band.

[0039] exist Figure 1 In the example shown in , the input vector 128 includes four input values ​​IN1, IN2, IN3 and IN4. As an example, the layer 102 is configured to perform a linear operation between the input vector 128 and the weights A1 to A4. As an example, the input value IN1 is supplied to the neuron 104, which is configured to perform the multiplication A1×IN1. Similarly, each input value IN2, IN3 or IN4 is supplied to a corresponding neuron with weights A2, A3 or A4, and it is configured to generate corresponding values ​​IN′2=A2×IN2, IN′3=A3×IN3 and IN′42=A4×IN4.

[0040] As an example, neuron 108 is configured to transmit the value IN′1=A1×IN1 to neurons 116 and 120 of layer 104. As an example, neuron 116 also receives values ​​IN′2=A2×IN2 and IN′3=A3×IN3. Neuron 116 is configured to generate the value IN″1=B1×(IN′1+IN′2+IN′3) and transmit it to neuron 122 of layer 106, for example.

[0041] exist Figure 1In the example shown in , neuron 120 is configured to generate a value IN″3 based on the values ​​supplied by neurons 108 and 114. As an example, the value IN″3 is equal to the linear combination B3×(IN′1+IN′4). Neuron 120 is also configured to supply the value IN″3 to neurons 122, 124 and 126 of layer 106, for example.

[0042] exist Figure 1 In the example shown in , neuron 122 is configured to generate an output value O1. The output values ​​are, for example, components of output vector 130. As an example, value O1 is equal to linear combination C1×(IN″1+IN″2+IN″3), where value IN″2 is a value generated by neuron 118, for example, based on values ​​IN′2 and IN′3 and weights B2 and B3. Similarly, neurons 124 and 126 are configured to generate output values ​​O2 and O3, respectively, based on weights C2 and C3 and values ​​IN″1 to IN″3 supplied thereto.

[0043] Thus, the artificial neural network 100 is, for example, configured to perform operations of the multiply and accumulate (MAC) type.

[0044] According to an embodiment, in order to avoid transfer time between a non-volatile memory storing neuron weights, a volatile memory storing, for example, intermediate results (such as the values ​​of IN′1 to IN′4 and IN″1 to IN″3), and a processor configured to perform MAC operations, the MAC operations are performed directly in the non-volatile memory (“in-memory computing”—IMC).

[0045] Figure 2 is a block diagram illustrating a non-volatile memory 200. As an example, the non-volatile memory 200 implements a neural network similar to the neural network 100. As an example, the neural network implemented in the non-volatile memory 200 is a convolutional neural network (CNN), a fully connected neural network, etc. As an example, the neural network implemented in the non-volatile memory 200 has a relatively limited size, for example, including about ten layers.

[0046] According to an embodiment, the non-volatile memory 200 includes two memory areas 202 (half array 1) and 202' (half array 2). The memory areas 202 and 202' each include, for example, memory cell arrays 203 and 203' (bit cell arrays (BITCELL ARRAY)). As an example, the memory cell arrays 203 and 203' each include a plurality of memory cells or storage elements, which can be addressed by rows and columns and by word lines and bit lines. The areas 202 and 202' each include column decoders 204 and 204' (column decoders (COLUMN DECODERS)) and row decoders 206 and 206' (WL decoders). Thus, each memory cell of the arrays 203 and 203' can be addressed via the decoders 204 and 206 and 204' and 206'. As an example, each memory cell implements a neuron of the neural network 100.

[0047] The memory 200 further comprises a control circuit 208 (CTRL CIRCUIT) configured to control the decoders 204, 206, 204' and 206' via a digital circuit 210 (DIGITAL CTRL). As a result of the control of the control circuit 208, the decoders 204 and 206, 204' and 206' then activate a read path comprising memory cells in the array 203 or 203'. The read path corresponds, for example, to a synapse feeding a neuron, each neuron being typically fed by a plurality of synapses.

[0048] According to an embodiment, the memory 200 further comprises at least one computation circuit 212 (IMC). Figure 2 Three circuits 212 are shown, but memory 200 may of course include a greater or lesser number of computational circuits 212. In some cases, memory 200 includes a plurality of computational circuits 212. Each circuit 212 is coupled to an assembly of at least one read path in array 203 and is configured to perform one or more computational operations based on the current intensity at the output of the read path assembly. Each computational circuit 212 is also configured to generate a value based on the current at the output of the read path assembly. Each computational circuit 212 is also coupled to another storage element ( Figure 2 Similarly, each circuit 212 is coupled to at least one assembly of read paths in the array 203' and is configured to perform one or more computational operations based on the current strength at the output of the assembly of read paths.

[0049] As an example, the control circuit 208 places the memory 200 in one of three operating modes. The calculation mode enables the memory to feed one or more read paths and enables the calculation circuit 212 to perform one or more calculation operations. The programming mode enables the memory to program the resistive element ( Figure 2 The read mode allows reading the value programmed in the resistive element included in the memory 200.

[0050] Similarly, non-volatile memory 200 includes other computational circuits 212, each of which is coupled to an assembly of read paths in array 203'. These computational circuits 212 are also configured to generate values ​​based on the current at the output of the assembly of read paths and store these values ​​in other storage elements ( Figure 2 (not shown).

[0051] Each array 203 and 203' includes memory cells representing neurons of multiple layers of a neural network. In particular, each array 203 and 203' includes neurons of layers of the same parity (e.g., odd / even). In other words, if array 203 includes neurons of an input layer (e.g., layer 102, i.e., the first layer) of neural network 100, then it also includes neurons of a third layer (e.g., layer 106, etc.) of neural network 100. Array 203 then includes the second layer (e.g., layer 104) of the network and any other even-parity layers (if present). In another example, neurons of the input layer are included in array 203'.

[0052] As an example, the neural network implemented by the memory 200 is a relatively small-scale network including, for example, approximately ten layers, and, for example, including at least 3 layers and at most 10 layers in total.

[0053] Figure 3 A portion of a non-volatile memory 200 is shown. In particular, Figure 3 Illustrated in further detail is the assembly 300 of the read path included in array 203 and coupled to computation circuitry 212 .

[0054] As an example, the assembly 300 of the read path includes resistive elements 302, 304 and 306 with different resistances, which encode the weights of three neurons of the layer of the neural network. Each resistive element 302, 304 and 306 is coupled to the source or drain of transistors 308, 310 and 312 respectively through its electrode and coupled to the bit lines BL1, BL2 and BL3 (to which a read voltage (READ VOLT) is applied). Resistive elements 302, 304 and 306 are powered by the bit lines BL1, BL2 and BL3, for example, respectively, via the read voltage. The gates of transistors 308, 310 and 312 are respectively coupled to word lines WL1, WL2 and WL3. Transistors 308, 310 and 312 are also coupled to ground (GND) through their drains or sources. As an example, word lines WL1, WL2 and WL3 are different from each other. In another example, at least two resistive elements 302, 304 or 306 are coupled to the same word line. The control circuit 208 is, for example, configured to control power supply of the word lines WL1, WL2, and WL3 via the digital circuit 210. As an example, to control power supply of the word lines, the control circuit 208 places the memory 200 in a computing mode.

[0055] The control circuit 208 is also configured via the digital circuit 210 and the decoder 206 to supply the current at the output of each resistive element 302, 304 and 306 to one of the calculation circuits 212. The calculation circuit 212 is, for example, configured to generate a current based on the current at the output of the elements 302, 304 and 306. As an example, the current generated by the circuit 212 is a function of the sum of the currents at the outputs of the elements 302, 304 and 306. As an example, the calculation circuit 212 also includes a current amplifier configured to amplify the sum of the currents at the outputs of the elements 302, 304 and 306. As an example, the calculation circuit 212 is also configured to apply compensation and / or threshold and / or offset and / or scaling effects based on the currents at the outputs of the elements 302, 304 and 306.

[0056] The calculation circuit 212 is configured, for example, to supply the generated current to the programming circuit 313 (PROG.PATH). The programming circuit is included, for example, in the area 202'.

[0057] As an example, the programming circuit 313 includes a current generator 314 (CURRENT GENERATOR). For example, the reference current value of the current generator 314 is equal to the current supplied by the calculation circuit 212, or is a function of the current.

[0058] The programming circuit 313 also includes, for example, a current mirror 316 (CURRENT MIRROR). As an example, the current mirror 316 is coupled to the current generator 314 and is configured to replicate the current at the output of the current generator 314.

[0059] In other embodiments, for example, if current mirror 316 is configured to apply a gain between the current supplied by computation circuit 212 and the current supplied to storage element 318 , circuit 314 is omitted.

[0060] The current mirror 316 is also coupled to another resistive element 318, and is configured to program the other resistive element 318 to a resistance value according to the current generated by the calculation circuit 212. For example, the current generator 314 is configured to generate a programming current based on the current supplied by the calculation circuit 212. As an example, the resistive element 318 is an element that can be reprogrammed multiple times, and the programming circuit 313 is configured to reprogram the resistive element 318 from a current resistance value to a new resistance value based on the programming current.

[0061] The resistive element 318 is coupled to a reference voltage (HV VOLT) through one of its electrodes and to a source or drain of a transistor 320 through another of its electrodes. As an example, the reference voltage is applied to the resistive element 318 only when the control circuit 208 is in a programming state. The transistor 320 is coupled to ground, for example, through its drain or its source, and its gate is coupled to a word line WL', for example. The word line WL' is controlled, for example, by the decoder 204'. The column decoder 206' is configured to select the correct column to be connected to the current mirror 316, for example. The column decoder 206' is also configured to select a path of the coupling unit.

[0062] The value to which the resistive element 318 is programmed corresponds, for example, to an input value for the next layer of the neural network. Figure 1, the resistive elements 302, 304 and 306 program the weights of the neurons 108, 110 and 112, respectively. Then, the bit lines BL1, BL2 and BL3 supply currents I1, I2 and I3, respectively, which are functions of the states of the transistors 308, 310 and 312 and the resistive elements 302, 304 and 306. Then, the assembly 300 of the read path corresponds to the combination of the neurons 108, 110 and 112 coupled to the neuron 116 of the layer 104. Then, the calculation circuit 212 is configured to perform a layer operation, for example, between the layers 102 and 104. As an example, the layer operation corresponds to the sum of the weight-input value products of the neurons 108, 110 and 112. The current generated by the calculation circuit encodes the input value IN′1+IN′2+IN′3. Therefore, the resistive element 318 is configured to temporarily store the input value of the neuron 116 of the layer 104. In another example, the resistive elements 302, 304, and 306 encode the weights of the neurons 116, 118, and 120, respectively, and the computation circuit 212 is configured to generate a value corresponding to the value IN″1+IN″2+IN″3. As an example, the computation circuit 212 is a node coupling the bit lines of each read path. In other cases, the computation circuit 212 integrates other functions that modify the sum of the currents at the output of the assembly 300 of the read paths. The resistive element 318 is then configured as the input value of the neuron 122 of the storage layer 106.

[0063] Thus, memory 200 includes a plurality of read path assemblies (similar to assembly 300), but the number of resistive elements varies from path assembly to path assembly. For example, each path assembly is coupled to a computational circuit 212. Each circuit 212 is configured to supply a current in a resistive element similar to element 318 for programming a value corresponding to an input value of one or more neurons of the next layer.

[0064] Under the control of decoder 204' and by activating one or more word lines of array 203', the value programmed in element 318 is transferred to the array 203' in the form of a current generated via current mirror 316 and current generator 314. Figure 2 Array 203'.

[0065] Figure 4 is a diagram illustrating multiple neurons implemented directly in non-volatile memory. In particular, Figure 4 An example of the structure of the arrays 203 and 203 ′ is illustrated.

[0066] Each of the arrays 203 and 203' includes a plurality of memory cells 400 addressable in rows and columns. All cells of the same row of the array 203 or 203' are coupled to the same word line (WL1, ..., WLN) controlled by a decoder 204 or 204', N being an integer equal to the number of word lines. Similarly, all cells of the same column of the array 203 or 203' are coupled to the same bit line (BL1, BL2, etc.) controlled by a decoder 206 or 206'. The decoder 206 or 206' is itself coupled to one or more computation circuits 212.

[0067] Memory cells 400 each include a resistive element similar to that described with respect to Figure 3 The resistive element 302, 304 and 306 of each cell 400 is coupled via its electrode to a bit line and a source or drain of a transistor similar to that described with respect to Figure 3 Transistors 308, 310 and 312 are depicted. Each transistor is also coupled to ground via its drain or its source and is activated via the gate by activation of one of the word lines.

[0068] Thus, when the control circuit 208 controls, for example, the activation of the word lines WL1 and WL2 and the power supply of the bit line BL2, the memory cells 402 and 404 located in the first and second rows of the second column of the array 203 or 203' are powered. Then, the cells 402 and 404 form an assembly of, for example, a read path. In particular, the memory cells 402 and 404 are, for example, powered simultaneously. In other words, the memory cells 402 and 404 are each simultaneously supplied with an input current (the input current applied to the cell 402 is, for example, different from the input current applied to the cell 404). As an example, with respect to Figure 1 , units 402 and 404 form an assembly including neurons 116 and 118 and transmit values ​​IN”2 and IN”3 to neuron 122 of layer 106.

[0069] Those skilled in the art will be able to organize the memory cells of arrays 203 and 203' so that activation of the word lines and bit lines effectively powers the desired memory cells. In fact, for example, to power the cells on the first row and first column and the cells on the second row and second column, word lines WL1 and WL2 and bit lines BL1 and BL2 will be activated. Thus, the cells on the first row and second column and the cells on the second row and first column will also be powered and contribute to the current supplied to the computation circuit 212.

[0070] Figure 5A The diagram illustrates the computational operations performed between layers 102 and 104 of neural network 100. In particular, Figure 5A The operations between layers 102 and 104 are illustrated as being implemented by non-volatile memory 200 .

[0071] A control signal I1 corresponding to the input value IN1 is supplied to a memory cell 500 implementing the neuron 108 (read path (READ PATH) A1) via one of the word lines (e.g., WL1). The control signal I1 is configured, for example, to control the gate of a transistor on one or more word lines. As an example, the control signal I1 is based on a voltage value. In another example, the control signal is a PWM (“pulse width modulation”) type control signal based on a duty cycle. The resistive element of the cell 500 has been programmed upstream to the value of the encoding weight A1. Similarly, signals I2, I3, and I4 are supplied to memory cells 502, 504, and 506 implementing neurons 110 (read path (READ PATH) A2), 112 (read path (READ PATH) A3), and 114 (read path (READ PATH) A4), respectively, via word lines (e.g., word line WL2 and word lines WL3 and WL4 (not shown)). The resistive elements of cells 502, 504, and 506 have been programmed upstream to the values ​​of encoding weights A2, A3, and A4, respectively.

[0072] For example, the outputs of memory cells 500, 502, and 504 are supplied to computation circuit 212_1. Computation circuit 212_1 is then configured to generate input values ​​for memory cells implementing neuron 116 and included in array 203' based on the outputs of cells 500, 502, and 504. The generated value (e.g., encoded signal I'1) is then programmed into resistive element 508 (PROG / ERASE I'1) similar to resistive element 318. Thus, signal I'1 is read and reused as input to word decoder 204.

[0073] Similarly, the outputs of memory cells 502 and 504 and cells 500 and 506 are, for example, supplied to calculation circuits 212_2 and 212_3, respectively. Then, calculation circuits 212_2 and circuits 212_3 are respectively configured to generate input values ​​for memory cells that implement neurons 118 and 120, respectively, and are included in array 203', based on the outputs of cells 502 and 504 and cells 500 and 506, respectively. Then, the generated values ​​(e.g., respectively encoding signals I'2 and I'3) are respectively programmed into resistive elements 510 (PROG / ERASE I'2) and 512 (PROG / ERASE I'3). Therefore, signals I'2 and I'3 are respectively read and reused as inputs to word decoder 204.

[0074] The control circuit 208 is configured, for example, to first control the power supply of the assembly of the read path formed by the cells 500, 502 and 504 and coupled to the calculation circuit 212_1. Once the outputs of the cells 500, 502 and 504 are supplied to the calculation circuit 212_1, the control circuit 208 controls, for example, in parallel, the power supply of the assembly of the path formed by the cells 502 and 504 and coupled to the calculation circuit 212_2 and the power supply of the assembly of the path formed by the cells 514 and 518 and coupled to the calculation circuit 212_3. In practice, the parallel power supply of these two assembly of paths is possible because these two assembly of read paths do not contain common memory cells.

[0075] Figure 5B The diagram illustrates the computational operations performed between layers 104 and 106 of neural network 100. In particular, Figure 5B Operations between layers 104 and 106 are illustrated as being effected by nonvolatile memory 200 , for example, as a result of programming resistive elements 508 , 510 , and 512 .

[0076] Signal I'1 is supplied via one of the bit lines of region 202' to memory cell 514 (READ PATH B1) implementing neuron 116. The resistive element of cell 514 has been programmed upstream to the value of encoding weight B1. Similarly, signals I'2 and I'3 are supplied via word lines of region 202' to memory cells 516 (READ PATH B2) and 518 (READ PATH B3) implementing neurons 118 and 120, respectively. The resistive elements of cells 516 and 518 have been programmed upstream to the values ​​of encoding weights B2 and B3, respectively.

[0077] For example, the outputs of memory cells 514, 516, and 518 are supplied to computation circuit 212_4. Computation circuit 212_4 is then configured to generate input values ​​for memory cells implementing neuron 122 and included in array 203 based on the outputs of cells 514, 516, and 518. The generated value (e.g., corresponding to signal I”1) is then programmed in resistive element 522 (PROG / ERASE I”1), which is similar to resistive element 318. As an example, the programming of the generated value is performed by suppressing the value already stored in element 522. Thus, signal I”1 is read and reused as input to word decoder 204.

[0078] Similarly, the outputs of memory cells 516 and 518 and the outputs of cells 514 and 518 are supplied, for example, to computation circuits 212_5 and 212_6, respectively. Computation circuits 212_5 and circuits 212_6 are then configured to generate input values ​​for memory cells implementing neurons 124 and 126, respectively, and included in array 203, based on the outputs of cells 516 and 518 and the outputs of cells 514 and 518, respectively. The generated values ​​(e.g., encoding signals I”2 and I”3, respectively) are then programmed into resistive elements 524 (PROG / ERASE I”2) and 526 (PROG / ERASE I”3), respectively. Thus, signals I”2 and I”3 are read, respectively, and reused as inputs to word decoder 204.

[0079] The control circuit 208 is configured, for example, to first control the power supply of the assembly of paths formed by the cells 514, 516, and 518 and coupled to the computing circuit 212_4. Then, the control circuit 208 is configured to control the power supply of the assembly of paths formed by the cells 516 and 518 and coupled to the computing circuit 212_5, and then to control the power supply of the assembly of paths formed by the cells 514 and 518 and coupled to the computing circuit 212_6. Each assembly has at least one memory cell in common with one of the other assemblies, and the power supply is performed assembly by assembly.

[0080] Figure 6 is a block diagram illustrating non-volatile memory 600. In particular, volatile memory 600 is similar to non-volatile memory 200, except that array 203 is replaced by or includes sub-arrays 602 (TILE 1), 604 (TILE 2), and 606 (TILE 3). Similarly, array 203' is replaced by or includes sub-arrays 602' (TILE 1), 604' (TILE 2), and 606' (TILE 3). Although Figure 6 Three sub-arrays are illustrated in FIG. 2 , but arrays 203 and 203 ′ may be replaced with or include more or less than three sub-arrays.

[0081] As an example, each subarray includes assembled memory cells of a read path. In another example, each subarray includes assembled memory cells of multiple read paths without common memory cells. Thus, as an example, memory cell 500 is replicated in subarray 602 and subarray 606, for example. In general, each memory cell that appears in an assembly of at least two read paths is replicated in a subarray.

[0082] The implementation of duplication of memory cells common to the sub-arrays and the assembly of multiple read paths allows the output of each assembly of paths to be powered and delivered in parallel to the associated computational circuitry.

[0083] Fig. 7A An example of computational operations performed between layers 102 and 104 of neural network 100 is illustrated. In particular, Fig. 7A The operations between layers 102 and 104 are illustrated as being implemented by non-volatile memory 600 .

[0084] As an example, memory cell 500 is, for example, included in subarray 602 and replicated in cell 500' included in subarray 606. Similarly, cells 502 and 504 included in subarray 602 are replicated in cells 502' and 504' included in subarray 604. Memory cell 506 is included in a single path assembly, which is, for example, not replicated and is implemented only in subarray 606.

[0085] Then, power supply of the assembly of the paths and output transfer to the calculation circuits 212_1 , 212_2 , and 212_3 are performed in parallel.

[0086] Figure 7B An example of the computations performed between layers 104 and 106 of neural network 100 is illustrated. In particular, Figure 7B Operations between layers 104 and 106 are illustrated as being effectuated by nonvolatile memory 600 , for example, as a result of programming resistive elements 508 , 510 , and 512 .

[0087] As an example, memory cell 514 is included in subarray 602' and is copied to cell 514' in subarray 606'. Similarly, cell 516 included in subarray 602' is copied to cell 516' included in subarray 604'. Figure 5B The three paths shown are common to the assembly and are replicated in cell 518' contained in subarray 604' and in cell 518" contained in subarray 606'.

[0088] The power supply of the assembly of the paths and the transfer of the outputs to the calculation circuits 212_4 , 212_5 , and 212_6 are then performed in parallel.

[0089] An advantage of the described embodiments is that all computational operations performed by the neural network are performed within the non-volatile memory. Therefore, there is no latency due to data transfer between the memory and the processor.

[0090] A number of embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0091] Finally, based on the above functional indications, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, the arrangement of the different memory cells, in particular the programming of the resistive elements, is within the capabilities of a person skilled in the art.

Claims

1. A non-volatile memory, comprising: a first memory area comprising a first plurality of storage elements configured to store weight values ​​associated with a first plurality of neurons of the neural network; a second memory region comprising a second plurality of storage elements; a control circuit configured to apply one or more first input values ​​to a plurality of first read paths, each first read path including a storage element among the first plurality of storage elements and configured to generate a read current based on at least one of the one or more first input values; a first calculation circuit configured to add the read currents generated by the first read paths to generate a first output current; as well as The programming circuit is configured to convert the first output current into a first programming current and program a first storage element of the second plurality of storage elements using the first programming current.

2. The non-volatile memory according to claim 1: wherein the control circuit is further configured to apply one or more second input values ​​generated by reading a first storage element of the second plurality of storage elements to a plurality of second read paths, each second read path including a storage element of the second plurality of storage elements and configured to generate a read current; and The nonvolatile memory further includes a second calculation circuit configured to add the read currents generated by the second read paths to generate a second output current; The programming circuit is configured to convert the second output current into a second programming current and use the second programming current to program another storage element of the first memory region.

3. The non-volatile memory according to claim 2: wherein the control circuit is further configured to apply one or more third input values ​​generated by reading the other storage elements of the first memory region to a plurality of third read paths, each third read path comprising a storage element among the first plurality of storage elements and configured to generate a read current; and wherein the first calculation circuit is further configured to add the current generated by the third read path to generate a third output current; and The programming circuit is further configured to convert the third output current into a third programming current, and reprogram the first storage element of the second plurality of storage elements by using the third programming current.

4. The non-volatile memory of claim 3, wherein the storage elements included in the first read path define weights associated with an input layer of the neural network, and wherein the storage elements included in the third read path define weights associated with another layer of the neural network. The non-volatile memory according to claim 4 , wherein the another layer is an output layer.

6. A non-volatile memory according to claim 1, wherein the weight values ​​stored by the first plurality of storage elements define weights of neurons belonging to a verified layer of a neural network, and the weights stored by the second plurality of storage elements define weights of neurons belonging to another verified layer of a neural network.

7. The nonvolatile memory according to claim 6, wherein the one parity is odd parity, and the other parity is even parity.

8. The nonvolatile memory of claim 1 , wherein each of the first plurality of storage elements and the second plurality of storage elements belongs to a memory cell, each memory cell being coupled to a control circuit via a word line and a bit line, the control circuit being configured to activate or deactivate the word line and the bit line. 9 . The nonvolatile memory according to claim 1 , wherein the first calculation circuit is configured to generate the first output value based on a current supplied by a memory cell included in a read path among the first read paths. 10 . The nonvolatile memory of claim 1 , wherein the first calculation circuit is further configured to apply a compensation effect based on current supplied by a memory cell included in a read path among the first read paths. 11 . The nonvolatile memory of claim 1 , wherein the first calculation circuit is further configured to apply a threshold effect based on a current supplied by a memory cell included in a read path among the first read paths. 12 . The nonvolatile memory of claim 1 , wherein the first calculation circuit is further configured to apply an offset effect based on a current supplied by a memory cell included in a read path among the first read paths. 13 . The nonvolatile memory of claim 1 , wherein the first calculation circuit is further configured to apply a scaling effect based on current supplied by a memory cell included in a read path among the first read paths.

14. The nonvolatile memory according to claim 1, wherein the storage element and the other storage elements are programmable resistive elements.

15. The nonvolatile memory according to claim 1 further includes a third calculation circuit, which is configured to generate another output value based on a read current supplied by one or more memory cells included in a read path among the first read paths and the one or more first input values. 16 . The nonvolatile memory of claim 15 , wherein the first calculation circuit and the third calculation circuit are configured to generate output values ​​based on one or more cells common in the plurality of first read paths, the common cells being replicated in at least two portions in the first region.

17. The nonvolatile memory of claim 1, wherein the one or more first input values ​​are applied to the first read path simultaneously.

18. A method comprising: applying one or more first input values ​​to a plurality of first read paths, each first read path comprising one of a first plurality of storage elements of a first region of a non-volatile memory, the first plurality of storage elements being configured to store weight values ​​associated with a first plurality of neurons of a neural network; summing the currents supplied by the first read paths to generate a first output current; converting the first output current into a first programming current; as well as A first storage element of a second plurality of storage elements of a second region of nonvolatile memory is programmed using the first programming current.

19. The method according to claim 18, further comprising: applying one or more second input values ​​generated by reading a first storage element of the second plurality of storage elements to a plurality of second read paths, each second read path including one of the storage elements of the second plurality of storage elements; summing the currents supplied by the second read paths to generate a second output current; converting the second output current into a second programming current; as well as Another storage element of the first region of the nonvolatile memory is programmed by using the second programming current.

20. The method of claim 18, wherein applying comprises applying the one or more first input values ​​to the first read path simultaneously.

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