NAND configuration and state anomaly detection and reset method, device and equipment

Abstract

The invention provides an NAND configuration and state anomaly detection and reset method, device and equipment, and relates to the technical field of computer storage, and the method comprises the following steps: carrying out anomaly detection on NAND configuration and state, and obtaining a target Die meeting a pre-judgment condition of an NAND configuration error or a state machine anomaly; performing recovery and reset operation on the obtained target Die; if the NAND is still not recovered to be normal after the obtained target Die is subjected to recovery and reset operation, it is determined that the Die is permanently invalid, and a Die failure processing flow is started, and otherwise, the Die failure processing flow does not need to be started. According to the method, NAND configuration errors or state machine abnormalities are detected, the cause of the abnormalities is identified to determine whether the Die is permanently invalid or not, the function and use of the non-permanently invalid Die can be recovered through operations such as resetting, and the service life of the SSD is prolonged.

Description

Technical Field

[0001] The present application relates to the field of computer storage technology, and in particular to a method, device and equipment for detecting and resetting abnormal NAND configuration and status. Background Art

[0002] Due to the device characteristics of NAND (flash memory), the data transmission quality varies greatly under different application conditions. Typically, the normal operating temperature range of NAND is 0-70 degrees, and the normal operating voltage of NAND is usually between 2.35 volts and 3.6 volts. It is necessary to ensure that NAND works within this temperature and voltage range. During operation, NAND will inevitably encounter extreme environments such as overheating and unstable power supply voltage, which are prone to high bit error probability and even state machine disorder of some Die (memory particles). During operation, there are not only basic operations of data reading, writing and erasing, but also operations such as ARC (Adaptive Replacement Cache) and SBSBR (Single Bit Soft BitRead, an operation to retrieve Soft Information or Soft Data from NAND media) that involve data recovery, which will change the NAND configuration. In general, SSD (solid state drive) only considers the recovery of user data errors, but ignores the problems of NAND configuration change errors and state machine disorder during operation in extreme environments.

[0003] When a certain die or some dies of a flash memory particle have configuration errors or state machine disorder problems, it may generally cause a large number of erase, program and read failures, so that the die will be treated as a permanently failed die. When the die fails, the entire memory bar will not work properly, causing the computer to be unable to read or write data. This not only directly affects the user's data reading and writing experience, but may also cause data loss or damage. Therefore, it is necessary to provide a solution that can realize timely and accurate detection and reset of NAND configuration errors and state machine disorder. Summary of the invention

[0004] The purpose of this application is to provide a method, device and equipment for detecting and resetting NAND configuration and state anomalies, so as to avoid the problem of directly judging a die as a failed die when an anomaly or error is detected, thereby wasting the service life of the SSD. By detecting NAND configuration errors or state machine anomalies, identifying the cause of the anomaly to determine whether the die is permanently failed, and restoring the function and use of non-permanently failed dies through operations such as reset, the service life of the SSD can be extended.

[0005] To achieve the above-mentioned purpose, as the first aspect of the present application, the present application provides a NAND configuration and state abnormality detection and reset method, the method comprising: performing abnormality detection on the NAND configuration and state, obtaining a target Die that meets the predicted conditions of the NAND configuration error or state machine abnormality; performing recovery and reset operations on the obtained target Die; if the NAND still does not return to normal after the recovery and reset operations on the obtained target Die, it is determined that the Die is permanently failed and the Die failure processing flow is started, otherwise, there is no need to start the Die failure processing flow.

[0006] The NAND configuration and state abnormality detection and reset method as described above, wherein the abnormality detection of the NAND configuration and state includes: real-time detection of parameter value abnormality of known characteristic addresses, real-time detection of characteristic address parameter configuration operation abnormality, real-time detection of storage unit operation abnormality, real-time detection of state machine abnormality, real-time detection of SLC and TLC mode switching abnormality, and real-time detection of at least one of the abnormality of pause and resume switching of erasing and programming.

[0007] As described above, the NAND configuration and state abnormality detection and reset method, wherein the recovery and reset operations on the acquired target Die include: reconfiguring correct parameters on the target Die, performing a lightweight reset on the target Die, and performing a heavyweight reset on the target Die.

[0008] The NAND configuration and state abnormality detection and reset method as described above, wherein the real-time detection of the abnormality of the parameter value of the known characteristic address includes: reading the parameter value of the known characteristic address in real time; verifying the read parameter value of the known characteristic address according to the parameter value of the known characteristic address recorded in the storage unit to determine whether there is an abnormality.

[0009] The NAND configuration and state abnormality detection and reset method as described above, wherein the real-time detection of characteristic address parameter configuration operation abnormality includes: selecting a known characteristic address and setting it to other parameter values; reading the parameter value of the characteristic address and setting the characteristic address to the original parameter value; if the read parameter value is different from the other parameter value set to it, it means that the characteristic address parameter configuration operation is abnormal, otherwise, it means that the characteristic address parameter configuration is normal.

[0010] The NAND configuration and status abnormality detection and reset method as described above, wherein real-time detection of storage unit operation abnormality includes: selecting an address different from the target Die read address as a special read operation address; executing a first read operation: reading data in a register according to the special read operation address; issuing a read storage unit command, and setting an execution time threshold range for the read operation; reading the status data of the target Die; in response to the read storage unit command, executing a second read operation: reading data from the register; determining whether the execution time of the second read operation is within the set execution time threshold range, if so, the storage unit operation is normal, otherwise, the storage unit operation is abnormal; determining whether the data read by the second read operation is the same as that read by the first read operation, if so, the storage unit operation is normal, otherwise, the storage unit operation is abnormal.

[0011] The NAND configuration and state abnormality detection and reset method as described above, wherein the real-time detection of state machine abnormality includes: when the target Die fails to erase and program continuously, the actual results of erasure and programming are detected through a read operation; if the data read out by the read operation is the correct data after the erase and programming operations, the state machine is abnormal, otherwise the state machine is normal.

[0012] As described above, the NAND configuration and status abnormality detection and reset method, wherein the SLC and TLC mode switching abnormality real-time detection includes: in the SLC mode, executing the storage unit operation abnormality real-time detection method, if the read operation execution time exceeds the set execution time threshold range or there is an error in the read data, the SLC and TLC mode switching is abnormal.

[0013] The NAND configuration and status abnormality detection and reset method as described above, wherein the real-time detection of the pause and resume switching abnormalities of erasing and programming includes: first, recording the busy time after the pause command is issued, and judging whether the busy time exceeds the preset maximum busy time threshold. If so, the pause mode is abnormal, otherwise, the pause mode is normal; second, reading the target Die status after issuing the resume command. If the target Die does not enter the busy state, the recovery mode is abnormal, otherwise, the recovery mode is normal.

[0014] As a second aspect of the present application, the present application provides a NAND configuration and state abnormality detection and reset device, including: an abnormality detection module, used to perform abnormality detection on the NAND configuration and state, and obtain a Die that meets the predicted conditions of the NAND configuration error or state machine abnormality; a recovery and reset module, used to perform recovery and reset operations on the obtained Die; a recognition module, used to determine that the Die is permanently failed and start the Die failure processing process if the NAND has not returned to normal after the obtained Die is restored and reset, otherwise, there is no need to start the Die failure processing process.

[0015] As a third aspect of the present application, the present application provides a device, which includes: a processor and a memory, wherein the memory includes an intelligent control program, and when the intelligent control program is executed by the processor, the NAND configuration and state abnormality detection and reset method as described above is implemented.

[0016] The beneficial effects achieved by this application are as follows:

[0017] (1) The present application realizes real-time and accurate detection of NAND configuration errors and state machine disorder anomalies. By detecting NAND configuration errors or state machine anomalies, the cause of the anomaly is accurately identified, and then it is determined whether the Die is a permanent failure, thereby improving the accuracy of the Die permanent failure judgment.

[0018] (2) When the present application detects abnormal NAND configuration and status, it does not directly determine the Die as permanently failed. Instead, it first performs recovery and reset operations on the Die. If the NAND still does not return to normal after the Die recovery and reset operations, the Die is determined to be permanently failed, thereby improving the accuracy of NAND abnormality judgment.

[0019] (3) This application can restore the function and use of non-permanently failed Dies through operations such as resetting, thereby extending the service life of the SSD. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For those skilled in the art, other drawings can also be obtained based on these drawings.

[0021] Figure 1 This is a flow chart of a NAND configuration and state abnormality detection and reset method according to an embodiment of the present application.

[0022] Figure 2 This is a flow chart of a method for real-time detection of abnormal parameter values ​​of a known characteristic address according to an embodiment of the present application.

[0023] Figure 3 This is a flow chart of a method for real-time detection of characteristic address parameter configuration operation anomalies according to an embodiment of the present application.

[0024] Figure 4 This is a flow chart of a method for real-time detection of abnormal storage unit operation according to an embodiment of the present application.

[0025] Figure 5 This is a flow chart of a method for real-time detection of state machine anomalies according to an embodiment of the present application.

[0026] Figure 6This is a flow chart of a method for real-time detection of SLC and TLC mode switching anomalies according to an embodiment of the present application.

[0027] Figure 7 This is a flow chart of a method for real-time detection of abnormalities in pause and resume switching of erase and programming according to an embodiment of the present application.

[0028] Figure 8 A schematic diagram of a NAND configuration and state abnormality detection and reset method according to an embodiment of the present application.

[0029] Fig. 9 A schematic diagram of the structure of a NAND configuration and state abnormality detection and reset device according to an embodiment of the present application.

[0030] Fig.10 A schematic diagram of the structure of a device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] As a specific embodiment of the present invention, the range of abnormalities caused by NAND configuration errors and state machine disorders includes: abnormal parameter values ​​of known characteristic addresses (including: abnormal parameter values ​​of known characteristic addresses that will be dynamically modified in the running state, and abnormal parameter values ​​of known characteristic addresses that will no longer be modified after power-on initialization), abnormal parameter values ​​of unknown characteristic addresses, abnormal characteristic address parameter configuration operations, abnormal storage unit operations (including: erase exceptions, programming exceptions and read exceptions), state machine exceptions (including: erase and programming are successful but report failure), mode switching exceptions (SLC and TLC mode switching exceptions), and pause and resume switching exceptions of erase and programming, etc.

[0033] As a specific embodiment of the present invention, the operations for real-time detection of NAND configuration errors and state machine disorders include: characteristic address parameter value setting operation, characteristic address parameter value reading operation, read operation, program operation, and erase operation.

[0034] Embodiment 1

[0035] like Figure 1 As shown, the present application provides a NAND configuration and state abnormality detection and reset method, the method comprising the following steps:

[0036] Step S1, perform abnormality detection on NAND configuration and state, and obtain a target Die that meets the pre-judgment conditions of NAND configuration error or state machine abnormality.

[0037] As a specific embodiment of the present invention, abnormality detection of NAND configuration and status includes: real-time detection of parameter value abnormalities of known characteristic addresses, real-time detection of characteristic address parameter configuration operation abnormalities, real-time detection of storage unit operation abnormalities, real-time detection of state machine abnormalities, real-time detection of SLC and TLC mode switching abnormalities, and at least one of real-time detection of pause and resume switching abnormalities of erasing and programming.

[0038] As a specific embodiment of the present invention, during the real-time detection of abnormal parameter values ​​of known characteristic addresses, only the parameter value reading operation of the characteristic address is used. In addition, at least one storage unit is provided in the SSD for recording the parameter value of the known characteristic address. The parameter value of the known characteristic address (block erase count, bad block mark, wear leveling index, etc.) that will be dynamically modified by the NAND in the running state also needs to be updated and recorded in the storage unit in a timely manner, so as to be used for real-time detection of abnormal parameter values ​​of known characteristic addresses.

[0039] like Figure 2 As shown, real-time detection of abnormal parameter values ​​of known characteristic addresses includes the following steps:

[0040] Step S110, reading the parameter value of the known characteristic address in real time.

[0041] Step S120 , verifying the parameter value of the known characteristic address read according to the parameter value of the known characteristic address recorded in the storage unit to determine whether there is an abnormality.

[0042] Specifically, if the parameter value of the known characteristic address read is the same as the parameter value of the known characteristic address recorded in the storage unit, then there is no abnormality; otherwise, there is an abnormality.

[0043] It should be explained that if the parameter value of a known characteristic address that is dynamically modified during operation is abnormal, the parameter value of this characteristic address needs to be reset correctly so that the parameter value of the known characteristic address is restored to normal. If the parameter value of a known characteristic address that is no longer modified after power-on initialization is abnormal, then there may be an abnormal parameter value of an unknown characteristic address.

[0044] As a specific embodiment of the present invention, during the real-time detection of abnormalities in characteristic address parameter configuration operations, a characteristic address parameter value setting operation and a characteristic address parameter value reading operation are used.

[0045] like Figure 3 As shown in the figure, the real-time detection of abnormal operation of characteristic address parameter configuration includes the following steps:

[0046] Step S210, selecting a known characteristic address and setting it to other parameter values.

[0047] Specifically, known characteristic addresses refer to some specific, predetermined addresses in NAND flash memory, and the storage units corresponding to these addresses have specific functions or store specific parameter values ​​related to the characteristics of NAND flash memory. Examples of known characteristic addresses include bad block marking addresses and wear leveling related addresses.

[0048] Step S220, read the parameter value of the characteristic address, and set the characteristic address to the original parameter value; if the read parameter value is different from the other parameter value it is set to, it means that the characteristic address parameter configuration operation is abnormal, otherwise, it means that the characteristic address parameter configuration is normal.

[0049] It should be explained that the real-time detection of abnormal operation of characteristic address parameter configuration is not allowed to be interrupted by other operations of target Die, otherwise it will affect the correctness of other operations of target Die. If the parameter value read is different from the parameter value set before, it means that the characteristic address parameter configuration operation is abnormal, otherwise, it means that the characteristic address parameter configuration operation is normal.

[0050] As a specific embodiment of the present invention, the real-time detection process of abnormal storage unit operation includes read operation, programming operation and erase operation. Among them, the execution time of programming operation and erase operation is relatively long, which is not suitable for real-time detection and will affect performance. In addition, considering the improvement of bus utilization and performance, the read operation will reduce the reading of the status register as much as possible, and other dies will be cut in the middle for operation, so the ordinary read operation cannot be used as a detection means. Therefore, the real-time detection of abnormal storage unit operation adopts a special read operation.

[0051] like Figure 4 As shown, the real-time detection of storage unit operation abnormality includes the following steps:

[0052] Step S310, selecting an address different from the target Die read address as a special read operation address.

[0053] Specifically, a special read operation is adopted, and an address different from the target Die read address is selected as the special read operation address.

[0054] Step S320, executing a first read operation: reading data in the register according to a special read operation address.

[0055] The data in the cache register where the target address is located is read out according to the special read operation address, and then a read storage unit command is issued.

[0056] Step S330, issuing a storage unit read command and setting an execution time threshold range for the read operation.

[0057] Specifically, setting the execution time threshold range of the read operation includes: setting a minimum threshold and a maximum threshold of the execution time of the read operation.

[0058] Step S340, reading the status data of the target Die.

[0059] Specifically, after the storage unit read command is issued, the target Die status data is read including: immediately reading the busy and ready status of the target Die, and before the ready status is obtained, the busy and ready status of the target Die need to be read as frequently and as small an interval as possible until the ready status is obtained.

[0060] Step S350 , in response to the memory cell read command, executing a second read operation: reading data from the register.

[0061] It should be explained that reading data from the register means taking data from the cache register. This operation must be continuous and cannot be interrupted by other operations of the current Die and other Dies, so as to ensure that the data in the cache register will not be flushed and the execution time of the read operation is accurately obtained.

[0062] Step S360, determining whether the execution time of the second read operation is within a set execution time threshold range, if so, the storage unit operates normally, otherwise, the storage unit operates abnormally.

[0063] Step S370, determining whether the data read by the second read operation is the same as the data read by the first read operation, if so, the storage unit operates normally, otherwise, the storage unit operates abnormally.

[0064] like Figure 5 As shown, the real-time detection of state machine anomalies includes the following steps:

[0065] Step S410: When the target Die fails to be erased and programmed continuously, the actual results of the erase and programming are detected through a read operation.

[0066] Step S420, determining whether the data read out by the read operation is the correct data after the erasing and programming operations. If the data read out by the read operation is the correct data after the erasing and programming operations, the state machine is abnormal, otherwise the state machine is normal.

[0067] It should be explained that since the execution time of programming and erasing operations is relatively long, for the detection of state machine abnormalities (erasing and programming are successful but reporting failure), specific erasing and programming operations cannot be designed for real-time detection, which will affect performance.

[0068] like Figure 6As shown, the real-time detection of abnormal switching between SLC and TLC modes includes the following steps:

[0069] Step S510: In the SLC mode, a real-time detection method for abnormal storage unit operation is executed.

[0070] Step S520: If the execution time of the read operation exceeds the set execution time threshold range or there is an error in the read data, the switching between the SLC and TLC modes is abnormal.

[0071] What needs to be explained is that the special read operation that also uses real-time detection of storage unit operation anomalies is just performed in SLC mode. The execution time of the SLC read operation is different from that of the TLC read operation, and the minimum and maximum thresholds for setting the execution time of the read operation are also different. If anomalies occur in the execution time and data, it means that the switching between the SLC and TLC modes is abnormal.

[0072] It should be explained that the read operation in SLC mode has a relatively short and stable execution time. The read operation in TLC mode requires more complex processing, takes a long time to execute and has a large fluctuation range.

[0073] It should be explained that for read operations in SLC mode, the minimum threshold T_{SLCmin} and the maximum threshold T_{SLCmax} are set according to the normal read operation execution time distribution to ensure that the normal SLC read operation execution time is within this range. When performing a read operation, if the current mode is SLC, the read operation execution time should be between T_{SLCmin} and T_{SLCmax}. If it exceeds this range, or the read operation is within the time range but the read data has errors, incompleteness and other abnormal conditions, it may be caused by abnormal mode switching.

[0074] It should be explained that for the read operation in TLC mode, the corresponding minimum threshold T_{TLCmin} and maximum threshold T_{TLCmax} are also set according to its characteristics, and T_{TLCmin}>T_{SLCmax}. In the read operation in TLC mode, the read operation execution time should be between T_{TLCmin} and T_{TLCmax}, otherwise the mode switching abnormality may also occur.

[0075] like Figure 7 As shown, the real-time detection of the abnormality of the pause and resume switching of erase and program includes the following steps:

[0076] Step S610, recording the busy time after the pause command is issued, and determining whether the busy time exceeds a preset maximum busy time threshold. If so, the pause mode is abnormal, otherwise, the pause mode is normal.

[0077] Step S620, after issuing the recovery command, read the target Die status, if the target Die is not in a busy state, the recovery mode is abnormal, otherwise, the recovery mode is normal.

[0078] It should be explained that, since the execution time of programming and erasing operations is relatively long, for the detection of abnormalities in the pause and resume switching of erasing and programming, specific erasing and programming operations cannot be designed for real-time detection, which will affect performance.

[0079] First, it is necessary to record the busy time after the pause command is issued and set a maximum threshold of the busy time after the pause command is issued. If the busy time exceeds the maximum threshold, it means that entering the pause mode is abnormal.

[0080] Second, read the status immediately after issuing the recovery command. If the target Die does not enter the busy state after issuing the recovery command, it means that the recovery mode is abnormal.

[0081] Step S2, recovering and resetting the acquired target Die.

[0082] It should be explained that for Die that meets the pre-judgment conditions of configuration error or state machine disorder, recovery and reset operations are required.

[0083] Specifically, the recovery and reset operations on the acquired target Die include: reconfiguring correct parameters on the target Die, performing a lightweight reset on the target Die, and performing a heavyweight reset on the target Die.

[0084] What needs to be explained is that the correct parameters are reconfigured for the target Die: the operation execution time is the shortest and the performance is not affected.

[0085] It needs to be explained that a lightweight reset operation is performed on the target Die: the execution time is longer, all operations being executed are canceled, the command register is cleared, and preparation is made for the next command. The target Die configuration will not be changed, and the performance impact is small.

[0086] It needs to be explained that the heavyweight reset operation is performed on the target Die: the execution time is long. In addition to the function of the lightweight reset operation, there will also be an initialization similar to the first reset command executed when the device is powered on, which initializes the parameters and configurations of all Dies to the default values. After the heavyweight reset, the configuration of the target Die must be reinitialized, and ZQ calibration and DCC training must be performed, which has a greater impact on performance. ZQ calibration: used for the calibration of memory modules to ensure the signal transmission stability and reliability of memory modules under different working conditions. DCC training is a dynamic clock control technology suitable for DDR memory. It optimizes the signal transmission quality by dynamically adjusting the clock signal, reduces interference and reflections, and ensures stable system operation.

[0087] Considering the impact on performance, corresponding recovery and reset operations need to be performed first for different exceptions. However, considering that different exceptions also affect each other, for example, the abnormal parameter value of the unknown characteristic address is difficult to detect, but it may cause other exceptions. Therefore, after executing the corresponding recovery and reset operations, NAND configuration and status abnormalities will still occur. In this case, it is necessary to follow the recovery and reset sequence (the recovery and reset sequence is: reconfigure the correct parameters, lightweight reset operation, heavyweight reset operation) until the NAND configuration and status abnormalities disappear.

[0088] Among them, for known characteristic address parameter value abnormalities that will be dynamically modified during operation, it is necessary to reconfigure the correct parameters accordingly. For known characteristic address parameter value abnormalities that are no longer modified after power-on initialization, there is a high probability that the parameter value of the unknown characteristic address will also be abnormal, and a heavyweight reset operation needs to be performed directly. For other NAND configuration and status abnormalities, a lightweight reset operation needs to be performed first.

[0089] Step S3: If the NAND still does not return to normal after the recovery and reset operations are performed on the acquired target Die, the Die is deemed to be permanently invalid and the Die invalidation processing flow is started; otherwise, there is no need to start the Die invalidation processing flow.

[0090] Specifically, if the above anomaly still does not return to normal after the final heavyweight reset, the current Die is considered to be permanently failed, and the failed Die processing flow is started to avoid data loss on the failed Die.

[0091] This application detects abnormal NAND configuration and status, but does not directly determine the Die as permanently failed. Instead, it first recovers and resets the Die. If the NAND still does not return to normal after the Die recovery and reset operations, the Die is determined to be permanently failed, thereby improving the accuracy of NAND judgment.

[0092] Embodiment 2

[0093] like Figure 8 As shown, the present application provides a NAND configuration and state abnormality detection and reset method, the method comprising the following steps:

[0094] Step T1, perform abnormality detection on NAND configuration and status to determine whether there is an abnormality. If so, execute step T2, if not, end the process.

[0095] Step T2, reconfigure the correct parameters for the target Die.

[0096] Step T3, continue to perform abnormal detection on the NAND configuration and status to determine whether there is an abnormality. If so, execute step T4, if not, end the process.

[0097] Step T4, performing a lightweight reset on the target Die.

[0098] Step T5, continue to perform abnormal detection on the NAND configuration and status to determine whether there is an abnormality. If so, execute step T6, if not, end the process.

[0099] Step T6, perform a heavyweight reset on the target Die.

[0100] Step T7, initialize NAND configuration.

[0101] Step T8, ensuring the signal output quality by adjusting the terminal resistance.

[0102] Step T9, DCC training (RE-t and RE-C signals recalibration).

[0103] Step T10, end the process.

[0104] Embodiment 3

[0105] like Figure 7 As shown, the present application provides a NAND configuration and state abnormality detection and reset device 100, comprising:

[0106] The abnormality detection module 101 is used to detect abnormalities in NAND configuration and state, and obtain Die that meets the pre-judgment conditions of NAND configuration error or state machine abnormality;

[0107] A recovery and reset module 102, used for recovering and resetting the acquired Die;

[0108] The identification module 103 is used to identify the Die as permanently invalid and start the Die invalidation processing flow if the NAND still does not return to normal after the recovery and reset operations are performed on the acquired Die. Otherwise, there is no need to start the Die invalidation processing flow.

[0109] Embodiment 4

[0110] like Fig.10 As shown, the present application provides a device 200, which includes: a processor 201 and a memory 202, wherein the memory 202 includes an intelligent control program, and when the intelligent control program is executed by the processor 201, the NAND configuration and state abnormality detection and reset method as described above is implemented.

[0111] The present application also provides a computer storage medium, wherein the computer storage medium stores computer instructions, and when the computer instructions are called, they are used to execute the address mapping method of the large-capacity solid-state hard disk. The computer storage medium contains one or more program instructions, and the one or more program instructions are used by the processor to execute a NAND configuration and state abnormality detection and reset method.

[0112] The embodiments disclosed in the present invention provide a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are executed on a computer, the computer executes the above-mentioned NAND configuration and state abnormality detection and reset method.

[0113] An embodiment of the present invention provides a processor for processing the above-mentioned NAND configuration and state abnormality detection and reset method.

[0114] In the embodiment of the present invention, the processor may be an integrated circuit chip having the ability to process signals. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0115] The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The processor reads the information in the storage medium and completes the steps of the above method in combination with its hardware.

[0116] The storage medium may be a memory, which may be, for example, a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.

[0117] Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct RAM bus random access memory (DRRAM).

[0118] The beneficial effects achieved by this application are as follows:

[0119] (1) The present application realizes real-time and accurate abnormal detection of NAND configuration errors and state machine disorders. By detecting NAND configuration errors or state machine abnormalities, the cause of the abnormality is identified, and then it is determined whether the Die is a permanent failure, thereby improving the accuracy of the Die permanent failure judgment.

[0120] (2) When the present application detects abnormal NAND configuration and status, it does not directly determine the Die as permanently failed. Instead, it first performs recovery and reset operations on the Die. If the NAND still does not return to normal after the Die recovery and reset operations, the Die is determined to be permanently failed, thereby improving the accuracy of NAND abnormality judgment.

[0121] (3) This application can restore the function and use of non-permanently failed Dies through operations such as resetting, thereby extending the service life of the SSD.

[0122] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0123] In the description of the present application, the word "for example" is used to mean "used as an example, illustration or explanation". Any embodiment described as "for example" in the present application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is given to enable any technician in the field to implement and use the present invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present invention can be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present application.

[0124] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A NAND configuration and state abnormality detection and reset method, characterized in that: The method includes: Perform abnormality detection on NAND configuration and status to obtain target Die that meets the prediction conditions of NAND configuration error or state machine abnormality; Restore and reset the acquired target Die; If the NAND still does not return to normal after the acquired target Die is restored and reset, the Die is deemed to be permanently failed and the Die failure processing flow is started. Otherwise, there is no need to start the Die failure processing flow.

2. The NAND configuration and state abnormality detection and reset method according to claim 1, characterized in that: Anomaly detection of NAND configuration and status includes: Real-time detection of parameter value anomalies of known characteristic addresses, real-time detection of characteristic address parameter configuration operation anomalies, real-time detection of storage unit operation anomalies, real-time detection of state machine anomalies, real-time detection of SLC and TLC mode switching anomalies, and real-time detection of at least one of suspend and resume switching anomalies of erase and program.

3. The NAND configuration and state abnormality detection and reset method according to claim 2, characterized in that: The recovery and reset operations on the acquired target Die include: reconfiguring correct parameters on the target Die, performing a lightweight reset on the target Die, and performing a heavyweight reset on the target Die.

4. The NAND configuration and state abnormality detection and reset method according to claim 2, characterized in that: Real-time detection of abnormal parameter values ​​of known feature addresses includes: Read the parameter values ​​of known characteristic addresses in real time; According to the parameter value of the known characteristic address recorded in the storage unit, the parameter value of the known characteristic address read is verified to determine whether there is an abnormality.

5. The NAND configuration and state abnormality detection and reset method according to claim 2, characterized in that: Real-time detection of abnormalities in feature address parameter configuration operations includes: Select a known characteristic address and set it to other parameter values; Read the parameter value of the characteristic address and set the characteristic address to the original parameter value; If the parameter value read is different from the other parameter values ​​set, it means that the characteristic address parameter configuration operation is abnormal, otherwise, it means that the characteristic address parameter configuration is normal.

6. The NAND configuration and state abnormality detection and reset method according to claim 2, characterized in that: Real-time detection of storage unit operation anomalies includes: Select an address different from the target Die read address as the special read operation address; Execute the first read operation: read the data in the register according to the special read operation address; Sending a storage unit read command and setting a time threshold range for the read operation; Read the status data of the target Die; In response to a read memory cell command, a second read operation is performed: reading data from a register; Determine whether the execution time of the second read operation is within a set execution time threshold range, if so, the storage unit operates normally, otherwise, the storage unit operates abnormally; It is determined whether the data read by the second read operation is the same as the data read by the first read operation. If so, the storage unit operates normally; otherwise, the storage unit operates abnormally.

7. The NAND configuration and state abnormality detection and reset method according to claim 5, characterized in that: Real-time detection of abnormal SLC and TLC mode switching includes: In the SLC mode, a real-time detection method for abnormal storage unit operation is executed. If the execution time of the read operation exceeds the set execution time threshold range or there is an error in the read data, the switching between the SLC and TLC modes is abnormal.

8. The NAND configuration and state abnormality detection and reset method according to claim 2, characterized in that: Real-time detection of erase and program suspend and resume switching anomalies includes: First, record the busy time after the pause command is issued, and determine whether the busy time exceeds the preset maximum busy time threshold. If so, the pause mode is abnormal, otherwise, the pause mode is normal; Second, after issuing the recovery command, read the target Die status. If the target Die is not busy, the recovery mode is abnormal. Otherwise, the recovery mode is normal.

9. A NAND configuration and state abnormality detection and reset device, characterized in that: include: The anomaly detection module is used to detect anomalies in NAND configuration and state, and obtain Dies that meet the pre-judgment conditions of NAND configuration error or state machine anomaly; The recovery and reset module is used to recover and reset the acquired Die; The identification module is used to identify the Die as permanently invalid and start the Die invalidation processing flow if the NAND still does not return to normal after the obtained Die is restored and reset. Otherwise, there is no need to start the Die invalidation processing flow.

10. A device, characterized in that: The device includes: a processor and a memory, The memory includes an intelligent control program, and when the intelligent control program is executed by the processor, the NAND configuration and state abnormality detection and reset method according to any one of claims 1 to 8 is implemented.

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