Capacitor, manufacturing method thereof, chip and electronic equipment

Abstract

The invention relates to the technical field of capacitors, provides a capacitor and a manufacturing method thereof, a chip and electronic equipment, and can solve the problem of low capacitance density of a capacitor in the related technology. The capacitor comprises a plurality of sub-capacitors which are arranged in a stacked mode. Each of the plurality of sub-capacitors comprises a bearing layer and a capacitor unit embedded on the bearing layer, and the capacitor unit is provided with an electrode; in the plurality of sub-capacitors, at least one of two adjacent sub-capacitors is provided with a conductive hole, and the electrodes of the two adjacent sub-capacitors are electrically connected through the conductive hole, so that the capacitor units of the two adjacent sub-capacitors are connected in parallel. The method can be applied to electronic equipment such as a mobile phone and a notebook computer.

Description

Technical Field

[0001] The present application relates to the technical field of capacitors, and in particular to a capacitor and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Capacitors are important electronic components that store charge, make voltage change smoothly, block direct current and pass alternating current, bypass high-frequency noise, etc. As modern electronic devices continue to develop towards multi-function, high integration, low power consumption, and miniaturization, the requirements for the capacitance density of capacitors are getting higher and higher. How to improve the capacitance density of capacitors has become one of the important topics in the industry.

[0003] A capacitor in the related art includes a substrate layer, a groove arranged on the substrate layer, and a capacitor unit partially located in the groove. Compared with a chip-type multilayer ceramic capacitor, the capacitor has lower parasitic inductance and thinner thickness, but lower capacitance density, so that under the same capacitance value, the occupied area of ​​the capacitor is larger, which is not conducive to the optimized layout of other devices around the capacitor. Summary of the invention

[0004] The embodiments of the present application provide a capacitor and a manufacturing method thereof, a chip, and an electronic device, which are used to solve the problem of low capacitance density of capacitors in related technologies.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In the first aspect, an embodiment of the present application provides a capacitor, comprising a plurality of sub-capacitors arranged in a stacked manner; each of the plurality of sub-capacitors comprises a carrying layer and a capacitor unit embedded in the carrying layer, and the capacitor unit has electrodes; among the plurality of sub-capacitors, at least one of two adjacent sub-capacitors is provided with a conductive hole, and the conductive hole electrically connects the electrodes of the two adjacent sub-capacitors so that the capacitor units of the two adjacent sub-capacitors are connected in parallel.

[0007] The capacitor in the embodiment of the present application has a conductive hole on at least one of the two adjacent sub-capacitors, and the conductive hole electrically connects the electrodes of the two adjacent sub-capacitors so that the capacitance units of the two adjacent sub-capacitors are connected in parallel, so that the equivalent capacitance of the capacitor is equal to the sum of the capacitance values ​​of the capacitance units in the multiple sub-capacitors, thereby increasing the capacitance value of the capacitor. In addition, since the multiple sub-capacitors of the capacitor are stacked, the capacitor increases the capacitance value while reducing the occupied area of ​​the capacitor, thereby increasing the capacitance density of the capacitor. With the increase in capacitance density, the capacitor occupies a smaller area when achieving the same capacitance value, which is conducive to the optimized layout of other devices around the capacitor.

[0008] In some embodiments, in the two adjacent sub-capacitors, for any one of the conductive holes, the conductive hole penetrates the carrier layer of one of the sub-capacitors, and the first end of the conductive hole is electrically connected to the electrode of one of the sub-capacitors, and the second end of the conductive hole is electrically connected to the electrode of the other sub-capacitor through an interconnection structure. In this way, the interconnection structure can electrically connect the conductive holes at different positions to the electrodes of the other sub-capacitor, thereby facilitating the arrangement of the conductive holes.

[0009] In some embodiments, the interconnection structure includes a bump, a first pad, and a second pad, wherein the first pad is disposed on one of the sub-capacitors and electrically connected to the second end of the conductive hole, the second pad is disposed on the other sub-capacitor and electrically connected to the electrode of the other sub-capacitor, and the bump is disposed between the first pad and the second pad. This arrangement reduces the difficulty of designing and manufacturing the interconnection structure, thereby helping to reduce the design and manufacturing costs of the capacitor.

[0010] In some embodiments, the interconnection structure is a hybrid bonding structure and includes a plurality of third pads and a plurality of fourth pads, each of the third pads is disposed on one of the sub-capacitors and electrically connected to the second end of the conductive hole; each of the fourth pads is disposed on the other sub-capacitor and electrically connected to the electrode of the other sub-capacitor, and each of the third pads is in contact with the corresponding fourth pad. Such a configuration can achieve a shorter interconnection distance and a higher interconnection density.

[0011] In some embodiments, one of the sub-capacitors further includes a first redistribution layer, the first redistribution layer covers the second end of the conductive via; the first redistribution layer includes a first insulating layer, and a first conductive layer and a first via embedded in the first insulating layer, the first via is connected between the first conductive layer and the second end of the conductive via, and a portion of the interconnection structure is disposed on the first insulating layer and electrically connected to the first conductive layer. This arrangement can facilitate the arrangement of the interconnection structure.

[0012] In some embodiments, the first redistribution layer further includes a fifth pad, the fifth pad is embedded in the first insulating layer, the fifth pad is disposed at the second end of the conductive hole, and the first via is connected between the fifth pad and the first conductive layer. This arrangement facilitates electrical connection between the second end of the conductive hole and the first via.

[0013] In some embodiments, the other sub-capacitor further includes a second redistribution layer, the second redistribution layer covers the electrode of the other sub-capacitor; the second redistribution layer includes a second insulating layer, and a second conductive layer and a second via embedded in the second insulating layer, the second via is connected between the second conductive layer and the electrode of the other sub-capacitor, and a portion of the interconnection structure is disposed on the second insulating layer and electrically connected to the second conductive layer. This arrangement can facilitate the arrangement of the interconnection structure.

[0014] In some embodiments, the carrier layer includes a front side and a back side that are arranged opposite to each other, the electrode includes a first electrode and a second electrode, and the first electrode and the second electrode are both arranged on the front side of the carrier layer; the two adjacent sub-capacitors are respectively a first sub-capacitor and a second sub-capacitor, and the back side of the first sub-capacitor is arranged adjacent to the front side of the second sub-capacitor; the conductive hole connected between the first electrodes of the two adjacent sub-capacitors, and the conductive hole connected between the second electrodes of the two adjacent sub-capacitors are both arranged on the first sub-capacitor and penetrate the carrier layer of the first sub-capacitor. Such an arrangement simplifies the connection process between the electrodes of the first sub-capacitor and the second sub-capacitor, thereby helping to reduce the manufacturing cost of the capacitor.

[0015] In some embodiments, the first sub-capacitor further includes a second redistribution layer, the second redistribution layer covers the front surface of the carrier layer; the second redistribution layer includes a second insulating layer, and a second conductive layer and a second via embedded in the second insulating layer; the second conductive layer includes a first sub-layer and a second sub-layer; the first sub-layer is electrically connected to the first electrode and a part of the conductive vias through the second vias, and the second sub-layer is electrically connected to the second electrode and another part of the conductive vias through the second vias. With such a configuration, the second redistribution layer can electrically connect the conductive vias at different positions to the first electrode and the second electrode, thereby facilitating the configuration of the conductive vias.

[0016] In some embodiments, the second redistribution layer further includes a sixth pad, the sixth pad is embedded in the second insulating layer, the sixth pad is disposed at the first end of the conductive hole, and is electrically connected to the corresponding second via hole. This arrangement can facilitate the electrical connection between the first end of the conductive hole and the second via hole.

[0017] In some embodiments, in the first sub-capacitor, a capacitor array is provided on the carrier layer, the capacitor array includes a plurality of capacitor units, and a first conductive hole and a second conductive hole are provided between two adjacent capacitor units in the capacitor array; wherein the first conductive hole is the conductive hole electrically connected to the first electrode, and the second conductive hole is the conductive hole electrically connected to the second electrode. In this way, the mutual inductive coupling between adjacent first conductive holes and second conductive holes can be reduced.

[0018] In some embodiments, in the capacitor array, a plurality of the capacitor units are arranged along a first direction, and the first electrodes of the capacitor units form a first electrode array, and the second electrodes of the capacitor units form a second electrode array, and the second electrode array and the first electrode array are arranged in a second direction, and the second direction is perpendicular to the first direction; along the first direction, the first conductive hole is arranged between two adjacent first electrodes, and the second conductive hole is arranged between two adjacent second electrodes. Such an arrangement facilitates the electrical connection between the first conductive hole and the adjacent first electrode, and facilitates the electrical connection between the second conductive hole and the adjacent second electrode.

[0019] In some embodiments, the first sublayer is in a strip shape and extends along the first direction, and the projection of the first sublayer on the carrier layer overlaps with each of the first electrodes and each of the first conductive vias. This arrangement not only facilitates electrical connection between the first sublayer and the first conductive vias and each of the first electrodes, but also reduces the occupied area of ​​the first sublayer on the second redistribution layer.

[0020] In some embodiments, the second sub-layer is in a strip shape and extends along the first direction, and the projection of the second sub-layer on the carrier layer overlaps with each of the second electrodes and each of the second conductive vias. This arrangement not only facilitates the electrical connection between the second sub-layer and the second conductive vias and each of the second electrodes, but also reduces the occupied area of ​​the second sub-layer on the second redistribution layer.

[0021] In some embodiments, in the capacitor array, a plurality of the capacitor units are arranged along a first direction, and the first electrodes of the capacitor units form a first electrode array, and the second electrodes of the capacitor units form a second electrode array, and the second electrode array and the first electrode array are arranged in a second direction, and the second direction is perpendicular to the first direction; the first conductive holes and the second conductive holes are alternately arranged along the first direction to form a conductive hole array, and the conductive hole array is located between the first electrode array and the second electrode array, and the first conductive holes and the second conductive holes adjacent to the conductive hole array are respectively located on both sides of the corresponding capacitor unit. Such an arrangement can further reduce the mutual inductive coupling between the adjacent first conductive holes and the second conductive holes in the conductive hole array.

[0022] In some embodiments, the first sublayer includes a first routing line and a second routing line connected to one side of the first routing line, the first routing line extends along the first direction, and the projection on the carrier layer overlaps with each of the first electrodes, and the first routing line is electrically connected to each of the first electrodes through the second vias; the projection of the second routing line on the carrier layer overlaps with the first conductive vias, and the second routing line is electrically connected to the first conductive vias through the second vias. Such a configuration not only facilitates the electrical connection of the first sublayer with the first conductive vias and each of the first electrodes, but also reduces the occupied area of ​​the first sublayer on the second redistribution layer.

[0023] In some embodiments, the second sublayer includes a third routing line and a fourth routing line connected to one side of the third routing line, the third routing line extends along the first direction, and the projection on the carrier layer overlaps with each second electrode, and the third routing line is electrically connected to each second electrode through the second via hole; the projection of the fourth routing line on the carrier layer overlaps with the second conductive hole, and the fourth routing line is electrically connected to the second conductive hole through the second via hole. Such a configuration not only facilitates the electrical connection of the second sublayer with each second electrode of the second conductive hole, but also reduces the occupied area of ​​the second sublayer on the second redistribution layer.

[0024] In a second aspect, an embodiment of the present application provides a chip, including a carrier substrate, a bare chip disposed on the carrier substrate, and the capacitor described in the first aspect, wherein the capacitor is disposed on the carrier substrate.

[0025] The beneficial effects of the chip in the embodiment of the present application are the same as the beneficial effects of the capacitor in the first aspect, and will not be repeated here.

[0026] In some embodiments, the capacitor is disposed on a side surface of the carrier substrate away from the bare chip, and the projection of the capacitor on the carrier substrate at least partially overlaps with the projection of the core of the bare chip on the carrier substrate. This arrangement can improve the decoupling effect of the capacitor to optimize the intermediate frequency resonant noise of the power link of the electronic device.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, comprising a circuit board and the chip described in the second aspect, wherein the chip is arranged on the circuit board.

[0028] The beneficial effects of the electronic device in the embodiment of the present application are the same as the beneficial effects of the chip in the second aspect, and will not be repeated here.

[0029] In some embodiments, a first capacitor is disposed on a surface of the circuit board away from the bare chip, and a projection of the first capacitor on the carrier substrate at least partially overlaps with a projection of the core of the bare chip on the carrier substrate. This arrangement can improve the decoupling effect of the first capacitor, thereby reducing the low-frequency transient noise of the power link of the electronic device.

[0030] In some embodiments, the first capacitor is a chip-type multilayer ceramic capacitor.

[0031] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a capacitor, wherein the capacitor includes a plurality of sub-capacitors, each of the plurality of sub-capacitors includes a carrier layer and a capacitor unit embedded in the carrier layer, and the capacitor unit has electrodes; the method for manufacturing the capacitor includes: stacking the plurality of sub-capacitors; wherein at least one of two adjacent sub-capacitors is provided with a conductive hole, and the conductive hole electrically connects the electrodes of the two adjacent sub-capacitors so that the capacitor units of the two adjacent sub-capacitors are connected in parallel.

[0032] The beneficial effects of the method for manufacturing the capacitor in the embodiment of the present application are the same as the beneficial effects of the capacitor in the first aspect, and will not be repeated here.

[0033] In some embodiments, before stacking the two adjacent sub-capacitors, the method further includes: providing the conductive hole on at least one of the two adjacent sub-capacitors. This arrangement can reduce the damage to the conductive hole caused by the sub-capacitor manufacturing and transportation process, and can also improve the versatility of the sub-capacitor.

[0034] In some embodiments, for a sub-capacitor on which the conductive hole is to be set, setting the conductive hole on the sub-capacitor includes: setting a blind hole on the front side of the bearing layer; setting a conductor in the blind hole; thinning the bearing layer from the back side of the bearing layer so that the conductor is exposed from the back side of the bearing layer to form the conductive hole. With such a setting, the production of the conductive hole causes less damage to other structures of the sub-capacitor; and before the back side of the bearing layer is thinned, the bottom of the blind hole can support the conductor, so there is no need to set other structures to support the conductor, thereby simplifying the production process of the conductive hole.

[0035] In some embodiments, the electrodes of the capacitor unit are disposed on the front side of the carrier layer; the two adjacent sub-capacitors are respectively the first sub-capacitor and the second sub-capacitor, and the conductive holes connected between the electrodes of the two adjacent sub-capacitors are disposed on the first sub-capacitor and penetrate the carrier layer of the first sub-capacitor; the two adjacent sub-capacitors are stacked, including: the electrodes of the second sub-capacitor are electrically connected to the conductive holes on the first sub-capacitor through an interconnection structure, so that the first sub-capacitor and the second sub-capacitor are stacked. Such a configuration can facilitate the configuration of the interconnection structure.

[0036] In some embodiments, the electrode of the second sub-capacitor is electrically connected to the conductive hole on the first sub-capacitor through an interconnection structure, including: arranging a first redistribution layer on the back side of the carrier layer of the first sub-capacitor to be electrically connected to the conductive hole; arranging a second redistribution layer on the front side of the carrier layer of the second sub-capacitor to be electrically connected to the electrode of the second sub-capacitor; and electrically connecting the second redistribution layer to the first redistribution layer through the interconnection structure. In this way, the second redistribution layer can electrically connect the conductive holes at different positions to the electrodes of the first sub-capacitor, thereby facilitating the arrangement of the conductive holes.

[0037] In some embodiments, before the second sub-capacitor is electrically connected to the conductive hole on the first sub-capacitor through the interconnection structure, the method further includes: arranging a second redistribution layer on the front surface of the carrier layer of the first sub-capacitor to electrically connect the electrode of the first sub-capacitor to the conductive hole. This arrangement can reduce the number of flipping times of the first sub-capacitor to simplify the manufacturing process of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a structural schematic diagram of a capacitor in the related art;

[0039] Figure 2 A front view schematic diagram of an electronic device (mobile phone) in some embodiments of the present application;

[0040] Figure 3 for Figure 2 AA cross-sectional view of the electronic device in;

[0041] Figure 4 for Figure 3 A schematic diagram of the structure of a module formed by a chip and a circuit board;

[0042] Figure 5 is a simplified structural diagram of a capacitor in the first embodiment of the present application;

[0043] Figure 6 for Figure 5 Equivalent circuit diagram of the capacitor in;

[0044] Figure 7 for Figure 5 Schematic diagram of the structure of the sub-capacitor;

[0045] Figure 8 is a top view of the capacitor in the first embodiment of the present application;

[0046] Fig. 9 for Figure 8 BB cross-sectional view of the capacitor in;

[0047] Fig.10 for Figure 8 CC cross-sectional view of the capacitor in FIG.

[0048] Fig.11 This is the first structural embodiment of the interconnection structure in the embodiments of the present application;

[0049] Fig.12 This is the second structural embodiment of the interconnection structure in the embodiment of the present application;

[0050] Fig.13 is a three-dimensional diagram of a capacitor in a second embodiment of the present application;

[0051] Fig.14a Schematic diagram of the arrangement of electrodes and conductive holes of a sub-capacitor in the second embodiment of the present application;

[0052] Fig.14b It is a schematic diagram of the arrangement of electrodes, conductive holes, and a second conductive layer of a sub-capacitor in the second embodiment of the present application;

[0053] Fig.15 for Fig.14b DD cross-sectional view of the capacitor in;

[0054] Fig.16 for Fig.14b EE cross-sectional view of the capacitor in;

[0055] Fig.17 is a simplified structural diagram of a capacitor in the third embodiment of the present application;

[0056] Fig.18 is a longitudinal cross-sectional view of a capacitor in a third embodiment of the present application;

[0057] Fig.19 is a simplified structural diagram of a capacitor in a fourth embodiment of the present application;

[0058] Fig. 20 is a top view of a capacitor in a fourth embodiment of the present application;

[0059] Fig.21 for Fig. 20 FF cross-sectional view of the capacitor in FIG.

[0060] Fig. 22 is a schematic structural diagram of a sub-capacitor in a fourth embodiment of the present application;

[0061] Fig.23 is a simplified structural diagram of a capacitor in a fifth embodiment of the present application;

[0062] Fig.24a Schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application Figure 1 ;

[0063] Figure 24b Schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application Figure 2 ;

[0064] Fig.24c The manufacturing process of the capacitor in the first embodiment of the present application is shown in FIG. Figure 3 ;

[0065] Fig.24d Schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application Figure 4 ;

[0066] Fig.24e Schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application Figure 5 ;

[0067] Figure 24f Schematic diagram of the manufacturing process of the capacitor in the first embodiment of the present application Figure 6 ;

[0068] Figure 24g The manufacturing process of the capacitor in the first embodiment of the present application is shown in FIG. Figure 7 ;

[0069] Fig.25a A flowchart of a manufacturing process of a capacitor in some embodiments of the present application;

[0070] Fig.25b FIG. 1 is a flow chart of a process for manufacturing a conductive via of a capacitor in some embodiments of the present application. DETAILED DESCRIPTION

[0071] The technical solutions in some embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0072] like Figure 1 As shown, Figure 1 Schematic diagram of the structure of a capacitor in the related art. The capacitor is an IPD (Integrated Passive Device) capacitor, which is generally made by a deep trench process. The capacitor includes a substrate layer 01, a trench 011 disposed on the substrate layer 01, and a capacitor unit 02 partially located in the trench 011. The capacitor unit 02 includes a first polysilicon layer 021, a second polysilicon layer 022, and a dielectric layer 023. The dielectric layer 023 is located between the first polysilicon layer 021 and the second polysilicon layer 022. The capacitor unit 02 has a first electrode 031 and a second electrode 032. The first electrode 031 is disposed on the first polysilicon layer 021, and the second electrode 032 is disposed on the second polysilicon layer 022.

[0073] As shown in Table 1, Table 1 shows a parameter comparison between this capacitor in the related art and a chip multilayer ceramic capacitor (Multi-layer Ceramic Capacitors; MLCC for short). It can be seen from Table 1 that this capacitor in the related art has lower parasitic inductance (Equivalent series inductance; ESL for short) and thinner thickness, but lower capacitance density (the ratio of the capacitance value of the capacitor to the area occupied). In this way, when achieving the same capacitance value, the capacitor in the related art occupies a larger area, which is not conducive to the optimized layout of other devices around the capacitor.

[0074] Table 1

[0075]

[0076] To this end, an embodiment of the present application provides a capacitor and a manufacturing method thereof, a chip, and an electronic device. The capacitor includes multiple sub-capacitors. The capacitance density of the capacitor is improved by stacking the multiple sub-capacitors and connecting the capacitance units of two adjacent sub-capacitors in parallel through conductive holes provided on the sub-capacitors.

[0077] The electronic device in the embodiments of the present application can be a mobile phone, a tablet computer, a wearable device (such as a smart watch, a smart bracelet, smart glasses, smart jewelry, etc.), a vehicle-mounted device, an augmented reality (AR) device, a virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), and other electronic devices with capacitors.

[0078] The following uses a mobile phone as an example to introduce the structure of the capacitor of the electronic device in the embodiment of the present application. Other types of electronic devices can be specifically configured with reference to the structure of the capacitor in the mobile phone embodiment, which will not be described in detail here.

[0079] like Figure 2 and Figure 3 As shown, Figure 2 is a front view of an electronic device (mobile phone) in some embodiments of the present application, Figure 3 for Figure 2 AA cross-sectional view of an electronic device in FIG. The electronic device includes a housing 200 , a display screen 300 , a circuit board 400 and a chip 100 .

[0080] In some embodiments, Figure 2 and Figure 3 As shown, the housing 200 includes a middle frame 210 (also called a front shell or a front frame) and a back cover 220 (also called a battery cover). The display screen 300 and the back cover 220 are respectively mounted on opposite sides of the middle frame 210, the display screen 300 and the middle frame 210 enclose a first accommodation space 230, and the back cover 220 and the middle frame 210 enclose a second accommodation space 240.

[0081] The middle frame 210 and the back cover 220 may be detachably connected or may be an integral structure, which is not specifically limited here.

[0082] In some embodiments, Figure 3 As shown, the display screen 300 is a liquid crystal display screen, and a backlight source 500 is disposed in the first receiving space 230. However, the present invention is not limited thereto, and the display screen 300 may also be an OLED (Organic Light-Emitting Diode) display screen.

[0083] A circuit board 400 is disposed in the second receiving space 240, and a chip 100 is disposed on the circuit board 400. The chip 100 may be a SOC (System on Chip) chip.

[0084] like Figure 4 As shown, Figure 4 for Figure 3 Schematic diagram of the structure of the module formed by the chip 100 and the circuit board 400. The chip 100 includes a carrier substrate 110, a capacitor 120, and a bare chip (DIE) 130 disposed on the carrier substrate 110. The capacitor 120 is an IPD capacitor and is disposed on the carrier substrate 110. However, it is not limited thereto, and the capacitor 120 may also be other types of silicon capacitors.

[0085] In some embodiments, Figure 4 As shown, the capacitor 120 is disposed on a side surface of the carrier substrate 110 away from the bare chip 130 (eg Figure 4 ), and a projection of the capacitor 120 on the carrier substrate 110 at least partially overlaps with a projection of a core 135 of the bare chip 130 on the carrier substrate 110 .

[0086] Among them, the core 135 can be at least one of a CPU (Central Processing Unit) core, a GPU (Graphics Processing Unit) core, and an NPU (Neural Processing Unit) core. The core 135 can be embedded in the bare chip 130, or it can be located on the surface of the bare chip 130, which is not specifically limited here. The projection of the capacitor 120 on the carrier substrate 110 and the projection of the core 135 on the carrier substrate 110 can partially overlap or completely overlap, which is not specifically limited here. The number of capacitors 120 can be one or more, which can be determined according to actual conditions.

[0087] Since the core 135 is the main load of the chip 100, the projection of the capacitor 120 on the carrier substrate 110 is at least partially overlapped with the projection of the core 135 on the carrier substrate 110, so that the capacitor 120 can be close to the load of the chip 100, thereby improving the decoupling effect of the capacitor 120, so as to optimize the intermediate frequency (frequency range is tens to hundreds of MHz) resonant noise of the power link of the electronic device, thereby improving the PI (Power Integrity) performance of the power link.

[0088] The power link includes a power source and a circuit connected between the power source and the load, wherein the power source may be a battery, a power supply port, etc.

[0089] In some embodiments, Figure 4As shown, a connection bump 140 is provided between the carrier substrate 110 and the circuit board 400, so that a setting gap 150 is formed between the carrier substrate 110 and the circuit board 400, and the capacitor 120 is disposed in the setting gap 150. The connection bump 140 electrically connects the carrier substrate 110 and the circuit board 400, thereby realizing electrical connection between the chip 100 and the circuit board 400.

[0090] In some embodiments, Figure 4 As shown, the chip 100 further includes a packaging layer 160 . The packaging layer 160 is disposed on the carrier substrate 110 and covers the bare chip 130 to protect the bare chip 130 .

[0091] In some embodiments, Figure 4 As shown, the circuit board 400 is away from the chip 100 on one side surface (eg Figure 4 A first capacitor 170 is provided on the lower surface of the circuit board 400 shown in FIG. 1 ), and the projection of the first capacitor 170 on the carrier substrate 110 at least partially overlaps with the projection of the core 135 on the carrier substrate 110. In this way, the first capacitor 170 can be close to the core 135 (that is, the load of the chip 100), which can improve the decoupling effect of the first capacitor 170, thereby reducing the low-frequency transient noise of the power link of the electronic device.

[0092] The projection of the first capacitor 170 on the carrier substrate 110 may partially overlap or completely overlap with the projection of the core 135 on the carrier substrate 110, which is not specifically limited here. The number of the first capacitor 170 may be one or more, depending on the actual situation.

[0093] In some embodiments, Figure 4 As shown, the first capacitor 170 is a chip-type multilayer ceramic capacitor, but it is not limited thereto. The first capacitor 170 may also be other types of capacitors, such as a silicon capacitor.

[0094] like Figure 5 As shown, Figure 5 1 is a simplified structural diagram of a capacitor 120 in the first embodiment of the present application. The capacitor 120 includes a plurality of sub-capacitors 1 stacked in layers. Each of the plurality of sub-capacitors 1 includes a carrier layer 11 and a capacitor unit 12 embedded in the carrier layer 11, wherein the capacitor unit 12 has an electrode 13; among the plurality of sub-capacitors 1, at least one of two adjacent sub-capacitors 1 is provided with a conductive hole 2, and the conductive hole 2 electrically connects the electrodes 13 of the two adjacent sub-capacitors 1, so that the capacitor units 12 of the two adjacent sub-capacitors 1 are connected in parallel.

[0095] Among them, Figure 5As shown, the conductive via 2 may be a through silicon via (TSV), but is not limited thereto. The conductive via 2 may also be other types of holes with conductive capabilities, such as holes with metal layers covering the hole walls.

[0096] The number of capacitor units 12 of each sub-capacitor 1 may be one or more, which is not specifically limited here; when each sub-capacitor 1 has multiple capacitor units 12, the capacitor units 12 corresponding to the positions on the multiple sub-capacitors 1 are connected in parallel through the conductive holes 2; for example Figure 5 As shown, in two adjacent sub-capacitors 1, the capacitor unit 12a is located on the carrier layer 11 of one of the sub-capacitors 1, and the capacitor unit 12b is located on the carrier layer 11 of the other sub-capacitor 1. The positions of the capacitor units 12a and 12b correspond to each other, and the electrodes 13 of the capacitor units 12a and 12b are electrically connected through the conductive holes 2 so that the capacitor units 12a and 12b are connected in parallel.

[0097] The capacitor 120 in the embodiment of the present application, because at least one of the two adjacent sub-capacitors 1 is provided with a conductive hole 2, the conductive hole 2 electrically connects the electrodes 13 of the two adjacent sub-capacitors 1, so that the capacitor units 12 of the two adjacent sub-capacitors 1 are connected in parallel, so that the equivalent capacitance of the capacitor 120 is equal to the sum of the capacitance values ​​of the capacitor units 12 in the multiple sub-capacitors 1, thereby increasing the capacitance value of the capacitor 120. In addition, because the multiple sub-capacitors 1 of the capacitor 120 are stacked, the capacitor 120 increases the capacitance value while reducing the occupied area of ​​the capacitor, thereby increasing the capacitance density of the capacitor 120. With the increase in capacitance density, the capacitor 120 occupies a smaller area when achieving the same capacitance value, which is conducive to the optimized layout of other devices around the capacitor 120.

[0098] In some embodiments, Figure 5 As shown, the carrier layer 11 includes a front surface 117 a and a back surface 117 b disposed opposite to each other. Specifically, along the thickness direction of the carrier layer 11 , the front surface 117 a is one side surface of the carrier layer 11 , and the back surface 117 b is the other side surface of the carrier layer 11 .

[0099] The electrode 13 includes a first electrode 131 (eg Figure 5 ) and the second electrode 132 (e.g. Figure 5 The first electrode 131 and the second electrode 132 are both disposed on the front surface 117a of the carrier layer 11. The two adjacent sub-capacitors 1 are respectively the first sub-capacitor 1a and the second sub-capacitor 1b, and the back surface 117b of the first sub-capacitor 1a is disposed adjacent to the front surface 117a of the second sub-capacitor 1b.

[0100] The conductive hole 2 (i.e., the first conductive hole 21 in the figure) connected between the first electrodes 131 of the first sub-capacitor 1a and the second sub-capacitor 1b, and the conductive hole 2 (i.e., the second conductive hole 22 in the figure) connected between the second electrodes 132 of the first sub-capacitor 1a and the second sub-capacitor 1b are both arranged on the first sub-capacitor 1a and pass through the supporting layer 11 of the first sub-capacitor 1a.

[0101] By setting the conductive holes 2 connecting the first electrode 131 and the second electrode 132 on the first sub-capacitor 1a, it is convenient to electrically connect the second end of the conductive hole 2 with the electrode 13 of the second sub-capacitor 1b, thereby simplifying the connection process between the electrodes 13 of the first sub-capacitor 1a and the second sub-capacitor 1b, which is beneficial to reducing the manufacturing cost of the capacitor 120.

[0102] like Figure 6 As shown, Figure 6 for Figure 5 The equivalent circuit diagram of the capacitor 120 in FIG. 1 is shown in FIG. 1 , wherein the first sub-capacitor 1a and the second sub-capacitor 1b are IPD capacitors, the conductive hole 2 is a silicon through-hole, and the equivalent circuit of the first sub-capacitor 1a is C IPD1 , ESL IPD1 、ESR IPD1 The three are connected in series; the equivalent circuit of the second sub-capacitor 1b is C IPD2 , ESL IPD2 、ESR IPD2 The three are connected in series; the equivalent circuit of conductive hole 2 is ESL TSV 、ESR TSV The first sub-capacitor 1a and the second sub-capacitor 1a are stacked and have a capacitance value C 12 C 12 ≈C 1 +C 2 ; Parasitic inductance ESL 12 <ESL 1 ; Parasitic resistance ESR 12 <ESR 1 It can be seen that the capacitor 120 formed by stacking a plurality of sub-capacitors 1 can achieve lower parasitic inductance and parasitic resistance while also increasing the capacitance per unit area of ​​the capacitor 120 .

[0103] In some embodiments, Figure 7 As shown, Figure 7 for Figure 5Schematic diagram of the structure of the sub-capacitor 1 in FIG. The carrier layer 11 of the sub-capacitor 1 includes a substrate layer 111, a first groove 112 is provided on the substrate layer 111, a capacitor unit 12 is partially (or entirely) disposed in the first groove 112, and the capacitor unit 12 includes a first capacitor conductive layer 121, a second capacitor conductive layer 122, and a dielectric layer 123 disposed between the first capacitor conductive layer 121 and the second capacitor conductive layer 122.

[0104] The carrier layer 11 of the sub-capacitor 1 further includes an upper insulating layer 113, which is disposed on the substrate layer 111 and covers the capacitor unit 12. The first electrode 131 and the second electrode 132 of the capacitor unit 12 are disposed on the upper insulating layer 113. The upper insulating layer 113 is provided with a first connecting via 114 and a second connecting via 115, wherein the first connecting via 114 is connected between the first electrode 131 and the first capacitor conductive layer 121, and the second connecting via 115 is disposed between the second electrode 132 and the second capacitor conductive layer 122.

[0105] The substrate layer 111 may be a silicon substrate layer, the first capacitor conductive layer 121 and the second capacitor conductive layer 122 may be polysilicon (Polysilicon; Poly for short) layers, or metal layers, such as copper layers or tungsten layers. The first connecting vias 114 and the second connecting vias 115 may both be silicon through-holes, or other types of holes with conductive capabilities, such as holes with metal layers covered on the hole walls.

[0106] In some embodiments, Figure 7 As shown, the first capacitor conductive layer 121 fills the first groove 112, a plurality of second grooves 1211 are spaced apart on the first capacitor conductive layer 121, the dielectric layer 123 includes a first dielectric layer 1231 and a second dielectric layer 1232, the first dielectric layer 1231 covers the groove wall of the second groove 1211, and the second dielectric layer 1232 is arranged at the edge of the second groove 1211 and connected to the first dielectric layer 1231;

[0107] The second capacitor conductive layer 122 includes a filling layer 1221 and a connecting layer 1222. The filling layer 1221 is disposed on the first dielectric layer 1231, and the filling layer 1221 and the first dielectric layer 1231 fill the second trench 1211. The connecting layer 1222 is disposed on the second dielectric layer 1232 and the filling layer 1221. The second connecting via 115 is connected between the connecting layer 1222 and the second electrode 132.

[0108] By setting a plurality of second grooves 1211 on the first capacitor conductive layer 121, and setting the dielectric layer 123 and the second capacitor conductive layer 122 in the second grooves 1211, this is equivalent to folding the plates of the capacitor unit 12 (i.e., the first capacitor conductive layer 121 and the second capacitor conductive layer 122), thereby expanding the area of ​​the substrate of the capacitor unit 12, which is beneficial to improving the capacitance value of the capacitor unit 12.

[0109] The first electrode 131 and the second electrode 132 of the capacitor unit 12 may be provided by one or more. For example, Figure 7 As shown, the capacitor unit 12 has two first electrodes 131 and four second electrodes 132 , each of the first electrodes 131 is electrically connected to the first capacitor conductive layer 121 through a first connection via 114 , and each of the second electrodes 132 is electrically connected to the connection layer 1222 through a second connection via 115 .

[0110] In some embodiments, Figure 8 , Fig. 9 and Fig.10 As shown, Figure 8 is a top view of the capacitor 120 in the first embodiment of the present application, Fig. 9 for Figure 8 The BB cross-sectional view of the capacitor 120, Fig.10 for Figure 8 CC cross-sectional view of capacitor 120 in FIG.

[0111] In the first sub-capacitor 1a and the second sub-capacitor 1b, for any one conductive hole 2, the conductive hole 2 penetrates the carrier layer 11 of the first sub-capacitor 1a, and the first end (the upper end shown in the figure) of the conductive hole 2 is electrically connected to the electrode 13 of the first sub-capacitor 1a, and the second end (the lower end shown in the figure) of the conductive hole 2 is electrically connected to the electrode 13 of the second sub-capacitor 1b through the interconnection structure 3. That is: in two adjacent sub-capacitors 1, for any one conductive hole 2, the conductive hole 2 penetrates the carrier layer 11 of one of the sub-capacitors 1, and the first end of the conductive hole 2 is electrically connected to the electrode 13 of one of the sub-capacitors 1, and the second end of the conductive hole 2 is electrically connected to the electrode 13 of the other sub-capacitor 1 through the interconnection structure 3.

[0112] By setting the interconnection structure 3, the interconnection structure 3 can electrically connect the conductive holes 2 at different positions to the electrode 13 of the second sub-capacitor 1b, so the conductive holes 2 do not need to be set at the positions corresponding to the electrode 13 of the second sub-capacitor 1b, thereby facilitating the setting of the conductive holes 2.

[0113] In some embodiments, Fig. 9As shown, the first sub-capacitor 1a also includes a first redistribution layer 14, which covers the second end of the conductive hole 2; the first redistribution layer 14 includes a first insulating layer 141, and a first conductive layer 142 and a first via 143 embedded in the first insulating layer 141, the first via 143 is connected between the first conductive layer 142 and the second end of the conductive hole 2, and a portion of the interconnection structure 3 is arranged on the first insulating layer 141 and is electrically connected to the first conductive layer 142.

[0114] By setting the first redistribution layer 14, the first redistribution layer 14 can electrically connect the interconnection structure 3 at different positions to the second end of the conductive hole 2, so the interconnection structure 3 does not need to be set at the position corresponding to the second end of the conductive hole 2, thereby facilitating the setting of the interconnection structure 3.

[0115] The first conductive layer 142 may be a linear conductive layer or a planar conductive layer, which is not specifically limited here; the first conductive layer 142 may be a metal layer, such as a copper layer.

[0116] In some embodiments, Fig. 9 As shown, the first redistribution layer 14 further includes a fifth pad 144, which is embedded in the first insulating layer 141, and is disposed at the second end of the conductive hole 2, and the first via 143 is connected between the fifth pad 144 and the first conductive layer 142. By providing the fifth pad 144 at the second end of the conductive hole 2, the fifth pad 144 acts as a connecting terminal of the conductive hole 2, and the fifth pad 144 can be set to different sizes according to actual needs, so that it can be conveniently electrically connected to the first via 143, avoiding the inconvenience of connecting to the first via 143 due to the small diameter of the conductive hole 2.

[0117] The material of the fifth pad 144 may be metal, such as copper or tungsten, etc., which is not specifically limited here. A first via hole 143 may be provided between the fifth pad 144 and the first conductive layer 142, such as Fig. 9 As shown, a plurality of first via holes 143 may also be provided, for example, two.

[0118] In some embodiments, Fig. 9 As shown, the second sub-capacitor 1b also includes a second redistribution layer 15, which covers the electrode 13 of the second sub-capacitor 1b; the second redistribution layer 15 includes a second insulating layer 151, and a second conductive layer 152 and a second via 153 embedded in the second insulating layer 151, the second via 153 is connected between the second conductive layer 152 and the electrode 13 of the second sub-capacitor 1b, and a portion of the interconnection structure 3 is arranged on the second insulating layer 151 and is electrically connected to the second conductive layer 152.

[0119] By setting the second redistribution layer 15, the second redistribution layer 15 can electrically connect the interconnection structure 3 at different positions with the electrode 13 of the second sub-capacitor 1b, so the interconnection structure 3 does not need to be set at the position corresponding to the electrode 13 of the second sub-capacitor 1b, thereby facilitating the setting of the interconnection structure 3.

[0120] The second conductive layer 152 may be a linear conductive layer or a planar conductive layer, which is not specifically limited here; the second conductive layer 152 may be a metal layer, such as a copper layer.

[0121] The specific structure of the interconnection structure 3 is not unique. Fig.11 The first structural embodiment of the interconnection structure 3 in the embodiment of the present application is shown. In this embodiment, the interconnection structure 3 includes a bump 31, a first pad 32 and a second pad 33. The first pad 32 is arranged on the first sub-capacitor 1a and is electrically connected to the second end of the conductive hole 2. The second pad 33 is arranged on the second sub-capacitor 1b and is electrically connected to the electrode 13 of the second sub-capacitor 1b. The bump 31 is arranged between the first pad 32 and the second pad 33. For example, the bump 31 can be welded between the first pad 32 and the second pad 33. By setting the interconnection structure 3 to a structure including the bump 31, the difficulty of designing and manufacturing the interconnection structure 3 is reduced, which is conducive to reducing the design and manufacturing costs of the capacitor 120.

[0122] Among them, Fig.11 As shown, the first pad 32 may be disposed on the first redistribution layer 14 and electrically connected to the first conductive layer 142. The second pad 33 may be disposed on the second redistribution layer 15 and electrically connected to the second conductive layer 152.

[0123] The bump 31 may be spherical, but is not limited thereto, and may be columnar or other irregular shapes. The material of the bump 31 includes at least one of Au, Ni, Cu, Pb, Sn, and In; the bump 31 may be a micro bump 31, and the maximum size of the micro bump 31 may be between 10 μm and 20 μm.

[0124] Fig.12 A second structural embodiment of the interconnection structure 3 in the embodiment of the present application is shown. In this embodiment, the interconnection structure 3 is a hybrid bonding structure and includes a plurality of third pads 34 and a plurality of fourth pads 35. Each third pad 34 is arranged on the first sub-capacitor 1a and is electrically connected to the second end of the conductive hole 2; each fourth pad 35 is arranged on the second sub-capacitor 1b and is electrically connected to the electrode 13 of the second sub-capacitor 1b, and each third pad 34 is in contact with the corresponding fourth pad 35, respectively.

[0125] By setting the interconnection structure 3 as a hybrid bonding structure, the following advantages are achieved: First, a shorter interconnection distance can be achieved. The interconnection is achieved through the contact between the third pad 34 and the fourth pad 35, which can reduce the gap between two adjacent sub-capacitors 1 and prevent impurities from entering the gap between two adjacent sub-capacitors 1 to affect the normal operation of the capacitor 120; Second, a higher interconnection density can be achieved. The size of the third pad 34 and the fourth pad 35 is relatively small, for example, it can be less than 10μm, so that a higher interconnection density can be achieved to facilitate the transmission of electrical signals in the interconnection structure 3.

[0126] Among them, Fig.12 As shown, the third pad 34 may be disposed on the first redistribution layer 14 and electrically connected to the first conductive layer 142. The fourth pad 35 may be disposed on the second redistribution layer 15 and electrically connected to the second conductive layer 152.

[0127] The material of the third pad 34 and the fourth pad 35 includes at least one of Au, Ni, Cu, Pb, Sn, and In. The shape of the third pad 34 and the fourth pad 35 can be circular, but not limited thereto, and can also be polygonal, such as square. The number of the third pad 34 and the fourth pad 35 can be 9, but not limited thereto, and can also be more than 9, or less than 9, depending on the actual situation.

[0128] In some embodiments, Figure 8 , Fig. 9 and Fig.10 As shown, the first sub-capacitor 1a further includes a second redistribution layer 15, which covers the front surface 117a of the carrier layer 11; the second redistribution layer 15 includes a second insulating layer 151, and a second conductive layer 152 and a second via 153 embedded in the second insulating layer 151; the second conductive layer 152 includes a first sub-layer 1521 and a second sub-layer 1522. Figure 8 and Fig. 9 As shown, the first sub-layer 1521 is connected to the first electrode 131 and a portion of the conductive holes 2 (such as Figure 8 The two conductive holes 2 on the left are electrically connected; Figure 8 and Fig.10 As shown, the second sub-layer 1522 is connected to the second electrode 132 and another number of conductive holes 2 (such as Figure 8 The two conductive holes 2) on the right side are electrically connected.

[0129] By setting the second redistribution layer 15, the second redistribution layer 15 can electrically connect the conductive holes 2 at different positions with the first electrode 131 and the second electrode 132, so the conductive holes 2 do not need to be set at the positions of the first electrode 131 and the second electrode 132, thereby facilitating the setting of the conductive holes 2.

[0130] In some embodiments, Fig. 9 and Fig.10 As shown, the second redistribution layer 15 also includes a sixth pad 154, which is embedded in the second insulating layer 151, and is arranged at the first end (the upper end shown in the figure) of the conductive hole 2 and is electrically connected to the corresponding second via 153.

[0131] By providing a sixth pad 154 at the first end of the conductive hole 2, the sixth pad 154 serves as a connecting terminal of the conductive hole 2. The sixth pad 154 can be set to different sizes according to actual needs, so that it can be conveniently electrically connected to the second via hole 153, avoiding the inconvenience of connecting the conductive hole 2 to the second via hole 153 due to the small diameter of the conductive hole 2.

[0132] The sixth pad 154 may be made of metal, such as copper or tungsten, which is not specifically limited here. A first via hole 143 may be provided between the sixth pad 154 and the second conductive layer 152. Fig. 9 As shown, a plurality of first via holes 143 may also be provided, for example, two.

[0133] In some embodiments, Fig. 9 and Fig.10 As shown, in the sub-capacitor 1 (that is, the first sub-capacitor 1a) located at the end of the capacitor 120, a connecting terminal 4 is provided on the second redistribution layer 15, and the connecting terminal 4 is electrically connected to the second conductive layer 152. The connecting terminal 4 is an external terminal of the capacitor 120 and is used to be electrically connected to the carrier substrate 110 of the chip 100.

[0134] Specifically, the connection terminal 4 includes a first connection terminal 41 and a second connection terminal 42 . The first connection terminal 41 is electrically connected to the first sub-layer 1521 , and the second connection terminal 42 is electrically connected to the second sub-layer 1522 .

[0135] Among them, Fig. 9 and Fig.10 As shown, the first connection terminal 41 and the second connection terminal 42 are both convex points. However, this is not limited thereto, and the first connection terminal 41 and the second connection terminal 42 may also be arranged in other structures.

[0136] In some embodiments, Figure 8 , Fig. 9 and Fig.10As shown, in the first sub-capacitor 1a, a capacitor array 116 is provided on the carrier layer 11, and the capacitor array 116 includes a plurality of capacitor units 12, and a first conductive hole 21 and a second conductive hole 22 are arranged between two adjacent capacitor units 12 in the capacitor array 116; wherein the first conductive hole 21 is a conductive hole 2 electrically connected to the first electrode 131, and the second conductive hole 22 is a conductive hole 2 electrically connected to the second electrode 132.

[0137] By arranging the first conductive via 21 and the second conductive via 22 between two adjacent capacitor units 12 in the capacitor array 116, the distance between the adjacent first conductive via 21 and the second conductive via 22 can be reduced, thereby reducing the mutual inductive coupling between the adjacent first conductive via 21 and the second conductive via 22. At the same time, the distances from the first conductive via 21 and the second conductive via 22 to the capacitor unit 12 can also be shortened, thereby facilitating the electrical connection between the first conductive via 21 and the first electrode 131, and the electrical connection between the second conductive via 22 and the second electrode 132.

[0138] In some embodiments, Figure 8 As shown, in the capacitor array 116, a plurality of capacitor units 12 are arranged along a first direction Y, and the first electrodes 131 of the capacitor units 12 form a first electrode array 133, and the second electrodes 132 of the capacitor units 12 form a second electrode array 134, and the second electrode array 134 and the first electrode array 133 are arranged in a second direction X, and the second direction X is perpendicular to the first direction Y. The first conductive hole 21 is disposed between the first electrodes 131 of two adjacent capacitor units 12, and the second conductive hole 22 is disposed between the second electrodes 132 of two adjacent capacitor units 12.

[0139] Such a configuration can shorten the distance between the first conductive hole 21 and the adjacent first electrode 131, and shorten the distance between the second conductive hole 22 and the adjacent second electrode 132, thereby facilitating the electrical connection between the first conductive hole 21 and the adjacent first electrode 131, and facilitating the electrical connection between the second conductive hole 22 and the adjacent second electrode 132.

[0140] Among them, Figure 8 As shown, the number of capacitor arrays 116 can be set to one, but it is not limited thereto, and the number of capacitor arrays 116 can also be set to multiple.

[0141] In some embodiments, Figure 8 and Fig. 9As shown, the first sublayer 1521 is strip-shaped and extends along the first direction Y, and the projection of the first sublayer 1521 on the carrier layer 11 overlaps with each first electrode 131 and each first conductive via 21. Such a configuration not only facilitates the electrical connection between the first sublayer 1521 and the first conductive via 21 and each first electrode 131, but also reduces the occupied area of ​​the first sublayer 1521 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the second redistribution layer 15.

[0142] In some embodiments, Figure 8 and Fig.10 As shown, the second sublayer 1522 is strip-shaped and extends along the first direction Y, and the projection of the second sublayer 1522 on the carrier layer 11 overlaps with each second electrode 132 and each second conductive via 22. Such a configuration not only facilitates the electrical connection between the second sublayer 1522 and the second conductive via 22 and each second electrode 132, but also reduces the occupied area of ​​the second sublayer 1522 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the second redistribution layer 15.

[0143] like Figure 13 to Figure 16 As shown, Fig.13 is a three-dimensional diagram of the capacitor 120 in the second embodiment of the present application, Fig.14a FIG. 1 is a schematic diagram of the arrangement of electrodes and conductive holes of a sub-capacitor in the second embodiment of the present application. Fig.14b FIG. 1 is a schematic diagram of the arrangement of electrodes, conductive holes, and the second conductive layer 152 of the sub-capacitor in the second embodiment of the present application. Fig.15 for Fig.14b DD cross-sectional view of capacitor 120, Fig.16 for Fig.14b EE cross-sectional view of the capacitor 120 in FIG. The capacitor 120 in this embodiment is Figure 5 to Figure 12 The main difference between the capacitor 120 shown in FIG. 1 and FIG. 2 is that the first conductive hole 21 and the second conductive hole 22 are arranged in different positions and in different ways, as described in detail below:

[0144] like Fig.13 and Fig.14a As shown, in the capacitor array 116, multiple capacitor units 12 are arranged along a first direction Y, and the first electrodes 131 of the capacitor units 12 form a first electrode array 133, and the second electrodes 132 of the capacitor units 12 form a second electrode array 134. The second electrode array 134 and the first electrode array 133 are arranged alternately along a second direction X, and the second direction X is perpendicular to the first direction Y.

[0145] The first conductive holes 21 and the second conductive holes 22 are alternately arranged along the first direction Y to form a conductive hole array 23. The conductive hole array 23 is located between the first electrode array 133 and the second electrode array 134, and adjacent first conductive holes 21 and second conductive holes 22 in the conductive hole array 23 are respectively located on both sides of the corresponding capacitor unit 12.

[0146] The first conductive holes 21 and the second conductive holes 22 are alternately arranged along the first direction Y, and the conductive hole array 23 is located between the first electrode array 133 and the second electrode array 134. In this way, the distance between adjacent first conductive holes 21 and second conductive holes 22 in the conductive hole array 23 is not limited by the positions of the first electrode 131 and the second electrode 132. Then, the distance between adjacent first conductive holes 21 and second conductive holes 22 can be designed to be smaller, thereby further reducing the mutual inductance coupling between adjacent first conductive holes 21 and second conductive holes 22 in the conductive hole array 23.

[0147] At the same time, since the conductive hole array 23 is located between the first electrode array 133 and the second electrode array 134, the first electrode array 133 and the second electrode array 134 can share the conductive hole array 23 (that is, the first electrode array 133 can be electrically connected to the first conductive holes 21 in the conductive hole array 23, and the second electrode array 134 can be electrically connected to the second conductive holes 22 in the conductive hole array 23), thereby reducing the number of conductive holes 2.

[0148] The number of the capacitor array 116 may be one or more, for example Fig.14a As shown, the number of capacitor arrays 116 is three, and the three capacitor arrays 116 are arranged along the second direction X. The capacitor units 12 of two adjacent capacitor arrays 116 share the electrode 13. Specifically, Fig.14a As shown, the capacitor array 116 on the left and the capacitor array 116 in the middle share the second electrode array 134 , and the capacitor array 116 in the middle and the capacitor array 116 on the left share the first electrode array 133 .

[0149] In some embodiments, Fig.14b and Fig.15As shown, the first sublayer 1521 includes a first wiring 1521a and a second wiring 1521b connected to one side of the first wiring 1521a. The first wiring 1521a extends along the first direction Y, and the projection on the carrier layer 11 overlaps with each first electrode 131. The first wiring 1521a is electrically connected to each first electrode 131 through the second via 153. The projection of the second wiring 1521b on the carrier layer 11 overlaps with the first conductive hole 21, and the second wiring 1521b is electrically connected to the first conductive hole 21 through the second via 153. Such a configuration not only facilitates the electrical connection between the first sublayer 1521 and the first conductive hole 21 and each first electrode 131, but also reduces the occupied area of ​​the first sublayer 1521 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the first redistribution layer 14.

[0150] In some embodiments, Fig.14b and Fig.16 As shown, the second sublayer 1522 includes a third routing line 1522a and a fourth routing line 1522b connected to one side of the third routing line 1522a. The third routing line 1522a extends along the first direction Y, and its projection on the carrier layer 11 overlaps with each second electrode 132. The third routing line 1522a is electrically connected to each second electrode 132 through the second via hole 153. The projection of the fourth routing line 1522b on the carrier layer 11 overlaps with the second conductive hole 22, and the fourth routing line 1522b is electrically connected to the second conductive hole 22 through the second via hole 153. Such a configuration not only facilitates the electrical connection between the second sublayer 1522 and the second conductive hole 22 and each second electrode 132, but also reduces the occupied area of ​​the second sublayer 1522 on the second redistribution layer 15, thereby facilitating the optimized layout of other structures on the second redistribution layer 15.

[0151] like Fig.17 and Fig.18 As shown, Fig.17 is a simplified structural diagram of the capacitor 120 in the third embodiment of the present application, Fig.18 FIG. 1 is a longitudinal cross-sectional view of a capacitor 120 in a third embodiment of the present application. The capacitor 120 in this embodiment is Figure 5 to Figure 12 The main difference between the capacitor 120 shown in FIG. 1 and FIG. 2 is that the number of sub-capacitors 1 in the capacitor 120 is different. Figure 5 to Figure 12 The number of sub-capacitors 1 in the capacitor 120 shown in FIG. 1 is two, and the number of sub-capacitors 1 in the capacitor 120 of this embodiment is three or more, as described in detail as follows:

[0152] The capacitor 120 includes three sub-capacitors 1 stacked together, the three sub-capacitors 1 being a first sub-capacitor 1a, a second sub-capacitor 1b, and a third sub-capacitor 1c. The first sub-capacitor 1a and the second sub-capacitor 1b are two adjacent sub-capacitors 1, and the second sub-capacitor 1b and the third sub-capacitor 1c are two adjacent sub-capacitors 1. The back surface 117b of the first sub-capacitor 1a is adjacent to the front surface 117a of the second sub-capacitor 1b, and the back surface 117b of the second sub-capacitor 1b is adjacent to the front surface 117a of the third sub-capacitor 1c. The positions of the capacitor unit 12a, the capacitor unit 12b, and the capacitor unit 12c correspond to each other.

[0153] For the first sub-capacitor 1a and the second sub-capacitor 1b, a conductive hole 2 is provided on the first sub-capacitor 1a, the capacitor unit 12a is located on the supporting layer 11 of the first sub-capacitor 1a, and the capacitor unit 12b is located on the supporting layer 11 of the second sub-capacitor 1b, and the electrodes 13 of the capacitor unit 12a and the capacitor unit 12b are respectively electrically connected through the conductive holes 2 on the first sub-capacitor 1a, so that the capacitor unit 12a and the capacitor unit 12b are connected in parallel.

[0154] For the second sub-capacitor 1b and the third sub-capacitor 1c, a conductive hole 2 is provided on the second sub-capacitor 1b, and the capacitor unit 12c is located on the supporting layer 11 of the third sub-capacitor 1c. The electrodes 13 of the capacitor unit 12b and the capacitor unit 12c are respectively electrically connected through the conductive holes 2 on the second sub-capacitor 1b, so that the capacitor unit 12b and the capacitor unit 12c are connected in parallel.

[0155] The number of the capacitor unit 12 in each sub-capacitor 1 may be one or more, and the capacitor units 12 in corresponding positions in the plurality of sub-capacitors 1 are connected in parallel through the conductive holes 2 .

[0156] The number of sub-capacitors 1 in the capacitor 120 of this embodiment is not limited to three, and may be four or more, and may be set according to actual needs.

[0157] like Figure 19 to Figure 22 As shown, Fig.19 is a simplified structural diagram of the capacitor 120 in the fourth embodiment of the present application, Fig. 20 is a top view of the capacitor 120 in the fourth embodiment of the present application, Fig.21 for Fig. 20 EE cross-sectional view of capacitor 120, Fig. 22 Schematic diagram of the structure of the sub-capacitor 1 in the fourth embodiment of the present application.

[0158] The capacitor 120 in this embodiment is Figure 5 to Figure 12 The main difference between the capacitor 120 shown in FIG. 1 is that the arrangement of the electrodes 13 of the capacitor unit 12 in the sub-capacitor 1 is different. Figure 5 to Figure 12 The first electrode 131 and the second electrode 132 of the sub-capacitor 1 shown in the figure are both arranged on the front side 117a of the carrier layer 11 of the sub-capacitor 1, while in this embodiment, the second electrode 132 of the sub-capacitor 1 is arranged on the front side 117a of the carrier layer 11, and the first electrode 131 of the sub-capacitor 1 is arranged on the back side 117b of the carrier layer 11, as described in detail as follows:

[0159] like Fig.19 As shown, the capacitor 120 includes two stacked sub-capacitors 1, the two sub-capacitors 1 are respectively a first sub-capacitor 1a and a second sub-capacitor 1b, and the first sub-capacitor 1a and the second sub-capacitor 1b are two adjacent sub-capacitors 1. The capacitor unit 12a is located on the carrier layer 11 of the first sub-capacitor 1a, the second electrode 132 of the capacitor unit 12a is located on the front side 117a of the carrier layer 11, and the first electrode 131 of the capacitor unit 12a is located on the back side 117b of the carrier layer 11; the capacitor unit 12b is located on the carrier layer 11 of the second sub-capacitor 1b, the second electrode 132 of the capacitor unit 12b is located on the front side 117a of the carrier layer 11, and the first electrode 131 of the capacitor unit 12b is located on the back side 117b of the carrier layer 11. The positions of the capacitor units 12a and 12b correspond.

[0160] The back side 117b of the first sub-capacitor 1a is adjacent to the front side 117a of the second sub-capacitor 1b, the second electrode 132 of the capacitor unit 12a is electrically connected to the second electrode 132 of the capacitor unit 12b through the second conductive hole 22, and the first electrode 131 of the capacitor unit 12a is electrically connected to the first electrode 131 of the capacitor unit 12b through the first conductive hole 21, so that the capacitor unit 12a is connected in parallel with the capacitor unit 12b.

[0161] Specifically, the second conductive via 22 penetrates the carrier layer 11 of the first sub-capacitor 1a, and the first end (upper end in the figure) of the second conductive via 22 is electrically connected to the second electrode 132 of the capacitor unit 12a, and the second end (lower end in the figure) of the second conductive via 22 is electrically connected to the second electrode 132 of the capacitor unit 12b through the interconnection structure 3. The first conductive via 21 penetrates the carrier layer 11 of the second sub-capacitor 1b, and the first end (lower end in the figure) of the first conductive via 21 is electrically connected to the first electrode 131 of the capacitor unit 12b, and the second end (upper end in the figure) of the first conductive via 21 is electrically connected to the first electrode 131 of the capacitor unit 12a through the interconnection structure 3. That is: in two adjacent sub-capacitors 1, for any one conductive via 2, the conductive via 2 penetrates the carrier layer 11 of one of the sub-capacitors 1, and the first end of the conductive via 2 is electrically connected to the electrode 13 of one of the sub-capacitors 1, and the second end of the conductive via 2 is electrically connected to the electrode 13 of the other sub-capacitor 1 through the interconnection structure 3.

[0162] In some embodiments, Fig. 20 and Fig.21 As shown, the back surface 117b of the first sub-capacitor 1a is provided with a first rewiring layer 14 covering the second end (lower end in the figure) of the second conductive via 22, and the first rewiring layer 14 is electrically connected to the second end of the second conductive via 22. The front surface 117a of the second sub-capacitor 1b is provided with a second rewiring layer 15 covering the second electrode 132 thereof, and the second rewiring layer 15 is electrically connected to the second electrode 132 of the second sub-capacitor 1b. An interconnection structure 3 is provided between the first rewiring layer 14 and the second rewiring layer 15 to electrically connect the second end of the second conductive via 22 to the second electrode 132 of the second sub-capacitor 1b.

[0163] In some embodiments, Fig.21 As shown, the front side 117a of the first sub-capacitor 1a is provided with a second redistribution layer 15 covering the first end (upper end in the figure) of the second conductive hole 22, and the second redistribution layer 15 electrically connects the first end of the second conductive hole 22 with the second electrode 132 of the first sub-capacitor 1a.

[0164] In some embodiments, Fig. 20 and Fig.21 As shown, the front side 117a of the second sub-capacitor 1b is provided with a first redistribution layer 14 covering the second end (upper end in the figure) of the first conductive via 21, and the first redistribution layer 14 is electrically connected to the second end of the first conductive via 21, and the back side 117b of the first sub-capacitor 1a is provided with a second redistribution layer 15 covering the first electrode 131 thereof, and the second redistribution layer 15 is electrically connected to the first electrode 131 of the first sub-capacitor 1a. An interconnection structure 3 is provided between the first redistribution layer 14 and the second redistribution layer 15 to electrically connect the second end of the first conductive via 21 to the first electrode 131 of the first sub-capacitor 1a.

[0165] In some embodiments, Fig.21 As shown, the back side 117b of the second sub-capacitor 1b is provided with a second redistribution layer 15 covering the first end (lower end in the figure) of the first conductive via 21, and the second redistribution layer 15 electrically connects the first end of the first conductive via 21 with the first electrode 131 of the second sub-capacitor 1b.

[0166] In some embodiments, Fig.21 As shown, the first redistribution layer 14 and the second redistribution layer 15 on the back side 117b of the first sub-capacitor 1a are the same redistribution layer and are made by the same process. Of course, the first redistribution layer 14 and the second redistribution layer 15 on the back side 117b of the first sub-capacitor 1a can also be separated and made by different processes.

[0167] In some embodiments, Fig.21As shown, the first redistribution layer 14 and the second redistribution layer 15 on the front side 117a of the second sub-capacitor 1b are the same redistribution layer and are made by the same process. Of course, the first redistribution layer 14 and the second redistribution layer 15 on the front side 117a of the second sub-capacitor 1b can also be separated and made by different processes.

[0168] In some embodiments, Fig. 22 As shown, the carrier layer 11 of the sub-capacitor 1 includes a substrate layer 111, a first groove 112 is provided on the substrate layer 111, a portion (or the whole) of the capacitor unit 12 is arranged in the first groove 112, and the capacitor unit 12 includes a first capacitor conductive layer 121, a second capacitor conductive layer 122, and a dielectric layer 123 arranged between the first capacitor conductive layer 121 and the second capacitor conductive layer 122.

[0169] The carrier layer 11 of the sub-capacitor 1 also includes an upper insulating layer 113, which is arranged on the substrate layer 111 and covers the capacitor unit 12. The second electrode 132 of the capacitor unit 12 is arranged on the upper insulating layer 113. The upper insulating layer 113 is provided with a second connection via 115, and the second connection via 115 is connected between the second electrode 132 and the second capacitor conductive layer 122; the first electrode 131 of the capacitor unit 12 is arranged on the lower surface of the substrate layer 111 (that is, the back side 117b of the carrier layer 11), and the lower surface of the substrate layer 111 is provided with a first connection via 114, and the first connection via 114 is arranged between the first electrode 131 and the first capacitor conductive layer 121.

[0170] In some embodiments, Fig. 22 As shown, the first capacitor conductive layer 121 fills the first groove 112, a plurality of second grooves 1211 are spaced apart on the first capacitor conductive layer 121, the dielectric layer 123 includes a first dielectric layer 1231 and a second dielectric layer 1232, the first dielectric layer 1231 covers the groove wall of the second groove 1211, and the second dielectric layer 1232 is arranged at the edge of the second groove 1211 and connected to the first dielectric layer 1231;

[0171] The second capacitor conductive layer 122 includes a filling layer 1221 and a connecting layer 1222. The filling layer 1221 is disposed on the first dielectric layer 1231, and the filling layer 1221 and the first dielectric layer 1231 fill the second trench 1211. The connecting layer 1222 is disposed on the second dielectric layer 1232 and the filling layer 1221. The second connecting via 115 is connected between the connecting layer 1222 and the second electrode 132.

[0172] The first electrode 131 and the second electrode 132 of the capacitor unit 12 may be provided by one or more. For example, Fig. 22As shown, the capacitor unit 12 has two first electrodes 131 and four second electrodes 132 , each of the first electrodes 131 is electrically connected to the first capacitor conductive layer 121 through a first connection via 114 , and each of the second electrodes 132 is electrically connected to the connection layer 1222 through a second connection via 115 .

[0173] like Fig.23 As shown, Fig.23 FIG. 1 is a simplified structural diagram of the capacitor 120 in the fifth embodiment of the present application. The capacitor 120 in this embodiment is Figure 19 to Figure 22 The main difference between the capacitor 120 shown in FIG. 1 and FIG. 2 is that the number of sub-capacitors 1 in the capacitor 120 is different, as described below:

[0174] Capacitor 120 includes three sub-capacitors 1 arranged in a stacked manner, and the three sub-capacitors 1 are respectively a first sub-capacitor 1a, a second sub-capacitor 1b and a third sub-capacitor 1c. The first sub-capacitor 1a and the second sub-capacitor 1b are two adjacent sub-capacitors 1, and the second sub-capacitor 1b and the third sub-capacitor 1c are two adjacent sub-capacitors 1. The back side 117b of the first sub-capacitor 1a is arranged adjacent to the front side 117a of the second sub-capacitor 1b, and the back side 117b of the second sub-capacitor 1b is arranged adjacent to the front side 117a of the third sub-capacitor 1c.

[0175] Capacitor unit 12a is located on the carrier layer 11 of the first sub-capacitor 1a, the second electrode 132 of capacitor unit 12a is located on the front side 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12a is located on the back side 117b of the carrier layer 11; capacitor unit 12b is located on the carrier layer 11 of the second sub-capacitor 1b, the second electrode 132 of capacitor unit 12b is located on the front side 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12b is located on the back side 117b of the carrier layer 11; capacitor unit 12c is located on the carrier layer 11 of the third sub-capacitor 1c, the second electrode 132 of capacitor unit 12c is located on the front side 117a of the carrier layer 11, and the first electrode 131 of capacitor unit 12c is located on the back side 117b of the carrier layer 11. The positions of capacitor unit 12a, capacitor unit 12b and capacitor unit 12c correspond to each other.

[0176] The first sub-capacitor 1a is provided with a second conductive hole 22 , the second sub-capacitor 1b is provided with a first conductive hole 21 and a second conductive hole 22 , and the third sub-capacitor 1c is provided with a first conductive hole 21 .

[0177] For the first sub-capacitor 1a and the second sub-capacitor 1b, the second electrodes 132 of the capacitor unit 12a and the capacitor unit 12b are electrically connected through the second conductive hole 22 on the first sub-capacitor 1a, and the first electrodes 131 of the capacitor unit 12a and the capacitor unit 12b are electrically connected through the first conductive hole 21 on the second sub-capacitor 1b, so that the capacitor unit 12a and the capacitor unit 12b are connected in parallel.

[0178] For the second sub-capacitor 1b and the third sub-capacitor 1c, the second electrodes 132 of the capacitor unit 12b and the capacitor unit 12c are electrically connected through the second conductive hole 22 on the second sub-capacitor 1b, and the first electrodes 131 of the capacitor unit 12b and the capacitor unit 12c are electrically connected through the first conductive hole 21 on the third sub-capacitor 1c, so that the capacitor unit 12b and the capacitor unit 12c are connected in parallel.

[0179] The number of the capacitor unit 12 in each sub-capacitor 1 may be one or more, and the capacitor units 12 in corresponding positions in the plurality of sub-capacitors 1 are connected in parallel through the conductive holes 2 .

[0180] In this embodiment, the number of sub-capacitors 1 in the capacitor 120 is not limited to three, and can also be four or more, which can be set according to actual needs.

[0181] like Figure 24a to Figure 24g As shown, Figure 24a to Figure 24g The schematic diagram of the manufacturing process of the capacitor 120 in the first embodiment of the present application is shown. The capacitor 120 includes a plurality of sub-capacitors 1, each of which includes a carrier layer 11 and a capacitor unit 12 embedded in the carrier layer 11, and the capacitor unit 12 has an electrode 13. Fig.25a As shown, the manufacturing method of the capacitor 120 includes:

[0182] S200, such as Figure 24f and Figure 24g As shown, a plurality of sub-capacitors 1 are stacked.

[0183] At least one of the two adjacent sub-capacitors 1 is provided with a conductive hole 2 , and the conductive hole 2 electrically connects the electrodes 13 of the two adjacent sub-capacitors 1 , so that the capacitor units 12 of the two adjacent sub-capacitors 1 are connected in parallel.

[0184] For example, Figure 24f and Figure 24g As shown, two adjacent sub-capacitors 1 are respectively a first sub-capacitor 1a and a second sub-capacitor 1b. A conductive hole 2 is provided on the supporting layer 11 of the first sub-capacitor 1a. The conductive hole 2 electrically connects the electrode 13 of the capacitor unit 12a of the first sub-capacitor 1a and the electrode 13 of the capacitor unit 12b in the second sub-capacitor 1b, so that the capacitor unit 12a is connected in parallel with the capacitor unit 12b.

[0185] The number of capacitor units 12 in the first sub-capacitor 1a and the second sub-capacitor 1b may be one or more, for example Figure 24f and Figure 24g As shown, the number of capacitor units 12 in the first sub-capacitor 1 a and the second sub-capacitor 1 b is two, and the capacitor units 12 in the first sub-capacitor 1 a and the second sub-capacitor 1 b that have corresponding positions are electrically connected through the conductive hole 2 .

[0186] In some embodiments, Fig.25a As shown, before the two adjacent sub-capacitors 1 are stacked, the method further includes:

[0187] S100, such as Figure 24a to Figure 24d As shown, a conductive hole 2 is provided on at least one of two adjacent sub-capacitors 1. That is, the conductive hole 2 is provided after the sub-capacitor 1 is manufactured, that is, the conductive hole 2 is provided on the carrier layer 11 of the finished sub-capacitor 1.

[0188] Such an arrangement can reduce the damage to the conductive hole 2 caused by the production and transportation process of the sub-capacitor 1, thereby improving the conductive reliability of the conductive hole 2; at the same time, this can also improve the versatility of the sub-capacitor 1, that is: the sub-capacitor 1 without the conductive hole 2 can be used alone, and the sub-capacitor 1 with the conductive hole 2 can be stacked together to assemble into a capacitor 120.

[0189] Of course, the conductive hole 2 can also be provided during the manufacturing stage of the sub-capacitor 1 . For example, the conductive hole 2 can be provided on the carrier layer 11 after the capacitor unit 12 is provided on the carrier layer 11 .

[0190] In some embodiments, Fig.25b As shown, for a sub-capacitor 1 to be provided with a conductive hole 2, providing the conductive hole 2 on the sub-capacitor 1 includes:

[0191] S110, such as Fig.24a As shown, a blind hole 25 is provided on the front side 117 a of the carrier layer 11 .

[0192] Among them, the blind hole 25 can be set between two adjacent capacitor units 12. The blind hole 25 can be formed by an etching process. For example, the blind hole 25 can be formed by laser etching. The diameter of the blind hole 25 is 1 to 10 μm, and the depth of the blind hole 25 is 30 to 150 μm. Of course, it is not limited to this. The diameter and depth of the blind hole 25 can also be set to other values ​​according to actual conditions.

[0193] S120, such as Figure 24b As shown, the conductor 24 is disposed in the blind hole 25 .

[0194] The material of the conductor 24 may be metal, such as copper or tungsten, etc. The conductor 24 may be formed in the blind hole 25 by electroplating, or may be directly filled in the blind hole 25, which is not specifically limited here.

[0195] In the case where the conductor 24 can be formed in the blind hole 25 by electroplating, before the conductor 24 is disposed in the blind hole 25, an insulating layer and a seed layer can be sequentially disposed on the hole wall of the blind hole 25. The seed layer can provide conductivity to facilitate electroplating, and the material of the seed layer can be titanium and copper, or gold, depending on the actual situation.

[0196] S130, such as Fig.24d As shown, the carrier layer 11 is thinned from the back side of the carrier layer 11 so that the conductor 24 is exposed from the back side 117 b of the carrier layer 11 to form the conductive hole 2 .

[0197] The back side 117b of the carrier layer 11 may be ground to thin the carrier layer 11. However, the present invention is not limited thereto, and the back side 117b of the carrier layer 11 may be laser etched to thin the carrier layer 11. Along the thickness direction of the carrier layer 11, the front side 117a is one side surface of the carrier layer 11, and the back side 117b is the other side surface of the carrier layer 11.

[0198] In this embodiment, the conductive hole 2 is formed by making a blind hole 25 + setting a conductor 24 + thinning the back side of the carrier layer 11. The making of the conductive hole 2 has little damage to other structures of the sub-capacitor 1, thereby ensuring the reliability of the sub-capacitor 1. At the same time, the conductor 24 is set in the blind hole 25. Before the back side of the carrier layer 11 is thinned, the bottom of the blind hole 25 can support the conductor 24, so there is no need to set other structures to support the conductor 24, thereby simplifying the manufacturing process of the conductive hole 2.

[0199] Of course, the conductive hole 2 can also be made by other methods, for example, a second redistribution layer 15 is set on the front side 117a of the carrier layer 11, and then a through hole is set on the back side 117b of the carrier layer 11, the through hole passes through the carrier layer 11, and the second redistribution layer 15 covers the opening of the through hole; a conductor 24 is set in the through hole to form the conductive hole 2, wherein the conductor 24 is electrically connected to the second redistribution layer 15.

[0200] In some embodiments, Figure 24f and Figure 24g As shown, the electrodes 13 of the capacitor unit 12 are all arranged on the front side 117a of the carrier layer 11; the conductive holes 2 connected between the electrodes 13 of two adjacent sub-capacitors 1 are all arranged on the first sub-capacitor 1a and penetrate the carrier layer 11 of the first sub-capacitor 1a.

[0201] The two adjacent sub-capacitors 1 are stacked and arranged, comprising:

[0202] S210, such as Figure 24f and Figure 24g As shown, the electrode 13 of the second sub-capacitor 1b is electrically connected to the conductive hole 2 on the first sub-capacitor 1a through the interconnection structure 3, so that the first sub-capacitor 1a and the second sub-capacitor 1b are stacked.

[0203] The electrode 13 of the second sub-capacitor 1b is electrically connected to the conductive hole 2 on the first sub-capacitor 1a through the interconnection structure 3. In this way, the interconnection structure 3 can electrically connect the conductive holes 2 at different positions to the electrode 13 of the second sub-capacitor 1b. Then, the conductive hole 2 does not need to be set at the position corresponding to the electrode 13 of the second sub-capacitor 1b, thereby facilitating the setting of the conductive hole 2.

[0204] In some embodiments, the electrode 13 of the second sub-capacitor 1 b is electrically connected to the conductive via 2 on the first sub-capacitor 1 a through the interconnect structure 3 , including:

[0205] S211, such as Fig.24e As shown, a first redistribution layer 14 is disposed on the back surface 117 b of the carrier layer 11 of the first sub-capacitor 1 a to be electrically connected to the conductive via 2 .

[0206] S212, such as Figure 24f As shown, a second redistribution layer 15 is disposed on the front surface 117a of the carrier layer 11 of the second sub-capacitor 1b to be electrically connected to the electrode 13 of the second sub-capacitor 1b.

[0207] S213, such as Figure 24g As shown, the second redistribution layer 15 is electrically connected to the first redistribution layer 14 through the interconnect structure 3 .

[0208] Of course, the order of the above steps S211 and S212 can also be reversed, that is, S212 is executed first, and then S211 is executed.

[0209] By providing the first redistribution layer 14, the first redistribution layer 14 can electrically connect the interconnection structure 3 at different positions to the second end of the conductive hole 2, so the interconnection structure 3 does not need to be provided at the position corresponding to the second end of the conductive hole 2, thereby facilitating the provision of the interconnection structure 3. By providing the second redistribution layer 15, the second redistribution layer 15 can electrically connect the interconnection structure 3 at different positions to the electrode 13 of the second sub-capacitor 1b, so the interconnection structure 3 does not need to be provided at the position corresponding to the electrode 13 of the second sub-capacitor 1b, thereby facilitating the provision of the interconnection structure 3.

[0210] In some embodiments, before the second sub-capacitor 1b is electrically connected to the conductive via 2 on the first sub-capacitor 1a through the interconnect structure 3, the method further includes: Fig.24c As shown, a second redistribution layer 15 is disposed on the front surface 117 a of the carrier layer 11 of the first sub-capacitor 1 a to electrically connect the electrode 13 of the first sub-capacitor 1 a and the conductive via 2 .

[0211] By setting the second redistribution layer 15, the second redistribution layer 15 can electrically connect the conductive holes 2 at different positions with the electrodes 13 of the first sub-capacitor 1a, so the conductive holes 2 do not need to be set at the positions of the electrodes 13 of the first sub-capacitor 1a, thereby facilitating the setting of the conductive holes 2.

[0212] In some embodiments, Figure 24b and Fig.24c As shown, after the conductor 24 is arranged in the blind hole 25, the second redistribution layer 15 is arranged on the front surface 117a of the carrier layer 11 of the first sub-capacitor 1a. In this way, after the back surface 117b of the carrier layer 11 is thinned, it is not necessary to flip the first sub-capacitor 1a to arrange the first redistribution layer 14, thereby reducing the number of flipping of the first sub-capacitor 1a and simplifying the manufacturing process of the capacitor.

[0213] Of course, after the conductive via 2 is fabricated on the first sub-capacitor 1 a , the second redistribution layer 15 may be disposed on the front surface 117 a of the carrier layer 11 of the first sub-capacitor 1 a .

[0214] The features in the embodiment of the method for manufacturing the capacitor 120 that are the same as or similar to those in the above-mentioned product embodiment of the capacitor 120 may be specifically referred to the description in the above-mentioned product embodiment of the capacitor 120 and will not be repeated here.

[0215] The types of section lines in the drawings of this application are used to distinguish different components and should not be understood as limiting the materials of the components. The drawings of this application are mainly used to illustrate the structure of the product and are not shown according to the actual proportion of the product.

[0216] Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to the implementation mode. On the contrary, the purpose of introducing the application in conjunction with the implementation mode is to cover other options or modifications that may be extended based on the claims of this application. In order to provide a deep understanding of the present application, many specific details will be included in the above description. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other without conflict.

[0217] In the embodiments of the present application, the terms "first", "second", "third", "fourth", "fifth", and "sixth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third", "fourth", "fifth", and "sixth" may explicitly or implicitly include one or more of the features.

[0218] In the embodiments of the present application, "and / or" is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0219] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The directional terms mentioned in the embodiments of the present application, such as "upper", "lower", "left", "right", "inside", "outside", etc., are only reference directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. "Multiple" means at least two.

[0220] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0221] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A capacitor, characterized in that: It comprises a plurality of sub-capacitors (1) arranged in a stacked manner; each of the plurality of sub-capacitors (1) comprises a carrier layer (11), a capacitor unit (12) embedded in the carrier layer (11), and the capacitor unit (12) has an electrode (13); Among the plurality of sub-capacitors (1), at least one of two adjacent sub-capacitors (1) is provided with a conductive hole (2), and the conductive hole (2) electrically connects the electrodes (13) of the two adjacent sub-capacitors (1) so that the capacitance units (12) of the two adjacent sub-capacitors (1) are connected in parallel.

2. The capacitor according to claim 1, characterized in that In the two adjacent sub-capacitors (1), for any one of the conductive holes (2), the conductive hole (2) penetrates the carrier layer (11) of one of the sub-capacitors (1), and the first end of the conductive hole (2) is electrically connected to the electrode (13) of one of the sub-capacitors (1), and the second end of the conductive hole (2) is electrically connected to the electrode (13) of the other sub-capacitor (1) through an interconnection structure (3).

3. The capacitor according to claim 2, characterized in that The interconnect structure (3) comprises a bump (31), a first pad (32) and a second pad (33); the first pad (32) is arranged on one of the sub-capacitors (1) and is electrically connected to the second end of the conductive hole (2); the second pad (33) is arranged on the other sub-capacitor (1) and is electrically connected to the electrode (13) of the other sub-capacitor (1); the bump (31) is arranged between the first pad (32) and the second pad (33).

4. The capacitor according to claim 2, characterized in that The interconnect structure (3) is a hybrid bonding structure and comprises a plurality of third pads (34) and a plurality of fourth pads (35), each of the third pads (34) being arranged on one of the sub-capacitors (1) and being electrically connected to the second end of the conductive hole (2); each of the fourth pads (35) being arranged on the other sub-capacitor (1) and being electrically connected to the electrode (13) of the other sub-capacitor (1), and each of the third pads (34) being in contact with the corresponding fourth pad (35).

5. The capacitor according to any one of claims 2 to 4, characterized in that: One of the sub-capacitors (1) further comprises a first redistribution layer (14), the first redistribution layer (14) covering the second end of the conductive hole (2); the first redistribution layer (14) comprises a first insulating layer (141), and a first conductive layer (142) and a first via hole (143) embedded in the first insulating layer (141), the first via hole (143) being connected between the first conductive layer (142) and the second end of the conductive hole (2); a portion of the interconnection structure (3) is disposed on the first insulating layer (141) and is electrically connected to the first conductive layer (142).

6. The capacitor according to claim 5, characterized in that The first redistribution layer (14) further comprises a fifth pad (144), wherein the fifth pad (144) is embedded in the first insulating layer (141), and the fifth pad (144) is arranged at the second end of the conductive hole (2), and the first via (143) is connected between the fifth pad (144) and the first conductive layer (142).

7. The capacitor according to any one of claims 2 to 6, characterized in that: The other sub-capacitor (1) further comprises a second redistribution layer (15), wherein the second redistribution layer (15) covers the electrode (13) of the other sub-capacitor (1); the second redistribution layer (15) comprises a second insulating layer (151), and a second conductive layer (152) and a second via hole (153) embedded in the second insulating layer (151), wherein the second via hole (153) is connected between the second conductive layer (152) and the electrode (13) of the other sub-capacitor (1); a portion of the interconnection structure (3) is disposed on the second insulating layer (151) and is electrically connected to the second conductive layer (152).

8. The capacitor according to any one of claims 1 to 6, characterized in that: The carrier layer (11) comprises a front side (117a) and a back side (117b) arranged opposite to each other, the electrode (13) comprises a first electrode (131) and a second electrode (132), and the first electrode (131) and the second electrode (132) are both arranged on the front side (117a) of the carrier layer (11); The two adjacent sub-capacitors (1) are respectively a first sub-capacitor (1a) and a second sub-capacitor (1b); the back surface (117b) of the first sub-capacitor (1a) and the front surface (117a) of the second sub-capacitor (1b) are arranged adjacent to each other; the conductive hole (2) connected between the first electrodes (131) of the two adjacent sub-capacitors (1) and the conductive hole (2) connected between the second electrodes (132) of the two adjacent sub-capacitors (1) are both arranged on the first sub-capacitor (1a) and penetrate the supporting layer (11) of the first sub-capacitor (1a).

9. The capacitor according to claim 8, characterized in that The first sub-capacitor (1a) further comprises a second redistribution layer (15), the second redistribution layer (15) covering the front surface (117a) of the carrier layer (11); the second redistribution layer (15) comprises a second insulating layer (151), and a second conductive layer (152) and a second via (153) embedded in the second insulating layer (151); The second conductive layer (152) comprises a first sublayer (1521) and a second sublayer (1522); the first sublayer (1521) is electrically connected to the first electrode (131) and a portion of the conductive holes (2) through the second via holes (153), and the second sublayer (1522) is electrically connected to the second electrode (132) and another portion of the conductive holes (2) through the second via holes (153).

10. The capacitor according to claim 9, characterized in that The second redistribution layer (15) further comprises a sixth pad (154), wherein the sixth pad (154) is embedded in the second insulating layer (151), and the sixth pad (154) is arranged at the first end of the conductive hole (2) and is electrically connected to the corresponding second via hole (153).

11. The capacitor according to claim 9 or 10, characterized in that: In the first sub-capacitor (1a), a capacitor array (116) is provided on the carrier layer (11), the capacitor array (116) comprises a plurality of capacitor units (12), and a first conductive hole (21) and a second conductive hole (22) are provided between two adjacent capacitor units (12) in the capacitor array (116); The first conductive hole (21) is the conductive hole (2) electrically connected to the first electrode (131), and the second conductive hole (22) is the conductive hole (2) electrically connected to the second electrode (132).

12. The capacitor according to claim 11, characterized in that In the capacitor array (116), a plurality of the capacitor units (12) are arranged along a first direction (Y), and the first electrodes (131) of the capacitor units (12) form a first electrode array (133), and the second electrodes (132) of the capacitor units (12) form a second electrode array (134), and the second electrode array (134) and the first electrode array (133) are arranged in a spaced relationship along a second direction (X), and the second direction (X) is perpendicular to the first direction (Y); Along the first direction (Y), the first conductive hole (21) is arranged between two adjacent first electrodes (131), and the second conductive hole (22) is arranged between two adjacent second electrodes (132).

13. The capacitor according to claim 11, characterized in that In the capacitor array (116), a plurality of the capacitor units (12) are arranged along a first direction (Y), and the first electrodes (131) of the capacitor units (12) form a first electrode array (133), and the second electrodes (132) of the capacitor units (12) form a second electrode array (134), and the second electrode array (134) and the first electrode array (133) are arranged in a spaced relationship along a second direction (X), and the second direction (X) is perpendicular to the first direction (Y); The first conductive holes (21) and the second conductive holes (22) are alternately arranged along the first direction (Y) to form a conductive hole array (23); the conductive hole array (23) is located between the first electrode array (133) and the second electrode array (134); and adjacent first conductive holes (21) and second conductive holes (22) in the conductive hole array (23) are respectively located on both sides of the corresponding capacitor unit (12).

14. A chip, characterized in that: It comprises a carrier substrate (110), a bare chip (130) arranged on the carrier substrate (110), and a capacitor (120) according to any one of claims 1 to 13, wherein the capacitor (120) is arranged on the carrier substrate (110).

15. The chip according to claim 14, characterized in that: The capacitor (120) is arranged on a side surface of the carrier substrate (110) away from the bare chip (130), and a projection of the capacitor (120) on the carrier substrate (110) at least partially overlaps with a projection of a core (135) of the bare chip (130) on the carrier substrate (110).

16. An electronic device, characterized in that: It comprises a circuit board (400) and the chip (100) according to claim 14 or 15, wherein the chip (100) is arranged on the circuit board (400).

17. The electronic device according to claim 16, characterized in that: A first capacitor (170) is provided on a surface of a side of the circuit board (400) away from the bare chip (130), and a projection of the first capacitor (170) on the carrier substrate (110) at least partially overlaps with a projection of the core (135) of the bare chip (130) on the carrier substrate (110).

18. A method for manufacturing a capacitor, characterized in that: The capacitor comprises a plurality of sub-capacitors (1), each of the plurality of sub-capacitors (1) comprising a carrier layer (11), a capacitor unit (12) embedded in the carrier layer (11), and the capacitor unit (12) having an electrode (13); The method for manufacturing the capacitor comprises: stacking the plurality of sub-capacitors (1); At least one of the two adjacent sub-capacitors (1) is provided with a conductive hole (2), and the conductive hole (2) electrically connects the electrodes (13) of the two adjacent sub-capacitors (1) so that the capacitor units (12) of the two adjacent sub-capacitors (1) are connected in parallel.

19. The method for manufacturing a capacitor according to claim 18, wherein: Before stacking the two adjacent sub-capacitors (1), the method further comprises: The conductive hole (2) is provided on at least one of the two adjacent sub-capacitors (1).

20. The method for manufacturing a capacitor according to claim 19, wherein: For a sub-capacitor (1) on which the conductive hole (2) is to be provided, providing the conductive hole (2) on the sub-capacitor (1), comprising: A blind hole (25) is provided on the front side (117a) of the bearing layer (11); placing a conductor (24) in the blind hole (25); The carrier layer (11) is thinned from the back side of the carrier layer (11) so that the conductor (24) is exposed from the back side (117b) of the carrier layer (11) to form the conductive hole (2).

21. The method for manufacturing a capacitor according to claim 19 or 20, characterized in that: The electrodes (13) of the capacitor units (12) are all arranged on the front side (117a) of the carrier layer (11); the two adjacent sub-capacitors (1) are respectively a first sub-capacitor (1a) and a second sub-capacitor (1b); the conductive holes (2) connected between the electrodes (13) of the two adjacent sub-capacitors (1) are all arranged on the first sub-capacitor (1a) and penetrate the carrier layer (11) of the first sub-capacitor (1a); The two adjacent sub-capacitors (1) are stacked and arranged, comprising: The electrode (13) of the second sub-capacitor (1b) is electrically connected to the conductive hole (2) on the first sub-capacitor (1a) through an interconnection structure (3), so that the first sub-capacitor (1a) and the second sub-capacitor (1b) are stacked.

22. The method for manufacturing a capacitor according to claim 21, characterized in that: The electrode (13) of the second sub-capacitor (1b) is electrically connected to the conductive hole (2) on the first sub-capacitor (1a) through an interconnection structure (3), comprising: A first redistribution layer (14) is provided on the back side (117b) of the carrier layer (11) of the first sub-capacitor (1a) to be electrically connected to the conductive hole (2); A second redistribution layer (15) is provided on the front side (117a) of the carrier layer (11) of the second sub-capacitor (1b) to be electrically connected to the electrode (13) of the second sub-capacitor (1b); The second redistribution layer (15) is electrically connected to the first redistribution layer (14) through the interconnection structure (3).

23. The method for manufacturing a capacitor according to claim 21, characterized in that: Before the second sub-capacitor (1b) is electrically connected to the conductive hole (2) on the first sub-capacitor (1a) through the interconnection structure (3), the method further comprises: A second redistribution layer (15) is provided on the front side (117a) of the carrier layer (11) of the first sub-capacitor (1a) to electrically connect the electrode (13) of the first sub-capacitor (1a) and the conductive hole (2).

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