A surface polishing method for a semiconductor device

Abstract

The application belongs to the technical field of semiconductor manufacturing, and provides a surface grinding method of a semiconductor device, comprising the following steps: obtaining a first thickness of a surface structure layer of the semiconductor device; calculating a second thickness of an oxide layer to be removed according to the first thickness; setting a target thickness of a remaining oxide layer to be reserved; calculating a third thickness by using the target thickness and the second thickness; depositing the oxide layer with the third thickness on the surface structure layer; and removing the oxide layer with the second thickness. The third thickness of the oxide layer to be deposited is calculated in advance, so that the planarization effect of the semiconductor device can be ensured, the grinding amount can be reduced by removing the oxide layer with the second thickness of a smaller value, the production capacity can be avoided, the production efficiency can be improved, the third thickness can be changed accordingly with the change of the first thickness, the method is suitable for products of various specifications, the adaptability of the method is improved, and the method has great product promotion value.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a surface polishing method for semiconductor devices. Background Technology

[0002] With societal development and advancements in semiconductor technology, the market demands increasingly higher performance from semiconductor devices. To enhance product competitiveness, new semiconductor manufacturing processes are needed to improve performance. In semiconductor manufacturing, after the gate layer and / or metal layer are formed on the silicon wafer surface, they need to be patterned to create gate and / or metal layers with specific patterns. These patterned gate and / or metal layers contain stepped structures introduced by the patterning process, resulting in an uneven surface on the silicon wafer. To achieve a smooth silicon wafer surface, a dielectric layer needs to be deposited on the gate and / or metal layers to cover the surface. By grinding the deposited dielectric layer, a portion of the dielectric layer is removed, thereby achieving surface planarization of the silicon wafer.

[0003] However, due to the presence of steps on the silicon wafer surface, the deposited dielectric layer is also uneven. When grinding the dielectric layer to remove it, if the amount of grinding is small, the steps on the surface cannot be completely eliminated, thus failing to achieve the goal of planarization. This can lead to problems such as tungsten residue in subsequent processes. When the dielectric layer is deposited to a large thickness, although grinding can eliminate the surface steps and achieve the goal of planarization, it will introduce problems such as excessive grinding time, uneven silicon wafer film thickness, and wasted production capacity.

[0004] In view of this, in order to solve the above problems, this application provides a surface polishing method for semiconductor devices, which can quickly determine the thickness of the dielectric layer to be deposited on the silicon wafer, avoid production waste, and at the same time ensure that the surface planarization can be achieved through polishing. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a surface polishing method for semiconductor devices to solve the problems of wasted production capacity or inability to achieve planarization during silicon wafer surface planarization in the prior art, and to accurately determine the thickness of the oxide layer to be deposited on the silicon wafer surface.

[0006] To achieve the above and other related objectives, this application provides a surface polishing method for semiconductor devices, used to planarize the surface of a semiconductor device, wherein the surface of the semiconductor device has a patterned surface structure layer, comprising the following steps:

[0007] The thickness of the surface structure layer is obtained and recorded as the first thickness;

[0008] The thickness that needs to be removed by grinding is calculated based on the first thickness and recorded as the second thickness;

[0009] Set the thickness of the remaining oxide layer on the surface structure layer after planarization and record it as the target thickness;

[0010] The third thickness is calculated based on the target thickness and the second thickness;

[0011] An oxide layer of a third thickness is formed on the surface structure layer;

[0012] The oxide layer of the second thickness is removed to obtain a remaining oxide layer having the target thickness, in order to planarize the surface of the semiconductor device.

[0013] Optionally, the surface structure layer includes a gate layer, and the first thickness is the thickness of the gate layer.

[0014] Optionally, the surface structure layer includes a metal layer and an adhesive layer, wherein the first thickness is the sum of the thicknesses of the metal layer and the adhesive layer.

[0015] Optionally, the thickness to be removed by grinding is calculated based on the first thickness and recorded as the second thickness, including the following steps:

[0016] An exponential relationship is established between the second thickness and the surface transmittance of the semiconductor device, and the exponential relationship is denoted as h2=k1*a^(1-S), where h2 is the second thickness, a is the base parameter, k1 is the first coefficient, and S is the surface transmittance;

[0017] Based on the pattern structure of the surface structure layer, the surface transmittance S of the semiconductor device is calculated;

[0018] The first coefficient k1 is calculated using the first thickness;

[0019] Substituting the surface transmittance S and the first coefficient k1 into the above expression, the second thickness h2 is obtained.

[0020] Optionally, calculating the surface transmittance S of the semiconductor device includes the following steps:

[0021] In a top view of the semiconductor device, the coverage area s1 of the surface structure layer and the coverage area s2 of the oxide layer are obtained;

[0022] The surface transmittance S was calculated to be 1 - s1 / s2.

[0023] Optionally, the formula for calculating the first coefficient k1 is k1 = (m + 1) * q, where m is the first thickness, in units of... q is a preset second coefficient.

[0024] Optionally, the second coefficient q satisfies 1.5≤q≤1.7.

[0025] Optionally, the base parameter a satisfies 0.8 < a < 1.

[0026] Optionally, the base parameter a takes a value of 0.9 to 0.99.

[0027] Optionally, the third thickness is the sum of the second thickness and the target thickness, and the oxide layer of the second thickness is removed by grinding with a grinding device to planarize the surface of the semiconductor device.

[0028] As described above, the surface polishing method for semiconductor devices provided in this application has at least the following beneficial effects:

[0029] The surface polishing method for semiconductor devices disclosed in this application pre-calculates the third thickness of the oxide layer to be deposited based on the first thickness of the surface structure layer and the target thickness after polishing. This ensures that the surface of the semiconductor device is planarized after the second thickness of the oxide layer is removed through polishing, while avoiding production waste and improving polishing efficiency. Furthermore, the third thickness is linearly related to the first coefficient and exponentially related to the surface transmittance. The first coefficient is related to the first thickness, and the third thickness can adapt to changes in the first thickness or transmittance of the surface structure layer, making this method adaptable to various product specifications. The first coefficient is also related to the second coefficient, and adjusting the value of the second coefficient further improves the applicability of the method. Therefore, the surface polishing method for semiconductor devices disclosed in this application, by depositing an oxide layer of appropriate thickness, improves the polishing efficiency of semiconductor devices, ensures the planarization effect of the semiconductor device surface, avoids production waste, saves material costs, and is applicable to various product specifications, demonstrating good applicability and thus possessing significant product promotion value. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 The diagram shows a flow chart of a surface polishing method for a semiconductor device provided in an embodiment of this application.

[0032] Figure 2 and Figure 3The diagram shown is a schematic representation of the surface structure of a semiconductor device provided in an embodiment of this application.

[0033] Figure 4 and Figure 5 The diagram shown is a schematic representation of the surface structure of a semiconductor device after removing part of the oxide layer, as provided in an embodiment of this application.

[0034] Figure 6 The diagram shown is a structural schematic of Comparative Example 1 provided in the embodiments of this application.

[0035] Figure 7 The diagram shown is a structural schematic of the product 1 provided in this application embodiment.

[0036] Figure 8 The diagram shown is a structural schematic of Comparative Example 2 provided in the embodiments of this application.

[0037] Figure 9 The diagram shown is a structural schematic of the product 2 provided in this application embodiment.

[0038] Illustration of reference numerals in the attached diagram:

[0039] 10. Surface structure layer; 11. Metal layer; 12. Adhesive layer; 13. Gate layer; 21. Oxide layer. Detailed Implementation

[0040] To make the technical objectives, technical solutions, and technical effects of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] In the description of this application, it should be noted that the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example, which are included in at least one implementation or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0043] This embodiment provides a surface polishing method for semiconductor devices, used to planarize the surface of semiconductor devices. The surface of the semiconductor device has a patterned surface structure layer 10, in which a stepped structure is formed. Optionally, the semiconductor device is, for example, a wafer.

[0044] Reference Figure 1 The surface polishing method for semiconductor devices provided in this embodiment includes steps S1 to S6, specifically including:

[0045] Step S1: Obtain the thickness of the surface structure layer 10 and record it as the first thickness;

[0046] Step S2: Calculate the thickness of the oxide layer 21 to be removed based on the first thickness and record it as the second thickness;

[0047] Step S3: Set the thickness of the remaining oxide layer on the surface structure layer after planarization and record it as the target thickness;

[0048] Step S4: Calculate the third thickness based on the target thickness and the second thickness;

[0049] Step S5: Form an oxide layer 21 of a third thickness on the surface structure layer 10;

[0050] Step S6: Remove the second thickness oxide layer 21 to obtain a remaining oxide layer with the target thickness to planarize the surface of the semiconductor device.

[0051] The surface polishing method for semiconductor devices according to this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the process sequence of the surface polishing method for semiconductor devices protected by this application, and those skilled in the art can make changes according to the actual processing steps.

[0052] First, perform step S1 to obtain the thickness of the surface structure layer 10, which is denoted as the first thickness.

[0053] In this embodiment, the surface structure layer 10 refers to the outer structural layer of the semiconductor device in the current semiconductor process. After forming the surface structure layer 10 in the front-end process, a patterned surface structure layer 10 is formed through processes such as photolithography and etching. The patterned surface structure layer 10 forms a stepped structure with other structural layers of the semiconductor device, and the height of the stepped structure is numerically equal to the height of the surface structure layer 10. The surface structure layer 10 of the semiconductor device can be a single-layer structure or a multi-layer structure.

[0054] In an optional embodiment, refer to Figure 2 The surface structure layer 10 is, for example, a single-layer structure, including a gate layer 13, the first thickness of which is the thickness of the gate layer 13. The thickness of the gate layer 13 can be obtained directly through product specifications, process parameters of the preceding process, or other suitable methods.

[0055] In an optional embodiment, refer to Figure 3 The surface structure layer 10 is, for example, a multi-layer structure, including a metal layer 11 and an adhesive layer 12, with a first thickness being the sum of the thickness of the metal layer 11 and the thickness of the adhesive layer 12. The thicknesses of the metal layer 11 and the adhesive layer 12 can be directly obtained through product specification parameters, process parameters of the preceding process, or other suitable methods.

[0056] Then, proceed to step S2, where the thickness of the oxide layer 21 to be removed is calculated based on the first thickness and recorded as the second thickness.

[0057] In this embodiment, the second thickness refers to the thickness of the oxide layer 21 that needs to be removed subsequently. The value of the second thickness is affected by the thickness of the surface structure layer 10. Generally, when the thickness of the surface structure layer 10 increases, the value of the second thickness also increases accordingly. In addition, the inventors have found that the value of the second thickness is also affected by the surface transmittance, which refers to the light transmittance of the semiconductor device surface. When the surface transmittance decreases, the value of the second thickness also decreases accordingly. Further research has revealed that the value of the second thickness and the value of the surface transmittance have an exponential relationship.

[0058] In an optional embodiment, calculating the second thickness based on the first thickness includes the following steps: establishing an exponential relationship between the second thickness and the surface transmittance of the semiconductor device; calculating the surface transmittance of the semiconductor device based on the pattern structure of the surface structure layer; calculating a first coefficient using the first thickness; and substituting the surface transmittance and the first coefficient into the exponential relationship between the second thickness and the surface transmittance to obtain the second thickness. Specifically, the exponential relationship between the second thickness and the surface transmittance of the semiconductor device is given by the following formula:

[0059] h2=k1*a (1-S) (1)

[0060] Where h2 is the second thickness, k1 is the first coefficient, S is the surface transmittance, and a is the base parameter.

[0061] The surface structure layer 10 of a semiconductor device is generally a non-transparent structure, and light cannot pass through the surface structure layer 10. Therefore, the value of the surface transmittance can be described by the area ratio of the surface structure layer 10.

[0062] In an optional embodiment, calculating the surface transmittance of the semiconductor device includes the following steps: in a top view of the semiconductor device, obtaining the coverage area s1 of the surface structure layer 10 and the coverage area s2 of the oxide layer 21; and calculating the surface transmittance S = 1 - s1 / s2 based on the coverage areas s1 and s2. For example, the value of the surface transmittance S can be 30%, 40%, 50%, 60%, 70%, 80%, or other acceptable values.

[0063] The first coefficient k1 is a quantity related to the first thickness. The value of the first coefficient k1 can be adjusted according to the value of the first thickness so that the value of the second thickness can change with the change of the first thickness, so as to adapt to the working conditions of different surface structure layer 10 thicknesses and improve the adaptability of this method.

[0064] In an optional embodiment, the formula for calculating the first coefficient k1 is k1 = (h1 + 1) * q, where h1 is the first thickness, and the unit of the first thickness h1 is q. q is a preset second coefficient. The second coefficient q is a dimensionless constant. By setting an appropriate value for the second coefficient q, formula (1) can be adapted to various working conditions in actual production, ensuring that the calculated second thickness can meet the design requirements for surface flattening, while avoiding waste of production capacity and improving grinding efficiency.

[0065] Furthermore, the value of the second coefficient q satisfies 1.5 ≤ q ≤ 1.7. By controlling the value of the second coefficient q within the range of 1.5 to 1.7, a smooth surface can be obtained after forming the oxide layer and planarizing the semiconductor device surface. At the same time, it can avoid production waste and improve grinding efficiency. When the value of the second coefficient q is small, if the planarization effect on the semiconductor device surface cannot meet expectations in actual production, the value of q can be appropriately increased to improve the planarization effect. Moreover, by limiting the upper limit of the value of the second coefficient q, it is possible to avoid excessive thickness of the formed oxide layer, which would cause production waste.

[0066] In formula (1), 'a' is the base parameter, which characterizes the rate of change of the second thickness with the change of surface transmittance. The value of the base parameter 'a' satisfies the following relationship: 0.8 < a < 1. Optionally, the value of the base parameter 'a' is 0.9 to 0.99. For example, the value of the base parameter 'a' can be 0.9, 0.95, 0.99, or other suitable values. In this embodiment, the value of the base parameter 'a' is preferably 0.95. By controlling the value of 'a' within the range of 0.8 to 1, or further controlling it within the range of 0.9 to 0.99, formula (1) can more accurately reflect the relationship between the second thickness and the surface transmittance. Furthermore, it has been found that when the base parameter 'a' is 0.95, the relationship between the second thickness and the surface transmittance described by formula (1) can more accurately reflect the actual production situation. At this time, under the condition of satisfying surface flattening, the second thickness that needs to be removed can have a smaller value, preventing waste of production capacity and improving production efficiency.

[0067] In an optional embodiment, the second coefficient q is taken as a constant parameter, the first thickness h1 and the surface transmittance S are taken as variables, and the base parameter a is taken as 0.95. Then the formula (1) can be expressed as h2=(h1+1)*q*0.95^(1-S). The parameter q can be taken as 1.5, 1.6, 1.7 or other suitable values. The specific value of q can be adjusted according to the actual production situation.

[0068] Next, proceed to step S3, setting the thickness of the remaining oxide layer on the surface structure layer after planarization and recording it as the target thickness.

[0069] In this embodiment, refer to Figure 2 and Figure 3 The target thickness is the thickness of the remaining oxide layer on the surface structure layer 10 after removing part of the oxide layer 21. The remaining oxide layer is the oxide layer 21 remaining after removing part of the oxide layer 21. To ensure the planarization effect of the semiconductor device, the target thickness is a value greater than 0. The target thickness can be adaptively set according to process or design requirements. For example, the target thickness value can be set to... Or other suitable values. It should be noted that the execution order of step S3 can be after step S2 or before step S1 or step S2, and this embodiment is not limited to this.

[0070] Next, proceed to step S4, where the third thickness is calculated based on the target thickness and the second thickness.

[0071] In this embodiment, refer to Figure 2 and Figure 3The third thickness is the thickness of the oxide layer 21 to be formed on the surface structure layer 10 of the semiconductor device, specifically the distance between the top surface of the oxide layer 21 and the bottom surface of the surface structure layer 10. Optionally, if the third thickness is h3 and the target thickness is t, then the third thickness h3 = t + h2, that is, the third thickness is the sum of the second thickness and the target thickness.

[0072] Next, step S5 is performed to form an oxide layer 21 of a third thickness on the surface structure layer 10.

[0073] In this embodiment, an oxide layer 21 can be formed on the surface structure layer 10 by chemical vapor deposition or other suitable methods. For example, the oxide layer 21 can be formed on the semiconductor device by HDP or PECVD processes. The material of the oxide layer 21 can be silicon oxide or other acceptable dielectric materials, such as silicon dioxide.

[0074] In an optional embodiment, forming an oxide layer 21 of a third thickness on the surface structure layer 10 includes the following steps: placing a semiconductor device in a deposition apparatus; depositing an oxide film on the surface of the semiconductor device using the deposition apparatus, and ensuring that the oxide film completely covers the surface structure layer 10; controlling the thickness of the oxide film to a third thickness to form the oxide layer 21.

[0075] Finally, step S6 is performed to remove the second-thickness oxide layer 21 to obtain a remaining oxide layer with the target thickness, in order to planarize the surface of the semiconductor device.

[0076] In this embodiment, a portion of the oxide layer 21 on the surface of the semiconductor device can be removed using a chemical mechanical polishing (CMP) process or other acceptable methods to obtain the remaining oxide layer, thereby achieving planarization of the semiconductor device surface. (Refer to...) Figure 4 and Figure 5 The thickness of the oxide layer 21 to be removed is the second thickness. After removing the second thickness of the oxide layer 21, the thickness of the remaining oxide layer on the surface of the semiconductor device is the target thickness, which realizes the planarization of the semiconductor device surface. In addition, the value of the second thickness is relatively small, which reduces the amount of grinding on the oxide layer 21, improves the production efficiency of this process, and avoids problems such as production capacity waste.

[0077] In an optional embodiment, removing a portion of the oxide layer 21 on the surface of the semiconductor device includes the following steps: mounting the semiconductor device below the polishing head of the polishing equipment so that the oxide layer 21 faces the polishing pad of the polishing equipment; controlling the polishing disk and polishing head of the polishing equipment to rotate, thereby driving the polishing pad and the semiconductor device to rotate respectively; spraying polishing slurry onto the polishing pad and making the surface structure layer 10 contact the polishing pad to perform polishing operation on the oxide layer 21; after removing the second thickness of the oxide layer 21, moving the semiconductor device away from the polishing pad to complete the polishing operation.

[0078] In an optional embodiment, after step S6 to remove part of the oxide layer 21 on the surface of the semiconductor device to planarize the surface of the semiconductor device, the following step is further included: cleaning the semiconductor device. A cleaning device can be used to clean the polished semiconductor device to remove contaminants such as polishing particles remaining on the surface of the polished semiconductor device.

[0079] Furthermore, cleaning semiconductor devices includes the following steps: placing the semiconductor device in a cleaning device; spraying a cleaning solution onto the surface of the semiconductor device; and cleaning the semiconductor device using the cleaning brushes of the cleaning device. The cleaning solution can be deionized water or other suitable materials.

[0080] To further illustrate the technical effects of the present application, products 1 and 2 using the present embodiment are provided, as well as comparative examples 1 and 2 corresponding to products 1 and 2 respectively, and products 1, comparative example 1, product 2 and comparative example 2 are tested respectively.

[0081] Among them, the target thickness of product 1 The surface transmittance S = 47%, the surface structure layer 10 consists of a metal layer 11 and an adhesive layer 12, and the first thickness of the surface structure layer 10 is... The second coefficient q = 1.7. Comparative Example 1 has the same structural parameters as Product 1 as described above. The thickness of the oxide layer 21 deposited in Comparative Example 1 is... The third thickness of oxide layer 21, calculated using formula (1), for product 1 is: The experimental results for Comparative Example 1 and Product 1 were respectively referred to Figure 6 and Figure 7 As can be seen, the surface of the product in Comparative Example 1 has obvious defects due to insufficient flattening, while the surface of Product 1 obtained by the present application has no obvious defects and is well flattened.

[0082] Target thickness of product 2 The surface transmittance S = 51%, the surface structure layer 10 consists of a metal layer 11 and an adhesive layer 12, and the first thickness of the surface structure layer 10 is... The second coefficient q = 1.5. Comparative Example 2 has the same structural parameters as Product 2 as described above. The thickness of the oxide layer 21 deposited in Comparative Example 2 is... The third thickness of oxide layer 21, calculated using formula (1), for product 2 is: The experimental results of Comparative Example 2 and Product 2 were respectively referred to Figure 8 and Figure 9 As can be seen, the surface of the product in Comparative Example 2 has obvious defects in flattening, while the surface of Product 2 obtained by the present application has no obvious defects and is well flattened.

[0083] As described above, the surface polishing method for semiconductor devices of this application, in a first aspect, calculates in advance the third thickness of the oxide layer 21 to be deposited based on the first thickness of the surface structure layer 10 and the target thickness of the oxide layer 21 to be retained after polishing. This ensures that after polishing to remove the oxide layer 21 of the second thickness, the surface of the semiconductor device can be planarized. At the same time, the value of the second thickness is small, which can reduce the amount of polishing in the polishing process, avoid wasting production capacity, improve production efficiency, and avoid problems such as poor uniformity of wafer film thickness distribution caused by excessive polishing time.

[0084] Secondly, the third thickness is linearly related to the first coefficient and exponentially related to the surface transmittance. The first coefficient is a function of the first thickness. When the specifications of the semiconductor device change, such as when the first thickness or surface transmittance of the surface structure layer 10 changes, the third thickness can be adaptively changed, making this method applicable to products of various specifications. The first coefficient is also related to the second coefficient, which is a constant parameter. By adjusting the value of the second coefficient, the third thickness calculated by this method can be made more accurate, while ensuring that it is suitable for products of various specifications in actual production, further improving the applicability of the method.

[0085] Thirdly, in this application, the second thickness and the third thickness can be quickly calculated according to formula (1), without the need for additional stretching tests on semiconductor devices to obtain the value of the third thickness, which greatly improves production efficiency and saves time and material costs.

[0086] As can be seen, the surface polishing method for semiconductor devices of this application greatly improves wafer production efficiency by depositing an oxide layer 21 of appropriate thickness, while ensuring a good planarization effect on the surface of semiconductor devices, avoiding production capacity waste, saving time and material costs, and being applicable to products with various specifications and parameters, thus having great applicability and great product promotion value.

[0087] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify, alter, or combine the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A surface polishing method for a semiconductor device, used to planarize the surface of the semiconductor device, wherein the surface of the semiconductor device has a patterned surface structure layer, characterized in that... Includes the following steps: The thickness of the surface structure layer is obtained and recorded as the first thickness; The thickness of the oxide layer to be removed is calculated based on the first thickness and recorded as the second thickness; Set the thickness of the remaining oxide layer on the surface structure layer after planarization and record it as the target thickness; The third thickness is calculated based on the target thickness and the second thickness; An oxide layer of a third thickness is formed on the surface structure layer; The oxide layer of the second thickness is removed to obtain a remaining oxide layer having the target thickness, in order to planarize the surface of the semiconductor device; The process of calculating the thickness to be removed by grinding based on the first thickness and recording it as the second thickness includes the following steps: An exponential relationship is established between the second thickness and the surface transmittance of the semiconductor device, and the exponential relationship is denoted as h2=k1*a^(1-S), where h2 is the second thickness, a is the base parameter, the base parameter a satisfies 0.8<a<1, k1 is the first coefficient, and S is the surface transmittance. Based on the pattern structure of the surface structure layer, the surface transmittance S of the semiconductor device is calculated; the steps include: in the top view of the semiconductor device, obtaining the coverage area s1 of the surface structure layer and the coverage area s2 of the oxide layer; and calculating the surface transmittance S = 1 - s1 / s2. The first coefficient k1 is calculated using the first thickness; the formula for calculating the first coefficient k1 is k1=(h1+1)*q, where h1 is the first thickness in kÅ, and q is a preset second coefficient that satisfies 1.5≤q≤1.

7. Substituting the surface transmittance S and the first coefficient k1 into the expression of the exponential relationship, the second thickness h2 is obtained.

2. The surface polishing method for semiconductor devices according to claim 1, characterized in that, The surface structure layer includes a gate layer, and the first thickness is the thickness of the gate layer.

3. The surface polishing method for semiconductor devices according to claim 1, characterized in that, The surface structure layer includes a metal layer and an adhesive layer, and the first thickness is the sum of the thickness of the metal layer and the thickness of the adhesive layer.

4. The surface polishing method for semiconductor devices according to claim 1, characterized in that, The base parameter a takes a value of 0.9 to 0.

99.

5. The surface polishing method for semiconductor devices according to claim 1, characterized in that, The third thickness is the sum of the second thickness and the target thickness. The oxide layer of the second thickness is removed by grinding with a grinding device to planarize the surface of the semiconductor device.

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