Semiconductor structure and forming method thereof

Abstract

The method comprises: forming a functional circuit on a semiconductor substrate of a device die, the functional circuit being located in a functional circuit region of the device die; forming a passive device over the semiconductor substrate, where the passive device is in a passive device region of the device die; forming a first plurality of bond pads in the functional circuit region and at a surface of the device die, where the first plurality of bond pads have a first pattern density; and forming a second plurality of bond pads in the passive device region and at the surface of the device die. The second plurality of bond pads has a second pattern density lower than the first pattern density. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor chip may include active devices and passive devices, such as transistors, capacitors, inductors, etc. In the semiconductor chip, transistors are formed on the surface of the semiconductor substrate of the semiconductor chip. Passive devices may be formed above the semiconductor chip. Bonding pads that can be used to bond to another package component such as a semiconductor chip, an interposer, a package substrate, etc. may be formed above the passive devices and the active devices. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is located in a functional circuit area of ​​the device die; forming a passive device above the semiconductor substrate, wherein the passive device is located in a passive device area of ​​the device die; forming a first plurality of bonding pads in the functional circuit area and at a surface of the device die, wherein the first plurality of bonding pads have a first pattern density; and forming a second plurality of bonding pads in the passive device area and at the surface of the device die, wherein the second plurality of bonding pads have a second pattern density lower than the first pattern density.

[0004] Other embodiments of the present application provide a semiconductor structure, including: a device die, including: a functional circuit area; a first plurality of bonding pads, located in the functional circuit area, wherein the functional circuit area has a first pattern density of bonding pads; a functional circuit, located in the functional circuit area and below the first plurality of bonding pads; a passive device area; a passive device, located in the passive device area; a second plurality of bonding pads, located in the passive device area and above the passive device, wherein the passive device area has a second pattern density of bonding pads, and the second pattern density is lower than the first pattern density; a transition area, located between the functional circuit area and the passive device area; and a third plurality of bonding pads, located in the transition area, wherein the transition area has a third pattern density of bonding pads, and the third pattern density is lower than the first pattern density and greater than the second pattern density.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a plurality of metal layers located above the semiconductor substrate; an inductor located above the plurality of metal layers; a first plurality of bonding pads, wherein a first chip region occupied by the first plurality of bonding pads overlaps with the inductor, and the first plurality of bonding pads have a first spacing; a second plurality of bonding pads located in a second chip region surrounding the first plurality of bonding pads, wherein the second plurality of bonding pads have a second spacing smaller than the first spacing; and a third plurality of bonding pads located in a third chip region surrounding the second plurality of bonding pads, wherein the third plurality of bonding pads have a third spacing smaller than the second spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of a device die including passive devices and bonding pads thereon is shown in accordance with some embodiments.

[0008] Figure 2 A top view of a device die including passive devices and bonding pads thereon is shown in accordance with some embodiments.

[0009] Figure 3 A top view of a passive device region, a transition region, and a functional circuit region is shown in accordance with some embodiments.

[0010] Figure 4 A top view of a passive device area is shown in accordance with some embodiments.

[0011] Figure 5 A top view of a transition region having a gradient pattern density is shown in accordance with some embodiments.

[0012] Figure 6 A cross-sectional view of a portion of a device die including passive devices, transition regions, functional circuit regions, and upper bonding pads is shown in accordance with some embodiments.

[0013] Figure 7 Various distribution patterns of bonding pads in a passive device region are shown in accordance with some embodiments.

[0014] Figure 8 and Fig. 9 Possible top-view shapes of bonding pads in a passive device area are shown in accordance with some embodiments.

[0015] Fig.10 Various distribution patterns of cluster bond pads in a passive device region are shown in accordance with some embodiments.

[0016] Fig.11 Various distribution patterns of bonding pads in the transition region are shown in accordance with some embodiments.

[0017] Fig.12 and Fig.13 A cross-sectional shape of a redistribution line according to some embodiments is shown.

[0018] Fig.14 A cross-sectional view of two bonded device dies is shown in accordance with some embodiments.

[0019] Figures 15 to 26 A cross-sectional view illustrates an intermediate stage in the formation of a top structure of a device die in accordance with some embodiments.

[0020] Figures 27 to 35 Cross-sectional views of some structures employing embodiments are shown according to some embodiments.

[0021] Fig.36 A process flow for forming a top structure according to some embodiments is shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] A device die including an optimized arrangement of passive devices and bonding pads and a method for forming the same are provided. According to some embodiments, a passive device such as an inductor is formed in a passive device area. A functional circuit including an active device is formed in a functional circuit area. A transition region is formed to separate the passive device area from the functional circuit area. Bonding pads are formed in the passive device area and the transition region (except the functional circuit area) to reduce the pattern loading effect. In order to minimize the adverse effects of the bonding pads in the passive device area on the performance of the passive devices and circuits, the pattern density in the passive device area is lower than the pattern density in the functional circuit area. The pattern density in the transition region can be further higher than the pattern density in the passive device area and lower than the pattern density in the functional circuit area to mitigate the pattern density difference between the passive device area and the functional circuit area.

[0025] The embodiments discussed herein are intended to provide examples of the subject matter of the disclosed embodiments that can be manufactured or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0026] Figure 1 A cross-sectional view of wafer 20 is shown. According to some embodiments, wafer 20 is or may include a device wafer including active and passive devices represented as integrated circuit devices 26. Wafer 20 may include a plurality of chips (device dies) 20' therein, of which one of the device dies 20' is shown.

[0027] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. A shallow trench isolation (STI) region (not shown) may be formed in semiconductor substrate 24 to isolate active regions in semiconductor substrate 24.

[0028] According to some embodiments, wafer 20 includes integrated circuit devices 26 formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown herein.

[0029] An interconnect structure 32 including an ILD 28 and a contact plug 30 is formed over the integrated circuit device 26. The interlayer dielectric (ILD) 28 fills the space between the gate stacks (not shown) of the transistors in the integrated circuit device 26. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 can be formed using spin coating. According to alternative embodiments, the ILD 28 can also be formed using a deposition method, such as flowable chemical vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0030] Contact plug 30 is formed in ILD 28 and is used to electrically connect integrated circuit device 26 to the metal lines and vias above. According to some embodiments, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plug 30 may include: forming a contact opening in ILD 28; filling the contact opening with a conductive material; and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0031] The interconnect structure 32 also includes metal lines 34 and vias 36 formed in a dielectric layer 38 (also referred to as an intermetallic dielectric (IMD)) and an etch stop layer 37. Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments, the interconnect structure 32 includes a plurality of metal layers including metal lines 34 interconnected by vias 36. The metal lines 34 and vias 36 may be formed of copper or a copper alloy, and may also be formed of other metals such as tungsten, nickel, etc.

[0032] According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.5 or 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. Etch stop layer 37 is formed below the corresponding dielectric layer 38 and may be formed of or include aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, etc. or multiple layers thereof.

[0033] The formation of metal lines 34 and vias 36 in dielectric layer 38 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 38, followed by filling the trench or via opening with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portion of the conductive material above the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via opening. In a dual damascene process, trenches and via openings are formed in the dielectric layer, wherein the via opening is located below the trench and connected to the trench. Conductive material is then filled into the trench and via opening to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0034] Metal lines 34 include top conductive (metal) features (denoted as 34T), such as metal lines, metal pads, or vias in a top dielectric layer (denoted as dielectric layer 38T), which is a top layer of dielectric layer 38. According to some embodiments, dielectric layer 38T is formed of a low-k dielectric material similar to the material of lower dielectric layer 38. Metal features 34T in top dielectric layer 38T may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0035] Passivation layer 42 (sometimes referred to as passivation-1 or pass-1) is formed over interconnect structure 32. According to some embodiments, passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. Passivation layer 42 may be formed of or include an inorganic dielectric material, which may include, but is not limited to, undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), etc., combinations thereof and / or multilayers thereof. According to some embodiments, the top surfaces of top dielectric layer 38T and metal line / pad 34T are flush with each other. Therefore, passivation layer 42 may be a planar layer.

[0036] According to some embodiments, a via 44 is formed in the passivation layer 42 to electrically connect to the top metal feature 34T below. A redistribution line (RDL) 46, which may include a metal line and a metal pad, is further formed over the via 44. According to some embodiments, the RDL 46 includes aluminum, aluminum copper, or the like. A passivation layer 48 (sometimes referred to as passivation-2 or pass-2) is also formed that may extend on the sidewalls and top surface of the RDL 46. The passivation layer 48 may be formed of or include silicon oxide, silicon nitride, or the like, or multiple layers thereof.

[0037] According to some embodiments, a dielectric layer 50 is formed. The dielectric layer 50 may be planarized and referred to as a planarization layer. According to some embodiments, the dielectric layer 50 may be formed by dispensing a polymer in a flowable form and then curing the polymer layer 50. The dielectric layer 50 may also be formed by deposition. The dielectric layer 50 is patterned to expose the RDL 46. The dielectric layer 50 (when formed of a polymer) may be formed of or include polyimide, polybenzoxazole (PBO), or the like. Alternatively, the dielectric layer 50 may be formed of or include an inorganic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0038] A dielectric layer 56 is formed over the dielectric layer 50. A bonding pad 54 and a bonding via 52 are formed in the dielectric layer 56 to electrically connect to the RDL 46 below. The detailed structure, material, and formation process of the bonding via 52, the bonding pad 54, and the dielectric layer 56 are referred to as Figures 15 to 26 The process shown in is discussed.

[0039] According to some embodiments, the device die 20' includes a functional circuit area 58F, and the functional circuit area 58F includes a functional circuit 26. The functional circuit 26 may include active devices, such as transistors. Bonding pads 54F are formed at the surface of the device die 20' and in the functional circuit area 58F, and the bonding pads 54F are part of the bonding pads 54. At least some of the bonding pads 54F are electrically connected to the integrated circuit device 26. There may or may not be dummy bonding pads (also represented as 54F) in the functional circuit area 58F. The dummy bonding pads have no electrical function and may be electrically floating (when the device die 20' is powered on). According to some embodiments, all bonding pads 54F overlap with the functional circuit 26 in the functional circuit area 58F.

[0040] Device die 20' also includes a passive device region 58P, which includes a passive device 62. Bonding pads 54P are formed at the surface of device die 20' and passive device region 58P, and bonding pads 54P are part of bonding pads 54. Passive device 62 may be or may include an inductor, a capacitor, etc. Figure 1 , a passive device 62 is schematically shown. According to some embodiments, the passive device 62 includes multiple portions of the RDL 46, the via 44, and the underlying metal line 34T, and when the passive device 62 includes an inductor, these multiple portions are interconnected to form a coil (spiral). According to other embodiments, the passive device 62 can be formed in the RDL 46 and does not include a portion of the underlying top metal layer. According to still other embodiments, the entire passive device 62 can be formed in a lower metal layer that includes the top metal layer and may be located below the top metal layer.

[0041] According to some embodiments, below the passive device 62, there are integrated circuit devices 26, metal lines 34, and / or vias 36 formed in the passive device region 58P, which can be electrically connected to the bonding pads 54P above. According to some embodiments, all bonding pads 54P overlap with the functional circuits 26 in the passive device region 58P. According to alternative embodiments, no integrated circuit devices 26, metal lines 34, and / or vias 36 are formed below the passive device 62. Therefore, the integrated circuit devices 26, metal lines 34, and / or vias 36 in the passive device region 58P are shown as dashed lines to indicate that these components may or may not be formed.

[0042] According to some embodiments, depending on the number of passive devices 62, the number of terminals of passive devices 62, the number of bonding pads 54P, and the connection scheme of passive devices 62 to integrated circuit devices 26, there may or may not be dummy bonding pads (also indicated as 54P) in passive device region 58P. According to some embodiments, all bonding pads 54P are connected to passive devices 62 and / or the underlying integrated circuit devices 26. According to alternative embodiments, all bonding pads 54P are dummy bonding pads. According to still other alternative embodiments, some of bonding pads 54P are connected to passive devices 62 and / or the underlying integrated circuit devices 26, while other bonding pads 54P are dummy bonding pads.

[0043] Transition region 58T is located between functional circuit region 58F and passive device region 58P. According to some embodiments, transition region 58T includes bonding pad 54T (which is also part of bonding pad 54). Bonding pad 54T may be a dummy bonding pad. According to some embodiments, some or all of bonding pads 54T do not have underlying vias 52. According to some embodiments, no integrated circuit device 26, metal line 34, and / or via 36 are formed in transition region 58T and below bonding pad 54T.

[0044] According to alternative embodiments, there may also be some integrated circuit devices 26, metal lines 34, and / or vias 36 formed in the transition region 58T and below the bonding pad 54T. According to still other alternative embodiments, there may be some dummy metal lines 34 and / or vias 36 (not shown) in the transition region 58T and below the bonding pad 54T, wherein the dummy metal lines 34 and / or vias 36 are respectively used to reduce the pattern loading effect in the formation of the metal lines 34 and / or vias 36. These dummy metal lines 34 and / or vias 36 may be electrically floating and may be electrically connected to the bonding pad 54T or electrically disconnected from the bonding pad 54T.

[0045] Figure 2A top view of a portion of device die 20' is shown in accordance with some embodiments. Passive device region 58P may be surrounded by transition region 58T. Transition region 58T separates passive device region 58P from functional circuit region 58F, which may further surround transition region 58T. Figure 1 The cross-sectional view shown in Figure 2 The cross section 1-1 in FIG.

[0046] In each of regions 58F, 58T, and 58P, the corresponding bonding pads 54 have a pattern density calculated as the ratio of the total area of ​​the bonding pads 54 in the corresponding region to the total chip area of ​​the region. Thus, the bonding pads 54F in the functional circuit region 58F have a pattern density PD 54F , the bonding pad 54T in the transition region 58T has a pattern density PD 54T , and the bonding pads 54p in the passive device region 58P have a pattern density PD 54P In addition, because the pattern density of the bonding pad 54 has a large fluctuation when calculated for a smaller chip area, the pattern density of the bonding pad 54 is defined as being calculated in a minimum chip area where both the length and width are equal to or greater than 50 μm. According to some embodiments, PD 54P The pattern density can be calculated based on the entire area of ​​the passive device region 58P, and PD 54T The pattern density of PD can be calculated based on the entire area of ​​the transition region 58T. 54F The pattern density of φ may be calculated based on the annular chip area having a width W3 greater than 1.5 μm or the entire area of ​​the functional circuit region 58F.

[0047] The bonding pad 54P ( Figure 1 ) may adversely affect the performance of the passive device 62 and the circuits connected to the passive device 62. In order to reduce the adverse effects, the pattern density PD of the passive device region 58P is 54P Designed to be smaller and smaller than the pattern density PD of the functional circuit area 58F 54F However, the pattern density PD 54P Reduced to less than the pattern density PD 54F This may exacerbate the pattern loading effect, for example, in the planarization process used to form the bonding pad 54 (see Fig.26 (under discussion).

[0048] To solve this problem, the pattern density PD in the transition region 58T 54T Designed to be smaller than the pattern density PD 54F and is greater than the pattern density PD 54PThis can mitigate pattern loading effects and can reduce the likelihood of non-bonding issues. According to some embodiments, the pattern density PD in the passive device region 58P is 54P The pattern density PD in the transition region 58T may be in the range between about 0% (when there is no bonding pad in the passive device region 58P) and about 6%. 54T The pattern density PD in the functional circuit region 58F may be in the range between about 0.5% and about 2%. 54F The ratio PD may be in the range between about 5% and about 25%. 54P / PD 54T may be in the range between about 0 and about 0.3, and the ratio PD 54T / PD 54F The ratio PD may be in the range between about 0.3 and about 1. 54P / PD 54F It may be less than about 0.3, and may be within a range between about 0 and about 0.3.

[0049] According to some embodiments, the length L1 and width W1 of the passive device region 58P may be in a range between about 3 μm and about 3,000 μm. The width W2 of the annular transition region 58T may be in a range between about 2 μm and about 40 μm. The width W3 of the annular functional circuit region 58F may be in a range between about 3 μm and about 3,000 μm.

[0050] Figure 3 An exemplary top view of a passive device region 58P, a transition region 58T, and a functional circuit region 58F and corresponding bonding pads 54P, 54T, and 54F is shown in accordance with some embodiments. An exemplary inductor 62 is also shown. Figure 3 As shown in , the spacing S1 of the bonding pads 54P can be equal to or greater than the spacing S2 of the bonding pads 54T, and / or the spacing S2 of the bonding pads 54T can be equal to or greater than the spacing S3 of the bonding pads 54F. The diameter D1 of the bonding pad 54P can also be equal to or less than the diameter D2 of the bonding pad 54T, and / or the diameter D2 of the bonding pad 54T can be equal to or less than the diameter D3 of the bonding pad 54F. Therefore, the difference in pattern density can be achieved by different spacing (or pitch) and / or different lateral dimensions (diameter or length and width) of the bonding pads 54P, 54T and 54F. According to some embodiments, the diameters D1, D2 and D2 can be in the range from about 0.5μm to about 20μm.

[0051] According to some embodiments, the bonding pads 54T in the transition region 58T may include multiple columns of bonding pads, for example, greater than about 5 or 10 columns of bonding pads. Figure 2 and Figure 3It can be appreciated that the bonding pads 54T can be aligned with multiple rings, wherein the outer ring surrounds the corresponding inner ring. The bonding pads 54T aligned with the same ring can be referred to as bonding pad rings. The bonding pads 54F in the functional circuit area 58F can also include multiple (e.g., more than 5 or 10) bonding pad rings.

[0052] Figure 4 An exemplary top view of a passive device region 58P according to some embodiments is shown. The passive device region 58P according to these embodiments may have a Figure 3 In the embodiment of the present invention, a larger number of bonding pads 54P are provided. In addition, some of the bonding pads 54P may overlap with the passive device 62 and / or the underlying integrated circuit device 26 (if any), while in Figure 3 In the embodiment of FIG. 5 , the bonding pads 54P may form a rectangular pattern surrounding the passive device 62 , wherein the bonding pads 54P are located in a position close to but not overlapping the passive device 62 and / or the underlying integrated circuit device 26 .

[0053] According to some embodiments, all of the bonding pads 54P overlap with the passive devices 62 and / or the underlying integrated circuit device 26. According to alternative embodiments, the bonding pads 54P may include bonding pads that overlap with the passive devices 62 and / or the underlying integrated circuit device 26, and may or may not include a bonding pad ring that does not overlap and surrounds the passive devices 62 and / or the underlying integrated circuit device 26 in the top view.

[0054] According to some embodiments, the bonding pads 54T in the transition region 54T are uniformly distributed at uniform intervals and thus have a uniform pattern density. According to alternative embodiments, the bonding pads 54T in the transition region 54T have gradient intervals and thus have a gradient pattern density. For example, Figure 3 Dashed lines are used to mark multiple sub-regions 58T1, 58T2, and 58T3 (or more) of transition region 58T. Dashed lines indicate that the pattern density of bonding pads 54T may be uniform or may be gradient. According to some embodiments, the number of sub-regions may range from 2 to 20.

[0055] According to some embodiments, the bonding pads 54T in each of the sub-regions (such as 58T1, 58T2, and 58T3) have a uniform pattern density and uniform spacing. However, the pattern density and spacing of adjacent sub-regions are different from each other. In order to minimize the pattern loading effect, the bonding pads 54T in the sub-region closer to the passive device region 58P have a lower pattern density (and a larger spacing and / or a smaller lateral dimension) than the bonding pads 54T in the corresponding sub-region closer to the functional circuit region 54F. In other words, in the transition region 58T, the pattern density can gradually increase in the direction pointing upward from the passive device region 54P to the functional circuit region 54F, which means that the diameter (lateral dimension) of the bonding pads 54P can gradually increase, and / or the spacing can gradually decrease. For example, Figure 5 Three sub-regions 58T1 , 58T2 , and 58T3 are shown having intervals S1A, S1B, and S1C, respectively, wherein interval S1B is smaller than interval S1A, and interval S1C is smaller than interval S1B.

[0056] According to some exemplary embodiments where there are three sub-regions, the pattern densities in sub-regions 58T1, 58T2, and 58T3 may be about 1% to 3%, about 8% to 15%, and about 18% to 22%, respectively. According to an alternative embodiment where there are five sub-regions, the pattern densities in sub-regions 58T1, 58T2, 58T3, 58T4 (not shown), and 58T5 (not shown) may be about 1% to 3%, about 5% to 8%, about 9% to 13%, about 14% to 16%, and about 18% to 22%, respectively.

[0057] Figure 6 The top components in three device regions 58P, 58T, and 58F are shown in accordance with some embodiments. Some components, such as details of the dielectric layer, are not shown. In accordance with some embodiments, RDL 46 (which forms passive devices 62 in passive device region 58P and metal pads in functional circuit region 58F) can have a rounded top surface, which results from copper plating.

[0058] Figure 7 Some possible arrangements of bonding pads 54P in passive device region 58P according to some embodiments are shown. For example, bonding pads 54P may be located on nodes and form a square array, a rectangular array, a diamond array, a pentagonal array, a hexagonal array, etc., or any other regular or irregular pattern.

[0059] The top view shape of the bonding pad 54 (54P, 54T and / or 54F) may be any shape, including but not limited to a circular shape ( Figure 3 ),square( Figure 8 ),rectangle( Fig. 9), oval, hexagon, octagon, etc.

[0060] Fig.10 Some possible arrangements of bonding pads 54P in a passive device region 58P according to some embodiments are shown. The bonding pads 54P may be arranged in a plurality of clusters, and the clusters may be further arranged in a regular or irregular pattern. The patterns of the plurality of clusters may be the same as or different from each other. Fig.10 As shown in , the clusters of bonding pads 54P may be located at nodes and form a square array, rectangular array, hexagonal array, diamond array, etc., or any other regular or irregular pattern.

[0061] Fig.11 Some possible arrangements of the bonding pads 54T in the transition device region 58T according to some embodiments are shown. For example, the bonding pads 54T may be located on nodes and form a square array, a rectangular array, a diamond array, a pentagonal array, a hexagonal array, etc., or any other regular or irregular pattern.

[0062] Fig.12 and Fig.13 FIG. 4 shows the cross-sectional shape of the RDL 46 forming the passive device 62 in the passive device region 58P and the metal pad in the functional circuit region 58F. Fig.12 In the embodiment, the RDL 46 has a flat top surface. This can be achieved by aluminum or aluminum copper plating. Fig.13 In the embodiment, RDL 46 has a rounded top surface. According to some embodiments, this can be achieved by copper plating.

[0063] Fig.14 The bonding of two device dies 20' (including 20'-1 and 20'-2) to each other according to some embodiments is shown. The device die 20'-1 has a bonding pad corresponding to the bonding pad of the device die 20'-2. For example, after bonding, the passive device area 58P, transition area 58T and functional circuit area 58F of the device die 20'-1 overlap with the passive device area 58P, transition area 58T and functional circuit area 58F of the device die 20'-2, respectively. In addition, the position and size of the bonding pads 54P, 54T and 54F of the device die 20'-1 can be the same as the position and size of the bonding pads 54P, 54T and 54F of the device die 20'-2. According to some embodiments, the passive device 62 in the device die 20'-1 is connected in parallel or in series to the passive device 62 in the device die 20'-2.

[0064] Figures 15 to 262. A method for forming a circuit including a passive device 62 ( Figure 1 ) of the upper structure. The corresponding processes are also schematically reflected in the following Fig.36 The process flow 200 shown in FIG. Figure 1 The substructure in the embodiment of the present invention is still present below the portion shown. Figure 1 Discussed Figures 15 to 26 Some of the components shown in . Figures 15 to 26 The discussion of the process in can be compared with reference Figure 1 It should be understood that these processes are examples and other applicable processes, structures and materials may be used.

[0065] refer to Fig.15 , a top metal feature 34T is formed in the top dielectric layer 38T. A passivation layer 42 is then deposited over the top metal feature 34T. The corresponding process is shown as follows Fig.36 The passivation layer may include silicon oxide or a reference Figure 1 Other materials discussed. Fig.16 The etching process is shown to form an opening 43 in the passivation layer 42, wherein the top metal feature 34T is exposed. The corresponding process is shown as follows Fig.36 Process 204 in the process flow 200 shown in FIG.

[0066] Next, if Fig.17 As shown in FIG. 4 , a metal seed layer (which is also a barrier layer) 45A is deposited, which may include a titanium layer and a copper layer above the titanium layer. The corresponding process is shown as follows Fig.36 The process 206 in the process flow 200 shown in FIG. Then, a patterned photoresist 47 is formed. The corresponding process is shown as follows. Fig.36 The process 208 in the process flow 200 is shown in FIG. Fig.18 , a plating process is performed to deposit a metal material 45B, such as copper. The corresponding process is shown as follows Fig.36 The process 210 in the process flow 200 shown in FIG. The resulting top surface of the metal material 45B may be rounded, such as Fig.13 As shown in . Optionally, the metal material 45B may include aluminum, which may have a flat top surface, such as Fig.12 as shown in .

[0067] In the subsequent process, the photoresist 47 is removed to expose the lower portion of the metal seed layer 45A. The exposed metal seed layer 45A is then removed by etching. The corresponding process is shown as follows. Fig.36The process 212 in the process flow 200 shown in FIG. The metal seed layer 45A and the remaining portion of the metal material 45B together form the via 44 and the RDL 46, which are Fig.19 and also shown in Figure 1 RDL 46 may be used to form passive devices 62 as well as RDL and metal pads in functional circuit region 58F.

[0068] Next, if Fig. 20 As shown in FIG. 4 , for example, a passivation layer 48 is deposited using a material including silicon nitride, silicon oxide, etc. The corresponding process is shown as follows. Fig.36 The process 214 in the process flow 200 is shown in FIG. The passivation layer 48 may be formed as a conformal layer, for example, by a conformal deposition process such as ALD, CVD, or the like.

[0069] refer to Fig.21 , depositing a dielectric layer 50A, which is also called a planarization layer. The dielectric layer 50A may be a polymer layer formed of polyimide, PBO, etc. The corresponding process is shown as follows Fig.36 The process 216 in the process flow 200 shown in FIG. Fig. 22 In the process, multiple dielectric layers are deposited. The corresponding process is shown as follows Fig.36 218 in the process flow 200 shown in FIG. The plurality of dielectric layers may include dielectric layers 50B, 50C, 56A, and 56B. According to some embodiments, dielectric layers 50B, 50C, 56A, and 56B may include silicon nitride, silicon oxide, silicon nitride, silicon oxide, respectively, while other materials may be used. Dielectric layers 50A, 50B, and 50C are collectively referred to as dielectric layers 50. Dielectric layers 56A and 56B are collectively referred to as dielectric layers 56, which are also referred to as bonding films according to some embodiments.

[0070] refer to Fig.23 , forming a patterned photoresist 57. Using the patterned photoresist 57 as an etching mask, the dielectric layers 56B and 56A are etched to form a trench 59. The corresponding process is shown as follows Fig.36 The process 220 in the process flow 200 shown in FIG. The etching of dielectric layer 56B can be performed using dielectric layer 56A as an etch stop layer and then etching through dielectric layer 56A. The patterned photoresist 57 is then removed.

[0071] Fig.24 and Fig.25 The formation of a via opening 63 is shown in accordance with some embodiments. Fig.24 , forming a patterned photoresist 61. The dielectric layers 50C, 50B and 50A and the passivation layer 48 are etched using the patterned photoresist 61 as an etching mask, thereby forming a through hole opening 63. The corresponding process is shown as follows Fig.36The process 222 in the process flow 200 shown in FIG. The resulting structure is Fig.25 The patterned photoresist 61 is then removed.

[0072] In subsequent processes, such as Fig.26 As shown in FIG. 5 , a through hole 52 and a bonding pad 54 are formed. The bonding pad 54 represents Figure 1 The bonding pads 54P, 54T and 54F are shown. The corresponding process is shown as follows Fig.36 The process 224 in the process flow 200 shown in FIG. The formation process may include depositing the barrier layer 53A and the metal material 53B, and a subsequent planarization process to remove excess portions of the deposition barrier layer 53A and the metal material 53B.

[0073] Figures 27 to 35 Some packages in which device die 20 ′ may be used are shown. Fig. 27 A structure is shown in which two system-on-chip (SoC) packages are bonded to an underlying SOC package by die bonding on wafer. One or more of the three packages may include any combination of Figure 1 Device die 20' is shown.

[0074] Fig.28 Two chips chip1 and chip2 are shown bonded by wafer-to-wafer bonding, and thus after sawing, the edges of chips chip1 and chip2 are vertically aligned. Either or both of chips chip1 and chip2 may adopt any combination of device die 20 ′ structures.

[0075] Fig.29 A high bandwidth memory (HBM) and another package bonded to an interposer are shown. The package includes a SoC package SoC-1 bonded to two SoC packages SoC-2 and SoC-3. The interposer is further bonded to a package substrate. One or more or all of the SoC packages SoC-1, SoC-2, and SoC-3 may employ any combination of device die 20' structures.

[0076] Fig.30 A package is shown that includes a top package bonded to a bottom package. The top package may include a dynamic random access memory (DRAM) die bonded to a package substrate. The bottom package may be an integrated fan-out (InFO) package that includes another package, wherein the other package includes SoC packages SoC-1, SoC-2, and SoC-3. One or more or all of the SoC packages SoC-1, SoC-2, and SoC-3 may adopt the structure of the device die 20' in any combination.

[0077] Fig.31A package including two chips chipA and chipB bonded to a package substrate is shown. Either or both of the chips chipA and chipB may adopt any combination of device die 20 ′ structures.

[0078] Fig.32 A package including a SoC package and two HBMs bonded to an InFO package is shown, the InFO package further being located on a package substrate. The InFO package may include a passive device die and a bridge die. The SoC package may adopt a device die 20 'structure.

[0079] Fig.33 A package including a DRAM package bonded to an InFO package is shown. The InFO package may include a logic device die. The logic device die may adopt the structure of device die 20'.

[0080] Fig.34 A package is shown that includes an InFO package that includes a top package bonded to a bottom package. The bottom package (which has an InFO structure) includes a SoC package that may include a device die 20 ′ structure.

[0081] Fig.35 A package including an InFO package is shown, the InFO package including a top package bonded to a bottom package. The structure is similar to Fig.29 The structure shown in Fig.35 In the structure shown in , there is a single SoC package (rather than three SoC packages) that may include the structure of device die 20 ′.

[0082] Embodiments of the present disclosure have some advantageous features. By reducing the pattern density of the bonding pads in the passive device area, the adverse effects of the bonding pads on the circuit are reduced. However, the difference in pattern density may cause pattern loading effects. The pattern loading effect can be reduced by making the bonding pads in the transition region have a pattern density between the pattern density of the bonding pads in the passive device area and the functional circuit area.

[0083] According to some embodiments, the method includes: forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is located in a functional circuit area of ​​the device die; forming a passive device above the semiconductor substrate, wherein the passive device is located in a passive device area of ​​the device die; forming a first plurality of bonding pads in the functional circuit area and at a surface of the device die, wherein the first plurality of bonding pads have a first pattern density; and forming a second plurality of bonding pads in the passive device area and at the surface of the device die, wherein the second plurality of bonding pads have a second pattern density lower than the first pattern density.

[0084] In an embodiment, the method further comprises: forming a third plurality of bonding pads in the transition region and at the surface of the device die, wherein the transition region is located between the passive device region and the functional circuit region, and wherein the third plurality of bonding pads has a third pattern density lower than the first pattern density. In an embodiment, the third pattern density is greater than the second pattern density. In an embodiment, the third plurality of bonding pads are dummy pads. In an embodiment, the transition region has an annular shape surrounding the passive device region. In an embodiment, the third pattern density is a gradient, wherein the pattern density in the portion of the transition region closer to the passive device region is lower than the density in the portion of the transition region closer to the functional circuit region.

[0085] In an embodiment, forming the passive device includes forming an inductor, and wherein forming the inductor includes forming and interconnecting a plurality of redistribution lines. In an embodiment, the method further includes: bonding the device die to a package assembly, wherein the first plurality of bonding pads and the second plurality of bonding pads are physically bonded to additional bonding pads of the package assembly. In an embodiment, forming the first plurality of bonding pads and forming the second plurality of bonding pads include: forming a dielectric layer; etching the dielectric layer to form a plurality of openings; filling the plurality of openings with a conductive material; and performing a planarization process to level the top surfaces of the dielectric layer and the conductive material, wherein the remaining portion of the conductive material includes the first plurality of bonding pads and the second plurality of bonding pads.

[0086] According to some embodiments, a structure includes: a device die, including: a functional circuit area; a first plurality of bonding pads located in the functional circuit area, wherein the functional circuit area has a first pattern density of bonding pads; a functional circuit located in the functional circuit area and below the first plurality of bonding pads; a passive device area; a passive device located in the passive device area; a second plurality of bonding pads located in and above the passive device area, wherein the passive device area has a second pattern density of bonding pads, and the second pattern density is lower than the first pattern density; a transition area located between the functional circuit area and the passive device area; and a third plurality of bonding pads located in the transition area, wherein the transition area has a third pattern density of bonding pads, and the third pattern density is lower than the first pattern density and greater than the second pattern density.

[0087] In an embodiment, the second plurality of bonding pads comprises electrically floating bonding pads. In an embodiment, the third plurality of bonding pads are electrically floating. In an embodiment, the transition region comprises a plurality of sub-regions, and wherein a first plurality of sub-regions closer to the passive device region has a lower pattern density than a corresponding second plurality of sub-regions closer to the functional circuit region.

[0088] In an embodiment, there are no active devices in the transition region. In an embodiment, the passive device includes an inductor. In an embodiment, the structure further includes a package assembly bonded to the device die, wherein the first plurality of bonding pads, the second plurality of bonding pads, and the third plurality of bonding pads are in physical contact with and bonded to the package assembly.

[0089] According to some embodiments, the structure includes: a semiconductor substrate; a plurality of metal layers located above the semiconductor substrate; an inductor located above the plurality of metal layers; a first plurality of bonding pads, wherein a first chip region occupied by the first plurality of bonding pads overlaps with the inductor and the first plurality of bonding pads have a first spacing; a second plurality of bonding pads located in a second chip region surrounding the first plurality of bonding pads, wherein the second plurality of bonding pads have a second spacing less than the first spacing; and a third plurality of bonding pads located in a third chip region surrounding the second plurality of bonding pads, wherein the third plurality of bonding pads have a third spacing less than the second spacing.

[0090] In an embodiment, the first plurality of bonding pads has a first pattern density, and wherein the second plurality of bonding pads has a second pattern density greater than the first pattern density, and the third plurality of bonding pads has a third pattern density greater than the second pattern density. In an embodiment, the first plurality of bonding pads has a first lateral dimension, and wherein the second plurality of bonding pads has a second lateral dimension greater than the first lateral dimension, and the third plurality of bonding pads has a third lateral dimension greater than the second lateral dimension.

[0091] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is located in a functional circuit area of ​​the device die; forming a passive device above the semiconductor substrate, wherein the passive device is located in a passive device area of ​​the device die; forming a first plurality of bonding pads in the functional circuit area and at a surface of the device die, wherein the first plurality of bonding pads have a first pattern density; and forming a second plurality of bonding pads in the passive device area and at the surface of the device die, wherein the second plurality of bonding pads have a second pattern density lower than the first pattern density.

[0092] In some embodiments, the method further comprises: forming a third plurality of bonding pads in a transition region and at a surface of the device die, wherein the transition region is located between the passive device region and the functional circuit region, and wherein the third plurality of bonding pads has a third pattern density lower than the first pattern density. In some embodiments, the third pattern density is greater than the second pattern density. In some embodiments, the third plurality of bonding pads are dummy pads. In some embodiments, the transition region has an annular shape surrounding the passive device region. In some embodiments, the third pattern density is gradient, wherein the pattern density in a portion of the transition region closer to the passive device region is lower than the density in a portion of the transition region closer to the functional circuit region. In some embodiments, forming the passive device comprises forming an inductor, and wherein forming the inductor comprises forming and interconnecting a plurality of redistribution lines. In some embodiments, the method further comprises: bonding the device die to a package assembly, wherein the first plurality of bonding pads and the second plurality of bonding pads are physically bonded to additional bonding pads of the package assembly. In some embodiments, forming the first plurality of bonding pads and forming the second plurality of bonding pads include: forming a dielectric layer; etching the dielectric layer to form a plurality of openings; filling the plurality of openings with a conductive material; and performing a planarization process to make the dielectric layer and the top surface of the conductive material flush, wherein the remaining portion of the conductive material includes the first plurality of bonding pads and the second plurality of bonding pads. In some embodiments, the ratio of the second pattern density to the first pattern density is less than about 0.3.

[0093] Other embodiments of the present application provide a semiconductor structure, including: a device die, including: a functional circuit area; a first plurality of bonding pads, located in the functional circuit area, wherein the functional circuit area has a first pattern density of bonding pads; a functional circuit, located in the functional circuit area and below the first plurality of bonding pads; a passive device area; a passive device, located in the passive device area; a second plurality of bonding pads, located in the passive device area and above the passive device, wherein the passive device area has a second pattern density of bonding pads, and the second pattern density is lower than the first pattern density; a transition area, located between the functional circuit area and the passive device area; and a third plurality of bonding pads, located in the transition area, wherein the transition area has a third pattern density of bonding pads, and the third pattern density is lower than the first pattern density and greater than the second pattern density.

[0094] In some embodiments, the second plurality of bonding pads include electrically floating bonding pads. In some embodiments, the third plurality of bonding pads are electrically floating. In some embodiments, the transition region includes a plurality of sub-regions, and wherein a first plurality of sub-regions closer to the passive device region have a lower pattern density than a corresponding second plurality of sub-regions closer to the functional circuit region. In some embodiments, there are no active devices in the transition region. In some embodiments, the passive device includes an inductor. In some embodiments, the semiconductor structure further includes a packaging assembly bonded to the device die, wherein the first plurality of bonding pads, the second plurality of bonding pads, and the third plurality of bonding pads are in physical contact with and bonded to the packaging assembly.

[0095] Some other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a plurality of metal layers located above the semiconductor substrate; an inductor located above the plurality of metal layers; a first plurality of bonding pads, wherein a first chip region occupied by the first plurality of bonding pads overlaps with the inductor, and the first plurality of bonding pads have a first spacing; a second plurality of bonding pads located in a second chip region surrounding the first plurality of bonding pads, wherein the second plurality of bonding pads have a second spacing smaller than the first spacing; and a third plurality of bonding pads located in a third chip region surrounding the second plurality of bonding pads, wherein the third plurality of bonding pads have a third spacing smaller than the second spacing.

[0096] In some embodiments, the first plurality of bonding pads has a first pattern density, and wherein the second plurality of bonding pads has a second pattern density greater than the first pattern density, and the third plurality of bonding pads has a third pattern density greater than the second pattern density. In some embodiments, the first plurality of bonding pads has a first lateral dimension, and wherein the second plurality of bonding pads has a second lateral dimension greater than the first lateral dimension, and the third plurality of bonding pads has a third lateral dimension greater than the second lateral dimension.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is located in a functional circuit region of the device die; forming a passive device over the semiconductor substrate, wherein the passive device is located in a passive device region of the device die; forming a first plurality of bonding pads in the functional circuit region and at a surface of the device die, wherein the first plurality of bonding pads has a first pattern density; and A second plurality of bonding pads is formed in the passive device region and at a surface of the device die, wherein the second plurality of bonding pads has a second pattern density lower than the first pattern density.

2. The method according to claim 1, further comprising: A third plurality of bonding pads are formed in a transition region and at a surface of the device die, wherein the transition region is between the passive device region and the functional circuit region, and wherein the third plurality of bonding pads has a third pattern density lower than the first pattern density.

3. The method according to claim 2, wherein: The third pattern density is greater than the second pattern density.

4. The method according to claim 2, wherein: The third plurality of bonding pads are dummy pads.

5. The method according to claim 2, wherein: The transition region has a ring shape surrounding the passive device region.

6. The method according to claim 2, wherein: The third pattern density is gradient, wherein the pattern density in a portion of the transition region closer to the passive device region is lower than the density in a portion of the transition region closer to the functional circuit region.

7. The method according to claim 1, wherein: Forming the passive device includes forming an inductor, and wherein forming the inductor includes forming and interconnecting a plurality of redistribution lines.

8. The method according to claim 1, further comprising: The device die is bonded to a package assembly, wherein the first plurality of bond pads and the second plurality of bond pads are physically bonded to additional bond pads of the package assembly.

9. A semiconductor structure comprising: Device die, including: Functional circuit area; a first plurality of bonding pads located in the functional circuit area, wherein the functional circuit area has a first pattern density of bonding pads; a functional circuit located in the functional circuit region and below the first plurality of bonding pads; Passive device area; A passive device, located in the passive device area; a second plurality of bonding pads located in the passive device region and over the passive device, wherein the passive device region has a second pattern density of bonding pads, and the second pattern density is lower than the first pattern density; A transition region located between the functional circuit region and the passive device region; and a third plurality of bonding pads located in the transition region, wherein the transition region has a third pattern density of bonding pads, and the third pattern density is lower than the first pattern density and greater than the second pattern density.

10. A semiconductor structure comprising: Semiconductor substrate; A plurality of metal layers located above the semiconductor substrate; an inductor disposed above the plurality of metal layers; a first plurality of bonding pads, wherein a first chip area occupied by the first plurality of bonding pads overlaps the inductor, and the first plurality of bonding pads have a first pitch; a second plurality of bonding pads located in a second chip region surrounding the first plurality of bonding pads, wherein the second plurality of bonding pads have a second pitch smaller than the first pitch; and A third plurality of bonding pads are located in a third chip region surrounding the second plurality of bonding pads, wherein the third plurality of bonding pads have a third pitch smaller than the second pitch.

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