Semiconductor structure and forming method thereof

Abstract

An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure including a dielectric layer and a metallization pattern therein. The method also includes forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition. The method also includes forming a warpage control dielectric layer over the redistribution pad. The method also includes forming a bond via and a bond pad over the redistribution pad, the bond pad in the warpage control dielectric layer, the bond via electrically coupled to the redistribution pad. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid development due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, the improvement in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative packaging technologies for semiconductor die. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first interconnect structure above a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern; forming redistribution vias and redistribution pads above the first interconnect structure, the redistribution vias and the redistribution pads being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution vias and the redistribution pads having the same material composition; forming a warpage control dielectric layer above the redistribution pads; and forming bonding vias and bonding pads above the redistribution pads, the bonding pads being located in the warpage control dielectric layer, the bonding vias being electrically coupled to the redistribution pads.

[0004] Some other embodiments of the present application provide a semiconductor structure, comprising: a first interconnect structure, located above a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern; a passivation layer, located above the metallization pattern of the first interconnect structure; a redistribution via and a redistribution pad, located above the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via passing through the passivation layer, the redistribution pad being located above the passivation layer, and the redistribution via passing through the passivation layer. The passivation layer and the redistribution pad have the same material composition; a conformal dielectric layer located above the passivation layer and the redistribution pad; a planarization dielectric layer located above the conformal dielectric layer; one or more warpage control dielectric layers located above the planarization dielectric layer; a bonding dielectric layer located on the warpage control dielectric layer; and bonding vias and bonding pads located above the redistribution pad, the bonding pads being located in the warpage control dielectric layer and the bonding dielectric layer, the bonding vias being located in the planarization dielectric layer and electrically coupled to the redistribution pad.

[0005] Some other embodiments of the present application provide a semiconductor structure, comprising: a first interconnect structure, located above a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern; a substrate through hole, extending through the first interconnect structure and the first substrate; a redistribution through hole, located above the first interconnect structure, the redistribution through hole being electrically coupled to at least one of the metallization patterns of the first interconnect structure; a redistribution pad, located above the redistribution through hole, the redistribution pad being electrically coupled to the redistribution through hole, the redistribution pad and the redistribution through hole being continuous conductive material. material; a via defining layer located above the redistribution pad, the via defining layer being a conformal dielectric layer; a planarization dielectric layer located above the via defining layer; one or more warpage control dielectric layers located above the planarization dielectric layer; a bonding via located in the planarization dielectric layer and the via defining layer, the bonding via being electrically coupled to the redistribution pad, the bonding via overlapping the redistribution via; and a bonding pad located in the one or more warpage control dielectric layers, the bonding pad being electrically coupled to the bonding via, the bonding pad overlapping the redistribution via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 25A cross-sectional view is shown of an intermediate stage in the formation of a package in accordance with some embodiments.

[0008] Fig.26 A cross-sectional view is shown of an intermediate stage in the formation of a package in accordance with some embodiments.

[0009] Fig. 27 A cross-sectional view is shown of an intermediate stage in the formation of a package in accordance with some embodiments.

[0010] Fig.28A , Fig.28B , Fig.28C and Fig.28D A cross-sectional view of a bonded redistribution structure is shown in accordance with some embodiments.

[0011] Fig.29A , Fig.29B , Fig.29C and Fig.29D A cross-sectional view of a bonded redistribution structure is shown in accordance with some embodiments.

[0012] Fig. 30A and Fig. 30B A cross-sectional view of a bonded redistribution structure is shown in accordance with some embodiments.

[0013] Fig.31A , Fig.31B , Fig.31C and Fig.31D A cross-sectional view of a bonded redistribution structure is shown in accordance with some embodiments.

[0014] Fig.32A and Fig.32B A cross-sectional view of a bonded redistribution structure is shown in accordance with some embodiments.

[0015] Fig.33A and Fig.33B A cross-sectional view of a bonded redistribution structure is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] The embodiments discussed herein may be discussed in a specific context, i.e., a redistribution structure that may be integrated into a device (e.g., a chip or die) or a package (e.g., a chip-on-wafer (CoW) packaging structure or a wafer-on-wafer (WoW) packaging structure). The redistribution structure includes redistribution vias and lines having a flush or flat upper surface to allow for smaller spacing and minimum distances between adjacent redistribution lines and bonding pads and bonding pad vias. In some embodiments, the redistribution vias and lines are formed in the same process, e.g., a dual damascene process. In some embodiments, a warpage layer and a bonding layer having a high modulus and high thermal conductivity are formed over the redistribution lines to improve warpage control and heat dissipation. In addition, the ratio of the thickness of the bonding pad via to the bonding pad is less than that of conventional bonding pad vias and bonding pads. By having such a smaller thickness ratio, the electrical conductivity and thermal conductivity of the structure are improved.

[0019] In addition, the teachings of the embodiments of the present disclosure are applicable to any redistribution structure, wherein the flat top surface of the redistribution vias and / or pads can reduce the minimum spacing of the redistribution structure. Other embodiments contemplate other applications, such as different package types or different configurations, which will be apparent to a person of ordinary skill in the art reading the embodiments of the present disclosure. It should be noted that the embodiments discussed herein may not necessarily illustrate every component or part that may be present in the structure. For example, multiples of components may be omitted from the accompanying drawings, such as when a discussion of one of the components is sufficient to convey various aspects of the embodiment. In addition, the method embodiments discussed herein may be discussed as being implemented in a particular order; however, other method embodiments may be implemented in any logical order.

[0020] Figures 1 to 26 A cross-sectional view illustrating an intermediate stage in the formation of a package in accordance with some embodiments.

[0021] Figure 1 A cross-sectional view of an integrated circuit die 20 according to some embodiments is shown. The integrated circuit die 20 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 20 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0022] The integrated circuit die 20 can be formed in a wafer, which may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 20 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 20 includes a substrate 22 (such as silicon, doped or undoped) or an active layer of a semiconductor on insulator (SOI) substrate. The substrate 22 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 22 has an active surface (e.g., Figure 1 the upward-facing surface) (sometimes called the front side) and the inactive surface (e.g. Figure 1The downward-facing surface (sometimes called the dorsal side) is the central surface of the brain.

[0023] Devices (not shown) may be formed at the front side of substrate 22. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc., or combinations thereof. An interlayer dielectric (ILD) (not shown separately) is located above the front side of substrate 22. The ILD surrounds the devices and may cover the devices. The ILD may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0024] Conductive plugs (not shown separately) extend through the ILD to electrically and physically couple the device. For example, when the device is a transistor, the conductive plug can couple the gate and source / drain regions of the transistor. The conductive plug can be formed by tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. Interconnection structure 24 is located above the ILD and the conductive plug. Interconnection structure 24 interconnects the devices to form an integrated circuit. Interconnection structure 24 can be formed by, for example, a metallization pattern in a dielectric layer on the ILD. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnection structure 24 is electrically coupled to the device through the conductive plug. The metallization pattern can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, etc.

[0025] After forming the interconnect structure 24, as shown in FIG. Figure 2 As shown in FIG. 1 , a mask 30 is formed and patterned on the interconnect structure 24. In some embodiments, the mask 30 is a photoresist and may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the upper portion of the subsequently formed through substrate via (TSV) 44 (see, for example, FIG. 1 ). Figure 6). At least one opening is patterned through the photoresist 30 to expose the interconnect structure 24. In some embodiments, before the mask 30, a stop layer (not shown), such as a chemical mechanical polishing (CMP) stop layer, is deposited over the top surface of the interconnect structure 24. The CMP stop layer can be used to prevent the subsequent CMP process from removing too much material by resisting the subsequent CMP process and / or by providing a detectable stopping point for the subsequent CMP process. In some embodiments, the CMP stop layer may include one or more dielectric material layers. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), oxycarbides (such as SiOC, etc.), carbonitrides (such as SiCN, etc.), carbides (such as SiC, etc.), combinations thereof, etc., and may be formed using spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc., or combinations thereof.

[0026] exist Figure 3 In the embodiment of the present invention, the remaining mask 30 is used as a mask during the etching process to remove the exposed and underlying portions of the dielectric layer of the interconnect structure 24 and the substrate 22. A single etching process can be used to etch the opening 34 in the interconnect structure 24 and the substrate 22, or a first etching process can be used to etch the interconnect structure 24, and a second etching process can be used to etch the substrate 22. In some embodiments, the opening 34 is formed using a plasma dry etching process, a reactive ion etching (RIE) process, such as a deep RIE (DRIE) process. In some embodiments, the DRIE process includes an etching cycle and a passivation cycle, wherein the etching cycle uses, for example, SF6, and the passivation cycle uses, for example, C4F8. A highly anisotropic etching process can be achieved using a DRIE process with a passivation cycle and an etching cycle. In some embodiments, the etching process can be any acceptable etching process, such as by wet etching or dry etching.

[0027] like Figure 4 As shown in FIG, after forming the opening 34, the photoresist 30 is removed. The photoresist 30 may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like.

[0028] In addition, Figure 4In the embodiment of the present invention, a liner layer 38 is conformally deposited on the interconnect structure 24 and on the bottom surface and sidewalls of the opening 34. In some embodiments, the liner layer 38 includes one or more dielectric material layers and can be used to physically and electrically isolate the subsequently formed via from the substrate 22. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), combinations thereof, etc. The liner layer 38 can be formed using CVD, PECVD, ALD, etc., or combinations thereof.

[0029] In the subsequent steps, Figure 4 As shown in , a seed layer 40 is formed over the pad layer 38. In some embodiments, the seed layer 40 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 40 includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. In some embodiments, before forming the seed layer 40, a barrier layer (not shown) can be formed on the pad layer 38. The barrier layer can include Ti, TiN, etc., or a combination thereof.

[0030] exist Figure 5 In the embodiment, a conductive material 42 filling the opening 34 is formed on the seed layer 40. The conductive material 42 may be formed by plating, such as electroplating including electrochemical plating, chemical plating, etc. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc.

[0031] After forming conductive material 42, an annealing process is then performed. The annealing process may be performed to prevent subsequent extrusion (sometimes referred to as TSV pumping) of the conductive material of TSV 44. TSV pumping is caused by a mismatch in the coefficient of thermal expansion (CTE) between conductive material 42 and substrate 22, and may cause damage to structures above the TSV (e.g., metallization patterns).

[0032] After the annealing process, a planarization process is performed to remove the conductive material 42, the seed layer 40, and the portion of the liner layer 38 located outside the opening 34 to form a TSV 44. Figure 6 . The top surface of TSV 44 and the topmost dielectric layer of interconnect structure 24 are coplanar within process variations after a planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. The upper portion of TSV 44 (formed in interconnect structure 24) has a greater width than the lower portion of TSV 44 (formed in substrate 22).

[0033] refer to Figure 7 ,exist Figure 6 The interconnect structure 50 is formed above the structure. The interconnect structure 50 includes a dielectric layer 52, a metallization pattern and a via 54, and a top metal 56. Fig.14 5. The interconnect structure 50 is connected to the interconnect structure 24 and TSV 44 through the metallization pattern and via formed in the dielectric layer 52. The metallization pattern and via can be formed using similar processes and materials as the interconnect structure 24, and will not be described again here. In some embodiments, there is more than one layer of top metal 56, such as two top metal layers.

[0034] In some embodiments, dielectric layer 52 is the same material as the dielectric layer of interconnect structure 24, for example, a low-k dielectric. In other embodiments, dielectric layer 52 is formed of a silicon-containing oxide (which may or may not include oxygen). For example, dielectric layer 52 may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc.

[0035] The metallization pattern and the via 54 and the top metal 56 can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, and the like. Examples of forming the metallization pattern and the via 54 and the top metal 56 by a damascene process include: etching the dielectric layer 52 to form an opening; depositing a conductive barrier layer into the opening; plating a metal material, such as copper or a copper alloy; and performing planarization to remove excess portions of the metal material. In other embodiments, the formation of the dielectric layer 52, the metallization pattern and the via 54 and the top metal 56 may include: forming the dielectric layer 52; patterning the dielectric layer 52 to form an opening; forming a metal seed layer (not shown); forming a patterned plating mask (such as a photoresist) to cover some portions of the metal seed layer while leaving other portions exposed; plating the metallization pattern and the via 54 and the top metal 56; removing the plating mask; and etching undesired portions of the metal seed layer. The metallization pattern and the via 54 and the top metal 56 may be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, and the like, or a combination thereof. In some embodiments, top metal 56 is thicker than metallization pattern 54 , such as three times thicker, five times thicker, or any suitable thickness ratio between metallization layers.

[0036] Figure 7 A passivation layer 58 is also shown formed over the dielectric layer 52. In some embodiments, the passivation layer 58 is formed of the same material as the dielectric layer 52. In some embodiments, the passivation layer 58 may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc.; or a combination thereof. The passivation layer 58 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The passivation layer 58 may have a substantially flush upper surface within process variations.

[0037] exist Figure 8 In the embodiment of the present invention, an opening 59 is formed through the passivation layer to expose the surface of the top metal 56. The opening may be formed by any suitable process, such as an etching process.

[0038] exist Fig. 9 In the embodiment of the present invention, a seed layer 60 is formed above the passivation layer 58, in the opening 59, and on the exposed portion of the top metal 56 located in the opening 59. In some embodiments, the seed layer 60 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 60 includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. In some embodiments, a barrier layer (not shown) can be formed before forming the seed layer 60. The barrier layer can include Ti, TiN, etc., or a combination thereof.

[0039] exist Fig.10 In the embodiment, a photoresist 62 is formed and patterned over the seed layer 60. The photoresist 62 may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the redistribution pad 66 (see Fig.12 ).

[0040] exist Fig.11 In the embodiment of the present invention, a conductive material 64 is formed on the exposed seed layer 60 in the opening of the photoresist 62. The conductive material 64 is formed on the seed layer 60 and fills the through hole opening 59. The conductive material 64 can be formed by plating, such as electroplating including electrochemical plating, electroless plating, etc. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. In some embodiments, the electroplating process is a bottom-up plating process that produces a flat upper surface of the conductive material 64.

[0041] exist Fig.12 , the photoresist 62 and the lower portion of the seed layer 60 are removed to form the redistribution pads and vias 66. The photoresist 62 can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Portions of the seed layer 60 can be removed by an acceptable etching process. Because the top surface of the passivation layer 58 is flat, the top surface of the redistribution pads 66 is flat or flush. By making the top surface of the redistribution pads 66 have a flat or flush surface, the bonding vias and bonding pads located above the pads can be formed directly above the redistribution vias and can have a reduced minimum spacing.

[0042] exist Fig.13 In the embodiment of the present invention, a dielectric layer 68 is formed over the passivation layer 58 and the redistribution pads 66. In some embodiments, the dielectric layer 68 is a conformal layer. The dielectric layer 68 can provide an etch stop function for the via openings for the bonding vias formed subsequently (see, for example, Fig.17), and can be considered as an etch stop layer or via defining layer 68. In some embodiments, dielectric layer 68 is formed of a silicon-containing layer. For example, dielectric layer 68 can include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, etc., or a combination thereof.

[0043] exist Fig.14 In the embodiment of the present invention, a dielectric layer 70 is formed over the dielectric layer 68. The dielectric layer 70 provides a flat top surface for forming subsequent layers thereon (see, for example, Fig.15 ), and can be considered a planarization dielectric layer 70. In some embodiments, dielectric layer 70 is formed of a silicon-containing layer. For example, dielectric layer 70 can include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, etc., or a combination thereof. In some embodiments, dielectric layer 70 has a different material composition than dielectric layer 68, thereby making it easier to detect dielectric layer 68 during an etching process that etches through dielectric layers 70 and 68. For example, dielectric layer 68 can be formed of silicon nitride, and dielectric layer 70 can be formed of silicon oxide.

[0044] exist Fig.15 In the embodiment, dielectric layers 72 and 74 are formed over dielectric layer 70. Dielectric layer 72 may provide a warpage control function and may be considered as warpage control layer 72. Dielectric layer 74 may provide a dielectric bonding function and may be considered as bonding dielectric layer 74.

[0045] In some embodiments, the warpage control layer 72 and the bonding dielectric layer 74 can be formed of high modulus and high thermal conductivity materials. In some embodiments, the high modulus material has a modulus greater than 100 gigapascals (GPa). In some embodiments, the high thermal conductivity material has a thermal conductivity greater than 2 watts per meter Kelvin (W / mK). High modulus and high thermal conductivity materials include materials such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, etc., or combinations and sublayers thereof.

[0046] In some embodiments, dielectric layer 72 has a different material composition than dielectric layer 70, thereby making it easier to detect dielectric layer 70 during an etch process that etches through dielectric layers 74 and 72. Fig.15 Three dielectric layers 70, 72, and 74 are shown, but more or less than three dielectric layers may be formed (see, e.g., FIG. 29A to FIG. 29D ).

[0047] By having a warpage layer and bonding layer with high modulus and high thermal conductivity, the warpage control and heat dissipation of the structure are improved.

[0048] Figures 16 to 19Bond pad vias 86 and bond pads 88 are shown formed in dielectric layers 70, 72, and 74. Bond pad vias 86 and bond pads 88 may be formed using any suitable process, such as a single damascene process, a dual damascene process, combinations thereof, or the like. Figures 16 to 19 A dual damascene process is shown.

[0049] exist Fig.16 , opening 78 is located in dielectric layers 74 and 72. In some embodiments, a photoresist (not shown) is formed and patterned on dielectric layer 74. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pattern for bonding pad 88 (see FIG. Fig.19 ) opening 78. In addition, Fig.16 , dielectric layers 74 and 72 are patterned using a patterned photoresist as a mask to form opening 78, wherein the patterning process stops on dielectric layer 70. Dielectric layer 70 is used to stop the etching process for opening 78. Exposed portions of dielectric layer 74 may be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0050] Fig.17 The patterning of dielectric layer 70 is shown. The previous photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. A new photoresist (not shown) may be formed and patterned over patterned dielectric layer 74 and at least partially in opening 78. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pattern for bonding pad vias 86 (see FIG. 1 ). Fig.19 ) opening 80. In addition, Fig.17 In the embodiment of the present invention, the dielectric layer 70 is patterned using the patterned photoresist as a mask to form the opening 80, wherein the patterning process exposes a portion of the redistribution pad 66. The exposed portion of the dielectric layer 70 may be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0051] Fig.18 Barrier layer 84 is shown formed in openings 78 and 80. In some embodiments, barrier layer 84 may include Ti, TiN, etc., or a combination thereof. Barrier layer 84 may be formed in the openings prior to forming bond pad via 86 and bond pad 88.

[0052] exist Fig.19, bonding pad vias 86 and bonding pads 88 can be formed on barrier layer 84 in openings 78 and 80. Bonding pad vias 86 and bonding pads 88 can be formed by processes and materials similar to metallization patterns and vias 54 and redistribution pad vias and pads 66, and are not repeated here. For example, bonding pads 88 can be formed of or include copper. Adjacent bonding pads 88 have a spacing P1. In some embodiments, spacing P1 is as small as 3.0 μm. In some embodiments, spacing P1 is in a range from 3.0 μm to 5.4 μm. According to embodiments in which bonding vias and bonding pads are formed directly above (e.g., overlapping) redistribution vias 66, adjacent redistribution and bonding structures may have a smaller minimum spacing.

[0053] The top surface of the bonding pad 88 is coplanar with the top surface of the uppermost dielectric layer 74. The planarization is achieved by a chemical mechanical polishing (CMP) process or a mechanical grinding process.

[0054] like Fig. 20 As shown in , the integrated circuit die 20 is thinned by thinning the substrate 22 before the subsequent singulation process. The thinning can be performed by a planarization process such as a mechanical grinding process or a CMP process. The thinning process exposes the TSV 44 and the liner 38. After thinning, the TSV 44 provides electrical connections (e.g., interconnects 24 and 50 and bonding pads 88) from the back side of the substrate 22 to the front side of the substrate 22.

[0055] Fig.21 Package structure 100 is shown. Package structure 100 includes substrate 102 similar to substrate 22 of integrated circuit die 20 and interconnect structure 104 including bond pads 106. Interconnect structure 104 and bond pads 106 may be similar to interconnect structures 24 and 50 and bond pads 88, respectively, described above, and are not repeated here.

[0056] exist Fig. 22 , the integrated circuit die 20 is bonded to the package structure 100. Bonding the integrated circuit die 20 to the package structure 100 may be accomplished by direct bonding, where metal-to-metal direct bonds (between bond pads 88 and 106) and dielectric-to-dielectric bonds (such as Si-O-Si bonds between the integrated circuit die 20 and the surface dielectric layer of the package structure 100) are formed. In addition, there may be a single integrated circuit die 20 or multiple dies 20 bonded to the same package structure 100. Multiple dies 20 bonded to the same package structure 100 may be the same or different from each other to form a homogeneous or heterogeneous structure.

[0057] The die 20 is disposed face-down so that the front side of the die 20 faces the package structure 100 and the back side of the die 20 faces away from the package structure 100. The die 20 is bonded to the package structure 100 at the interface 108. Fig.16 As shown, the direct bonding process directly bonds the topmost dielectric layer of the interconnect structure 104 of the package structure 100 to the topmost dielectric layer 74 of the die 20 at the interface 108 by fusion bonding. In an embodiment, the bond between the topmost dielectric layer of the interconnect structure 104 and the topmost dielectric layer 74 of the die 20 can be an oxide-to-oxide bond. The direct bonding process also directly bonds the bond pad 88 of the die 20 to the bond pad 106 of the package structure 100 at the interface 108 by direct metal-to-metal bonding. Therefore, the electrical connection between the die 20 and the package structure 100 is provided by the physical connection of the bond pad 88 to the bond pad 106.

[0058] As an example, the direct bonding process begins by aligning die 20 with package structure 100, for example, by aligning bond pads 88 with bond pads 106. When die 20 and package structure 100 are aligned, bond pads 88 may overlap corresponding bond pads 106. Next, the direct bonding includes a pre-bonding step during which die 20 is in contact with package structure 100. The hybrid bonding process continues with an annealing step, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, such that copper in bond pads 88 and bond pads 106 interdiffuse into each other and thereby form a direct metal-to-metal bond.

[0059] Next, if Fig.23 As shown in , a gap filling process is performed to seal the integrated circuit die 20 in the sealant 110. After formation, the sealant 110 seals the integrated circuit die 20. The sealant 110 may include an oxide. Alternatively, the sealant may be a molding compound, a molded underfill, a resin, an epoxy resin, etc. The sealant 110 may be applied by compression molding, transfer molding, etc., and may be applied in a liquid or semi-liquid form, and then subsequently cured. After depositing the sealant 110, a planarization process is performed to make the backside surface of the integrated circuit die 20 flush with the top surface of the sealant 110 and expose the TSV 44. The surfaces of the TSV 44, the substrate 22, and the sealant 110 are coplanar within the process variation after the planarization process. The planarization process may be, for example, a CMP, a grinding process, etc. In some embodiments, planarization may be omitted, for example, if the TSV 44 has been exposed.

[0060] exist Fig.24In the embodiment of the present invention, a redistribution structure 112 is deposited on the encapsulant 110, the TSV 44 and the integrated circuit die 20. The redistribution structure 112 may include redistribution lines (RDLs), such as metal traces (or metal lines) and vias located under and connected to the metal traces. The redistribution lines of the redistribution structure 112 are physically and electrically connected to the TSV 44 of the die 20.

[0061] According to some embodiments of the present disclosure, the RDL is formed by a plating process, wherein each of the RDLs includes a seed layer (not shown) and a metallized material above the seed layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the RDL. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The seed layer and the metallized material can be formed of the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the seed layer are removed on which the conductive material is not formed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching. The seed layer and the remaining portion of the conductive material form the RDL.

[0062] A dielectric layer or passivation layer may be formed over each layer of metal traces. In some embodiments, the dielectric layer or passivation layer is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layer or passivation layer is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, PSG; etc. The dielectric layer or passivation layer may be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0063] A patterning process may be used to form openings in the top dielectric layer or passivation layer, exposing some or all of the top metal layer of the redistribution structure 112. The patterning process may be an acceptable process, such as by exposing the dielectric layer or passivation layer to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0064] like Fig.25As shown in , a bump 114 is formed through an opening in the dielectric layer of the redistribution structure 112 to contact the metallization pattern in the redistribution structure 112. The bump 114 can be a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), a ball grid array (BGA) bump, etc. In an embodiment, the bump 114 is a C4 bump. The bump 114 can be formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The bump 114 can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer (not shown) is formed on the top of the bump 114. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and can be formed by a plating process.

[0065] Further Fig.25 As shown in , a conductive connector 116 is formed on the bump 114. The conductive connector 116 can be formed of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 116 is formed by initially forming a solder layer by a method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the conductive connector 116 into a desired bump shape.

[0066] Fig.25 The embodiment depicted in FIG. 1 is a chip-on-wafer structure bonded in a face-to-face configuration. Alternatively, the integrated circuit die 20 and the package structure 100 may be bonded in a face-to-back configuration, such as Fig.26 For example, in Fig.26 , the back of die 20 (eg, exposed ends of TSVs 44 and substrate 22) are bonded to a face of package structure 100. Details regarding this embodiment similar to those for previously described embodiments are not repeated here.

[0067] Fig. 27 A cross-sectional view of a wafer-on-wafer structure according to some embodiments is shown. Figures 1 to 25 The embodiment shown is different in that it is a wafer-on-wafer structure rather than a chip-on-wafer structure. Details about this embodiment similar to those for the previously described embodiments will not be repeated here.

[0068] exist Fig. 27In the embodiment, the structure is a wafer-on-wafer structure bonded in a face-to-face configuration, wherein the upper structure is a wafer 20. Wafer 20 is formed similarly to the die 20 described above, and is not repeated here. With respect to this embodiment, the steps of slicing the die 20 and forming the sealant 110 in the previous embodiment are no longer required, and those steps can be omitted from this embodiment. In this embodiment, both wafer 20 and package structure 100 are wafers and are the same size.

[0069] In other embodiments, wafer 20 may be bonded to package structure 100 in a face-to-back configuration. For example, the back of wafer 20 (eg, exposed ends of TSVs 44 and substrate 22 ) may be bonded to a face of package structure 100 .

[0070] The die / wafer 20 may be included in various other packages, such as an integrated fan-out package or a chip-on-wafer-on-substrate package. For example, the die 20 may be bonded to an interposer that is bonded to a package substrate in a chip-on-wafer-on-substrate package. In addition, multiple dies 20 may be packaged together with a redistribution structure (similar to 112 discussed above) in an integrated fan-out package. In addition, the die 20 may be sealed in a molding compound and have a molded through-hole adjacent to the die 20, wherein another packaging structure is bonded above the die 20 in the integrated fan-out package. In other words, the disclosed bonding pads and redistribution structures may be included in any packaging structure in which they are suitable.

[0071] Fig.28A , Fig.28B , Fig.28C and Fig.28D A cross-sectional view illustrating a detailed view of a redistribution and bonding pad structure according to various embodiments. FIG. 28A to FIG. 28D Various alignments of redistribution vias 66 and bonding pad vias 86 are shown in accordance with some embodiments. Fig.28A In FIG. 1 , the edge of the redistribution via 66 is aligned with the edge of the bond pad via 86 such that there is little to no overlap between the two vias 66 and 86 (see, for example, line 120A). Fig.28B , the edge of redistribution via 66 is aligned with the center of bonding pad via 86 such that there is some overlap (e.g., substantially half overlap) between the two vias 66 and 86 (see, e.g., line 120B). Fig.28C , the edge of the redistribution via 66 is aligned with the edge of the bond pad via 86 such that there is a substantially complete overlap between the two vias 66 and 86 (see, e.g., line 120C). Fig.28D, the center of the redistribution via 66 is aligned with the center of the bonding pad via 86 such that there is a complete overlap between the two vias 66 and 86 (see, e.g., line 120D). These embodiments show various configurations of the alignment of the bonding pad via 86 and the redistribution via 66. Fig.28D In embodiments where the through holes are centrally aligned (eg, centrally aligned vias), a maximum reduction in pitch for the bonding pads 88 may be allowed.

[0072] Fig.29A , Fig.29B , Fig.29C and Fig.29D A cross-sectional view illustrating a detailed view of a redistribution and bonding pad structure according to various embodiments. FIG. 29A to FIG. 29D Various configurations of the warpage control layer 72 and the bonding layer 74 are shown according to some embodiments. Fig.29A In , the two layers 74 and 72 are replaced by a single layer 72 / 74 that functions as both a warp control layer and a bonding layer. Fig.29B In, similar to Figures 1 to 20 In the embodiment of FIG. 5 , the planarization layer 70, the warpage control layer 72, and the bonding layer 74 are each separate layers. Fig.29C and Fig.29D In FIG. 7 , the warpage control layer 72 includes sublayers 72A-72C. Fig.29C In FIG. 7 , there are two sub-layers 72A and 72B of the warpage control layer 72. Fig.29D In FIG. 7 , there are three sub-layers 72A, 72B and 72C of the warpage control layer 72 .

[0073] exist FIG. 29A to FIG. 29D In an embodiment, the warpage control layer 72 and the bonding layer 74 have a high modulus and high thermal conductivity material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, etc. or combinations and sub-layers thereof.

[0074] Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.31C and Fig.31D A cross-sectional view illustrating a detailed view of a redistribution and bonding pad structure according to various embodiments. FIG. 30A to FIG. 30B and FIG. 31A to FIG. 31DVarious configurations of layers 70, 72, and 74 (including an intermediate layer 130 between these layers) are shown. The intermediate layer 130 is located between the bonding layer 74 and the warpage control layer 72, between the warpage control layers 72, and / or between the planarization layer 70 and the warpage control layer 72 to improve the adhesion between these layers. The intermediate layer 130 includes a first element from the lower layer and a second element from the upper layer. For example, when the lower layer includes SiN and the upper layer includes SiC, the intermediate layer 130 can be SiCN. As another example, when the bonding layer 74 and the warpage control layer 72 include SiN, SiON, SiC, SiCN, and / or SiCO, respectively, the intermediate layer 130 between them can include SiCN, SiON, and / or SiCO.

[0075] Fig. 30A and Fig. 30B A configuration with an intermediate layer 130 and a warpage control layer 72 is shown. Fig. 30A In the embodiment, the intermediate layer 130 is located between the warpage control layer 72 and the bonding layer 74. Fig. 30B In FIG. 1 , there are two intermediate layers 130A and 130B. The intermediate layer 130A is located between the warpage control layer 72 and the bonding layer 74 , and the intermediate layer 130B is located between the warpage control layer 72 and the planarization layer 70 .

[0076] FIG. 31A to FIG. 31D A configuration having an intermediate layer 130 and multiple warpage control layers 72 is shown. Fig.31A In the embodiment, the intermediate layer 130 is located between the warpage control layer 72A and the bonding layer 74. Fig.31B In the embodiment, the first intermediate layer 130A is located between the warpage control layer 72A and the bonding layer 74, and the second intermediate layer 130B is located between the warpage control layers 72A and 72B. Fig.31C In the embodiment, the first intermediate layer 130A is located between the warpage control layer 72A and the bonding layer 74, the second intermediate layer 130B is located between the warpage control layers 72A and 72B, and the third intermediate layer 130C is located between the warpage control layers 72B and 72C. Fig.31D In the figure, the first intermediate layer 130A is located between the warping control layer 72A and the bonding layer 74, the second intermediate layer 130B is located between the warping control layers 72A and 72B, the third intermediate layer 130C is located between the warping control layers 72B and 72C, and the fourth intermediate layer 130D is located between the warping control layer 72C and the planarization layer 70.

[0077] FIG. 32A to FIG. 32B and FIG. 33A to FIG. 33B A cross-sectional view illustrating a detailed view of a redistribution and bonding pad structure according to various embodiments. FIG. 32A to FIG. 32B and FIG. 33A to FIG. 33B Various configurations of the height and width of the bond pad vias 86 and bond pads 88 are shown. Fig.32A and Fig.32B In the embodiment, the bonding pad 88 has a height H1 as measured from the bottom surface to the top surface, and the bonding pad via 86 has a height H2 as measured from the bottom surface to the top surface. In some embodiments, the ratio of height H2 / H1 can be from 0.5 to 15. In some embodiments, it can be less than 1, such as 0.5. By increasing the bonding pad height H1 relative to the bonding pad via height H2, the device has improved electrical and thermal conductivity.

[0078] exist Fig.33A and Fig.33B In the embodiment of the present invention, the bonding pad 88 has a width W1 as measured from the outer surface, and the bonding pad via 86 has a width W2 as measured from the outer surface. In some embodiments, the ratio of width W1 / W2 can be from 1 to 1.38. If the ratio of W1 / W2 is 1, the bonding pad via 86 and the bonding pad 88 can be formed with a single photolithography process.

[0079] Considering height and width adjustments together, the height ratio H2 / H1 may range from 1-10, and the width ratio W1 / W2 may range from 1-3.

[0080] Described above FIG. 28A to FIG. 33B The various configurations of can be combined together in various configuration combinations. Only some of the configurations considered are shown, but other configurations are also within the scope of the embodiments of the present disclosure.

[0081] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on 3D packages or 3DIC devices. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of 3D packages or 3DICs, using probes and / or probe cards, etc. In some embodiments, for more reliable probe testing, a solder layer may be formed above the redistribution pad 66, and then the solder may be removed before forming the upper layer and the bonding pad. Verification testing may be implemented on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification in conjunction with a known good die to increase yield and reduce cost.

[0082] The embodiments discussed herein may be discussed in a specific context, i.e., a redistribution structure that may be integrated into a device (e.g., a chip or die) or a package (e.g., a chip-on-wafer (CoW) packaging structure or a wafer-on-wafer (WoW) packaging structure). The redistribution structure includes redistribution vias and lines having a flush or flat upper surface to allow for smaller spacing and minimum distances between adjacent redistribution lines and bonding pads and bonding pad vias. In some embodiments, the redistribution vias and lines are formed in the same process, e.g., a dual damascene process. In some embodiments, a warpage layer and a bonding layer having a high modulus and high thermal conductivity are formed over the redistribution lines to improve warpage control and heat dissipation. In addition, the ratio of the thickness of the bonding pad via to the bonding pad is less than that of conventional bonding pad vias and bonding pads. By having such a smaller thickness ratio, the electrical conductivity and thermal conductivity of the structure are improved.

[0083] Embodiments include methods, the methods comprising: forming a first interconnect structure over a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern. The method also comprises: forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having the same material composition. The method also comprises: forming a warpage control dielectric layer over the redistribution pad. The method also comprises: forming a bonding via and a bonding pad over the redistribution pad, the bonding pad being located in the warpage control dielectric layer, the bonding via being electrically coupled to the redistribution pad.

[0084] Embodiments may include one or more of the following features. A method, wherein the redistribution vias and the redistribution pads each include copper. The bonding pads and the bonding vias each include copper. The redistribution vias and the redistribution pads are formed by a single deposition process. Forming the redistribution vias and the redistribution pads above the first interconnect structure includes: forming a dielectric layer above the metallization pattern of the first interconnect structure; forming an opening in the dielectric layer to expose the top metal structure of the first interconnect structure; forming a seed layer on the exposed top metal structure above the dielectric layer and in the opening of the dielectric layer; forming and patterning a mask layer above the seed layer; and performing a plating process to form redistribution vias and redistribution pads in the patterned mask layer, the redistribution vias being located in the opening of the dielectric layer. The method also includes: removing the patterned mask layer; and removing the exposed seed layer from the top surface of the dielectric layer. The bonding pad via overlaps the redistribution via. The method also includes: forming a dielectric layer above the metallization pattern of the first interconnect structure, the redistribution via passes through the dielectric layer, and the redistribution pad is located above the dielectric layer; forming a conformal dielectric layer above the dielectric layer and the redistribution pad; forming a planarization dielectric layer above the conformal dielectric layer, and the warpage control dielectric layer is located on the planarization dielectric layer; and forming a bonding dielectric layer on the warpage control dielectric layer. The bonding via extends through the planarization dielectric layer and the conformal dielectric layer, and wherein the bonding pad extends through the bonding dielectric layer and the warpage control dielectric layer. The method also includes: forming a second warpage control dielectric layer on the warpage control dielectric layer, the material composition of the second warpage control dielectric layer is different from that of the warpage control dielectric layer. The method also includes: forming an intermediate layer between the second warpage control dielectric layer and the warpage control dielectric layer, the material composition of the intermediate layer is different from that of the second warpage control dielectric layer and the warpage control dielectric layer. The method also includes forming a first bonding dielectric layer on the warpage control dielectric layer; and directly bonding the first bonding dielectric layer and the bonding pad to a second bonding dielectric layer and a second bonding pad of a package structure including a second substrate and a second interconnect structure over the second substrate.

[0085] Embodiments include a structure including a first interconnect structure located above a first substrate, the first interconnect structure including a dielectric layer and a metallization pattern. The structure also includes a passivation layer located above the metallization pattern of the first interconnect structure. The structure also includes: redistribution vias and redistribution pads located above the first interconnect structure, the redistribution vias and the redistribution pads being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution vias passing through the passivation layer, and the redistribution pads being located above the passivation layer, the redistribution vias and the redistribution pads having the same material composition; and a conformal dielectric layer located above the passivation layer and the redistribution pads. The structure also includes a planarization dielectric layer located above the conformal dielectric layer. The structure also includes one or more warpage control dielectric layers located above the planarization dielectric layer. The structure also includes a bonding dielectric layer located on the warpage control dielectric layer. The structure also includes a bonding via and a bonding pad located above the redistribution pad, the bonding pad being located in the warpage control dielectric layer and the bonding dielectric layer, the bonding via being located in the planarization dielectric layer and being electrically coupled to the redistribution pad.

[0086] Embodiments may include one or more of the following features. A structure wherein the height of the bonding pad is greater than the height of the bonding via. The redistribution via, the redistribution pad, the bonding pad, and the bonding via each include copper. The bonding via overlaps the redistribution via. The one or more warpage control dielectric layers include a plurality of warpage control dielectric layers. The bonding dielectric layer and the plurality of warpage control dielectric layers each include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or combinations and sublayers thereof.

[0087] Embodiments include structures, the structures including a first interconnect structure located above a first substrate, the first interconnect structure including a dielectric layer and a metallization pattern. The structure also includes a substrate through hole extending through the first interconnect structure and the first substrate. The structure also includes a redistribution through hole located above the first interconnect structure, the redistribution through hole electrically coupled to at least one of the metallization patterns of the first interconnect structure. The structure also includes a redistribution pad located above the redistribution through hole, the redistribution pad electrically coupled to the redistribution through hole, and the redistribution pad and the redistribution through hole are continuous conductive materials. The structure also includes a through hole defining layer located above the redistribution pad, the through hole defining layer is a conformal dielectric layer. The structure also includes a planarization dielectric layer located above the through hole defining layer. The structure also includes one or more warpage control dielectric layers located above the planarization dielectric layer. The structure also includes a bonding through hole located in the planarization dielectric layer and the through hole defining layer, the bonding through hole electrically coupled to the redistribution pad, and the bonding through hole overlaps the redistribution through hole. The structure also includes a bonding pad in the one or more warpage control dielectric layers, the bonding pad being electrically coupled to the bonding via, the bonding pad overlapping the redistribution via.

[0088] Embodiments may include one or more of the following features. The structure also includes a bonding dielectric layer located above the one or more warpage control dielectric layers, the bonding vias being located in the bonding dielectric layer.

[0089] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first interconnect structure above a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern; forming redistribution vias and redistribution pads above the first interconnect structure, the redistribution vias and the redistribution pads being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution vias and the redistribution pads having the same material composition; forming a warpage control dielectric layer above the redistribution pads; and forming bonding vias and bonding pads above the redistribution pads, the bonding pads being located in the warpage control dielectric layer, the bonding vias being electrically coupled to the redistribution pads.

[0090] In some embodiments, each of the redistribution vias and the redistribution pads comprises copper. In some embodiments, each of the bonding pads and the bonding vias comprises copper. In some embodiments, the redistribution vias and the redistribution pads are formed by a single deposition process. In some embodiments, forming the redistribution vias and the redistribution pads above the first interconnect structure comprises: forming a dielectric layer above the metallization pattern of the first interconnect structure; forming an opening in the dielectric layer to expose a top metal structure of the first interconnect structure; forming a seed layer on the exposed top metal structure above the dielectric layer and in the opening of the dielectric layer; forming and patterning a mask layer above the seed layer; and performing a plating process to form the redistribution vias and the redistribution pads in the patterned mask layer, the redistribution vias being located in the opening of the dielectric layer. In some embodiments, the method further comprises: removing the patterned mask layer; and removing the exposed seed layer from the top surface of the dielectric layer. In some embodiments, the bonding pad vias overlap the redistribution vias. In some embodiments, the method further comprises: forming a dielectric layer over the metallization pattern of the first interconnect structure, the redistribution via passing through the dielectric layer, and the redistribution pad being located over the dielectric layer; forming a conformal dielectric layer over the dielectric layer and the redistribution pad; forming a planarization dielectric layer over the conformal dielectric layer, the warpage control dielectric layer being located over the planarization dielectric layer; and forming a bonding dielectric layer over the warpage control dielectric layer. In some embodiments, the bonding via extends through the planarization dielectric layer and the conformal dielectric layer, and wherein the bonding pad extends through the bonding dielectric layer and the warpage control dielectric layer. In some embodiments, the method further comprises: forming a second warpage control dielectric layer over the warpage control dielectric layer, the second warpage control dielectric layer having a material composition different from that of the warpage control dielectric layer. In some embodiments, the method further comprises: forming an intermediate layer between the second warpage control dielectric layer and the warpage control dielectric layer, the intermediate layer having a material composition different from that of the second warpage control dielectric layer and the warpage control dielectric layer. In some embodiments, the method also includes: forming a first bonding dielectric layer on the warpage control dielectric layer; and directly bonding the first bonding dielectric layer and the bonding pad to a second bonding dielectric layer and a second bonding pad of a packaging structure, wherein the packaging structure includes a second substrate and a second interconnect structure located above the second substrate.

[0091] Some other embodiments of the present application provide a semiconductor structure, comprising: a first interconnect structure, located above a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern; a passivation layer, located above the metallization pattern of the first interconnect structure; a redistribution via and a redistribution pad, located above the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via passing through the passivation layer, the redistribution pad being located above the passivation layer, and the redistribution via passing through the passivation layer. The passivation layer and the redistribution pad have the same material composition; a conformal dielectric layer located above the passivation layer and the redistribution pad; a planarization dielectric layer located above the conformal dielectric layer; one or more warpage control dielectric layers located above the planarization dielectric layer; a bonding dielectric layer located on the warpage control dielectric layer; and bonding vias and bonding pads located above the redistribution pad, the bonding pads being located in the warpage control dielectric layer and the bonding dielectric layer, the bonding vias being located in the planarization dielectric layer and electrically coupled to the redistribution pad.

[0092] In some embodiments, the height of the bonding pad is greater than the height of the bonding via. In some embodiments, each of the redistribution via, the redistribution pad, the bonding pad, and the bonding via comprises copper. In some embodiments, the bonding via overlaps the redistribution via. In some embodiments, the one or more warpage control dielectric layers comprise a plurality of warpage control dielectric layers. In some embodiments, each of the bonding dielectric layer and the plurality of warpage control dielectric layers comprises silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or combinations thereof and sublayers thereof.

[0093] Some other embodiments of the present application provide a semiconductor structure, comprising: a first interconnect structure, located above a first substrate, the first interconnect structure comprising a dielectric layer and a metallization pattern; a substrate through hole, extending through the first interconnect structure and the first substrate; a redistribution through hole, located above the first interconnect structure, the redistribution through hole being electrically coupled to at least one of the metallization patterns of the first interconnect structure; a redistribution pad, located above the redistribution through hole, the redistribution pad being electrically coupled to the redistribution through hole, the redistribution pad and the redistribution through hole being continuous conductive material. material; a via defining layer located above the redistribution pad, the via defining layer being a conformal dielectric layer; a planarization dielectric layer located above the via defining layer; one or more warpage control dielectric layers located above the planarization dielectric layer; a bonding via located in the planarization dielectric layer and the via defining layer, the bonding via being electrically coupled to the redistribution pad, the bonding via overlapping the redistribution via; and a bonding pad located in the one or more warpage control dielectric layers, the bonding pad being electrically coupled to the bonding via, the bonding pad overlapping the redistribution via.

[0094] In some embodiments, the semiconductor structure further includes: a bonding dielectric layer located above the one or more warpage control dielectric layers, the bonding via being located in the bonding dielectric layer.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent configurations do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first interconnect structure over a first substrate, wherein the first interconnect structure comprises a dielectric layer and a metallization pattern; forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having the same material composition; forming a warpage control dielectric layer over the redistribution pad; as well as A bonding via and a bonding pad are formed over the redistribution pad, the bonding pad being located in the warpage control dielectric layer, the bonding via being electrically coupled to the redistribution pad.

2. The method according to claim 1, wherein: Each of the redistribution via and the redistribution pad includes copper.

3. The method according to claim 2, wherein: Each of the bonding pad and the bonding via includes copper.

4. The method according to claim 1, wherein: The redistribution via and the redistribution pad are formed by a single deposition process.

5. The method according to claim 1, wherein: Forming a redistribution via and a redistribution pad above the first interconnect structure includes: forming a dielectric layer over the metallization pattern of the first interconnect structure; forming an opening in the dielectric layer to expose a top metal structure of the first interconnect structure; forming a seed layer over the dielectric layer and on the exposed top metal structure in the opening of the dielectric layer; forming and patterning a mask layer over the seed layer; and A plating process is performed to form the redistribution via and the redistribution pad in the patterned mask layer, the redistribution via being located in the opening of the dielectric layer.

6. The method according to claim 5, further comprising: removing the patterned mask layer; as well as The exposed seed layer is removed from a top surface of the dielectric layer.

7. The method according to claim 1, wherein: The bonding pad via overlaps the redistribution via.

8. The method according to claim 1, further comprising: forming a dielectric layer over the metallization pattern of the first interconnect structure, the redistribution via passing through the dielectric layer, and the redistribution pad being located over the dielectric layer; forming a conformal dielectric layer over the dielectric layer and the redistribution pad; forming a planarization dielectric layer over the conformal dielectric layer, the warpage control dielectric layer being located on the planarization dielectric layer; and A bonding dielectric layer is formed on the warpage control dielectric layer.

9. A semiconductor structure comprising: A first interconnect structure, located above the first substrate, wherein the first interconnect structure comprises a dielectric layer and a metallization pattern; a passivation layer located above the metallization pattern of the first interconnect structure; a redistribution via and a redistribution pad, located above the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via passing through the passivation layer, and the redistribution pad being located above the passivation layer, the redistribution via and the redistribution pad having the same material composition; a conformal dielectric layer located above the passivation layer and the redistribution pad; a planarization dielectric layer located above the conformal dielectric layer; one or more warpage control dielectric layers located above the planarization dielectric layer; a bonding dielectric layer located on the warpage control dielectric layer; as well as A bonding via and a bonding pad are located above the redistribution pad, the bonding pad is located in the warpage control dielectric layer and the bonding dielectric layer, the bonding via is located in the planarization dielectric layer and is electrically coupled to the redistribution pad.

10. A semiconductor structure comprising: A first interconnect structure, located above the first substrate, wherein the first interconnect structure comprises a dielectric layer and a metallization pattern; a through substrate via extending through the first interconnect structure and the first substrate; a redistribution via located above the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure; a redistribution pad located above the redistribution through hole, the redistribution pad being electrically coupled to the redistribution through hole, the redistribution pad and the redistribution through hole being continuous conductive material; a via defining layer, located above the redistribution pad, wherein the via defining layer is a conformal dielectric layer; a planarized dielectric layer located above the via defining layer; one or more warpage control dielectric layers located above the planarization dielectric layer; a bonding via located in the planarization dielectric layer and the via definition layer, the bonding via being electrically coupled to the redistribution pad, the bonding via overlapping the redistribution via; as well as A bonding pad is located in the one or more warpage control dielectric layers, the bonding pad is electrically coupled to the bonding via, and the bonding pad overlaps the redistribution via.

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