Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps of providing a substrate and a gate structure located on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; the interlayer dielectric layer is etched, a groove is formed in the interlayer dielectric layer, and the groove is located at the corresponding position of the gate structure; forming a blocking structure in the groove; the interlayer dielectric layer and the blocking structure are etched to form a first through hole and a second through hole, the first through hole is located in the gate structure and penetrates through the blocking structure, the second through hole is located in the substrate on at least one side of the gate structure, and the depth of the second through hole is larger than that of the first through hole. The blocking structure is located at the corresponding position of the gate structure, and the etching rate of the corresponding position of the first through hole is delayed, so that the occurrence of an over-etching phenomenon at the position of the first through hole in the gate structure when the second through hole in the substrate is etched is effectively reduced, the probability of causing the loss of the gate structure is reduced, and the yield of the device is improved. And the performance stability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Semiconductor integrated circuits are integrated on the same wafer, i.e., semiconductor substrate, such as silicon substrate. Each doped region of the integrated circuit device on the wafer needs to be led out through contact holes and metal layers, which form a metal interconnection structure. In the semiconductor manufacturing process, silicon contact hole etching mainly forms two structures, one is the contact hole on the polysilicon gate, and the other is the contact hole on the active area (formed on the electron / hole heavily doped silicon substrate).

[0003] However, the current contact hole forming method still needs to be improved. Summary of the invention

[0004] The problem solved by the present invention is how to improve the method for forming the contact hole so that when the contact hole on the active area is formed, the contact hole on the polysilicon gate is not over-etched.

[0005] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a gate structure located on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; etching the interlayer dielectric layer to form a groove in the interlayer dielectric layer, wherein the groove is located at a position corresponding to the gate structure; forming a blocking structure in the groove; etching the interlayer dielectric layer and the blocking structure to form a first through hole and a second through hole, wherein the first through hole is located on the gate structure and passes through the blocking structure, and the second through hole is located on the substrate on at least one side of the gate structure and the depth of the second through hole is greater than that of the first through hole.

[0006] Optionally, a width of the first through hole is not greater than a width of the blocking structure.

[0007] Optionally, in the step of etching the interlayer dielectric layer and the blocking structure to form the first through hole and the second through hole, the etching rate of the material of the interlayer dielectric layer is greater than the etching rate of the material of the blocking structure.

[0008] Optionally, the material of the interlayer dielectric layer is silicon oxide; and the material of the blocking structure is silicon nitride.

[0009] Optionally, in the step of providing a substrate and a gate structure located on the substrate, the gate structure has a first height relative to the substrate; in the step of etching the interlayer dielectric layer and the blocking structure to form a first through hole and a second through hole, the etching rate of the material of the interlayer dielectric layer and the etching rate of the material of the blocking structure have a first ratio; in the step of forming a blocking structure in the groove, the thickness of the blocking structure is determined based on the first height and the first ratio.

[0010] Optionally, in the step of forming a blocking structure in the groove, a thickness of the blocking structure is a ratio of the first height to the first ratio.

[0011] Optionally, the step of forming a blocking structure in the groove includes: filling a blocking material in the groove; and performing a planarization process to form a blocking structure located in the groove.

[0012] Optionally, the step of etching the interlayer dielectric layer and the blocking structure includes: forming a patterned material on the blocking structure and the interlayer dielectric layer; patterning the patterned material to form a patterned structure having a first opening and a second opening, wherein the first opening is located at a corresponding position of the blocking structure; using the patterned structure as a mask, etching the interlayer dielectric layer and the blocking structure to form the first through hole and the second through hole.

[0013] Optionally, the method further includes: forming a first conductive plug located in the first through hole and a second conductive plug located in the second through hole.

[0014] Optionally, the step of forming a first conductive plug in the first through hole and a second conductive plug in the second through hole includes: filling the first through hole and the second through hole with conductive material to form a first initial conductive plug in the first through hole and a second initial conductive plug in the second through hole; and planarizing the first initial conductive plug, the second initial conductive plug and the interlayer dielectric layer to form a first conductive plug and a second conductive plug.

[0015] Optionally, the first initial conductive plug, the second initial conductive plug, and the interlayer dielectric layer are planarized, and the blocking structure is removed during the process of forming the first conductive plug and the second conductive plug.

[0016] Optionally, in the step of providing a substrate and a gate structure located on the substrate, there are source-drain doped regions in the substrate on both sides of the gate structure; in the step of forming a first conductive plug and a second conductive plug, the first conductive plug is electrically connected to the gate structure, and the second conductive plug is electrically connected to the source-drain doped regions.

[0017] Correspondingly, the present invention further provides a semiconductor structure, which is formed by any of the above-mentioned methods for forming a semiconductor structure.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the method for forming a semiconductor structure of the present invention, the interlayer dielectric layer and the barrier structure are etched to form the first through hole, and the interlayer dielectric layer is etched to form the second through hole, and the depth of the second through hole is greater than that of the first through hole. The barrier structure is located at a position corresponding to the gate structure, which slows down the etching rate at a position corresponding to the first through hole, thereby effectively reducing the occurrence of over-etching at a position where the first through hole on the gate structure is located when the etching of the second through hole on the substrate is completed, reducing the probability of causing loss of the gate structure, and improving the performance stability of the semiconductor device.

[0020] In an optional solution of the present invention, in the step of etching the interlayer dielectric layer and the blocking structure to form the first through hole and the second through hole, the etching rate of the material of the interlayer dielectric layer and the etching rate of the material of the blocking structure have a first ratio. According to the first ratio, the thickness of the blocking structure is regulated, so as to reduce the occurrence of over-etching at the location of the first through hole on the gate structure when the etching of the second through hole on the substrate is completed, reduce the probability of causing loss of the gate structure, and improve the performance stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 to Figure 2 is a schematic structural diagram of each step of a formation process of a semiconductor structure according to an embodiment;

[0022] Figures 3 to 12 It is a structural schematic diagram of each step of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As can be seen from the background technology, there are still problems in the method for forming contact holes in the prior art. The reasons for the problems are analyzed in conjunction with an embodiment:

[0024] Please refer to Figure 1 , providing a substrate 100 and a gate structure 101 located on the substrate 100 ; forming an interlayer dielectric layer 102 on the substrate 100 and the gate structure 101 .

[0025] The material of the interlayer dielectric layer 102 is silicon oxide.

[0026] Please refer to Figure 2, the interlayer dielectric layer 102 is etched to form a first through hole 103 and a second through hole 104, wherein the first through hole 103 is located on the gate structure 101, and the second through hole 104 is located on the substrate 100 on at least one side of the gate structure 101, and the depth of the second through hole 104 is greater than that of the first through hole 103.

[0027] The depth of the second through hole 104 is greater than that of the first through hole 103, and the etched materials are both silicon oxide during the process of etching the first through hole 103 and the second through hole 104. This causes the first through hole 103 on the gate structure 101 to be over-etched when the etching of the second through hole 104 on the substrate 100 is completed, causing loss to the gate structure 101 and affecting the stability of the semiconductor device.

[0028] In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a gate structure located on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; etching the interlayer dielectric layer to form a groove in the interlayer dielectric layer, wherein the groove is located at a position corresponding to the gate structure; forming a blocking structure in the groove; etching the interlayer dielectric layer and the blocking structure to form a first through hole and a second through hole, wherein the first through hole is located on the gate structure and passes through the blocking structure, and the second through hole is located on the substrate on at least one side of the gate structure and the depth of the second through hole is greater than that of the first through hole.

[0029] In the method for forming a semiconductor structure of the technical solution of the present invention, the interlayer dielectric layer and the barrier structure are etched to form a first through hole, and the interlayer dielectric layer is etched to form a second through hole, and the depth of the second through hole is greater than that of the first through hole. The barrier structure is located at a position corresponding to the gate structure, which slows down the etching rate at a position corresponding to the first through hole, thereby effectively reducing the occurrence of over-etching at the position where the first through hole on the gate structure is located when the etching of the second through hole on the substrate is completed, reducing the probability of causing loss of the gate structure, and improving the performance stability of the semiconductor device.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Please refer to Figure 3 , providing a substrate 200 and a gate structure 201 located on the substrate 200 ; forming an interlayer dielectric layer 202 on the substrate 200 and the gate structure 201 .

[0032] The material of the substrate 200 includes: silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 200 includes an active region and an isolation region.

[0033] The material of the interlayer dielectric layer 202 is silicon oxide.

[0034] The gate structure 201 is located on the active region. The substrate 200 has source and drain doping regions on both sides of the gate structure 201. The source and drain doping regions are located in the active region.

[0035] Specifically, in some embodiments of the present invention, the gate structure 201 has a first height H relative to the substrate 200 .

[0036] Please refer to Figure 4 , the interlayer dielectric layer 202 is etched to form a groove 203 in the interlayer dielectric layer 202 , and the groove 203 is located at a position corresponding to the gate structure 201 .

[0037] The groove 203 is located at a position corresponding to the gate structure 201 , that is, the projection of the gate structure 201 on the surface of the substrate 200 is located within the projection range of the groove 203 on the surface of the substrate 200 .

[0038] The interlayer dielectric layer 202 is etched to form a groove 203 in the interlayer dielectric layer 202, comprising: forming a mask layer on the interlayer dielectric layer 202, wherein the mask layer exposes a portion of the interlayer dielectric layer 202; using the mask layer as a mask, the interlayer dielectric layer 202 is etched to form a groove 203 in the interlayer dielectric layer 202, wherein the groove 203 is located at a position corresponding to the gate structure 201.

[0039] Specifically, in some embodiments of the present invention, the etching is dry etching.

[0040] Specifically, in some embodiments of the present invention, the etching is anisotropic etching.

[0041] The position of the groove 203 defines the position of a blocking structure 205 to be formed subsequently, and the groove 203 provides a structural basis for the blocking structure 205 to be formed subsequently.

[0042] Please refer to Figures 5 and 6 In the groove 203 (such as Figure 4 The step of forming the blocking structure 205 in the groove 203 includes: Figure 5 As shown, a barrier material 204 is filled in the groove 203; Figure 6 As shown, a planarization process is performed to form a blocking structure 205 located in the groove 203 .

[0043] The top surface of the blocking structure 205 is flush with the surface of the interlayer dielectric layer 202. The top surface of the blocking structure 205 is flush with the top surface of the interlayer dielectric layer 202, thereby providing a flat growth foundation for the patterned material 206 subsequently formed on the surface of the blocking structure 205 and the surface of the interlayer dielectric layer 202.

[0044] Specifically, in some embodiments of the present invention, the material of the blocking structure 205 is silicon nitride. In other embodiments, the material of the blocking structure may also be other materials.

[0045] The thickness h of the blocking structure 205 is determined based on the first height H of the gate structure 201 and the ratio of the etching rate of the material of the interlayer dielectric layer 202 to the etching rate of the material of the blocking structure 205 .

[0046] The purpose of the planarization process is to obtain a barrier structure 205 with a flat surface.

[0047] The planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0048] Please refer to Figures 7 to 10 , the interlayer dielectric layer 202 and the blocking structure 205 are etched to form a first through hole 210 and a second through hole 211, wherein the first through hole 210 is located on the gate structure 201 and passes through the blocking structure 205, and the second through hole 211 is located on the substrate 200 on at least one side of the gate structure 201 and the depth of the second through hole 211 is greater than that of the first through hole 210.

[0049] The step of etching the interlayer dielectric layer 202 and the blocking structure 205 includes: Figure 7 As shown, a patterned material 206 is formed on the blocking structure 205 and the interlayer dielectric layer 202; Figure 8 As shown, the patterned material 206 is patterned to form a patterned structure 209 having a first opening 207 and a second opening 208, wherein the first opening 207 is located at a position corresponding to the blocking structure 205; Fig. 9As shown, the interlayer dielectric layer 202 and the blocking structure 205 are etched using the patterned structure 209 as a mask to form the first through hole 210 and the second through hole 211. Fig.10 As shown, after the first through hole 210 and the second through hole 211 are formed, the patterned structure 209 is removed.

[0050] The patterned material 206 provides a structural basis for forming a patterned structure 209 .

[0051] The top surface of the blocking structure 205 is flush with the surface of the interlayer dielectric layer 202 , and the surface of the formed patterned material 206 is flat, which can effectively ensure the implementation of the patterning process of the patterned material 206 and the accuracy of the patterning of the patterned material 206 .

[0052] The first opening 207 of the patterned structure 209 is used to define the position and width of the first through hole 210 ; the second opening 208 of the patterned structure 209 is used to define the position and width of the second through hole 211 .

[0053] The width of the first through hole 210 is the size of the first through hole 210 in a direction from one gate structure 201 to an adjacent gate structure 201 .

[0054] The width of the second through hole 211 is the size of the second through hole 211 in a direction from one gate structure 201 to an adjacent gate structure 201 .

[0055] Specifically, in some embodiments of the present invention, the width of the first through hole 210 is not greater than the width of the blocking structure 205. That is, the projection of the first through hole 210 on the surface of the substrate 200 is within the projection range of the blocking structure 205 on the surface of the substrate 200, and the width of the blocking structure 205 is greater than or equal to the width of the first through hole 210, which can effectively expand the process window of the formed first through hole 210 and is conducive to improving the etching accuracy of the first through hole 210.

[0056] Specifically, in some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 and the blocking structure 205 to form the first through hole 210 and the second through hole 211, the etching rate of the material of the interlayer dielectric layer 202 is greater than the etching rate of the material of the blocking structure 205. The etching rate of the material of the blocking structure 205 is less than the etching rate of the material of the interlayer dielectric layer 202, so that within the same etching time, the depth of the etched first through hole 210 is less than the depth of the second through hole 211, thereby reducing the occurrence of over-etching at the location of the first through hole 210 on the gate structure 201, reducing the possibility of loss of the gate structure 201, and improving the performance stability of the semiconductor device.

[0057] Specifically, in some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 and the blocking structure 205 to form the first through hole 210 and the second through hole 211 , the etching is dry etching.

[0058] Specifically, in some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 and the blocking structure 205 to form the first through hole 210 and the second through hole 211, the etching is anisotropic etching.

[0059] In the step of etching the interlayer dielectric layer 202 and the blocking structure 205 to form the first through hole 210 and the second through hole 211, the etching rate of the material of the interlayer dielectric layer 202 and the etching rate of the material of the blocking structure 205 have a first ratio A. Specifically, in some embodiments of the present invention, in the step of forming the blocking structure 205 in the groove 203, the thickness h of the blocking structure 205 is determined based on the first height H of the gate structure 201 and the first ratio A. The relationship between the thickness h of the blocking structure 205 and the first height H and the first ratio A is:

[0060] h=H / (A-1).

[0061] Please refer to Figure 11 to Figure 12 After forming the first through hole 210 and the second through hole 211 , the method further includes: forming a first conductive plug 214 located in the first through hole 210 and a second conductive plug 215 located in the second through hole 211 .

[0062] The steps of forming the first conductive plug 214 in the first through hole 210 and the second conductive plug 215 in the second through hole 211 include: Fig.11As shown, the first through hole 210 and the second through hole 211 are filled with conductive material to form a first initial conductive plug 212 located in the first through hole 210 and a second initial conductive plug 213 located in the second through hole 211; Fig.12 As shown, the first initial conductive plug 212 , the second initial conductive plug 213 , and the interlayer dielectric layer 202 are planarized to form a first conductive plug 214 and a second conductive plug 215 .

[0063] In the step of filling the first through hole 210 and the second through hole 211 with a conductive material to form a first initial conductive plug 212 in the first through hole 210 and a second initial conductive plug 213 in the second through hole 211 , the conductive material includes tungsten.

[0064] Specifically, in some embodiments of the present invention, the first initial conductive plug 212, the second initial conductive plug 213 and the interlayer dielectric layer 202 are planarized to form the first conductive plug 214 and the second conductive plug 215, and the blocking structure 205 is removed.

[0065] In the step of forming the first conductive plug 214 and the second conductive plug 215 , the first conductive plug 214 is electrically connected to the gate structure 201 , and the second conductive plug 215 is electrically connected to the source-drain doped region.

[0066] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, which is formed by the above-mentioned method for forming a semiconductor structure, and will not be described in detail herein.

[0067] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate and a gate structure located on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; Etching the interlayer dielectric layer to form a groove in the interlayer dielectric layer, wherein the groove is located at a position corresponding to the gate structure; forming a blocking structure in the groove; The interlayer dielectric layer and the blocking structure are etched to form a first through hole and a second through hole, wherein the first through hole is located on the gate structure and passes through the blocking structure, and the second through hole is located on the substrate on at least one side of the gate structure and has a depth greater than that of the first through hole.

2. The method for forming a semiconductor structure according to claim 1, wherein: The width of the first through hole is not greater than the width of the blocking structure.

3. The method for forming a semiconductor structure according to claim 1, wherein: In the step of etching the interlayer dielectric layer and the barrier structure to form the first through hole and the second through hole, the etching rate of the material of the interlayer dielectric layer is greater than the etching rate of the material of the barrier structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the interlayer dielectric layer is silicon oxide; the material of the barrier structure is silicon nitride.

5. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate and a gate structure on the substrate, the gate structure has a first height relative to the substrate; In the step of etching the interlayer dielectric layer and the barrier structure to form the first through hole and the second through hole, the etching rate of the material of the interlayer dielectric layer and the etching rate of the material of the barrier structure have a first ratio; In the step of forming a blocking structure in the groove, a thickness of the blocking structure is determined based on the first height and the first ratio.

6. The method for forming a semiconductor structure according to claim 5, wherein: In the step of forming a blocking structure in the groove, a thickness of the blocking structure is a ratio of the first height to the first ratio.

7. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a blocking structure in the groove comprises: filling the groove with a barrier material; A planarization process is performed to form a blocking structure located in the groove.

8. The method for forming a semiconductor structure according to claim 1 or 7, wherein: The step of etching the interlayer dielectric layer and the blocking structure comprises: forming a patterned material on the barrier structure and the interlayer dielectric layer; Patterning the patterned material to form a patterned structure having a first opening and a second opening, wherein the first opening is located at a position corresponding to the blocking structure; The interlayer dielectric layer and the blocking structure are etched using the patterned structure as a mask to form the first through hole and the second through hole.

9. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A first conductive plug is formed in the first through hole and a second conductive plug is formed in the second through hole.

10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming a first conductive plug located in the first through hole and a second conductive plug located in the second through hole comprises: Filling the first through hole and the second through hole with a conductive material to form a first initial conductive plug in the first through hole and a second initial conductive plug in the second through hole; The first initial conductive plug, the second initial conductive plug and the interlayer dielectric layer are planarized to form a first conductive plug and a second conductive plug.

11. The method for forming a semiconductor structure according to claim 10, wherein: The first initial conductive plug, the second initial conductive plug and the interlayer dielectric layer are planarized, and the blocking structure is removed during the process of forming the first conductive plug and the second conductive plug.

12. The method for forming a semiconductor structure according to claim 9, wherein: In the step of providing a substrate and a gate structure located on the substrate, source and drain doped regions are provided in the substrate on both sides of the gate structure; In the step of forming the first conductive plug and the second conductive plug, the first conductive plug is electrically connected to the gate structure, and the second conductive plug is electrically connected to the source-drain doped region.

13. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure as claimed in any one of claims 1 to 12.

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