Packaging structure and packaging method

Abstract

The embodiment of the invention discloses a packaging structure and a packaging method. The packaging structure comprises a stacking structure and a bonding substrate, the stacking structure comprises a plurality of chips which are stacked in sequence; the bonding substrate is located between the packaging substrate and the stacking structure and comprises a first substrate and a second substrate which are connected in a bonding mode, at least one of the first substrate and the second substrate is provided with a heat dissipation channel for a heat dissipation medium to circulate, and the surface, making contact with the heat dissipation medium, of the heat dissipation channel is provided with a hydrophobic part.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor packaging technology, and are related to but not limited to a packaging structure and a packaging method. Background Art

[0002] Three Dimensions (3D) stacking packaging technology, also known as stacked chip packaging technology, is a packaging technology that stacks two or more chips vertically in the same packaging structure without changing the planar dimensions of the packaging structure. By stacking multiple chips in three dimensions, larger storage capacity, higher bandwidth, and greater computing power can be achieved, significantly improving the performance of the packaged device.

[0003] However, since multiple chips are stacked closely in the vertical direction, it becomes more difficult to dissipate the heat of the chip. If the heat generated by the chip during operation is difficult to dissipate quickly, the temperature of the chip will be too high, affecting the performance and reliability of the chip, and in severe cases, the chip may be damaged. Therefore, how to improve the heat dissipation performance of the packaging structure has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a packaging structure is provided, comprising: a stacking structure and a bonding substrate; the stacking structure comprises a plurality of chips stacked in sequence; the bonding substrate is located between the packaging substrate and the stacking structure and comprises a first substrate and a second substrate bonded to each other, wherein at least one of the first substrate and the second substrate has a heat dissipation channel for circulating a heat dissipation medium, and a surface where the heat dissipation channel contacts the heat dissipation medium has a hydrophobic portion.

[0005] In some embodiments, the heat dissipation channel includes a plurality of first heat dissipation channels that are connected; the first substrate includes: a first dielectric layer and a conductive wire; the first dielectric layer is located between the packaging substrate and the second substrate, wherein the first heat dissipation channel extends along a surface of the first dielectric layer relatively away from the packaging substrate into the first dielectric layer, and a height of the first heat dissipation channel is less than a height of the first dielectric layer; the conductive wire is located in the first dielectric layer, wherein the conductive wire and the first heat dissipation channel are spaced apart from each other.

[0006] In some embodiments, the heat dissipation channel includes a plurality of second heat dissipation channels that are connected to each other; the second substrate includes: a second dielectric layer, the second dielectric layer is located between the first substrate and the stacking structure, wherein the second heat dissipation channel extends along a surface of the second dielectric layer relatively close to the first substrate into the second dielectric layer, and a height of the second heat dissipation channel is less than a height of the second dielectric layer; the bonding substrate also includes: a connecting structure, the connecting structure extends through the second dielectric layer and a portion of the first dielectric layer and is connected to the conductive line.

[0007] In some embodiments, a plurality of the first heat dissipation channels correspond to a plurality of the second heat dissipation channels one by one, wherein the first heat dissipation channels are joined to the corresponding second heat dissipation channels, and the first dielectric layer is joined to the second dielectric layer.

[0008] In some embodiments, the bonding substrate further includes: a first bump and a second bump; the first bump is located between the packaging substrate and the first substrate, wherein the first bump connects the packaging substrate and the first substrate respectively; the second bump is located between the stacking structure and the second substrate, wherein the second bump connects the stacking structure and the second substrate respectively.

[0009] In some embodiments, the hydrophobic portion includes at least one of a hydrophobic group, a carbon nanotube-based coating, a silica-based coating, and a metal oxide-based coating.

[0010] According to a second aspect of an embodiment of the present disclosure, a packaging method is provided, comprising: forming a stacking structure, the stacking structure comprising a plurality of chips stacked in sequence; forming a first substrate and a second substrate, wherein at least one of the first substrate and the second substrate has a heat dissipation channel for a heat dissipation medium to flow through, and a surface in contact between the heat dissipation channel and the heat dissipation medium has a hydrophobic portion; bonding the first substrate and the second substrate to form a bonding substrate, and packaging the bonding substrate and the stacking structure to one side of a packaging substrate, so that the bonding substrate is located between the packaging substrate and the stacking structure.

[0011] In some embodiments, the forming of the first substrate includes: forming a first dielectric layer and a conductive line on one side of a first carrier, the conductive line being located in the first dielectric layer; etching the first dielectric layer to form a plurality of first heat dissipation channels extending into and connected to the first dielectric layer, wherein a height of the first heat dissipation channels is less than a height of the first dielectric layer; bonding the first substrate and the second substrate to form a bonded substrate includes: bonding the first substrate and the second substrate on which the plurality of first heat dissipation channels are formed, wherein the heat dissipation channels include the plurality of first heat dissipation channels; removing the first carrier to form the bonded substrate.

[0012] In some embodiments, the forming of the second substrate includes: forming a second dielectric layer on one side of a second carrier; etching the second dielectric layer to form a plurality of second heat dissipation channels extending into and connected to the second dielectric layer, wherein a height of the second heat dissipation channels is less than a height of the second dielectric layer; bonding the first substrate and the second substrate to form a bonded substrate includes: bonding the first substrate on which the plurality of first heat dissipation channels are formed and the second substrate on which the plurality of second heat dissipation channels are formed, wherein the heat dissipation channels include the plurality of first heat dissipation channels and the plurality of second heat dissipation channels; removing the first carrier and the second carrier to form the bonded substrate.

[0013] In some embodiments, the bonding of the first substrate and the second substrate to form a bonded substrate also includes: bonding the first substrate and the second substrate so that a plurality of the first heat dissipation channels and a plurality of the second heat dissipation channels correspond one to one, wherein the first heat dissipation channels and the corresponding second heat dissipation channels are bonded, and the first dielectric layer and the second dielectric layer are bonded; forming a connection structure extending through the second dielectric layer and a portion of the first dielectric layer, the connection structure connecting the conductive wires.

[0014] In the disclosed embodiment, the packaging structure includes a stacking structure and a bonding substrate, the stacking structure includes a plurality of chips stacked in sequence, the bonding substrate is located between the packaging substrate and the stacking structure and includes a first substrate and a second substrate bonded to each other, at least one of the first substrate and the second substrate has a heat dissipation channel for the circulation of a heat dissipation medium, and the surface where the heat dissipation channel contacts the heat dissipation medium has a hydrophobic portion. In this way, on the first hand, the heat dissipation channel is closer to the bottom chip in the stacking structure, and by adding a circulated heat dissipation medium to the heat dissipation channel, the heat dissipation medium can promptly take away the heat generated by the bottom chip at work, thereby achieving a better heat dissipation effect, which is beneficial to improving the heat dissipation performance of the packaging structure and ensuring the stable operation of the chip; on the second hand, since the surface where the heat dissipation channel contacts the heat dissipation medium has a hydrophobic portion, the hydrophobic portion can prevent the heat dissipation medium from damaging the surface of the heat dissipation channel, thereby playing a role in protecting the heat dissipation channel. On the third hand, the packaging structure is simple in structure and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0016] Figure 1 It is a schematic diagram of a packaging structure provided by an exemplary embodiment.

[0017] Figure 2 It is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure.

[0018] Figure 3 It is a flow chart of a packaging method provided by an embodiment of the present disclosure.

[0019] Figure 4 It is a schematic diagram of forming a stacking structure provided by an embodiment of the present disclosure.

[0020] Figures 5 to 14 It is a schematic diagram of a bonding substrate having a heat dissipation channel provided by an embodiment of the present disclosure.

[0021] Fig.15 and Fig.16 It is a schematic diagram of packaging a stacking structure and a bonding substrate onto a packaging substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0023] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0024] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0025] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0027] Before introducing the embodiments of the present disclosure, various directions that may be involved in the following description are defined. A first direction (represented as the x direction in the accompanying drawings) and a second direction (represented as the y direction in the accompanying drawings) that intersect are defined in a plane parallel to the semiconductor layer, and a direction perpendicular to the plane of the semiconductor layer is defined as a third direction (represented as the z direction in the accompanying drawings). The x direction and the y direction intersect, and the angle between the x direction and the y direction includes an acute angle, a right angle, or an obtuse angle. For ease of understanding, the angle between the x direction and the y direction will be taken as a right angle below, that is, the x direction, the y direction, and the z direction are perpendicular to each other.

[0028] In today's three-dimensional stacking process, memory chips and logic chips can be stacked up and down to effectively improve computing performance. However, during the operation of high-performance chips, a large amount of heat energy is easily generated on the memory chips and logic chips. Due to the three-dimensional integrated packaging structure, the geothermal energy is concentrated, resulting in poor heat dissipation performance of the packaged devices, leading to energy efficiency and performance degradation of three-dimensional integrated devices. Therefore, how to solve the heat dissipation problem of three-dimensional integrated devices has become the key to industry development research. The following will combine Figure 1 An exemplary description is given.

[0029] Figure 1 1 is a schematic diagram of a three-dimensional integrated device provided by an exemplary embodiment, wherein the three-dimensional integrated device includes but is not limited to a high-performance storage and computing integrated chip, for example, a high bandwidth memory (HBM). Figure 1 As shown, the three-dimensional integrated device 10 includes a first chip 11, a second chip 12 and a plurality of third chips 13 stacked in sequence. The first chip 11 includes but is not limited to a system-on-chip (SoC), on which at least one of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), a video processor (VPU), and a digital signal processor (DSP) is integrated. The second chip 12 includes but is not limited to a logic chip, which includes various control circuits for controlling the memory chip to perform logic operations. The third chip 13 includes but is not limited to a memory chip, which includes but is not limited to a dynamic random access memory (DRAM). By stacking and packaging the first chip 11, the second chip 12 and a plurality of third chips 13 in sequence, a large-capacity, high-bandwidth memory array can be realized.

[0030] However, Figure 1 In the three-dimensional integrated device shown, the heat dissipation performance of the lower half area where the first chip 11 and the second chip 12 are located is poor. The heat generated by the first chip 11 and the second chip 12 is difficult to dissipate through an external heat sink or fan, thereby limiting the improvement of the heat dissipation performance of the three-dimensional integrated device.

[0031] Based on one or more of the above technical problems, an embodiment of the present disclosure provides a packaging structure. The packaging structure includes: a stacking structure and a bonding substrate; the stacking structure includes a plurality of chips stacked in sequence; the bonding substrate is located between the packaging substrate and the stacking structure and includes a first substrate and a second substrate bonded to each other, wherein at least one of the first substrate and the second substrate has a heat dissipation channel for the circulation of a heat dissipation medium, and the surface where the heat dissipation channel and the heat dissipation medium contact each other has a hydrophobic portion. In this way, on the first hand, since the bonding substrate with the heat dissipation channel is located between the packaging substrate and the stacking structure, the heat dissipation channel is close to the bottom chip (for example, the first chip and the second chip) in the stacking structure, and by adding a circulated heat dissipation medium to the heat dissipation channel, the heat dissipation medium can promptly take away the heat generated by the bottom chip at work, thereby achieving a better heat dissipation effect, which is beneficial to improving the heat dissipation performance of the packaging structure; on the second hand, since the surface where the heat dissipation channel and the heat dissipation medium contact each other has a hydrophobic portion, the hydrophobic portion can prevent the heat dissipation medium introduced into the heat dissipation channel from causing damage (for example, corrosion, etc.) to the surface of the heat dissipation channel, thereby protecting the heat dissipation channel.

[0032] Figure 2 is a schematic diagram of a packaging structure provided by an embodiment of the present disclosure, and the packaging structure includes but is not limited to a high-performance storage and computing integrated chip, such as HBM, etc. Figure 2 As shown, the packaging structure includes a stacking structure 100, a bonding substrate 200 and a packaging substrate 300, wherein the bonding substrate 200 is located between the packaging substrate 300 and the stacking structure 100, and the bonding substrate 200 can have both connection and heat dissipation functions.

[0033] The stacking structure 100 includes a plurality of chips stacked in sequence, and the plurality of chips may include a first chip 110, a second chip 120, and a plurality of third chips 130 stacked in sequence. The first chip 110 includes but is not limited to SoC, and at least one of the processors such as CPU, GPU, NPU, VPU, DSP, etc. is integrated on the SoC. The second chip 120 includes but is not limited to a logic chip, and the logic chip includes various control circuits for controlling the memory chip to complete the logic operation. The third chip 130 includes but is not limited to a memory chip, and the memory chip includes but is not limited to DRAM. By stacking and packaging the first chip 110, the second chip 120, and the plurality of third chips 130 in sequence, a large-capacity, high-bandwidth storage array can be realized. Multiple chips can be vertically connected to each other through advanced packaging technologies such as through-silicon vias (TSV), micro bumps, and stack bonding. Exemplarily, TSV technology can be used to form a through-silicon connection structure 140 in each chip, and micro bump technology can be used to form micro bumps 150 on the surface of each chip.

[0034] The bottommost chip (i.e., the first chip 110) among the multiple chips can be bonded to the bonding substrate 200, and the topmost chip (i.e., the topmost third chip 130) among the multiple chips can be in contact with the substrate 101, and the substrate 101 can serve as a supporting substrate for supporting the multiple chips. The material of the substrate 101 includes a single semiconductor material (e.g., silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art. In this embodiment, the substrate 101 is a silicon substrate as an example for description.

[0035] The bonding substrate 200 includes a first substrate 210 and a second substrate 220 that are bonded to each other, wherein at least one of the first substrate 210 and the second substrate 220 has a heat dissipation channel for the heat dissipation medium to flow through. In this embodiment, both the first substrate 210 and the second substrate 220 have heat dissipation channels, and the setting of the heat dissipation channels can effectively remove the heat generated by the stacked structure 100 through the heat dissipation medium, thereby improving the heat dissipation performance.

[0036] The heat dissipation medium may include at least one of a gas and a liquid. For example, a heat dissipation liquid, such as water or other liquids, may be added to the heat dissipation channel. For another example, a heat dissipation gas, such as an inert gas that has been cooled, may be added to the heat dissipation channel. It is understood that the flow of the heat dissipation medium can promptly take away the heat generated by the chip operation, especially the heat generated by the bottom chip, thereby avoiding the heat concentration of the bottom chip. For ease of understanding, the following description will be given by taking the heat dissipation medium as a liquid as an example.

[0037] The surface where the heat dissipation channel contacts the heat dissipation medium has a hydrophobic portion. The hydrophobic portion makes it difficult for the heat dissipation liquid to adsorb on the surface of the heat dissipation channel, thereby protecting the heat dissipation channel. The hydrophobic portion may include at least one of a hydrophobic film layer formed on the surface of the heat dissipation channel and a hydrophobic group formed on the surface of the heat dissipation channel. The material of the hydrophobic film layer includes at least one of a carbon nanotube-based coating, a silica-based coating, and a metal oxide-based coating. The hydrophobic group includes a hydrocarbon group containing aromatic, ester, ether, amine, amide, or a hydrocarbon group containing a double bond. Here, the surface of the heat dissipation channel may be subjected to at least one of surface treatment processes such as micro-nano structuring, chemical modification, self-assembly technology, and electrochemical deposition, thereby forming a hydrophobic group on the surface of the heat dissipation channel.

[0038] Of course, in other embodiments, only the first substrate 210 or the second substrate 220 has a heat dissipation channel. For example, a first groove is formed on the surface of the first substrate 210, and the bottom of the first groove is located in the first substrate 210. After the surface of the first substrate 210 formed with the first groove and the second substrate 220 are bonded, the first groove can form a sealed heat dissipation channel, that is, the first substrate 210 has a heat dissipation channel (hereinafter referred to as the first heat dissipation channel 212), and the surface of the second substrate 220 can be a flat surface. For another example, a second groove is formed on the surface of the second substrate 220, and the bottom of the second groove is located in the second substrate 220. After the surfaces of the first substrate 210 and the second substrate 220 formed with the second groove are bonded, the second groove can form a sealed heat dissipation channel, that is, the second substrate 220 has a heat dissipation channel (hereinafter referred to as the second heat dissipation channel 222), and the surface of the first substrate 210 can be a flat surface.

[0039] It should be noted that the two substrates may be bonded together using a bonding process, for example, a bond may be formed between the surfaces of the two substrates without using an intermediate layer such as solder or adhesive. The "bonding" referred to in the present disclosure may be any appropriate bonding technology, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, and eutectic bonding.

[0040] In the packaging structure provided by the embodiment of the present disclosure, on the first hand, the heat dissipation channel is close to the bottom chip (for example, the first chip 110 and the second chip 120) in the stacking structure 100. By adding a circulated heat dissipation medium into the heat dissipation channel, the heat dissipation medium can promptly take away the heat generated by the bottom chip at work, thereby achieving a better heat dissipation effect, which is beneficial to improving the heat dissipation performance of the packaging structure. On the second hand, since the surface where the heat dissipation channel and the heat dissipation medium contact has a hydrophobic portion, the hydrophobic portion can prevent the heat dissipation medium from causing damage to the surface of the heat dissipation channel (for example, corrosion, etc.), thereby playing a role in protecting the heat dissipation channel.

[0041] In some embodiments, the heat dissipation channel includes a plurality of first heat dissipation channels 212 that are connected; the first substrate 210 includes: a first dielectric layer 211 and a conductive wire 213; the first dielectric layer 211 is located between the packaging substrate 300 and the second substrate 220, wherein the first heat dissipation channel 212 extends into the first dielectric layer 211 along a surface of the first dielectric layer 211 that is relatively far away from the packaging substrate 300, and the height of the first heat dissipation channel 212 is less than the height of the first dielectric layer 211; the conductive wire 213 is located in the first dielectric layer 211, wherein the conductive wire 213 and the first heat dissipation channel 212 are spaced apart from each other. Here, the plurality of first heat dissipation channels 212 that are connected are used for the circulation of heat dissipation medium, and the surface of the first heat dissipation channel 212 that contacts the heat dissipation medium has a hydrophobic portion. The first substrate 210 may also include Figure 2 Other film layers not shown.

[0042] For example, refer to Figure 2 As shown, the first dielectric layer 211 has a first surface and a second surface relative to each other, the first surface may be a surface of the first dielectric layer 211 relatively far from the package substrate 300, and the second surface may be a surface of the first dielectric layer 211 relatively close to the package substrate 300. A plurality of first heat dissipation channels 212 may extend along the first surface into the first dielectric layer 211, that is, the bottom of the first heat dissipation channel 212 is located between the first surface and the second surface, therefore, the height of the first heat dissipation channel 212 is less than the height of the first dielectric layer 211, thereby ensuring the sealing of the first heat dissipation channel 212. The conductive wire 213 may be located between the first surface and the second surface, and the conductive wire 213 and the first heat dissipation channel 212 may be spaced apart from each other by the first dielectric layer 211, thereby avoiding mutual interference.

[0043] The material of the first dielectric layer 211 includes a dielectric material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The conductive wire 213 is used to realize the interconnection between the chip in the stacked structure 100 and the circuit in the packaging substrate 300. The material of the conductive wire 213 includes a conductive material, for example, at least one of copper, gold, silver, and platinum. The packaging substrate 300 includes but is not limited to a printed circuit board (PCB).

[0044] In the embodiment of the present disclosure, by setting both the first heat dissipation channel 212 and the conductive wire 213 in the first dielectric layer 211, and the conductive wire 213 and the first heat dissipation channel 212 are spaced apart from each other, the bonding substrate 200 can not only realize the heat dissipation function, but also realize the interconnection function between the chip and the packaging substrate 300. In addition, a certain amount of heat will be generated in the process of the conductive wire 213 transmitting the electrical signal, and the heat dissipation medium flowing in the first heat dissipation channel 212 can also take away the heat generated by the conductive wire 213 in time, further improving the heat dissipation performance of the packaging structure. In addition, since the surface of the first heat dissipation channel 212 has a hydrophobic portion, the hydrophobic portion can prevent the heat dissipation medium from damaging the surface of the first heat dissipation channel 212, thereby preventing the packaging structure from leaking electricity, short circuiting, etc.

[0045] In other embodiments, the heat dissipation channel includes a plurality of second heat dissipation channels 222 that are connected; the second substrate 220 includes: a second dielectric layer 221, the second dielectric layer 221 is located between the first substrate 210 and the stacked structure 100, wherein the second heat dissipation channel 222 extends into the second dielectric layer 221 along a surface of the second dielectric layer 221 that is relatively close to the first substrate 210, and the height of the second heat dissipation channel 222 is less than the height of the second dielectric layer 221; the bonding substrate 200 also includes: a connection structure 223, the connection structure 223 extends through the second dielectric layer 221 and a portion of the first dielectric layer 211 and is connected to the conductive wire 213. Here, the plurality of second heat dissipation channels 222 that are connected are used for the circulation of heat dissipation medium, and the surface of the second heat dissipation channel 222 that contacts the heat dissipation medium has a hydrophobic portion. The second substrate 220 may also include Figure 2 Other film layers not shown.

[0046] For example, refer to Figure 2As shown, the second dielectric layer 221 has a third surface and a fourth surface relative to each other. The third surface may be a surface of the second dielectric layer 221 relatively close to the first substrate 210, and the fourth surface may be a surface of the second dielectric layer 221 relatively far from the first substrate 210. Multiple second heat dissipation channels 222 may extend along the third surface into the second dielectric layer 221, that is, the bottom of the second heat dissipation channel 222 is located between the third surface and the fourth surface. Therefore, the height of the second heat dissipation channel 222 is less than the height of the second dielectric layer 221, thereby ensuring the sealing of the second heat dissipation channel 222. The connection structure 223 may extend through the third surface along the fourth surface until the connection conductive line 213 is connected, that is, the connection structure 223 extends through the second dielectric layer 221 and a portion of the first dielectric layer 211. The connection structure 223 and the second heat dissipation channel 222 may be spaced apart from each other by the second dielectric layer 221, thereby avoiding mutual interference.

[0047] The material of the second dielectric layer 221 includes dielectric materials, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The connection structure 223 is used to realize the interconnection between the chip and the conductive line 213 in the stacked structure 100, and the material of the connection structure 223 includes a conductive material, for example, polysilicon, doped polysilicon, metal (for example, tungsten, titanium, tantalum, etc.), metal silicide (for example, tungsten silicide, titanium silicide, etc.), metal nitride (for example, tungsten nitride, tantalum nitride, etc.) At least one. It can be understood that in this example, the bonding interface of the first substrate 210 and the second substrate 220 is the contact interface between the first surface and the third surface.

[0048] Of course, the above two embodiments can be combined, that is, a plurality of first heat dissipation channels 212 are formed in the first dielectric layer 211, and a plurality of second heat dissipation channels 222 are formed in the second dielectric layer 221, that is, the first substrate 210 and the second substrate 220 both have heat dissipation channels, and the heat dissipation channels of the bonding substrate 200 include a plurality of first heat dissipation channels 212 and a plurality of second heat dissipation channels 222.

[0049] In some embodiments, a plurality of first heat dissipation channels 212 and a plurality of second heat dissipation channels 222 correspond one to one, wherein the first heat dissipation channels 212 and the corresponding second heat dissipation channels 222 are joined, and the first dielectric layer 211 and the second dielectric layer 221 are joined. The first heat dissipation channels 212 and the corresponding second heat dissipation channels 222 can be aligned and joined, so that the height of the heat dissipation channels is increased, thereby improving the heat dissipation performance. Here, the aligned and joined first heat dissipation channels 212 and the second heat dissipation channels 222 can constitute a sub-heat dissipation channel, and the heat dissipation channel includes a plurality of sub-heat dissipation channels, and the plurality of sub-heat dissipation channels are connected to each other.

[0050] Of course, in other embodiments, the first heat dissipation channel 212 may also be joined to the corresponding second dielectric layer 221, and the second heat dissipation channel 222 may also be joined to the corresponding first dielectric layer 211, that is, the first heat dissipation channel 212 and the second heat dissipation channel 222 are not aligned and joined, so that the density of the heat dissipation channel per unit area is increased, thereby improving the heat dissipation performance.

[0051] In some embodiments, reference Figure 2 As shown, the bonding substrate 200 further includes: an input channel S1 and an output channel S2; wherein the heat dissipation channel is connected to the input channel S1 and the output channel S2 respectively. The input channel S1 and the output channel S2 can be located at the edge of the bonding substrate 200, the input channel S1 is used to pass the heat dissipation medium into the heat dissipation channel, and the output channel S2 is used to output the heat dissipation medium flowing through the heat dissipation channel.

[0052] In some embodiments, the bonding substrate 200 further includes: a first bump 214 and a second bump 224; the first bump 214 is located between the package substrate 300 and the first substrate 210, wherein the first bump 214 connects the package substrate 300 and the first substrate 210 respectively; the second bump 224 is located between the stacking structure 100 and the second substrate 220, wherein the second bump 224 connects the stacking structure 100 and the second substrate 220 respectively. Here, the first bump 214 and the second bump 224 are respectively located on opposite surfaces of the bonding substrate 200, and the first bump 214 and the second bump 224 can be respectively formed on opposite surfaces of the bonding substrate 200 by using micro-bump technology, and the materials of the first bump 214 and the second bump 224 include conductive materials, for example, at least one of copper, gold, silver, and platinum.

[0053] For example, refer to Figure 2 As shown, the first bump 214 is located on the second surface of the first dielectric layer 211, and the first bump 214 is respectively connected to the conductive line 213 and the circuit in the package substrate 300. The second bump 224 is located on the fourth surface of the second dielectric layer 221, and the second bump 224 is respectively connected to the connection structure 223 and the first chip 110. It can be understood that the first chip 110 can be connected to the circuit in the package substrate 300 through the second bump 224, the connection structure 223, the conductive line 213, and the first bump 214.

[0054] In the embodiment of the present disclosure, by respectively providing the first bump 214 and the second bump 224 on the opposite surfaces of the bonding substrate 200, the bonding substrate 200 can not only dissipate heat for the chip in the stacking structure 100, but also the chip in the stacking structure 100 can be connected to the packaging substrate 300 through the bumps, the connecting structure 223, the conductive wire 213, etc. in the bonding substrate 200, thereby realizing electrical connection between the chip in the stacking structure 100 and the packaging substrate 300. It should be noted that the bonding substrate 200 may also include Figure 2 Other metal wiring and / or metal interconnect layers, etc. not shown.

[0055] Based on the above packaging structure, an embodiment of the present disclosure provides a packaging method, which is used to form the packaging structure in any of the above embodiments.

[0056] Figure 3 is a flow chart of a packaging method provided by an embodiment of the present disclosure. It should be noted that: Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in order according to actual needs. Figure 3 As shown, the packaging method includes the following steps:

[0057] Step S410: forming a stacking structure, the stacking structure comprising a plurality of chips stacked in sequence;

[0058] Step S420: forming a first substrate and a second substrate, wherein at least one of the first substrate and the second substrate has a heat dissipation channel for the heat dissipation medium to flow through, and a surface of the heat dissipation channel contacting the heat dissipation medium has a hydrophobic portion;

[0059] Step S430: bonding the first substrate and the second substrate to form a bonding substrate, and packaging the bonding substrate and the stacking structure to one side of the packaging substrate, so that the bonding substrate is located between the packaging substrate and the stacking structure.

[0060] Figure 4 This is a schematic diagram of a stacking structure provided by an embodiment of the present disclosure. Figure 3 and Figure 4 The formation process of the stacking structure is exemplarily described.

[0061] Reference Figure 3 and Figure 4 As shown, the above step S410 includes: providing a substrate 101, and forming a plurality of third chips 130, a second chip 120 and a first chip 110 stacked in sequence on one side of the substrate 101. For the substrate 101, the first chip 110, the second chip 120 and the plurality of third chips 130, refer to Figure 2The relevant description will not be repeated here.

[0062] The substrate 101 and the third chip 130, the plurality of third chips 130, and the third chip 130 and the second chip 120 can be vertically connected to each other through advanced packaging technologies such as TSV, Micro bump, and stack bonding. For example, TSV technology can be used to form a through-silicon connection structure 140 in the chip, and Micro bump technology can be used to form a micro bump 150 on the surface of each chip, and then each chip is stacked and bonded in sequence.

[0063] It should be noted that the first chip 110 may include a first conductive layer 111 and a second conductive layer 112. The first conductive layer 111 is formed on the front side of the first chip 110, so the first conductive layer 111 is also called a top metal layer (Top Metal, TM); the second conductive layer 112 is formed on the back side of the first chip 110, so the second conductive layer 112 is also called a bottom metal layer. Here, after completing the front process of the first chip 110, a through-silicon connection structure extending through the first chip 110 can be formed from the back side of the first chip 110 using TSV technology, and then the second conductive layer 112 is formed. The second conductive layer 112 is connected to the micro-bumps 150 on the surface of the second chip 120, and the first conductive layer 111 and Figure 2 The second bump 224 in is connected.

[0064] Figures 5 to 14 This is a schematic diagram of a bonding substrate with a heat dissipation channel provided by an embodiment of the present disclosure. Figure 3 , Figures 5 to 14 The formation process of the bonding substrate with the heat dissipation channel is exemplarily described.

[0065] Reference Figure 3 , Figure 5 and Figure 6 As shown, forming the first substrate in the above step S420 includes: forming a first dielectric layer 211 and a conductive line 213 on one side of the first carrier 201, and the conductive line 213 is located in the first dielectric layer 211; etching the first dielectric layer 211 to form a plurality of first heat dissipation channels 212 extending into the first dielectric layer 211 and connected.

[0066] Reference Figure 5As shown, the formation process of the first dielectric layer 211 includes: depositing a first sub-dielectric layer 2111 on one side of the first carrier 201, and the conductive line 213 is located in the first sub-dielectric layer 2111; depositing a second sub-dielectric layer 2112 on a side of the first sub-dielectric layer 2111 relatively far away from the first sub-dielectric layer 2111. In this embodiment, the first sub-dielectric layer 2111 includes but is not limited to silicon oxide, and the second sub-dielectric layer 2112 includes but is not limited to silicon nitride, that is, the first dielectric layer 211 is a composite film layer composed of silicon oxide and silicon nitride. Of course, in other embodiments, the first dielectric layer 211 can be a single film layer of silicon oxide.

[0067] Reference Figure 6 As shown, the first dielectric layer 211 is etched from the surface of the first dielectric layer 211 to form a plurality of first heat dissipation channels 212, each of which extends into the first sub-dielectric layer 2111, that is, the height of the first heat dissipation channel 212 is less than the height of the first dielectric layer 211. Each first heat dissipation channel 212 and the conductive wire 213 can be spaced apart from each other by the first dielectric layer 211. The top view of the plurality of first heat dissipation channels 212 is shown in FIG. Figure 7 As shown, a plurality of first heat dissipation channels 212 are connected to each other. The etching includes at least one of dry etching and wet etching.

[0068] In some embodiments, reference Figure 8 As shown, forming the first substrate in the above step S420 further includes: performing hydrophobic treatment on the surface of the first heat dissipation channel 212 to form a hydrophobic portion 215 on the surface of the first heat dissipation channel 212. For example, a hydrophobic film layer may be formed on the surface of the first heat dissipation channel 212. For another example, at least one of surface treatment processes such as micro-nano structuring, chemical modification, self-assembly technology, and electrochemical deposition may be performed on the surface of the first heat dissipation channel 212 to form a hydrophobic group on the surface of the first heat dissipation channel 212.

[0069] In some embodiments, reference Fig. 9 As shown, forming the second substrate in the above step S420 includes: providing a second carrier 202; and forming a second dielectric layer 221 on one side of the second carrier 202. The second dielectric layer 221 includes silicon oxide or silicon nitride.

[0070] In some embodiments, reference Figure 3 , Figure 8 and Fig. 9 As shown, the bonding of the first substrate and the second substrate to form a bonded substrate in the above step S430 includes: bonding the first substrate with a plurality of first heat dissipation channels 212 formed thereon to the second substrate, wherein the heat dissipation channels include a plurality of first heat dissipation channels 212; removing the first carrier 201 to form a bonded substrate. Figure 8 The structure shown and Fig. 9 The structure shown in FIG. 1 is bonded face to face, so that the first dielectric layer 211 and the second dielectric layer 221 are located between the first carrier 201 and the second carrier 202. Then, the first carrier 201 is removed to obtain a bonded substrate. The retained first dielectric layer 211 and the conductive wire 213 form a substrate as shown in FIG. Figure 2 The first substrate shown has a heat dissipation channel. Of course, in order to reduce the overall height of the package structure, the second carrier 202 can also be removed, and the retained second dielectric layer 221 constitutes the second substrate. Here, the first substrate and the second substrate can be bonded to form a silicon nitride-silicon nitride bonding interface.

[0071] In some embodiments, reference Fig.10 As shown, forming the second substrate in the above step S420 further includes: etching the second dielectric layer 221 to form a plurality of second heat dissipation channels 222 extending into the second dielectric layer 221 and communicating with each other, each second heat dissipation channel 222 extending into the second dielectric layer 221, that is, the height of the second heat dissipation channel 222 is less than the height of the second dielectric layer 221. The top view of the plurality of second heat dissipation channels 222 is similar to Figure 7 , multiple second heat dissipation channels 222 are connected to each other.

[0072] In some embodiments, reference Fig.11 As shown, forming the second substrate in the above step S420 further includes: performing hydrophobic treatment on the surface of the second heat dissipation channel 222 to form a hydrophobic portion 225 on the surface of the second heat dissipation channel 222. The formation of the hydrophobic portion 225 on the surface of the second heat dissipation channel 222 can refer to the above embodiment, and for the sake of simplicity, it will not be repeated.

[0073] In other embodiments, referring to Figure 3 , Figure 8 and Fig.11 As shown, the bonding of the first substrate and the second substrate to form a bonded substrate in the above step S430 includes: bonding the first substrate having a plurality of first heat dissipation channels 212 and the second substrate having a plurality of second heat dissipation channels 222, wherein the heat dissipation channels include a plurality of first heat dissipation channels 212 and a plurality of second heat dissipation channels 222; removing the first carrier 201 and the second carrier 202 to form a bonded substrate. For example, Figure 8 The structure shown and Fig.11 The structure shown is bonded face to face, so that the first dielectric layer 211 and the second dielectric layer 221 are located between the first carrier 201 and the second carrier 202, as shown in FIG. Fig.12 As shown, the first carrier 201 and the second carrier 202 are then removed to obtain a bonding substrate, and the retained first dielectric layer 211 and the conductive wire 213 form a bonding substrate as shown in FIG. Figure 2 The first substrate 210 shown in FIG. 1 and the retained second dielectric layer 221 are formed as follows: Figure 2The second substrate 220 shown in FIG. 1 , the first substrate 210 and the second substrate 220 both have heat dissipation channels. Of course, in other embodiments, Figure 5 The structure shown and Fig.11 The structure shown is bonded face to face, and the first carrier 201 and the second carrier 202 are removed to obtain a bonded substrate, that is, the second substrate has a heat dissipation channel.

[0074] In some embodiments, reference Figure 12 to Figure 14 As shown, the bonding of the first substrate and the second substrate to form a bonded substrate in the above step S430 also includes: bonding the first substrate and the second substrate so that the plurality of first heat dissipation channels 212 and the plurality of second heat dissipation channels 222 correspond one to one, wherein the first heat dissipation channels 212 and the corresponding second heat dissipation channels 222 are bonded, and the first dielectric layer 211 and the second dielectric layer 221 are bonded; forming a connection structure 223 extending through the second dielectric layer 221 and a portion of the first dielectric layer 211, and the connection structure 223 connects the conductive wire 213.

[0075] Reference Fig.12 As shown, Figure 8 The structure shown and Fig.11 After the structure shown is bonded face to face, the second carrier 202 may be removed to expose the second dielectric layer 221, as shown in FIG. Fig.13 The second dielectric layer 221 is etched until the conductive line 213 is exposed, thereby forming a connection hole extending through the second dielectric layer 221 and a portion of the first dielectric layer 211, and a conductive material is filled into the connection hole to form a Fig.14 The connection structure 223 is shown. For ease of understanding, Fig.12 The hydrophobic portion is omitted.

[0076] Reference Fig.14 As shown, the micro bump technology can be used to form the second bump 224 on the connection structure 223. After the stacked structure is flipped on the bonding substrate, the first carrier 201 can be removed to expose the first dielectric layer 211, and the first bump 214 connected to the conductive line 213 is formed on the exposed first dielectric layer 211, thereby forming the first bump 214 and the second bump 224 on the opposite surfaces of the bonding substrate.

[0077] Fig.15 and Fig.16 This is a schematic diagram of packaging a stacked structure and a bonding substrate onto a packaging substrate provided by an embodiment of the present disclosure. Figure 3 , Fig.15 and Fig.16 The packaging process of the stacked structure and the bonded substrate is exemplarily described.

[0078] Can Figure 4The stacked structure 100 is shown flipped on Fig.14 In the structure shown in FIG. 1 , the stacked structure 100 and the bonding substrate are connected via the second bumps 224. Specifically, the second bumps 224 are respectively connected to the top metal layer of the first chip and the connection structure 223. Then, the first carrier 201 is removed to expose the first dielectric layer 211, thereby forming a structure as shown in FIG. Fig.15 The structure shown.

[0079] A first bump 214 connected to the conductive line 213 is formed on the exposed first dielectric layer 211, and the bonding substrate 200 formed with the first bump 214 is packaged on the packaging substrate 300, thereby forming a bonding substrate 200 as shown in FIG. Fig.16 In the structure shown, the bonding substrate 200 and the packaging substrate 300 are connected via the first bumps 214. Specifically, the first bumps 214 are connected to the conductive wires 213 and the circuits in the packaging substrate 300, respectively.

[0080] Here, after the bonding substrate 200 is packaged to the packaging substrate 300, holes may be punched at the exposed edge positions of the bonding substrate 200 on both sides of the stacking structure 100 to form a Figure 2 The input channel S1 and output channel S2 are shown, the input channel S1 can be connected to the infusion device, and the heat dissipation liquid provided by the infusion device can be transmitted to the heat dissipation channel via the input channel S1; the output channel S2 can be connected to the drainage device, and the heat dissipation liquid discharged from the heat dissipation channel can be transmitted to the drainage device via the output channel S2, thereby realizing the heat dissipation of the packaging structure.

[0081] In some embodiments, the packaging method further includes: forming a plastic packaging layer covering the stacking structure 100 and the bonding substrate 300 on one side of the packaging substrate 300 .

[0082] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0083] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0085] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0086] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: A stacking structure, the stacking structure comprising a plurality of chips stacked in sequence; A bonding substrate is located between the packaging substrate and the stacking structure and includes a first substrate and a second substrate that are bonded to each other, wherein at least one of the first substrate and the second substrate has a heat dissipation channel for a heat dissipation medium to flow through, and a surface of the heat dissipation channel in contact with the heat dissipation medium has a hydrophobic portion.

2. The packaging structure according to claim 1, characterized in that: The heat dissipation channel includes a plurality of first heat dissipation channels that are connected; and the first substrate includes: A first dielectric layer, the first dielectric layer is located between the packaging substrate and the second substrate, wherein the first heat dissipation channel extends along a surface of the first dielectric layer relatively away from the packaging substrate into the first dielectric layer, and a height of the first heat dissipation channel is less than a height of the first dielectric layer; A conductive line is located in the first dielectric layer, wherein the conductive line and the first heat dissipation channel are spaced apart from each other.

3. The packaging structure according to claim 2, characterized in that: The heat dissipation channel also includes a plurality of second heat dissipation channels connected to each other; the second substrate includes: a second dielectric layer, the second dielectric layer being located between the first substrate and the stacked structure, wherein the second heat dissipation channel extends along a surface of the second dielectric layer relatively close to the first substrate into the second dielectric layer, and a height of the second heat dissipation channel is less than a height of the second dielectric layer; The bonding substrate further includes a connection structure extending through the second dielectric layer and a portion of the first dielectric layer and connected to the conductive line.

4. The packaging structure according to claim 3, characterized in that: The plurality of first heat dissipation channels and the plurality of second heat dissipation channels correspond one to one, wherein the first heat dissipation channels are bonded to the corresponding second heat dissipation channels, and the first dielectric layer is bonded to the second dielectric layer.

5. The packaging structure according to claim 1, characterized in that: The bonding substrate further comprises: A first bump, wherein the first bump is located between the packaging substrate and the first substrate, wherein the first bump is respectively connected to the packaging substrate and the first substrate; A second bump is located between the stacking structure and the second substrate, wherein the second bump is respectively connected to the stacking structure and the second substrate.

6. The packaging structure according to claim 1, characterized in that: The hydrophobic portion includes at least one of a hydrophobic group, a carbon nanotube-based coating, a silicon dioxide-based coating, and a metal oxide-based coating.

7. A packaging method, characterized in that: include: forming a stacking structure, the stacking structure comprising a plurality of chips stacked in sequence; forming a first substrate and a second substrate, wherein at least one of the first substrate and the second substrate has a heat dissipation channel for a heat dissipation medium to flow through, and a surface of the heat dissipation channel contacting the heat dissipation medium has a hydrophobic portion; The first substrate and the second substrate are bonded to form a bonding substrate, and the bonding substrate and the stacking structure are packaged to one side of a packaging substrate, so that the bonding substrate is located between the packaging substrate and the stacking structure.

8. The packaging method according to claim 7, characterized in that: The forming of the first substrate comprises: forming a first dielectric layer and a conductive line on one side of the first carrier, wherein the conductive line is located in the first dielectric layer; Etching the first dielectric layer to form a plurality of first heat dissipation channels extending into and connected to the first dielectric layer, wherein the height of the first heat dissipation channels is less than the height of the first dielectric layer; The step of bonding the first substrate and the second substrate to form a bonded substrate comprises: bonding the first substrate and the second substrate on which the plurality of first heat dissipation channels are formed, wherein the heat dissipation channels include the plurality of first heat dissipation channels; The first carrier is removed to form the bonding substrate.

9. The packaging method according to claim 8, characterized in that: The forming of the second substrate comprises: forming a second dielectric layer on one side of the second carrier; Etching the second dielectric layer to form a plurality of second heat dissipation channels extending into and connected to the second dielectric layer, wherein the height of the second heat dissipation channels is less than the height of the second dielectric layer; The step of bonding the first substrate and the second substrate to form a bonded substrate comprises: Bonding the first substrate formed with the plurality of first heat dissipation channels and the second substrate formed with the plurality of second heat dissipation channels, wherein the heat dissipation channels include the plurality of first heat dissipation channels and the plurality of second heat dissipation channels; The first carrier plate and the second carrier plate are removed to form the bonding substrate.

10. The packaging method according to claim 9, characterized in that: The bonding of the first substrate and the second substrate to form a bonded substrate further includes: Bonding the first substrate and the second substrate so that the plurality of the first heat dissipation channels correspond to the plurality of the second heat dissipation channels one by one, wherein the first heat dissipation channels are bonded to the corresponding second heat dissipation channels, and the first dielectric layer is bonded to the second dielectric layer; A connection structure is formed extending through the second dielectric layer and a portion of the first dielectric layer, the connection structure connecting the conductive lines.

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