Method for manufacturing electronic device having through-hole substrate and electronic device

Abstract

The invention provides a manufacturing method of an electronic device with a through hole substrate and the electronic device. The manufacturing method of the electronic device with the through hole substrate comprises the following steps: irradiating local areas of two opposite surfaces of the substrate with laser light; and executing the step of forming the through hole in the local area of the substrate. The step of forming the through hole comprises the following steps of: executing an etching step so as to respectively form opposite etching contours in local areas of two opposite surfaces of the substrate; executing a buffer layer coating step so as to form buffer layers on the two opposite surfaces of the substrate and the opposite etching contours; and repeating the etching step and the buffer layer coating step until the through holes are formed in the opposite etching contours.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a manufacturing method thereof, and more particularly to an electronic device with a through-hole substrate and a manufacturing method thereof. Background Art

[0002] The manufacturing process of electronic devices is often accompanied by thermal processes. When electronic components are bonded to substrates, mismatched thermal expansion coefficients can easily lead to warping risks. Therefore, how to improve the structural strength of the substrate is a very important issue. Summary of the invention

[0003] The present disclosure provides an electronic device and a manufacturing method thereof, which are helpful to improve the structural strength of a substrate.

[0004] According to an embodiment of the present disclosure, a method for manufacturing an electronic device having a through-hole substrate includes: irradiating local areas of two opposite sides of a substrate with a laser; and performing a through-hole forming step in the local area of ​​the substrate. The through-hole forming step includes: performing an etching step to form relative etching profiles in the local areas of the two opposite sides of the substrate respectively; performing a buffer layer coating step to form a buffer layer on the two opposite sides of the substrate and the relative etching profiles; repeatedly performing the etching step and the buffer layer coating step until the relative etching profiles form a through-hole; and confirming whether the angle of the through-hole is less than or equal to 20 degrees.

[0005] According to an embodiment of the present disclosure, an electronic device includes a through-hole substrate, a conductive member, an electronic component, and a circuit board. The through-hole substrate has a first surface, a second surface opposite to the first surface, and a through hole, wherein the inner wall of the through hole is connected to the first surface and the second surface. The conductive member is disposed in the through hole. The electronic component is disposed on the first surface and is electrically connected to the circuit board through the conductive member. The surface roughness of the first surface is greater than the surface roughness of the inner wall of the through hole.

[0006] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view showing local areas of two opposite sides of a substrate irradiated with laser light;

[0008] Figure 2 is a cross-sectional schematic diagram showing the execution of an etching step;

[0009] Figure 3 is a cross-sectional schematic diagram showing a buffer layer coating step;

[0010] Figure 4 yes Figure 3 An enlarged schematic diagram of region R1;

[0011] Figure 5 is a cross-sectional schematic diagram showing relative etching profiles forming a through hole and the angle of the through hole is less than or equal to 20 degrees;

[0012] Figure 6 as well as Figure 7 They are Figure 5 An enlarged schematic diagram of region R2 and region R3;

[0013] Figure 8 is a schematic diagram showing immersing a laser-irradiated substrate in a mixed solution including an inhibitor and an etchant;

[0014] Fig. 9 is a schematic diagram showing that a substrate having oppositely-opposed conical holes is immersed in a mixed solution including an inhibitor and an etchant;

[0015] Figures 10 to 14 They are cross-sectional schematic diagrams of five electronic devices according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

[0018] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0019] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in various embodiments to describe the relative relationship of one component of the drawings to another component. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present disclosure are also considered as part of the disclosure.

[0020] A structure (or layer, component, substrate) described in the present disclosure is located on / above another structure (or layer, component, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" other structures, it may refer to that a certain structure is "directly" on other structures, or that a certain structure is "indirectly" on other structures, that is, at least one structure is sandwiched between a certain structure and other structures. In addition, a certain structure is disposed on other structures only for the convenience of description, and does not limit the process steps or sequence.

[0021] The terms "approximately", "substantially" or "substantially" are generally interpreted as within 10% of a given value or range, or as within 5%, 3%, 2%, 1% or 0.5% of a given value or range. In addition, the phrases "a range is from a first value to a second value", "a range is between a first value and a second value" indicate that the range includes the first value, the second value and other values ​​therebetween.

[0022] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claim.

[0023] The connection described in the present disclosure may include physical connection or electrical connection. Both physical connection and electrical connection may include direct contact or indirect contact. In the case of direct contact or direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect contact or indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited thereto.

[0024] In the present disclosure, the thickness, length and width can be measured by an optical microscope (OM), and the thickness or width can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. The surface roughness can be observed by a scanning electron microscope (SEM), a transmission electron microscope (TEM), etc. at the same appropriate magnification to observe the surface undulations, and the undulations can be compared by taking a unit length (e.g., 10 μm). An appropriate magnification means that at least one surface can see at least 10 undulating peaks or an average roughness under the field of view of this magnification.

[0025] In addition, any two values ​​or directions used for comparison may have a certain error. In addition, the phrases "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value", or "a given range is between a first value and a second value" indicate that the given range includes the first value, the second value, and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0027] In the present disclosure, the electronic device may include a power device, a semiconductor packaging device, a display device, a backlight device, an antenna device, a packaging device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may, for example, include liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (quantum dot, QD), other suitable display media or a combination of the foregoing. The antenna device may, for example, include a reconfigurable surface (Reconfigurable Intelligent Surface, RIS), a frequency selective surface (Frequency Selective Surface, FSS), a radio frequency filter (RF-Filter), a polarizer (Polarizer), a resonator (Resonator) or an antenna (Antenna), etc. The antenna may be a liquid crystal type antenna or a varactor diode (Varactor Diodes) antenna. The sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasound, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as known good die (KGD), capacitors, resistors, inductors, diodes, transistors, varactors, variable capacitors, filters, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, semiconductor-related process structures, or semiconductor-related process structures disposed on a substrate (such as polyimide, glass, silicon substrate or other suitable substrate materials), but not limited thereto. The diode may include a light-emitting diode, a varactor diode or a photodiode. The light-emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (quantum dot LED), but not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but not limited thereto. The packaged device may be a packaged device applicable to wafer-level package (WLP) technology or panel-level package (PLP) technology, such as a chip first process or a chip last load (RDLfirst) process.In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (for example, including augmented reality or virtual reality), a vehicle-mounted device (for example, including a car windshield) or a splicing device. The following embodiments illustrate some implementation forms of electronic devices with packaging devices, but are not limited to this. According to the embodiments of the present disclosure, the manufacturing method of the electronic device with a through-hole substrate provided can be applied to a wafer-level packaging process (wafer-level package, WLP) or a panel-level packaging (panel-level package, PLP) process, and a chip first process or a chip last / RDL first process can be adopted, which will be further described in detail below. According to the embodiments of the present disclosure, the packaging structure of the electronic device may include a system on chip (SoC), a system in package (SiP), an antenna package (AiP) or a combination thereof, but is not limited to this.

[0028] Figure 1 It is a schematic cross-sectional view showing partial regions of two opposing surfaces of a substrate irradiated with laser light. Figure 2 is a schematic cross-sectional view showing the etching step performed. Figure 3 2 is a schematic cross-sectional view showing the step of performing a buffer layer coating step. Figure 4 yes Figure 3 An enlarged schematic diagram of region R1. Figure 5 is a schematic cross-sectional view showing relative etching profiles forming a through hole with an angle of less than or equal to 20 degrees. Figure 6 as well as Figure 7 They are Figure 5 An enlarged schematic diagram of region R2 and region R3. Figure 8 is a schematic diagram showing that a laser-irradiated substrate is immersed in a mixed solution including an inhibitor and an etchant. Fig. 9 1 is a schematic diagram showing that a substrate having opposing tapered holes is immersed in a mixed solution including an inhibitor and an etchant. Figures 10 to 14 The following are cross-sectional schematic diagrams of five electronic devices according to some embodiments of the present disclosure. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0029] According to some embodiments of the present disclosure, a method for manufacturing an electronic device having a through-hole substrate may include: irradiating local areas (e.g., area PR) of two opposite surfaces (e.g., the first surface S1 and the second surface S2) of the substrate 10 with a laser LS, such as Figure 1 and performing a through-hole forming step in a local area (eg, area PR) of the substrate 10, such as Figures 2 to 7 The step of forming the through hole may include: performing an etching step to form a relative etching profile EP in local areas (eg, area PR) of two opposite sides (eg, the first side S1 and the second side S2) of the substrate 10, such as Figure 2 Execute a buffer layer coating step to form a buffer layer BL on two opposite sides of the substrate 10 (eg, the first side S1 and the second side S2) and on the opposite etching profile EP, such as Figure 3 as well as Figure 4 Repeat the etching step (refer to Figure 2 ) and buffer layer coating step (refer to Figure 3 as well as Figure 4 ) until the relative etching profile EP forms a through hole TH, such as Figure 5 As shown; and confirm whether the angle θ of the through hole TH meets the specification. According to some embodiments, the angle θ of the through hole TH is less than or equal to 30 degrees, or less than or equal to 20 degrees, such as Figure 5 shown.

[0030] In detail, Figure 1 1 shows the steps of laser modification. Laser LS can be used to irradiate the area of ​​the substrate 10 to be modified or the area to form a through hole (for example, area PR) from the first surface S1 or the second surface S2 of the substrate 10 to modify the area PR. The "modification" referred to in the present disclosure is to destroy the bonds in a local area of ​​the substrate 10 by laser or other suitable process methods to weaken the structural strength of the local area. In some embodiments, the laser LS can penetrate the substrate 10. The material of the substrate 10 includes, for example, glass, ceramics, wafers, semiconductor materials or other inorganic materials.

[0031] Figure 2The etching step is shown. Since laser modification can improve the etching efficiency, after the laser-modified substrate 10 is immersed in the etchant, the etching rate of the laser-modified region PR of the substrate 10 is greater than the etching rate of the region of the substrate 10 that has not been laser-modified (for example, the region other than the region PR), so that a relative etching profile EP (for example, a cone hole, but not limited to this) can be formed on the local area (for example, the region PR) of the two opposite sides (for example, the first side S1 and the second side S2) of the substrate 10 respectively until the relative etching profiles are connected to form a through hole, but not limited to this. According to some embodiments, the etchant can be provided from the first side S1 or the second side S2 until the through hole is formed. According to some embodiments, the etchant may include an acidic or alkaline etchant, wherein the acidic etchant includes hydrofluoric acid and the alkaline etchant includes sodium hydroxide, but not limited to this. The use of through-hole substrates in electronic devices can reduce raw material and production costs or improve yields. In addition, the through-hole substrate can have better electrical insulation capability, thereby reducing energy loss caused by leakage current or improving heating problems caused by leakage current under high-speed computing, thereby making the manufactured electronic devices more compliant with energy-saving and carbon-reduction regulations.

[0032] Figure 3 as well as Figure 4 It is shown that the buffer layer coating steps are repeated until a through-hole substrate is formed. The buffer layer BL can reduce the etching rate by reducing the contact between the substrate 10 and the etchant. In some embodiments, the buffer layer BL can be formed on the opposite sides (e.g., the first side S1 and the second side S2) of the substrate 10 and the opposite etching profile EP by immersing the substrate 10 formed with the etching profile EP in an inhibitor or by chemical vapor deposition (CVD). The inhibitor may include an organic material or an inorganic material, such as silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), hafnium dioxide (HfO2), indium tin oxide (ITO), indium zinc oxide (IZO), sodium phosphate (Na3PO4), sodium fluoride (NaF), potassium phosphate (K3PO4), potassium fluoride (KF), ammonium fluoride (NH4F), ammonium phosphate ((NH4)3PO4), organosilane compounds (organosilane) or a combination thereof, but is not limited thereto.

[0033] By using the concentration gradient characteristic of the inhibitor (the concentration of the inhibitor decreases from high to low from the opening of the etching profile EP to the bottom of the etching profile EP) or the generation characteristic of chemical vapor deposition, the thickness TBL of the buffer layer BL formed on the etching profile EP decreases from thick to thin from the opening of the etching profile EP to the bottom of the etching profile EP. The thickness TBL of the buffer layer BL is calculated from the direction perpendicular to the substrate surface (for example, the first surface S1, the second surface or the inner wall S3 of the etching profile EP), as shown in FIG. Figure 4 In some embodiments, the buffer layer BL does not cover the bottom of the etching profile EP, but is not limited thereto.

[0034] After the buffer layer coating step, an etching step may be performed again (see Figure 2 ). Since the thickness TBL of the buffer layer BL formed on the etching profile EP is gradually reduced from the opening of the etching profile EP to the bottom of the etching profile EP, as shown in FIG. Figure 4 As shown, the etching step (refer to Figure 2 ) has a higher etching rate at the bottom of the etching profile EP than at the opening of the etching profile EP. In other words, the buffer layer coating step can achieve regional etching rate modulation, for example, the rate at which the modified region PR of the substrate 10 is removed by the etchant in the longitudinal direction (for example, direction D3 or its opposite direction) is higher than the rate at which the etchant is removed in the lateral direction (for example, direction D1 or its opposite direction, direction D2 or its opposite direction).

[0035] In some embodiments, the etchant in the etching step may also remove at least a portion of the buffer layer BL, so the buffer layer coating step may be performed after the etching step to achieve regional etching rate modulation. In some embodiments, after performing repeated buffer layer coating steps or repeated etching steps, the concentration change of the inhibitor is monitored and feedback is given. For example, it can be monitored by a real-time concentration monitoring system. When the inhibitor concentration is lower than the set value, an alarm coupled to the concentration monitoring system will be activated, but it is not limited to this.

[0036] By repeatedly performing the etching step (refer to Figure 2 ) and buffer layer coating step (refer to Figure 3 as well as Figure 4 ) until the relative etching profile EP forms a through hole TH, such as Figure 5 As shown. The through hole TH is an opening penetrating the substrate 10, and the inner wall S3 of the through hole TH is connected to the first surface S1 and the second surface S2 of the substrate 10. In other words, the depth D of the through hole TH is equal to the thickness T10 of the substrate 10, wherein the thickness T10 of the substrate 10 is the maximum distance between the first surface S1 of the substrate 10 and the second surface S2 of the substrate 10 in the direction D3. According to some embodiments, the depth of the through hole TH is greater than or equal to 0.04 millimeters (mm) and less than or equal to 0.9 mm.

[0037] After forming the through hole TH penetrating the substrate 10, it can be confirmed whether the angle θ of the through hole TH meets the specifications, for example, whether the angle θ of the through hole TH is less than or equal to 20 degrees. The angle θ of the through hole TH refers to the angle between the extension line EL of the inner wall S3 of the through hole TH and the normal N of the first surface S1 (or the second surface S2). In some embodiments, if it is confirmed that the angle θ of the through hole TH is less than or equal to 20 degrees, the through hole forming step is terminated, and if it is confirmed that the angle θ of the through hole TH is greater than 20 degrees, the buffer layer coating step and the etching step are repeated until the angle θ of the through hole TH is less than or equal to 20 degrees. Specifically, after etching through the substrate 10, if it is confirmed that the angle θ of the through hole TH meets the specifications, it means that the production of the through hole substrate 10H has been completed, so there is no need to perform the buffer layer coating step and the etching step again. On the other hand, if it is confirmed that the angle θ of the through hole TH does not meet the specification, the buffer layer coating step and the etching step can be performed again, and the regional etching rate can be adjusted by controlling the design parameters of the buffer layer BL (such as the regional thickness and coverage of the buffer layer BL), thereby forming a through hole TH that meets the angle specification. In some embodiments, Figure 2 as well as Figure 3 As shown, the etching step and the buffer layer coating step can be performed separately. In addition, each etching step after etching through the substrate 10 can be followed by a step of confirming the angle of the through hole. If it is confirmed that the angle θ of the through hole TH meets the specification, it is not necessary to form the buffer layer BL. Therefore, the number of etching steps can be greater than the number of buffer layer coating steps. For example, if the number of buffer layer coating steps is X, the number of etching steps can be X+1, but is not limited thereto. According to some embodiments, the angle θ of the through hole TH can be checked through an optical inspection system (OM), but is not limited thereto.

[0038] Please refer to Figures 5 to 7 , after confirming that the angle θ of the through hole TH is less than or equal to 20 degrees, the production of the through hole substrate 10H is completed. In some embodiments, the ratio of the width W of the through hole TH to the depth D of the through hole TH may be 0.01 to 0.5, that is, 0.01≤W / D≤0.5, but not limited thereto. The width W of the through hole TH is the minimum distance in the lateral direction (such as direction D1 or direction D2) between the inner wall S3 of the through hole TH in the cross-sectional view. According to some embodiments, the ratio of the maximum distance to the minimum distance may be between 1.1 and 1.5. Through the above design, the electronic device may have better electrical characteristics, but not limited thereto.

[0039] The through-hole substrate 10H has a first surface S1, a second surface S2 opposite to the first surface S1, and a through hole TH, wherein an inner wall S3 of the through hole TH is connected to the first surface S1 and the second surface S2. The first surface S1 and the second surface S2 of the through-hole substrate 10H are the first surface S1 and the second surface S2 of the substrate 10 described above. Figure 2In the etching step shown, the first surface S1 and the second surface S2 are etched without being covered by the photoresist and / or the buffer layer BL, that is, the first surface S1 and the second surface S2 are in direct contact with the etchant. In addition, even if the etching is performed after the buffer layer coating step, the time, area and / or probability of the first surface S1 and the second surface S2 contacting the etchant are longer or greater than the time, area and / or probability of the inner wall S3 of the through hole TH contacting the etchant. Therefore, the surface roughness of the first surface S1 is, for example, greater than the surface roughness of the inner wall S3 of the through hole TH, and similarly, the surface roughness of the second surface S2 is, for example, greater than the surface roughness of the inner wall S3 of the through hole TH. In some embodiments, the ratio of the surface roughness of the inner wall S3 of the through hole TH to the surface roughness of the first surface S1 may be greater than or equal to 0.01 and less than 1. Similarly, the ratio of the surface roughness of the inner wall S3 of the through hole TH to the surface roughness of the second surface S2 may be greater than or equal to 0.01 and less than 1. According to some embodiments, the average surface roughness of the inner wall S3 of the through hole TH may be between 0.01 μm and 1.2 μm. Through the above design, the bonding force between the subsequent film layer and the inner wall S3 may be improved.

[0040] In some embodiments, Figure 6 As shown, the inner wall S3 of the through hole TH may have a plurality of protrusion structures P3, and the ratio of the maximum thickness TP3 of the plurality of protrusion structures P3 to the width W of the through hole TH may be 0.001 to 0.1, that is, 0.001≤TP3 / W≤0.1. For example, when the width W of the through hole TH is 200 μm, the maximum thickness TP3 of the protrusion structure P3 may be 0.05 μm to 10 μm. When the width W of the through hole TH is 100 μm, the maximum thickness TP3 of the protrusion structure P3 may be 0.1 μm to 10 μm. When the width W of the through hole TH is 50 μm, the maximum thickness TP3 of the protrusion structure P3 may be 0.1 μm to 5 μm. When the width W of the through hole TH is 5 μm, the maximum thickness TP3 of the protrusion structure P3 may be 0.01 μm to 1 μm.

[0041] In some embodiments, Figure 6 as well as Figure 7 As shown, the first surface S1 and the second surface S2 may have a plurality of protrusion structures (such as protrusion structure P1 and protrusion structure P2), and the thickness of the plurality of protrusion structures (such as thickness TP1 and thickness TP2) may be 0.2 μm to 10 μm. In some embodiments, Figure 7 As shown, in the cross-sectional view, at least one of the plurality of protruding structures may be in the shape of a triangle, and the vertex angle α of the triangle is, for example, between 60 degrees and 175 degrees, that is, 60 degrees<α<175 degrees.

[0042] Although the above embodiment is based on the example of performing the etching step and the buffer layer coating step separately, in other embodiments, such as Figure 8 and / or Fig. 9 As shown, the etching step and the buffer layer coating step can be performed simultaneously. Figure 8 For example, performing the etching step and the buffer layer coating step simultaneously may include: Figure 1 ) is immersed in a mixed solution MS including an inhibitor and an etchant. Under this structure, the etchant in the mixed solution MS will continuously etch the substrate 10, wherein the etching rate of the etchant on the laser-modified area PR is higher than the etching rate on the area not modified by the laser (such as the area outside the area PR). At the same time, the inhibitor in the mixed solution MS will deposit a buffer layer BL on the first surface S1, the second surface S2 and the inner wall S3 due to chemical action (refer to Figure 3 as well as Figure 4 ). The thickness TBL of the buffer layer BL and the modulation of the regional etching rate achieved can be referred to above and will not be repeated here. The buffer layer BL is partially removed by the etchant while being deposited to achieve a dynamic balance. The etching step and the buffer layer coating step are repeated until the through hole TH is formed in the corresponding etching profile EP, such as Figure 5 According to some embodiments, the inhibitor and the etching solution can be mixed in a proportion to form a mixed solution MS, and the modified substrate 10 can be immersed in the mixed solution MS, wherein the volume ratio of the inhibitor to the etching solution can be greater than or equal to 0.001 and less than or equal to 0.5. For example, 1 ml of the inhibitor can be added to 1 liter of the etching solution.

[0043] As another option, Fig. 9 As shown, after the laser LS (refer to Figure 1 ) before immersing the irradiated substrate 10 in the mixed solution MS, relative conical holes (such as etching profiles EP) can be formed in local areas PR on two opposite surfaces (for example, the first surface S1 and the second surface S2) of the substrate 10 to facilitate the formation of the through hole TH and / or utilize the concentration gradient characteristics of the inhibitor (the concentration of the inhibitor decreases from high to low from the opening of the etching profile EP to the bottom of the etching profile EP) to make the thickness TBL of the formed buffer layer BL decrease from thick to thin from the opening of the etching profile EP to the bottom of the etching profile EP.

[0044] In some embodiments, Fig.10 As shown, after completing the production of the through-hole substrate 10H, the manufacturing method of the electronic device having the through-hole substrate may also include: forming a conductive member 11 in the through-hole substrate 10H; and forming a first circuit structure 12 and a second circuit structure 13 on the first surface S1 and the second surface S2 of the through-hole substrate 10H, respectively, wherein the first circuit structure 12 is electrically connected to the second circuit structure 13 through the conductive member 11.

[0045] The conductive member 11 can be used to electrically connect a plurality of conductive structures respectively located on the first surface S1 and the second surface S2 of the through-hole substrate 10H. For example, the material of the conductive member 11 may include metal, alloy, or a combination thereof, and the method of forming the conductive member 11 may include chemical plating, electroplating, atomic deposition, vapor deposition, or a combination thereof, but is not limited thereto. In some embodiments, as Fig.10 As shown, the number of the conductive members 11 can be multiple, and the multiple conductive members 1 are respectively formed in the multiple through holes TH. For example, each through hole TH can be provided with a corresponding conductive member 11 and the conductive member 11 can fill the through hole 100, but it is not limited thereto. Fig.10 For example, the conductive element 11 may include a conductive column. According to some embodiments, the conductive element 11 may include a single layer or a multi-layer stack. For example, when the conductive element 11 includes a multi-layer stack, the conductive element 11 may include a plurality of sub-layers, one of which may be a seed layer, and the seed layer may be disposed on the first surface S1, the second surface S2 and the sidewall of the through hole TH of the through-hole substrate 10H. After the seed layer is formed, a conductive layer may be formed on the seed layer, and the thickness of the conductive layer is thicker than the seed layer. By providing the seed layer, the bonding force between the through-hole substrate 10H and the conductive layer or the electrical characteristics of the electronic device may be improved, but the present invention is not limited thereto. The materials of the seed layer and the conductive layer may include copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), nitride, carbide or other conductive materials or any combination thereof, but the present invention is not limited thereto.

[0046] The first circuit structure 12 and the second circuit structure 13 may also be referred to as a rewiring structure. The rewiring structure may be electrically connected to a chip or other electronic component through solder balls or other bonding components. The rewiring structure may include at least one dielectric layer and at least one conductive layer alternately stacked along direction D3. Through at least one dielectric layer and at least one conductive layer, the circuit may be rerouted and / or the circuit fan-out or fan-in area may be increased, or different electronic components may be electrically connected to each other through the rewiring structure. For example, the pitch of two adjacent contact pads at one end of the rewiring structure contacting the electronic component may be less than or equal to the pitch of two adjacent contact pads at one end of the rewiring structure away from the electronic component, so that the rewiring structure may adjust the circuit fan-out condition or electrically connect a circuit structure / electronic component having a first pitch to a circuit structure / electronic component having a second pitch, but is not limited thereto. The method of forming the rewiring structure may include using a lithography process, a surface treatment process, a laser process, an electroplating process, a deposition process or other processes to form at least one dielectric layer and at least one conductive layer. The surface treatment process includes roughening or activating the surface of the dielectric layer or the conductive layer to improve its bonding ability. For example, the bonding force between the subsequent film layer and the surface is improved by increasing the surface roughness.

[0047] by Fig.10 For example, the first circuit structure 12 may include a conductive layer C1, a dielectric layer IN1, an adjustment layer AL, a conductive layer C2, a dielectric layer IN2, and a conductive layer C3 sequentially disposed on the first surface S1 of the through-hole substrate 10H, but the present invention is not limited thereto. The materials of the dielectric layer IN1 and the dielectric layer IN2 may include polyimide (PI), photosensitive polyimide (PSPI), lead monoxide (PBO), epoxy resin, polymer, Ajinomoto Build-up Film (ABF), silicon oxide, silicon nitride, or a combination thereof, but the present invention is not limited thereto. Each of the conductive layer C1, the conductive layer C2, and the conductive layer C3 may be a single conductive layer or a conductive stack. When the conductive layer C1, the conductive layer C2, and the conductive layer C3 are multiple layers or conductive stacks, they may be similar to the combination of the conductive element 11, and will not be described in detail. In addition, the materials of the conductive layer C1, the conductive layer C2, and the conductive layer C3 may include metals, alloys, or a combination thereof, or may have the same material as the conductive element 11.

[0048] The conductive layer C1 may be a patterned conductive layer and may include a plurality of circuits CK1. The dielectric layer IN1 is disposed on the conductive layer C1. The conductive layer C2 is disposed on the dielectric layer IN1. The conductive layer C2 may be a patterned conductive layer and may include a plurality of circuits CK2. At least one circuit CK2 may penetrate the dielectric layer IN1 and be electrically connected to a corresponding circuit CK1. The dielectric layer IN2 is disposed on the dielectric layer IN1 and the conductive layer C2. The conductive layer C3 is disposed on the dielectric layer IN2. The conductive layer C3 may be a patterned conductive layer and may include a plurality of contact pads CK3. At least one contact pad CK3 may penetrate the dielectric layer IN2 and be electrically connected to a corresponding circuit CK2.

[0049] The second circuit structure 13 may include a conductive layer C4, a dielectric layer IN4, a conductive layer C5, a dielectric layer IN5, and a conductive layer C6 sequentially disposed on the second surface S2 of the through-hole substrate 10H, but is not limited thereto. The materials of the dielectric layer IN4 and the dielectric layer IN5 may refer to the materials of the dielectric layer IN1 and the dielectric layer IN2, and will not be repeated here. Each of the conductive layer C4, the conductive layer C4, and the conductive layer C6 may be a single conductive layer or a conductive stack. In addition, the materials of the conductive layer C4, the conductive layer C4, and the conductive layer C6 may refer to the materials of the conductive layer C1, the conductive layer C2, and the conductive layer C3, and will not be repeated here.

[0050] The conductive layer C4 may be a patterned conductive layer and may include a plurality of circuits CK4. At least one circuit CK4 may be electrically connected to a corresponding conductive member 11. The dielectric layer IN4 is disposed on the conductive layer C4. The conductive layer C5 is disposed on the dielectric layer IN4. The conductive layer C5 may be a patterned conductive layer and may include a plurality of circuits CK5. At least one circuit CK5 may penetrate the dielectric layer IN4 and be electrically connected to a corresponding circuit CK4. The dielectric layer IN5 is disposed on the dielectric layer IN4 and the conductive layer C5. The conductive layer C6 is disposed on the dielectric layer IN5. The conductive layer C6 may be a patterned conductive layer and may include a plurality of contact pads CK6. At least one contact pad CK6 may penetrate the dielectric layer IN5 and be electrically connected to a corresponding circuit CK5.

[0051] In some embodiments, Fig.10 As shown, an adjustment layer AL may be disposed between the dielectric layer and the conductive layer. The coefficient of thermal expansion (CTE) of the adjustment layer AL may be less than or equal to the coefficient of thermal expansion of the dielectric layer. According to some embodiments, the thermal expansion trend of the adjustment layer AL is opposite to the thermal expansion trend of the dielectric layer. For example, when the temperature changes, both sides of the dielectric layer warp upward along the direction D3 and both sides of the adjustment layer AL warp downward along the opposite direction of the direction D3. Therefore, the arrangement of the adjustment layer AL may improve the warping of the electronic device. The material of the adjustment layer AL may include an organic material or an inorganic material.

[0052] In some embodiments, Fig.10 As shown, the manufacturing method of an electronic device with a through-hole substrate may also selectively include: forming a component integration layer 14 on the first surface S1 of the through-hole substrate 10H; bonding the electronic component 15 to the first circuit structure 12 via a connector 16; forming a bottom filler 17 between the electronic component 15 and the first circuit structure 12; forming a packaging layer 18 on the first circuit structure 12, the bottom filler 17 and the electronic component 15; and bonding the second circuit structure 13 to the circuit board 19 via a connector 20.

[0053] In some embodiments, the component integration layer 14 may be disposed between the through-hole substrate 10H and the first circuit structure 12 and may include a dielectric layer IN3, an electronic component 140 disposed in the dielectric layer IN3, and a plurality of circuits CK. The electronic component 140 may be electrically connected to the first circuit structure 12, and the electronic component 15 may be electrically connected to the electronic component 140 through the connector 16 and the first circuit structure 12. According to different requirements, the electronic component 140 may include an active component, a passive component, or a combination thereof. For example, the electronic component 140 may include a transistor or an integrated passive device (IPD), but is not limited thereto. The dielectric layer IN3 may be a single layer or a composite layer, and the material of the dielectric layer IN3 may refer to the description of the aforementioned dielectric layer IN1, which will not be repeated here. At least one circuit CK may be electrically connected to a corresponding conductive member 11. Although not shown, at least one circuit CK can be electrically connected to a corresponding circuit CK1, and the electronic component 140 can be electrically connected to the circuit board 19 through the connector 16, the first circuit structure 12, the component integration layer 14, the conductive member 11, the second circuit structure 13 and the connector 20.

[0054] The electronic component 15 may be a digital chip, an analog chip, a mixed signal chip, a logic chip, a sensor chip, a semiconductor-related process structure, a resistor, a capacitor, an inductor, or a semiconductor-related process structure disposed on a substrate (for example, polyimide, glass, silicon substrate or other suitable substrate material) or other types of integrated circuit chips or a combination thereof. In some embodiments, the electronic component 15 may include multiple chips stacked on each other. In some embodiments, the electronic component 15 can be transferred to the first circuit structure 12 by a pick and place (PnP) process, and multiple pads 150 of the electronic component 15 can be joined to multiple connectors 16. The surface on which the multiple pads 150 of the electronic component 15 are located is the active surface, and the surface opposite to the active surface is the back side of the electronic component 15. In other embodiments, although not shown in Fig.10 , multiple electronic components can be transferred to the first circuit structure 12 and bonded to the first circuit structure 12. The multiple electronic components may include multiple electronic components with different design parameters such as purpose, size, type, shape, number of pads and / or pad pitch, but are not limited thereto. The connector 16 may be a solder ball, a micro bump or other conductive bonding member.

[0055] The bottom filler 17 surrounds the plurality of connectors 16 to protect the plurality of connectors 16 or to enhance the adhesion between the first circuit structure 12 and the electronic component 15 .

[0056] The encapsulation layer 18 surrounds the electronic component 15. For example, in the cross-sectional view, the encapsulation layer 18 contacts at least one side of the electronic component 15. The material of the encapsulation layer 18 includes, for example, a molding compound, a resin (e.g., an epoxy resin), a polymer, or a combination thereof, but is not limited thereto. In some embodiments, although not shown, the encapsulation layer 18 may be thinned by a planarization process. The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, or a combination thereof.

[0057] The connector 20 can connect the plurality of contact pads CK6 of the second circuit structure 13 to the circuit board 19. The connector 20 can be a solder ball, a micro bump or other conductive connectors.

[0058] After the second circuit structure 13 is bonded to the circuit board 19, the production of the electronic device 1 is preliminarily completed. According to some embodiments of the present disclosure, the electronic device 1 may include a through-hole substrate 10H, a conductive member 11, an electronic component 15, and a circuit board 19. The through-hole substrate 10H has a first surface S1, a second surface S2 relative to the first surface S1, and a through hole TH, wherein an inner wall S3 of the through hole TH is connected to the first surface S1 and the second surface S2. The conductive member 11 is disposed in the through hole TH. The electronic component 15 is disposed on the first surface S1 and is electrically connected to the circuit board 20 through the conductive member 11. The surface roughness of the first surface S1 is greater than the surface roughness of the inner wall S3 of the through hole TH.

[0059] In some embodiments, as described above, the surface roughness of the second surface S2 may also be greater than the surface roughness of the inner wall S3 of the through hole TH. In some embodiments, as described above, the angle θ of the through hole TH (refer to Figure 5 ) is, for example, less than or equal to 20 degrees. In some embodiments, as described above, the width W of the through hole TH (refer to Figure 5 ) and the depth D of the through hole TH (refer to Figure 5 ) is, for example, 0.01 to 0.5. In some embodiments, as described above, the inner wall S3 of the through hole TH may have a plurality of protruding structures P3 (see Figure 6 ), and the ratio of the maximum thickness TP3 of the plurality of protruding structures P3 to the width W of the through hole TH is, for example, 0.001 to 0.1. In some embodiments, as described above, the first surface S1 and the second surface S2 may have a plurality of protruding structures (refer to Figure 6 The protruding structures P1 and P2), and the thickness of the plurality of protruding structures (refer to Figure 6The thickness TP1 and the thickness TP2 are, for example, 0.2 μm to 10 μm. In some embodiments, as described above, in the cross-sectional view, at least one of the plurality of protruding structures may be in the shape of a triangle, and the vertex angle α of the triangle (refer to Figure 7 ) for example, between 60 degrees and 175 degrees. In some embodiments, as described above, the electronic device 1 may also selectively include a first circuit structure 12, a second circuit structure 13, a component integration layer 14, a connector 16, a bottom filler 17, a packaging layer 18 and / or a connector 20, but is not limited thereto. According to different requirements, the electronic device 1 may further include one or more components or film layers, or the electronic device 1 may omit the above one or more components or film layers.

[0060] Please refer to Fig.11 , the electronic device 1A and Fig.10 The main difference between the electronic device 1 and the electronic device 1A is that the electronic device 1A further includes a protective layer 21 covering the through-hole substrate 10H. Correspondingly, the manufacturing method of the electronic device having a through-hole substrate may further include: covering the through-hole substrate 10H with the protective layer 21. The protective layer 21 can be used to improve the adhesion between the through-hole substrate 10H and the conductive member 11, thereby improving the desorption problem between the through-hole substrate 10H and the conductive member 11. In addition, the protective layer 21 can utilize strain to release the internal stress generated by heat or other processes, thereby improving the structural strength of the through-hole substrate 10H or reducing the generation of cracks in the through-hole substrate 10H. For example, the material of the protective layer 21 may include polyimide (PI), parylene, benzocyclobutene (BCB), epoxy, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene terephthalate (PEN), other suitable materials or combinations thereof.

[0061] In some embodiments, the method of forming the protective layer 21 may include forming the material of the protective layer 21 on the first surface S1, the second surface S2 and the inner wall S3 by a chemical vapor deposition process. In other embodiments, the method of forming the protective layer 21 may include immersing the through-hole substrate 10H in a polymer solution. Before immersing the through-hole substrate 10H in the polymer solution, the through-hole substrate 10H may be selectively surface treated to enhance the adhesion of the protective layer 21 to the through-hole substrate 10H or reduce the risk of the protective layer 21 desorbing from the through-hole substrate 10H. The surface treatment may include a cleaning step, a laser irradiation step, a chemical treatment step, a heating step, other suitable steps or a combination thereof.

[0062] In some embodiments, the thickness T21 of the protective layer 21 is 0.01 μm to 10 μm, that is, 0.01 μm ≤ T21 ≤ 10 μm, considering the process cost, time, yield and / or the structural strength of the through-hole substrate 10H. The thickness T21 of the protective layer 21 is measured from the vertical direction (or the normal direction) of the setting surface (such as the first surface S1, the second surface S2 and the inner wall S3). In some embodiments, the ratio of the thickness T21 of the protective layer 21 to the width W of the through hole TH is 0.002 to 0.2, that is, 0.002 ≤ T21 / W ≤ 0.2, so as to improve the structural strength of the through-hole substrate 10H and reduce the damage to the through-hole substrate 10H caused by the internal stress generated by the subsequent process. For example, when W=5μm, T21=0.1μm to 1μm; when W=50μm, T21=0.1μm to 5μm; when W=100μm, T21=2μm to 10μm. In some embodiments, the thickness of the dielectric layer of the redistribution structure (such as the thickness TIN1 of the dielectric layer IN1) may be greater than the thickness T21 of the protective layer 21. For example, the thickness TIN1 of the dielectric layer IN1 is 5mm to 15mm, that is, 5mm≤TIN1≤15mm, but is not limited thereto. In some embodiments, such as Fig.11 As shown, the protective layer 21 may expose the central portion of the inner wall S3. For example, the range of the inner wall S3 covered by the protective layer 21 may be more than two-thirds of the depth of the through hole TH, and the range of the inner wall S3 exposed by the protective layer 21 (that is, the range of the inner wall S3 not covered by the protective layer 21) may be less than one-third of the depth of the through hole TH.

[0063] Please refer to Fig.12 , the electronic device 1B and Fig.11 The main differences between the electronic device 1A and the electronic device 1B are described below. In the electronic device 1B, the through hole TH and the conductive member 11 are in the shape of an hourglass. In addition, the inner wall S3 of the through hole TH is fully covered by the protective layer 21. In addition, the electronic device 1B does not include Fig.11 The component integration layer 14 is formed, and at least one circuit CK1 is electrically connected to a corresponding conductive element 11.

[0064] Please refer to Fig.13 , the electronic device 1C and Fig.12The main differences of the electronic device 1B are described as follows. In the electronic device 1C, the through-hole substrate 10H' further includes a blind hole BH, and the electronic device 1C further includes an electronic component 22. The electronic component 22 is disposed in the blind hole BH and is electrically connected to the electronic component 15 through the first circuit structure 12'. The electronic component 22 may be a connector or other types of electronic components, which are not limited here. In some embodiments, the electronic device 1C may further include an adhesive layer 23, a conductive member 24, and a filling layer 25. The electronic component 22 may be fixed in the blind hole BH through the adhesive layer 23. The adhesive layer 23 may include, for example, an optically clear adhesive (OCA) or an optically clear resin (OCR), but is not limited thereto. The electronic component 22 may be electrically connected to the first circuit structure 12' through the conductive member 24. The conductive member 24 may include, for example, a conductive bump or other conductive medium. The filling layer 25 can fill the space in the blind hole BH that is not occupied by the electronic component 22, the adhesive layer 23, and the conductive member 24, and the filling layer 25 can expose one end of the conductive member 24 to be connected to the first circuit structure 12'. The material of the filling layer 25 may include a bottom filler or other insulating filling materials. In some embodiments, the top surface of the conductive member 24 and the top surface of the filling layer 25 may be flush or have the same height, but is not limited thereto.

[0065] The first circuit structure 12' may further include a dielectric layer IN6 in addition to the conductive layer C1, the dielectric layer IN1, the conductive layer C2, the dielectric layer IN2 and the conductive layer C3, and the dielectric layer IN6, the conductive layer C1, the dielectric layer IN1, the conductive layer C2, the dielectric layer IN2 and the conductive layer C3 are, for example, sequentially formed on the first surface S1. The material of the dielectric layer IN6 can refer to the description of the dielectric layer IN1, which will not be repeated here. At least one circuit CK1 in the conductive layer C1 can penetrate the dielectric layer IN6 and be electrically connected to a corresponding conductive element 11 or conductive element 24.

[0066] The electronic device 1C may further include a solder resist layer 26 covering the first circuit structure 12'. The solder resist layer 26 exposes a plurality of contact pads CK3, so as to facilitate forming a plurality of connectors 16 on the plurality of contact pads CK3. In the electronic device 1C, the electronic component 15 is, for example, an electronic integrated circuit (EIC), and the electronic device 1C may further include an electronic component 28 and an optical fiber 29. A plurality of pads 280 of the electronic component 28 may be bonded to the plurality of contact pads CK3 through a plurality of connectors 16. The electronic component 28 is, for example, a photonic integrated circuit (PIC), and the electronic component 28 is optically coupled to the optical fiber 29. For example, the optical fiber 29 may be embedded in the packaging layer 18 and the end of the optical fiber 29 may be connected to the electronic component 28, but is not limited thereto. Other optical coupling methods between the electronic component 28 and the optical fiber 29 are also included in the protection scope of the present disclosure.

[0067] The second circuit structure 13' may further include a dielectric layer IN7 in addition to the conductive layer C4, the dielectric layer IN4, the conductive layer C5, the dielectric layer IN5 and the conductive layer C6, and the dielectric layer IN7, the conductive layer C4, the dielectric layer IN4, the conductive layer C5, the dielectric layer IN5 and the conductive layer C6 are, for example, sequentially formed on the second surface S2. The material of the dielectric layer IN7 can refer to the description of the dielectric layer IN3, which will not be repeated here. At least one line CK4 in the conductive layer C4 can penetrate the dielectric layer IN7 and be electrically connected to a corresponding conductive element 11.

[0068] The electronic device 1C may further include a solder resist layer 27 covering the second circuit structure 13'. The solder resist layer 27 exposes a plurality of contact pads CK6, so as to facilitate forming a plurality of connectors 20 on the plurality of contact pads CK6.

[0069] Please refer to Fig.14 , the electronic device 1D and Fig.11 The main differences of the electronic device 1A are described as follows. In the electronic device 1D, the inner wall S3 of the through hole TH is fully covered by the protective layer 21. In addition, the electronic device 1D includes two electronic components 15. The two electronic components 15 can be the same type or different types of electronic components, which is not limited here.

[0070] In some embodiments, Fig.14As shown, the electronic device 1D may also include a through-hole substrate 10H", a protective layer 21', a plurality of conductive elements 11', a plurality of circuits CK1', a plurality of circuits CK4', a bottom filler 17', a packaging layer 18' and a plurality of connectors 20', but is not limited thereto. The relative arrangement relationship of the through-hole substrate 10H", the protective layer 21', the plurality of conductive elements 11', the plurality of circuits CK1' and the plurality of circuits CK4' is similar to the relative arrangement relationship of the through-hole substrate 10H, the protective layer 21, the plurality of conductive elements 11, the plurality of circuits CK1 and the plurality of circuits CK4, and will not be repeated here. A plurality of connectors 20 are respectively arranged on a plurality of circuits CK1', a plurality of connectors 20' are respectively arranged on a plurality of circuits CK4', and a through-hole substrate 10H" is joined and electrically connected to a circuit board 19 through a plurality of connectors 20'. A plurality of connectors 20' can be pad-connected to two electronic components 15 through a plurality of circuits CK4', a plurality of conductive members 11', a plurality of circuits CK1', a plurality of connectors 20, a second circuit structure 13, a plurality of conductive members 11, a first circuit structure 12 and a plurality of connectors 16. The bottom filler 17' surrounds the plurality of connectors 20 to protect the plurality of connectors 20 or enhance the adhesion between the second circuit structure 13 and the through-hole substrate 10H". The packaging layer 18' is arranged on the through-hole substrate 10H" and the bottom filler 17' and can surround the packaging layer 18, the through-hole substrate 10H and the second circuit structure 13. The material of the packaging layer 18' can refer to the material of the packaging layer 18 and will not be repeated here.

[0071] In summary, in the embodiments of the present disclosure, the structural strength of the substrate can be improved by designing the manufacturing method, angle, surface roughness, etc. of the through hole.

[0072] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0073] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced with each other to form other new embodiments. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment. The scope of protection of the present disclosure shall be determined by the attached claims.

Claims

1. An electronic device, characterized in that: include: A through-hole substrate, comprising a first surface, a second surface opposite to the first surface, and a through-hole, wherein an inner wall of the through-hole is connected to the first surface and the second surface; A conductive member, disposed in the through hole; An electronic component, disposed on the first surface; as well as A circuit board, wherein the electronic component is electrically connected to the circuit board through the conductive member, and the surface roughness of the first surface is greater than the surface roughness of the inner wall of the through hole.

2. The electronic device according to claim 1, characterized in that: The surface roughness of the second surface is greater than the surface roughness of the inner wall of the through hole.

3. The electronic device according to claim 1, characterized in that: The angle of the through hole is less than or equal to 20 degrees.

4. The electronic device according to claim 1, characterized in that: The ratio of the width of the through hole to the depth of the through hole is 0.01 to 0.

5.

5. The electronic device according to claim 1, characterized in that: A ratio of the surface roughness of the inner wall of the through hole to the surface roughness of the first surface is greater than or equal to 0.01 and less than 1.

6. The electronic device according to claim 1, characterized in that: The first surface and the second surface have a plurality of protruding structures, and the thickness of the plurality of protruding structures is 0.2 μm to 10 μm.

7. The electronic device according to claim 6, characterized in that: In the cross-sectional view, at least one of the plurality of protruding structures is in the shape of a triangle, and a vertex angle of the triangle is between 60 degrees and 175 degrees.

8. A method for manufacturing an electronic device having a through-hole substrate, characterized in that: include: irradiating local areas of two opposite sides of the substrate with laser light; as well as The step of forming a through hole in the local area of ​​the substrate includes: Performing an etching step to form opposite etching profiles at the local areas of the two opposite surfaces of the substrate; Performing a buffer layer coating step to form a buffer layer on the two opposite surfaces of the substrate and the opposite etching profiles; and The etching step and the buffer layer coating step are repeatedly performed until the relative etching profiles form through holes.

9. The method for manufacturing an electronic device having a through-hole substrate according to claim 8, characterized in that: Also includes: The through-hole substrate is covered with a protective layer.

10. The method for manufacturing an electronic device having a through-hole substrate according to claim 8, wherein: Also includes: Confirm whether the angle of the through hole is less than or equal to 20 degrees. If it is confirmed that the angle of the through hole is less than or equal to 20 degrees, terminate the through hole forming step. If it is confirmed that the angle of the through hole is greater than 20 degrees, repeat the buffer layer coating step and the etching step until the angle of the through hole is less than or equal to 20 degrees.

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