Chip package
By filling and grinding the molded second metal layer with conductive glue in the chip package, the problems of holes and incomplete molding of the traditional copper heat-dissipating metal layer are solved, improving the yield and market competitiveness of the chip package, while reducing manufacturing costs.
Patent Information
- Application Number
- CN202311243894.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-25
- Publication Date
- 2025-03-25
AI Technical Summary
When existing chip packages realize electromagnetic shielding and chip heat dissipation, the copper heat dissipation metal layer is prone to surface depressions or incomplete molding, resulting in a reduced yield and complex process, increasing manufacturing costs.
The openings of the insulating layer and the first metal layer are filled with conductive glue, and a flat surface is formed by grinding to form a second metal layer to replace the traditional copper heat dissipation metal layer.
It effectively solves the problems of reduced chip packaging yield and complex process, improves the market competitiveness of the product, and reduces manufacturing costs.
Smart Images
Figure CN119695032A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a chip package capable of achieving electromagnetic shielding and chip heat dissipation, and in particular to a chip package capable of solving the problems of reduced chip packaging yield and relatively complex manufacturing process. Background Art
[0002] In order to achieve the effects of electromagnetic shielding and chip heat dissipation, the existing chip package generally sets an electromagnetic shielding layer on the top of the chip package, and drills a hole from the top of the chip package to expose the backside of the internal chip, and then electroplates a layer of copper metal on the backside as a heat dissipation metal layer to help the chip dissipate heat.
[0003] However, the copper heat dissipation metal layer formed by electroplating is prone to surface pits (i.e., unevenness) or incomplete surface formation, which reduces the yield of chip packaging and damages the market competitiveness of the product. In addition, the electroplating process of general copper metal is relatively complicated, which easily increases the cost of the manufacturing end.
[0004] Therefore, a chip package that can solve the problems of reduced chip packaging yield and relatively complex process is urgently expected by the relevant industries. Summary of the invention
[0005] The main purpose of the present invention is to provide a chip package, comprising at least one chip, an insulating layer, at least one first metal layer and at least one second metal layer; wherein each second metal layer is filled in at least one opening of the insulating layer and at least one opening of each first metal layer, and covers the back of each chip, and the first surface level of each second metal layer is the same as the first surface level of each first metal layer; wherein each second metal layer is formed after at least one conductive glue is filled in each opening of the insulating layer and each opening of the first metal layer; wherein the first surface of each second metal layer is a flat surface formed by a grinding operation to avoid affecting the yield of the product and effectively solve the problem of relatively complex chip packaging process.
[0006] To achieve the above-mentioned object, the present invention provides a chip package, which includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, an insulating layer, at least one first metal layer and at least one second metal layer; wherein the substrate has a first surface and an opposite second surface; wherein each of the first circuit layers is arranged on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein each of the second circuit layers is arranged on the second surface of the substrate, and wherein each of the second circuit layers is electrically connected to each of the first circuit layers through the substrate; wherein each of the chips is electrically connected on the first surface of each of the first circuit layers, and each of the chips has a backing (Ba ckside) and an opposite connection surface, each chip has at least two crystal pads on the connection surface, each chip is electrically connected to each first circuit layer through each crystal pad, wherein each chip is first electrically connected to the first surface of each first circuit layer, and then electrically connected to each second circuit layer through each first circuit layer, so that each chip can be electrically connected to the outside from each second circuit layer; wherein the insulating layer is arranged on the substrate and covers each chip, the insulating layer has a first surface and at least one opening, wherein each opening of the insulating layer can allow the crystal back of each chip to be exposed to the outside; wherein each first metal layer is arranged on the first surface of the insulating layer to fully cover Each of the first metal layers has a first surface and at least one opening, each of the openings of the first metal layer is connected to each of the openings of the insulating layer, wherein each of the openings of the first metal layer can allow the back of each chip to be exposed to the outside; wherein each of the second metal layers is filled in each of the openings of the insulating layer and each of the openings of the first metal layer, and covers the back of each chip, and the first surface level of each of the second metal layers is the same as the first surface level of each of the first metal layers, wherein each of the second metal layers is formed by filling each of the openings of the insulating layer and each of the openings of the first metal layer with at least one conductive glue, wherein The first surface of each second metal layer is a flat surface formed by grinding; each second metal layer is connected to each first metal layer to form a comprehensive protective metal layer structure for preventing each first circuit layer, each second circuit layer and each chip from being subjected to electromagnetic interference, and directly generating heat dissipation effect on the back of each chip; the manufacturing method of the chip package comprises the following steps: step S1: providing a substrate, wherein the substrate has a first surface and an opposite second surface, wherein at least one first circuit layer is disposed on the first surface of the substrate, each first circuit layer has a first surface, wherein at least one second circuit layer is disposed on the second surface of the substrate;Step S2: at least one chip is arranged on the first surface of each of the first circuit layers, wherein each of the chips has a back surface and a connection surface opposite thereto, and each of the chips has at least two pads on the connection surface; Step S3: an insulating layer is arranged on the substrate so that the insulating layer covers each of the chips, wherein the insulating layer has a first surface; Step S4: at least one first metal layer is arranged on the first surface of the insulating layer to fully cover the entire surface, wherein each of the first metal layers has a first surface; Step S5: drilling holes on the insulating layer and each of the first metal layers simultaneously, so that at least one opening is formed on the insulating layer and each of the first metal layers, respectively, wherein the Each opening of the insulating layer exposes the back of each chip, wherein each opening of each first metal layer is connected to each opening of the insulating layer; Step S6: each opening of the insulating layer and each opening of each first metal layer is filled with at least one conductive glue, and each conductive glue covers the back of each chip; Step S7: each conductive glue is ground to the same level as the first surface of each first metal layer by grinding operation. After the grinding operation is completed, each conductive glue located in each opening of the insulating layer and each opening of each first metal layer is formed into at least one second metal layer. ;
[0007] In a preferred embodiment of the present invention, each of the conductive pastes formed into each of the second metal layers is silver paste.
[0008] In a preferred embodiment of the present invention, each of the second circuit layers further has a first surface; wherein the chip package also has at least one first outer protective layer and at least one second outer protective layer; wherein each of the first outer protective layers is disposed on the first surface of each of the first metal layers and the first surface of each of the second metal layers; wherein each of the second outer protective layers is disposed on the first surface of each of the second circuit layers, and each of the second outer protective layers has at least one opening, and each of the openings enables the first surface of each of the second circuit layers to be exposed to the outside.
[0009] In a preferred embodiment of the present invention, the substrate further has at least one blind hole, each of which has a conducting circuit therein, and each of the first circuit layers is electrically connected to each of the second circuit layers via the conducting circuit in each of the blind holes.
[0010] In a preferred embodiment of the present invention, each of the blind holes of the substrate is further provided with at least one third metal layer filling the blind holes to serve as a conducting circuit in each of the blind holes, and the horizontal height of a first surface of each of the third metal layers is the same as the horizontal height of the first surface of each of the first circuit layers; wherein each of the second circuit layers is further electrically connected to each of the first circuit layers through each of the third metal layers.
[0011] In a preferred embodiment of the present invention, each of the third metal layers is silver metal. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a schematic plan view of a side cross-section of an embodiment of the present invention.
[0013] Figure 2 It is a schematic plan view of a side cross-section of the substrate of the present invention.
[0014] Figure 3 For Figure 2 Schematic diagram of arranging a chip on the first surface of the first circuit layer in FIG.
[0015] Figure 4 For Figure 3 Schematic diagram of providing an insulating layer on a substrate in FIG.
[0016] Figure 5 For Figure 4 Schematic diagram of a first metal layer being arranged on the first surface of the insulating layer to fully cover the entire surface.
[0017] Figure 6 For Figure 5 Schematic diagram of drilling holes simultaneously on the insulating layer and the first metal layer in FIG.
[0018] Figure 7 For Figure 6 Schematic diagram of filling the openings of the insulating layer and the first metal layer with conductive glue.
[0019] Figure 8 It is a schematic plan view of a side cross-section of another embodiment of the present invention (further having a first outer protective layer and a second outer protective layer).
[0020] Explanation of the accompanying drawings: 1-chip package; 10-substrate; 11-first surface; 12-second surface; 13-blind hole; 20-first circuit layer; 21-first surface; 30-second circuit layer; 31-first surface; 40-chip; 41-crystal back; 42-connection surface; 43-crystal pad; 50-insulating layer; 51-first surface; 52-opening; 60-first metal layer; 61-first surface; 62-opening; 70-second metal layer; 70a-conductive adhesive; 71-first surface; 80-first outer protective layer; 90-second outer protective layer; 91-opening; 100-third metal layer; 101-first surface. DETAILED DESCRIPTION
[0021] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.
[0022] refer to Figure 1 The present invention provides a chip package 1, which includes a substrate 10, at least a first circuit layer 20, at least a second circuit layer 30, at least a chip 40, an insulating layer 50, at least a first metal layer 60 and at least a second metal layer 70.
[0023] The substrate 10 has a first surface 11 and an opposite second surface 12. Figure 1 and Figure 8 shown.
[0024] Each first circuit layer 20 is disposed on the first surface 11 of the substrate 10. Each first circuit layer 20 has a first surface 21. Figure 1 and Figure 8 shown.
[0025] Each second circuit layer 30 is disposed on the second surface 12 of the substrate 10. Figure 1 and Figure 8 wherein each second circuit layer 30 is electrically connected to each first circuit layer 20 through the substrate 10, such as Figure 1 and Figure 8 shown.
[0026] Each chip 40 is electrically connected to the first surface 21 of each first circuit layer 20. Each chip 40 has a backside 41 and an opposite connection surface 42. The connection surface 42 of each chip 40 has at least two pads 43. Each chip 40 is electrically connected to each first circuit layer 20 via the pads 43. Figure 1 and Figure 8 As shown, in a preferred embodiment of the chip package 1 of the present invention, the number of the pads 43 on the chip package 1 is 2 but is not limited to Figure 1 wherein each chip 40 is first electrically connected to the first surface 21 of each first circuit layer 20, and then electrically connected to each second circuit layer 30 through each first circuit layer 20, so that each chip 40 can be electrically connected to the outside by each second circuit layer 30, such as Figure 1 and Figure 8 shown.
[0027] The insulating layer 50 is disposed on the substrate 10 and covers each chip 40. The insulating layer 50 has a first surface 51 and at least one opening 52. Each opening 52 of the insulating layer 50 can allow the back 41 of each chip 40 to be exposed to the outside. Figure 1 and Figure 8 shown.
[0028] Each first metal layer 60 is disposed on the first surface 51 of the insulating layer 50 so as to cover the entire surface. Each first metal layer 60 has a first surface 61 and at least one opening 62. Each opening 62 of each first metal layer 60 is connected to each opening 52 of the insulating layer 50. Figure 1 and Figure 8 wherein each opening 62 of each first metal layer 60 can expose the back surface 41 of each chip 40 to the outside, such as Figure 1 and Figure 8 shown.
[0029] Each second metal layer 70 is filled in each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60, and covers the back surface 41 of each chip 40, and a first surface 71 of each second metal layer 70 has the same level as the first surface 61 of each first metal layer 60. Figure 1 and Figure 8 wherein each second metal layer 70 is formed by filling each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 with at least one conductive glue 70a, as shown in FIG. Figure 1 wherein the first surface 71 of each second metal layer 70 is a flat surface formed by grinding operation, such as Figure 1 and Figure 8 shown.
[0030] Each second metal layer 70 is connected to each first metal layer 60 to form a comprehensive protective metal layer structure for preventing each first circuit layer 20, each second circuit layer 30 and each chip 40 from electromagnetic interference, and directly generating heat dissipation effect on the back surface 41 of each chip 40. Figure 1 and Figure 8 shown.
[0031] The manufacturing method of the chip package 1 comprises the following steps:
[0032] Step S1: Provide a substrate 10, such as Figure 2 wherein the substrate 10 has a first surface 11 and an opposite second surface 12, the first surface 11 is provided with at least one first circuit layer 20, each first circuit layer 20 has a first surface 21, such as Figure 2 wherein at least one second circuit layer 30 is disposed on the second surface 12, such as Figure 2 shown.
[0033] Step S2: Dispose at least one chip 40 on the first surface 21 of each first circuit layer 20, such as Figure 3 wherein each chip 40 has a back surface 41 and an opposite connection surface 42, the connection surface 42 having at least two pads 43, such as Figure 3 shown.
[0034] Step S3: an insulating layer 50 is disposed on the substrate 10 so that the insulating layer 50 covers each chip 40. Figure 4 wherein the insulating layer 50 has a first surface 51, such as Figure 4 shown.
[0035] Step S4: at least one first metal layer 60 is disposed on the first surface 51 of the insulating layer 50 to cover the entire surface. Figure 5 wherein each first metal layer 60 has a first surface 61, such as Figure 5 shown.
[0036] Step S5: drilling holes on the insulating layer 50 and each first metal layer 60 simultaneously, so that at least one opening 52, 62 is formed on the insulating layer 50 and each first metal layer 60 respectively. Figure 6 wherein each opening 52 of the insulating layer 50 exposes the back surface 41 of each chip 40 to the outside, such as Figure 6 wherein each opening 62 of each first metal layer 60 is connected to each opening 52 of the insulating layer 50, such as Figure 6 shown.
[0037] Step S6: Fill each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 with at least one conductive adhesive 70a, and each conductive adhesive 70a covers the back surface 41 of each chip 40. Figure 7 shown.
[0038] Step S7: Grind each conductive adhesive 70a by grinding until the surface level is the same as the level of the first surface 61 of each first metal layer 60. Figure 1 As shown, after the grinding operation is completed, each conductive glue 70a located in each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 is formed into at least one second metal layer 70. Figure 1 shown.
[0039] refer to Figure 1 , each conductive paste 70a formed into each second metal layer 70 is silver paste but is not limited.
[0040] refer to Figure 8, each second circuit layer 30 further has a first surface 31 but is not limited; wherein the chip package 1 also has at least one first outer protective layer 80 and at least one second outer protective layer 90, but is not limited, which helps to enhance the strength of the structure; wherein each first outer protective layer 80 is disposed on the first surface 61 of each first metal layer 60 and on the first surface 71 of each second metal layer 70; wherein each second outer protective layer 90 is disposed on the first surface 31 of each second circuit layer 30, and each second outer protective layer 90 has at least one opening 91, and each opening 91 can expose the first surface 31 of each second circuit layer 30 to the outside, so that each chip 40 can be electrically connected to the outside.
[0041] refer to Figure 1 The substrate 10 further has at least one blind hole 13, but not limited thereto, each blind hole 13 is provided with a conducting line, each first circuit layer 20 is electrically connected to each second circuit layer 30 through the conducting line in each blind hole 13, and in a preferred embodiment of the chip package 1 of the present invention, the number of each blind hole 13 on the chip package 1 is 2 but not limited thereto. Figure 1 As shown; wherein each blind hole 13 of the substrate 10 is further provided with at least one third metal layer 100 filled therein to serve as a conducting line in each blind hole 13 but is not limited to such Figure 1 As shown, it is beneficial to increase the conduction efficiency when the circuit layers in the chip package are electrically connected, and the level of a first surface 101 of each third metal layer 100 is the same as the level of the first surface 21 of each first circuit layer 20, which is beneficial to improve the yield; wherein each second circuit layer 30 is further electrically connected to each first circuit layer 20 through each third metal layer 100 but is not limited to the following Figure 1 As shown; wherein each third metal layer 100 is silver metal but not limited.
[0042] In summary, each conductive adhesive 70a of the present invention is first filled in each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 and covers the back surface 41 of each chip 40. Figure 7 As shown, each conductive adhesive 70a is then ground by grinding until the surface level is the same as the level of the first surface 61 of each first metal layer 60, as shown in FIG. Figure 1 As shown, after the grinding operation is completed, each second metal layer 70 is formed in each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60, as shown in FIG. Figure 1 As shown, the first surface 71 of each second metal layer 70 is a flat surface. Figure 1 and Figure 8 As shown, the chip package 1 of the present invention has the following advantages compared with the existing chip package:
[0043] (1) The second metal layers 70 of the present invention are at the same level as the first surface 61 of the first metal layers 60. Figure 1 As shown, the first surface 71 of each second metal layer 70 is a flat surface. Figure 1 and Figure 8 As shown, the problem that the copper heat dissipation metal layer of the existing chip has surface pits (ie, unevenness) or an incomplete surface is effectively solved, which helps to improve chip packaging and enhance the market competitiveness of products.
[0044] (2) Each second metal layer 70 of the present invention is formed in each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 by grinding, rather than forming a copper heat dissipation metal layer by a relatively complex electroplating process like the existing chip packaging, which helps to reduce the cost of the manufacturing end.
[0045] The above description is only a preferred embodiment of the present invention, which is only illustrative rather than restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of these will fall within the scope of protection of the present invention.
Claims
1. A chip package, characterized in that: Include: A substrate having a first surface and an opposite second surface; At least one first circuit layer, each of the first circuit layers is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; At least one second circuit layer, each of the second circuit layers is disposed on the second surface of the substrate; wherein each of the second circuit layers is electrically connected to each of the first circuit layers through the substrate; At least one chip, each of which is electrically connected to the first surface of each of the first circuit layers, each of which has a back surface and an opposite connection surface, each of which has at least two pads on the connection surface, and each of which is electrically connected to each of the first circuit layers via each of the pads; wherein each of the chips is first electrically connected to the first surface of each of the first circuit layers, and then electrically connected to each of the second circuit layers via each of the first circuit layers, so that each of the chips is electrically connected to the outside from each of the second circuit layers; an insulating layer, the insulating layer being disposed on the substrate and covering each of the chips, the insulating layer having a first surface and at least one opening; Each of the openings in the insulating layer allows the back side of each chip to be exposed to the outside; At least one first metal layer, each of which is disposed on the first surface of the insulating layer in a fully covering manner, and each of which has a first surface and at least one opening, and each of which is communicated with ... At least one second metal layer, each of the second metal layers is filled in each of the openings of the insulating layer and each of the openings of the first metal layer, and covers the back of each of the chips, and a first surface level of each of the second metal layers is the same as the first surface level of each of the first metal layers; each of the second metal layers is formed by filling each of the openings of the insulating layer and each of the openings of the first metal layer with at least one conductive paste; and the first surface of each of the second metal layers is a flat surface formed by grinding; Each of the second metal layers is connected to each of the first metal layers to form a comprehensive protective metal layer structure for preventing each of the first circuit layers, each of the second circuit layers and each of the chips from being subjected to electromagnetic interference, and directly generating a heat dissipation effect on the back of each of the chips; The manufacturing method of the chip package comprises the following steps: Step S1: providing a substrate; wherein the substrate has a first surface and an opposite second surface; wherein at least one first circuit layer is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein at least one second circuit layer is disposed on the second surface of the substrate; Step S2: disposing at least one chip on the first surface of each of the first circuit layers; wherein each of the chips has a back surface and an opposite connection surface, and each of the chips has at least two pads on the connection surface; Step S3: disposing an insulating layer on the substrate and making the insulating layer cover each of the chips; wherein the insulating layer has a first surface; Step S4: disposing at least one first metal layer on the first surface of the insulating layer to cover the entire surface; wherein each of the first metal layers has a first surface; Step S5: drilling holes on the insulating layer and each of the first metal layers simultaneously, so that at least one opening is formed on the insulating layer and each of the first metal layers respectively; wherein each of the openings of the insulating layer exposes the back of each of the chips; wherein each of the openings of each of the first metal layers is connected to each of the openings of the insulating layer; Step S6: filling each of the openings of the insulating layer and each of the openings of the first metal layer with at least one conductive adhesive, and each of the conductive adhesives covers the backside of each of the chips; and Step S7: Use a grinding operation to grind each of the conductive adhesives until the surface level is the same as the level of the first surface of each of the first metal layers. After the grinding operation is completed, each of the conductive adhesives located in each of the openings of the insulating layer and each of the openings of the first metal layer is formed into at least one second metal layer.
2. The chip package according to claim 1, characterized in that: Each of the conductive pastes formed into each of the second metal layers is silver paste.
3. The chip package according to claim 1, characterized in that: Each of the second circuit layers further has a first surface; wherein the chip package also has at least one first outer protective layer and at least one second outer protective layer; wherein each of the first outer protective layers is arranged on the first surface of each of the first metal layers and the first surface of each of the second metal layers; wherein each of the second outer protective layers is arranged on the first surface of each of the second circuit layers, and each of the second outer protective layers has at least one opening, and each of the openings allows the first surface of each of the second circuit layers to be exposed to the outside.
4. The chip package according to claim 1, wherein: The substrate further has at least one blind hole, each of which is provided with a conducting circuit, and each of the first circuit layers is electrically connected to each of the second circuit layers through the conducting circuit in each of the blind holes.
5. The chip package according to claim 4, characterized in that: Each of the blind holes in the substrate is further provided with at least one third metal layer filled therein to serve as a conducting circuit in each of the blind holes, and the horizontal height of a first surface of each of the third metal layers is the same as the horizontal height of the first surface of each of the first circuit layers; wherein each of the second circuit layers is further electrically connected to each of the first circuit layers through each of the third metal layers.
6. The chip package according to claim 5, characterized in that: Each of the third metal layers is silver metal.