Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes a first terminal, a first circuit, and a second circuit. The first terminal is connected to the first node and receives a control signal from the outside. The first circuit is connected to the first node, switches between a first state in which the first voltage is not output to the second node and a second state in which the first voltage is output to the second node on the basis of the logic level of the first node, and controls the slew rate of the output voltage when switching from the first state to the second state. The second circuit includes a switch, one end of which is connected to the first node and the other end of which is applied with a second voltage, and controls the switch based on the voltage of the second node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Japanese Patent Application No. 2023-158488 (filing date: September 22, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] As a semiconductor device, a pull-down circuit for fixing a voltage of a node is known. Summary of the invention

[0005] The semiconductor device according to the embodiment includes a first terminal, a first circuit, and a second circuit. The first terminal is connected to a first node and a control signal is inputted from the outside. The first circuit is connected to the first node and switches between a first state in which a first voltage is not output to a second node and a second state in which the first voltage is output to the second node based on a logic level of the first node, and controls the conversion rate of the output voltage when switching from the first state to the second state. The second circuit includes a switch having one end connected to the first node and the other end to which a second voltage is applied, and the switch is controlled based on the voltage of the second node.

[0006] According to one embodiment of the present invention, it is possible to provide a semiconductor device that suppresses malfunction due to noise and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing an example of the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a block diagram showing a specific example of the configuration of the output circuit and the control circuit according to the first embodiment.

[0009] Figure 3 This is a timing chart showing an operation example of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a block diagram showing a specific example of the configuration of an output circuit and a pull-down circuit according to a first modification of the first embodiment.

[0011] Figure 5 This is a circuit diagram showing an example of the structure of a semiconductor device according to the second embodiment.

[0012] Figure 6This is a timing chart showing an operation example of the semiconductor device according to the second embodiment.

[0013] Figure 7 This is a block diagram showing an example of the structure of a semiconductor device according to the third embodiment.

[0014] Figure 8 This is a timing chart showing an operation example of the semiconductor device according to the third embodiment.

[0015] Fig. 9 This is a block diagram showing a specific example of the structure of a semiconductor device according to a first modification of the third embodiment.

[0016] Fig.10 This is a block diagram showing an example of the structure of a semiconductor device according to the fourth embodiment.

[0017] Fig.11 It is a block diagram showing a specific example of the configuration of an output circuit and a control circuit according to the fourth embodiment.

[0018] Fig.12 This is a timing chart showing an operation example of the semiconductor device according to the fourth embodiment.

[0019] Fig.13 This is a block diagram showing an example of the structure of a semiconductor device according to a second modification of the first embodiment.

[0020] Fig.14 This is a block diagram showing an example of the structure of a semiconductor device according to a first modification of the fourth embodiment.

[0021] Fig.15 This is a block diagram showing an example of the structure of a semiconductor device according to a third modification of the first embodiment.

[0022] Fig.16 This is a block diagram showing an example of the structure of a semiconductor device according to a second modification of the fourth embodiment.

[0023] Fig.17 This is a block diagram showing an example of the structure of a semiconductor device according to a third modification of the fourth embodiment. DETAILED DESCRIPTION

[0024] The following is an explanation of the embodiments with reference to the accompanying drawings. When explaining, the components having substantially the same function and structure are marked with the same reference numerals. In addition, the embodiments shown below illustrate the technical ideas. The embodiments do not determine the material, shape, structure, configuration, etc. of the components. Various changes can be made to the embodiments.

[0025] <1> First Embodiment

[0026] A semiconductor device according to the first embodiment will be described.

[0027] <1-1>Structure

[0028] Figure 1 1 is a block diagram showing an example of the structure of a semiconductor device according to the first embodiment. The semiconductor device 1 according to the first embodiment is a load switch for supplying power to a load with a slew rate control function. The semiconductor device 1 is an IC (Integrated Circuit) chip that switches the validity or invalidity of an output based on a control signal input from the outside.

[0029] The semiconductor device 1 includes terminals TEN and TOUT, an output circuit 2, and a pull-down circuit 3. The terminal TEN is a control signal input terminal of the semiconductor device 1. The terminal TEN is configured to be connected to the outside of the semiconductor device 1. The terminal TEN is connected to the node N1. A control signal is input to the terminal TEN from a previous circuit (not shown) provided outside the semiconductor device 1. The terminal TOUT is an output terminal of the semiconductor device 1. The terminal TOUT is configured to be connected to the outside of the semiconductor device 1. Power is supplied to the outside of the semiconductor device 1 from the terminal TOUT. The terminal TOUT is connected to the node N2.

[0030] The output circuit 2 is a circuit that realizes the function as a load switch of the semiconductor device 1. The voltage VDD as the power supply voltage and the ground voltage GND are applied to the output circuit 2. The output circuit 2 is connected to the nodes N1 and N2, respectively. The output circuit 2 switches between the on state (second state) in which the voltage VDD is output to the node N2 and the off state (first state) in which the voltage VDD is not output to the node N2 according to the logic level of the node N1. Specifically, the output circuit 2 becomes an off state when the logic level of the node N1 is L (Low) level, and becomes an on state when the logic level of the node N1 is H (High) level. The output circuit 2 has a conversion rate control function. That is, when the output circuit 2 switches from the off state to the on state, the rising speed of the voltage that switches the output voltage from 0V (a state in which the voltage is not output) to the voltage VDD is controlled. In more detail, the output circuit 2 is configured to take, for example, 30 μsec or more from 0V to 1 / 2 of the final voltage, that is, from 0V to 1 / 2 of the voltage VDD.

[0031] The pull-down circuit 3 pulls down the node N1. Specifically, the pull-down circuit 3 switches between an on state in which the node N1 is pulled down and an off state in which the node N1 is not pulled down, based on the voltage of the node N2. Hereinafter, the case where the pull-down circuit 3 is in an on state is referred to as a state in which the pull-down circuit 3 is connected to the node N1. In addition, the case in which the pull-down circuit 3 is in an off state is referred to as a state in which the pull-down circuit 3 is disconnected from the node N1. The pull-down circuit 3 includes a resistor R1, a switch SW1, and a control circuit 4. The resistor R1 and the switch SW1 are connected in series. Figure 1 In the example shown, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and the other end of the switch SW1 is grounded. In other words, one end of the switch SW1 is connected to the node N1 via the resistor R1, and the ground voltage GND is applied to the other end of the switch SW1. The control circuit 4 controls the switch SW1 based on the voltage of the node N2. Specifically, the control circuit 4 sets the switch SW1 to be disconnected when it is detected that the output circuit 2 outputs a voltage above a preset threshold to the node N2. The control circuit 4 sets the switch SW1 to be connected when it is detected that the output circuit 2 does not output a voltage above the threshold to the node N2. That is, when a voltage above the threshold is applied to the node N2, the pull-down circuit 3 is disconnected from the node N1, and when a voltage above the threshold is not applied to the node N2, the pull-down circuit 3 is connected to the node N1.

[0032] Figure 2 1 is a block diagram showing a specific example of the configuration of the output circuit 2 and the control circuit 4 according to the first embodiment. Figure 2 As shown, the output circuit 2 according to the first embodiment includes a non-inverting logic circuit 20, transistors MN1, MP1 and MP2, and a current source CS1. The transistor MN1 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistors MP1 and MP2 are P-channel MOSFETs.

[0033] The voltage VDD and the ground voltage GND are applied to the non-inverting logic circuit 20. The signal input terminal of the non-inverting logic circuit 20 is connected to the node N1, and the signal output terminal is connected to the gates of the transistors MP1 and MN1. The non-inverting logic circuit 20 applies a voltage based on the logic level of the node N1 to the gates of the transistors MP1 and MN1. For example, when an H-level voltage is applied to the node N1, the non-inverting logic circuit 20 outputs an H-level voltage. In this case, the transistor MP1 is set to an OFF state, and the transistor MN1 is set to an ON state. In addition, for example, when an L-level voltage is applied to the node N1, the non-inverting logic circuit 20 outputs an L-level voltage. In this case, the transistor MP1 is set to an ON state, and the transistor MN1 is set to an OFF state.

[0034] The voltage VDD is applied to the source of the transistor MP1. The drain of the transistor MP1 and the drain of the transistor MN1 are connected to the gate of the transistor MP2. For example, when the non-inverting logic circuit 20 outputs a voltage of an L level, the transistor MP1 is set to an on state, and the transistor MN1 is set to an off state. Therefore, the transistor MP2 is set to an off state. In addition, when the non-inverting logic circuit 20 outputs a voltage of an H level, the transistor MP1 is set to an off state, and the transistor MN1 is set to an on state. Therefore, the transistor MP2 is set to an on state.

[0035] The current source CS1 is connected to the source of the transistor MN1 and is configured to allow a current to flow from the source of the transistor MN1 toward the ground voltage GND.

[0036] The voltage VDD is applied to the source of the transistor MP2. The drain of the transistor MP2 is connected to the node N2. The transistor MP2 applies the voltage VDD to the node N2 in the on state, and does not apply the voltage VDD to the node N2 in the off state. The transistors MP1 and MN1 and the current source CS1 function as a gate driver for driving the gate of the transistor MP2. In the gate driver, the current amount when the gate of the transistor MP2 is driven from the H level to the L level is controlled by the current source CS1. Thus, in the output circuit 2, the length of time for the transistor MP2 to switch from the off state to the on state is controlled. That is, the output circuit 2 involved in the first embodiment controls the conversion rate of the output voltage when switching from the off state to the on state.

[0037] Next, refer to Figure 2 The structure of the control circuit 4 included in the pull-down circuit 3 is described. Figure 2As shown, the control circuit 4 involved in the first embodiment includes a comparator 40 and a voltage source 41. The voltage source 41 outputs a voltage VREF1. The voltage VREF1 is a voltage higher than the ground voltage GND and lower than the voltage VDD. The voltage VREF1 is, for example, 1 / 2 of the voltage VDD. The positive output terminal of the voltage source 41 is connected to the non-inverting input terminal of the comparator 40. The negative output terminal of the voltage source 41 is grounded.

[0038] The inverting input terminal of the comparator 40 is connected to the node N2. The output terminal of the comparator 40 is connected to the switch SW1. The switch SW1 is controlled based on the output of the comparator 40. More specifically, when the output of the comparator 40 is at an H level, the switch SW1 is turned on. When the output of the comparator 40 is at an L level, the switch SW1 is turned off.

[0039] <1-2>Action

[0040] The operation of the semiconductor device 1 according to the first embodiment will be described. The voltage of the terminal TEN is referred to as a voltage VEN, and the voltage of the terminal TOUT is referred to as a voltage VOUT.

[0041] Figure 3 1 is a timing chart showing an operation example of the semiconductor device 1 according to the first embodiment. Figure 3 2 shows the operation when noise is applied to the terminal TEN, and the operation of the semiconductor device 1 is switched when an H level signal is applied to the terminal TEN. Figure 3 , the voltage VEN, the voltage VOUT, and the state of the switch SW1 are shown in order from the top.

[0042] exist Figure 3 In the state where the state where the L level is applied to the terminal TEN by the device at the previous stage is switched to the high impedance state, the timing diagram starts. In this state, the voltage VEN is 0V, the voltage VOUT is 0V, and the switch SW1 is in the on state. The switch SW1 is in the on state, so the node N1 is pulled down to 0V by the pull-down circuit 3. The voltage of the node N1 is 0V, that is, the L level, so the output circuit 2 is in the off state, and the voltage VOUT becomes 0V.

[0043] At time t11, noise is applied to the terminal TEN, and the voltage VEN rises sharply. For example, the peak value of the voltage VEN exceeds 1 / 2 of the voltage VDD. Then, the voltage VEN decreases and becomes 0V at time t12. The period from time t11 to time t12 is, for example, several μsec. The period from time t11 to time t12 is shorter than the time for the output of the output circuit 2 to switch from 0V to the voltage VDD. Therefore, the output circuit 2 maintains an output of 0V. The voltage VOUT is maintained at 0V, so the switch SW1 also remains in the on state during the period from time t11 to time t12.

[0044] At time t13, the device at the previous stage connected to the terminal TEN outputs the voltage VDD as an H level, and the voltage VEN becomes the voltage VDD. After time t13, the voltage VEN is maintained at the voltage VDD. The voltage VEN is higher than 1 / 2 of the voltage VDD, so at time t13, the output circuit 2 starts the operation of outputting the voltage VDD. During the period from time t13 to time t15, the voltage VOUT rises from 0V to the voltage VDD in a state where the conversion rate is controlled by the output circuit 2. In addition, at time t13, the voltage VOUT is lower than the voltage VREF1, so the switch SW1 remains in the on state.

[0045] At time t14, the voltage VOUT becomes larger than the voltage VREF1, and the switch SW1 changes from the on state to the off state. After time t14, the switch SW1 remains in the off state. When the switch SW1 is in the off state, the power consumed by the pull-down circuit 3 is reduced. Specifically, the power consumed by the resistor R1 is no longer consumed. In addition, the period from time t13 to time t14 is the time required for the voltage VOUT to rise from 0V to the final voltage, that is, 1 / 2 of the voltage VDD, and is therefore more than 30μsec.

[0046] At time t15, voltage VOUT reaches voltage VDD, and the rise of voltage VOUT stops. After time t15, voltage VOUT is maintained at voltage VDD.

[0047] <1-3>Effect

[0048] According to the semiconductor device 1 according to the first embodiment described above, it is possible to suppress malfunctions caused by noise and to suppress power consumption. Next, the effects of the semiconductor device 1 according to the first embodiment will be described in detail.

[0049] The pull-down circuit stabilizes the voltage of the node connected to the pull-down circuit and suppresses the disturbance of the logic level of the node due to interference such as noise. However, if an H-level signal is applied to the node connected to the pull-down circuit, current flows in the pull-down circuit and power is consumed. It is preferable to cut off the pull-down circuit from the node while the node connected to the pull-down circuit is continuously driven to the H level to suppress power consumption.

[0050] In addition, if the voltage of a node connected to a pull-down circuit rises momentarily due to noise, it may be driven to an H level by a circuit at a previous stage and rise. If the pull-down circuit is disconnected when the voltage of a node rises momentarily due to noise, the voltage of the node becomes unstable and the circuit may malfunction. It is preferable to maintain the connection of the pull-down circuit to the node when the voltage of the node rises momentarily due to noise, and disconnect the pull-down circuit from the node when the voltage of the node is driven to an H level by a circuit at a previous stage.

[0051] The semiconductor device 1 involved in the first embodiment includes: a terminal TEN, which is connected to the node N1 and a control signal is input from the outside; an output circuit 2, which is connected to the node N1 and switches between a first state in which the voltage VDD is not output to the node N2 and a second state in which the voltage VDD is output to the node N2 based on the logic level of the node N1, and controls the conversion rate of the output voltage when switching from the first state to the second state; and a pull-down circuit 3, which includes a switch SW1 having one end connected to the node N1 and the other end to which the ground voltage GND is applied, and the switch SW1 is controlled based on the voltage of the node N2.

[0052] The output circuit 2 can control the conversion rate of the output voltage so that even if the voltage of the node N1 rises momentarily due to noise, the voltage of the node N2 does not rise. The voltage of the node N2 does not change, so even if the voltage of the node N1 rises momentarily due to noise, the pull-down circuit 3 maintains the switch SW1 in the on state. That is, the pull-down circuit 3 maintains the state in which the node N1 is pulled down.

[0053] In this regard, when the node N1 is driven to the voltage VDD by the circuit of the previous stage, the output circuit 2 is switched to the on state, and the voltage of the node N2 rises. Furthermore, if the voltage of the node N2 becomes higher than the voltage VREF1, the pull-down circuit 3 sets the switch SW1 to the off state. That is, the pull-down circuit 3 sets the node N1 to a state where it is not pulled down.

[0054] As described above, the semiconductor device 1 according to the first embodiment maintains the connection of the pull-down circuit 3 when the voltage rises momentarily due to noise, and disconnects the pull-down circuit 3 when the output circuit 2 is operated by a control signal and the output voltage exceeds a threshold value. Thus, the semiconductor device 1 according to the first embodiment can suppress malfunctions due to noise and can suppress power consumption.

[0055] In addition, the semiconductor device 1 according to the first embodiment cuts off the pull-down circuit 3 when the output circuit 2 starts operating and the output voltage exceeds the threshold value after the control signal is applied. That is, the pull-down circuit 3 is cut off after the control signal becomes H level and the output of the output circuit 2 exceeds the threshold value. This waiting time prevents the pull-down circuit 3 from being cut off when a momentary voltage rise occurs.

[0056] For example, consider forming a circuit that uses a low-pass filter, waits for a certain period of time after the control signal becomes H level, and then cuts off the pull-down circuit 3. In this case, an area is required on the chip to form the low-pass filter. In addition, it is also considered that the standby time may vary due to manufacturing deviations of the elements that constitute the low-pass filter. In this regard, in the semiconductor device 1 involved in the first embodiment, the pull-down circuit 3 generates a standby time by monitoring the output of the output circuit 2. Therefore, in the semiconductor device 1 involved in the first embodiment, an area for forming a filter is not required, and the standby time will not vary.

[0057] In addition, the semiconductor device 1 according to the first embodiment disconnects the pull-down circuit 3 after the output circuit 2 starts operating and the output exceeds the voltage VREF1. That is, the pull-down circuit 3 is disconnected at the timing when the output of the output circuit 2 exceeds the threshold, not before the output circuit 2 starts operating or after the output of the output circuit 2 reaches the voltage VDD. As described above, the semiconductor device 1 according to the first embodiment can set the standby time that matches the operation timing of the circuit.

[0058] <1-4> Modifications

[0059] In the first embodiment, the control circuit 4 of the pull-down circuit 3 includes the comparator 40 and the voltage source 41. The structure of the control circuit 4 is not limited to this. For example, the control circuit 4 may also be composed of an inverter. In addition, the switch SW1 of the pull-down circuit 3 may also be composed of a transistor. Figure 4This is a block diagram showing a specific example of the structure of an output circuit and a pull-down circuit involved in the first variant of the first embodiment. The semiconductor device 1a involved in the first variant of the first embodiment is different from the semiconductor device 1 involved in the first embodiment in that the switch SW1 of the pull-down circuit 3 is composed of a transistor MN2 and the control circuit 4 is composed of an inverter 42.

[0060] The pull-down circuit 3a includes a resistor R1, a transistor MN2, and a control circuit 4a. The control circuit 4a includes an inverter 42. One end of the resistor R1 is connected to the node N1. The other end of the resistor R1 is connected to the drain of the transistor MN2. The source of the transistor MN2 is grounded. The input end of the inverter 42 is connected to the node N2. The output end of the inverter 42 is connected to the gate of the transistor MN2. The inverter 42 inverts the logic level of the node N2 and outputs the inverted logic level to the gate of the transistor MN2. The voltage VDD is applied to the positive power supply end of the inverter. The negative power supply end of the inverter is grounded.

[0061] The inverter 42 is used as a comparator, that is, it compares 1 / 2 of the applied power supply voltage with the input signal and outputs the magnitude relationship as an H level or an L level. The transistor MN2 is used as a switch that is turned off when an L level is applied to the gate and turned on when an H level is applied to the gate.

[0062] Even when the pull-down circuit 3 is configured as described above, the same effects as those of the semiconductor device 1 according to the first embodiment can be obtained.

[0063] <2> Second Embodiment

[0064] The structure of the semiconductor device according to the second embodiment is different from that of the semiconductor device according to the first embodiment in that the output circuit 2 is replaced by an output circuit 2a, and the pull-down circuit 3 is replaced by a pull-down circuit 3b. The differences between the semiconductor device 1b according to the second embodiment and the first embodiment will be described below.

[0065] <2-1>Structure

[0066] Figure 5 1 is a circuit diagram showing an example of the structure of a semiconductor device 1b according to the second embodiment. In the semiconductor device 1b according to the second embodiment, the output circuit 2 of the semiconductor device 1 described in the first embodiment is replaced by an output circuit 2a, and the pull-down circuit 3 is replaced by a pull-down circuit 3b.

[0067] The semiconductor device 1b according to the second embodiment is a linear regulator having a slew rate control function and supplying power to a load. More specifically, the semiconductor device 1b according to the second embodiment is a low saturation linear regulator, also called LDO (Low Dropout).

[0068] The output circuit 2a is a circuit that realizes the function of a linear regulator as the semiconductor device 1b. The voltage VDD and the ground voltage GND are applied to the output circuit 2a as the power supply voltage. The output circuit 2a is connected to the nodes N1 and N2 respectively. The output circuit 2a switches between the on state (second state) in which the voltage VLD is output to the node N2 and the off state (first state) in which the voltage VLD is not output to the node N2 according to the logic level of the node N1. The voltage VLD is a voltage lower than the voltage VDD and higher than the ground voltage GND. Specifically, the output circuit 2a becomes an off state when the logic level of the node N1 is an L level, and becomes an on state when the logic level of the node N1 is an H level. The output circuit 2a has a conversion rate control function. That is, when the output circuit 2a switches from the off state to the on state, the rising speed of the voltage that switches the output voltage from 0V (a state in which the voltage is not output) to the voltage VLD is controlled. More specifically, the output circuit 2a is configured so that, for example, 30 μsec or more is required for the voltage to reach 1 / 2 of the final voltage from 0 V, that is, for the voltage to reach 1 / 2 of the voltage VLD from 0 V.

[0069] The pull-down circuit 3b pulls down the node N1. The pull-down circuit 3b switches between an on state in which the node N1 is pulled down and an off state in which the node N1 is not pulled down, based on the voltage of the node N2. The pull-down circuit 3b includes a resistor R1, a switch SW1, and a control circuit 4b. The resistor R1 and the switch SW1 are connected in series. Figure 5 In the example shown, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and the other end of the switch SW1 is grounded. In other words, one end of the switch SW1 is connected to the node N1 via the resistor R1, and the other end of the switch SW1 is applied with the ground voltage GND. The control circuit 4b controls the switch SW1 based on the voltage of the node N2. Specifically, the control circuit 4b turns off the switch SW1 when it is detected that the output circuit 2a outputs a voltage above a preset threshold to the node N2. The control circuit 4b turns on the switch SW1 when it is detected that the output circuit 2a does not output a voltage above the threshold to the node N2.

[0070] Next, refer to Figure 5 A specific example of the structure of the output circuit 2a is described. Figure 5As shown, the output circuit 2a involved in the second embodiment includes transistors MN3 to MN8, transistors MP3 to MP9, current sources CS2 to CS5, resistors R2 and R3, capacitor 21 and voltage source 22. Transistors MN3 to MN8 are N-channel MOSFETs. Transistors MP3 to MP9 are P-channel MOSFETs. Voltage source 22 outputs voltage VREF2. Voltage VREF2 is a voltage higher than ground voltage GND and lower than voltage VDD.

[0071] The voltage VDD is applied to the source of the transistor MP3. The gate of the transistor MP3 is connected to the node N1. The gate of the transistor MN3 is connected to the node N1. The current source CS2 is connected to the source of the transistor MN3. The current source CS2 is configured to allow current to flow from the source of the transistor MN3 toward the ground voltage GND. The drain of the transistor MP3, the drain of the transistor MN3, the gate of the transistor MP4, and the gate of the transistor MN4 are connected. The current source CS3 is connected to the source of the transistor MP4. The current source CS3 is configured to allow current to flow from the voltage VDD toward the source of the transistor MP4. The source of the transistor MN4 is grounded. The drain of the transistor MP4, the drain of the transistor MN4, the gate of the transistor MP5, and one electrode of the capacitor 21 are connected. The other electrode of the capacitor 21 is grounded. The current source CS4 is connected to the source of the transistor MP5. The current source CS4 is configured to allow current to flow from the voltage VDD toward the source of the transistor MP5.

[0072] The source of transistor MN5 is grounded. The gate of transistor MN5 is connected to node N1. Current source CS5 is connected to the drain of transistor MN5. The source of transistor MN6 is grounded. The gate of transistor MN6 is connected to node N1. The source of transistor MN7, the source of transistor MN8 and current source CS5 are connected. Current source CS5 is configured to allow current to flow from the source of transistor MN7 and the source of transistor MN8 toward the drain of transistor MN5. The positive output terminal of voltage source 22 is connected to the gate of transistor MN8. The negative output terminal of voltage source 22 is connected to the drain of transistor MN6. The drain of transistor MN7, the gate of transistor MP6, the drain of transistor MP6 and the gate of transistor MP7 are connected. Voltage VDD is applied to the source of transistor MP6. Voltage VDD is applied to the source of transistor MP7. Voltage VDD is applied to the source of transistor MP8. The gate of transistor MP8 is connected to node N1. Voltage VDD is applied to the source of transistor MP9. The drain of transistor MP9 is connected to node N2. The drain of transistor MP5, the drain of transistor MN8, the drain of transistor MP7, the drain of transistor MP8 and the gate of transistor MP9 are connected. One end of resistor R2 is connected to node N2. The other end of resistor R2, one end of resistor R3 and the gate of transistor MN7 are connected. The other end of resistor R3 is grounded.

[0073] The output circuit 2a controls the gate voltage of the transistor MP9 to generate the voltage VLD according to the voltage VDD and outputs it to the node N2. In more detail, the transistors MN7 and MN8, the transistors MP6 and MP7, and the current source CS5 constitute a differential amplifier circuit. The differential amplifier circuit controls the gate voltage of the transistor MP9 so that the value after the voltage of the node N2 is divided by the resistors R2 and R3 is equal to the voltage VREF2 of the voltage source 22. The transistors MN5 and MN6 are turned on when the voltage of the node N1 is at an H level, and the differential amplifier circuit is activated. When the voltage of the node N1 is at an L level, they are turned off, thereby invalidating the differential amplifier circuit. The transistor MP8 is turned off when the voltage of the node N1 is at an H level and does not function. When the voltage of the node N1 is at an L level, it is turned on and the voltage of the gate of the transistor MP9 is fixed to the voltage VDD. That is, the transistor MP9 is turned off.

[0074] The transistors MN3 and MN4, the transistors MP3 to MP5, the current sources CS2 to CS4, and the capacitor 21 control the conversion rate of the output voltage of the output circuit 2a. More specifically, the current sources CS2 and CS3 and the capacitor 21 control the length of time for the gate of the transistor MP5 to switch from the L level to the H level when the node N1 switches from the L level to the H level. Thus, when the node N1 switches from the L level to the H level, the current injection to the gate of the transistor MP9 formed by the current source CS4 and the transistor MP5 continues for a period of time, and the change of the gate voltage of the transistor MP9 slows down. Thus, the output circuit 2a involved in the second embodiment controls the conversion rate of the output voltage when switching from the off state to the on state.

[0075] Next, refer to Figure 5 The structure of the control circuit 4b included in the pull-down circuit 3b is described. Figure 5 As shown, the control circuit 4b involved in the second embodiment includes a comparator 40 and a voltage source 41a. The voltage source 41a outputs a voltage VREF3. The voltage VREF3 is a voltage higher than the ground voltage GND and lower than the voltage VLD. The voltage VREF3 is, for example, 1 / 2 of the voltage VLD. The positive output terminal of the voltage source 41a is connected to the non-inverting input terminal of the comparator 40. The negative output terminal of the voltage source 41a is grounded.

[0076] The inverting input terminal of the comparator 40 is connected to the node N2. The output terminal of the comparator 40 is connected to the switch SW1. The switch SW1 is controlled based on the output of the comparator 40. More specifically, when the output of the comparator 40 is at an H level, the switch SW1 is turned on. When the output of the comparator 40 is at an L level, the switch SW1 is turned off.

[0077] <2-2>Action

[0078] The operation of the semiconductor device 1 b according to the second embodiment will be described. Figure 6 2 is a timing chart showing an operation example of the semiconductor device 1 b according to the second embodiment. Figure 6 , there are shown a case where the operation is performed when noise is applied to the terminal TEN, and a case where an H-level signal is applied to the terminal TEN and the operation of the semiconductor device 1 b is switched.

[0079] exist Figure 6 In the state where the state where the L level is applied to the terminal TEN by the device at the previous stage is switched to the high impedance state, the timing diagram starts. In this state, the voltage VEN is 0V, the voltage VOUT is 0V, and the switch SW1 is in the on state. The switch SW1 is in the on state, so the node N1 is pulled down to 0V by the pull-down circuit 3b. The voltage of the node N1 is 0V, that is, the L level, so the output circuit 2a becomes the off state, and the voltage VOUT becomes 0V.

[0080] At time t21, noise is applied to terminal TEN, and voltage VEN rises sharply. For example, the peak value of voltage VEN exceeds 1 / 2 of voltage VDD. Then, voltage VEN decreases and becomes 0V at time t22. The period from time t21 to time t22 is, for example, several μsec. The period from time t21 to time t22 is shorter than the time for the output of output circuit 2a to switch from 0V to voltage VLD. Therefore, output circuit 2a maintains an output of 0V. Voltage VOUT is maintained at 0V, so switch SW1 also remains in an on state during the period from time t21 to time t22.

[0081] During the period from time t22 to time t23 , the situation does not change, so the voltage VEN is maintained at 0 V, the voltage VOUT is maintained at 0 V, and the switch SW1 is maintained in the on state.

[0082] At time t23, the device at the previous stage connected to the terminal TEN outputs the voltage VDD as an H level, and the voltage VEN becomes the voltage VDD. After time t23, the voltage VEN is maintained at the voltage VDD. The voltage VEN becomes higher than 1 / 2 of the voltage VDD, so at time t23, the output circuit 2a starts the operation of outputting the voltage VLD. During the period from time t23 to time t25, the voltage VOUT rises from 0V to the voltage VLD in a state where the conversion rate is controlled by the output circuit 2a. In addition, at time t23, the voltage VOUT is lower than the voltage VREF3, so the switch SW1 remains in the on state.

[0083] At time t24, the voltage VOUT becomes larger than the voltage VREF3, and the switch SW1 changes from the on state to the off state. After time t24, the switch SW1 remains in the off state. The switch SW1 becomes in the off state, thereby reducing the power consumed by the pull-down circuit 3b. Specifically, the power consumed by the resistor R1 is no longer consumed. In addition, the period from time t23 to time t24 is the time required for the voltage VOUT to rise from 0V to the final voltage, that is, 1 / 2 of the voltage VLD, and is therefore more than 30μsec.

[0084] At time t25, voltage VOUT reaches voltage VLD, and the rise of voltage VOUT stops. After time t25, voltage VOUT is maintained at voltage VLD.

[0085] <2-3>Effect

[0086] According to the semiconductor device 1b according to the second embodiment described above, malfunction due to noise can be suppressed and power consumption can be suppressed, similarly to the semiconductor device 1 according to the first embodiment. Next, the effects of the semiconductor device 1b according to the second embodiment will be described in detail.

[0087] The semiconductor device 1b according to the second embodiment controls the conversion rate of the output voltage of the output circuit 2a, similarly to the semiconductor device 1 according to the first embodiment. Therefore, even if the voltage of the node N1 rises momentarily due to noise, the pull-down circuit 3b maintains the state in which the node N1 is pulled down. In addition, if an H-level control signal is applied to the node N1, and the output circuit 2a makes the voltage of the node N2 higher than the threshold, the pull-down circuit 3b sets the switch SW1 to the disconnected state, and the pull-down circuit 3b sets the node N1 to the state in which the node N1 is not pulled down. As a result, the semiconductor device 1b according to the second embodiment can suppress malfunctions caused by noise and suppress power consumption.

[0088] In addition, the semiconductor device 1b according to the second embodiment, like the semiconductor device 1 according to the first embodiment, waits for a period from when the control signal becomes H level until the output of the output circuit 2a actually exceeds the threshold value, and then cuts off the pull-down circuit 3b. That is, the pull-down circuit 3b monitors the output of the output circuit 2a, thereby generating a wait time. Thus, the wait time can be set to match the operation timing of the circuit.

[0089] <3> Third Embodiment

[0090] The structure of the semiconductor device according to the third embodiment is different from that of the semiconductor device according to the first embodiment in that the output circuit 2 is replaced by an output circuit 2b, and the pull-down circuit 3 is replaced by a pull-down circuit 3c. The differences between the semiconductor device 1c according to the third embodiment and the first embodiment will be described below.

[0091] <3-1>Structure

[0092] Figure 7 This is a block diagram showing an example of the structure of a semiconductor device 1c according to the third embodiment. In the semiconductor device 1c according to the third embodiment, the output circuit 2 of the semiconductor device 1 described in the first embodiment is replaced by an output circuit 2b, and the pull-down circuit 3 is replaced by a pull-down circuit 3c.

[0093] The semiconductor device 1 c according to the third embodiment is a logic IC that outputs a clock signal.

[0094] The output circuit 2b is a circuit that realizes the function of a logic IC as the semiconductor device 1c. The voltage VDD as the power supply voltage and the ground voltage GND are applied to the output circuit 2b. The output circuit 2b is connected to the nodes N1 and N2, respectively. The output circuit 2b switches between an on state (second state) in which the signal CLK as the clock signal is output to the node N2 and an off state (first state) in which the signal CLK is not output to the node N2 according to the logic level of the node N1. Specifically, the output circuit 2b becomes an off state when the logic level of the node N1 is an L level, and becomes an on state when the logic level of the node N1 is an H level.

[0095] The pull-down circuit 3c pulls down the node N1. The pull-down circuit 3c switches between an on state in which the node N1 is pulled down and an off state in which the node N1 is not pulled down based on a signal applied to the node N2. The pull-down circuit 3c includes a resistor R1, a switch SW1, and a control circuit 4c. The resistor R1 and the switch SW1 are connected in series. For example, one end of the resistor R1 is connected to the node N1, the other end of the resistor R1 is connected to one end of the switch SW1, and the other end of the switch SW1 is grounded. In other words, one end of the switch SW1 is connected to the node N1 via the resistor R1, and the other end of the switch SW1 is applied with a ground voltage GND. The control circuit 4c receives the signal CLK applied to the node N2 and counts the toggle of the signal CLK. The control circuit 4c sets the switch SW1 to off when the count value of the trigger exceeds a predetermined number of determinations, such as 10 times. In addition, the count value is reset at a certain period. When the count value of the trigger does not exceed the preset number of determination times before the count value completes the cycle and is reset, the control circuit 4 c turns on the switch SW1 .

[0096] <3-2>Action

[0097] The operation of the semiconductor device 1 c according to the third embodiment will be described. Figure 8 2 is a timing chart showing an operation example of the semiconductor device 1c according to the third embodiment. Figure 8 , there are shown a case where the operation is performed when noise is applied to the terminal TEN, and a case where an H-level signal is applied to the terminal TEN and the operation of the semiconductor device 1 c is switched.

[0098] exist Figure 8 In the state where the state where the L level is applied to the terminal TEN by the device at the previous stage is switched to the high impedance state, the timing diagram starts. In this state, the voltage VEN is 0V, the voltage VOUT is 0V, and the switch SW1 is in the on state. The switch SW1 is in the on state, so the node N1 is pulled down to 0V by the pull-down circuit 3. The voltage of the node N1 is 0V, that is, the L level, so the output circuit 2b is in the off state, and the voltage VOUT becomes 0V.

[0099] At time t31, noise is applied to the terminal TEN, and the voltage VEN rises sharply. For example, the peak value of the voltage VEN exceeds 1 / 2 of the voltage VDD. Then, the voltage VEN decreases and becomes 0V at time t32. The period from time t31 to time t32 is, for example, several μsec. The period from time t31 to time t32 is shorter than the time required for the control circuit 4c to count the triggering of the signal CLK from 0 times to the determination number. Therefore, the switch SW1 remains in the on state during the period from time t31 to time t32. During the period from time t31 to time t32, the output circuit 2b can respond to the noise and output the signal CLK that is triggered twice, for example, but Figure 8 The example shown maintains the output at 0V.

[0100] During the period from time t32 to time t33 , the situation does not change, so the voltage VEN is maintained at 0 V, the voltage VOUT is maintained at 0 V, and the switch SW1 is maintained in the on state.

[0101] At time t33, the device at the previous stage connected to the terminal TEN outputs the voltage VDD as an H level, and the voltage VEN becomes the voltage VDD. After time t33, the voltage VEN is maintained at the voltage VDD. The voltage VEN is higher than 1 / 2 of the voltage VDD, so at time t33, the output circuit 2b starts outputting the signal CLK. In addition, at time t33, the control circuit 4c cannot count the toggle of the clock signal, so the switch SW1 remains in the on state.

[0102] At time t34, the number of triggers of the signal CLK counted by the control circuit 4c exceeds the determination number, so the switch SW1 changes from the on state to the off state. The switch SW1 becomes the off state, thereby reducing the power consumed by the pull-down circuit 3c. Specifically, the power consumed by the resistor R1 is no longer consumed. After time t34, the output circuit 2b continues to output the signal CLK, so the count value of the control circuit 4c exceeds the determination number, and the switch SW1 is maintained in the off state.

[0103] <3-3>Effect

[0104] According to the semiconductor device 1c according to the third embodiment described above, it is possible to suppress malfunctions caused by noise and to suppress power consumption similarly to the semiconductor device 1 according to the first embodiment. Next, the effects of the semiconductor device 1c according to the third embodiment will be described in detail.

[0105] The semiconductor device 1c according to the third embodiment includes a control circuit 4c that counts the triggering of the clock signal. After the control signal becomes H level and the output circuit 2b outputs the signal CLK, the semiconductor device 1c according to the third embodiment waits until the count value of the triggering exceeds the number of determinations, and then turns on the pull-down circuit 3c. That is, the pull-down circuit 3c monitors the output of the output circuit 2b, thereby generating a standby time. By appropriately setting the number of determinations, the standby time that matches the operation timing of the circuit can be set.

[0106] The semiconductor device 1c according to the third embodiment maintains the connection of the pull-down circuit 3c during the instantaneous voltage rise caused by noise by this standby time. In contrast, when the control signal is applied and the output circuit 2b continues to operate for a longer time than the count value exceeds the determination number, the connection of the pull-down circuit 3c is disconnected. Thus, the semiconductor device 1c according to the third embodiment can suppress malfunction caused by noise and suppress power consumption.

[0107] <3-4> Modification examples

[0108] In the third embodiment, the case where the control circuit 4c of the pull-down circuit 3c counts the triggering of the clock signal is described as an example. The structure of the control circuit 4c is not limited to this. For example, the control circuit 4c can process the clock signal through a low-pass filter and determine the processed signal through a comparator, thereby determining the presence or absence of the clock signal. Fig. 9 This is a block diagram showing a specific example of the structure of a semiconductor device according to the first variant of the third embodiment. The semiconductor device 1d according to the first variant of the third embodiment is different from the semiconductor device 1c according to the third embodiment in that the pull-down circuit 3c is replaced by a pull-down circuit 3d including a control circuit 4d instead of a control circuit 4c.

[0109] The pull-down circuit 3d includes a resistor R1, a switch SW1, and a control circuit 4d. One end of the resistor R1 is connected to the node N1. The other end of the resistor R1 is connected to one end of the switch SW1. The other end of the switch SW1 is grounded. The control circuit 4d includes a comparator 40, a voltage source 41b, a resistor R4, and a capacitor 43. One end of the resistor R4 is connected to the node N2. The other end of the resistor R2 is connected to one electrode of the capacitor 43 and the inverting input end of the comparator 40. The other electrode of the capacitor 43 is grounded. The positive output end of the voltage source 41b is connected to the non-inverting input end of the comparator 40. The negative output end of the voltage source 41b is grounded. The voltage source 41b outputs a voltage VREF4. The voltage VREF4 is lower than the voltage VDD and higher than the ground voltage GND. For example, the voltage VREF4 is smaller than 1 / 2 of the voltage VDD. The output end of the comparator 40 is connected to the switch SW1. The switch SW1 is turned on when the output of the comparator 40 is at an H level, and is turned off when the output of the comparator 40 is at an L level.

[0110] The resistor R4 and the capacitor 43 form a low-pass filter. The input end of the low-pass filter is one end of the resistor R4, and the output end is the other end of the resistor R4 and one electrode of the capacitor 43. If the signal CLK output by the output circuit 2c passes through the filter, it is converted into a DC voltage with a height of approximately 1 / 2 of the amplitude of the signal CLK. The DC voltage and the voltage VREF4 are compared by the comparator 40, thereby determining whether the signal CLK is output.

[0111] Even when the pull-down circuit 3d is configured as described above, the same effects as those of the semiconductor device 1c according to the third embodiment can be obtained.

[0112] <4> Fourth embodiment

[0113] The structure of the semiconductor device according to the fourth embodiment is different from that of the semiconductor device according to the first embodiment in that the output circuit 2 is replaced by an output circuit 2c, and the pull-down circuit 3 is replaced by a pull-up circuit 5. Next, the differences between the semiconductor device 1e according to the fourth embodiment and the first embodiment will be described.

[0114] <4-1>Structure

[0115] Fig.10 This is a block diagram showing an example of the structure of a semiconductor device 1e according to the fourth embodiment. In the semiconductor device 1e according to the fourth embodiment, the output circuit 2 of the semiconductor device 1 described in the first embodiment is replaced by an output circuit 2c, and the pull-down circuit 3 is replaced by a pull-up circuit 5.

[0116] The semiconductor device 1 e according to the fourth embodiment is a load switch having a slew rate control function and supplying electric power to a load.

[0117] The semiconductor device 1e includes terminals TEN and TOUT, an output circuit 2c, and a pull-up circuit 5. Terminal TEN is a control signal input terminal of the semiconductor device 1e. Terminal TEN is connected to node N1. A control signal is applied to terminal TEN from a previous circuit (not shown) provided outside the semiconductor device 1e. Terminal TOUT is an output terminal of the semiconductor device 1e. Power is supplied to the outside of the semiconductor device 1e from terminal TOUT. Terminal TOUT is connected to node N2.

[0118] The output circuit 2c is a circuit that realizes the function of a load switch as a semiconductor device 1e. The voltage VDD and the ground voltage GND are applied to the output circuit 2c as the power supply voltage. The output circuit 2c is connected to the nodes N1 and N2 respectively. The output circuit 2c switches between the on state (second state) in which the voltage VDD is output to the node N2 and the off state (first state) in which the voltage VDD is not output to the node N2 according to the logic level of the node N1. Specifically, the output circuit 2c becomes the on state when the logic level of the node N1 is the L level, and becomes the off state when the logic level of the node N1 is the H level. The output circuit 2c has a conversion rate control function. That is, when the output circuit 2c switches from the off state to the on state, the rising speed of the voltage that switches the output voltage from 0V (the state in which the voltage is not output) to the voltage VDD is controlled. More specifically, the output circuit 2 c is configured so that, for example, 30 μsec or more is required for the voltage to reach 1 / 2 of the final voltage from 0 V, that is, for the voltage to reach 1 / 2 of the voltage VDD from 0 V.

[0119] The pull-up circuit 5 pulls up the node N1. Specifically, the pull-up circuit 5 switches between an on state in which the node N1 is pulled up and an off state in which the node N1 is not pulled up, based on the voltage of the node N2. The pull-up circuit 5 includes a resistor R5, a switch SW2, and a control circuit 6. The resistor R5 and the switch SW2 are connected in series. Fig.10 In the example shown, one end of the resistor R1 is connected to the node N1, the other end of the resistor R5 is connected to one end of the switch SW2, and the voltage VDD is applied to the other end of the switch SW2. In other words, one end of the switch SW2 is connected to the node N1 via the resistor R5, and the voltage VDD as the power supply voltage is applied to the other end of the switch SW2. The control circuit 6 controls the switch SW2 based on the voltage of the node N2. Specifically, the control circuit 6 turns off the switch SW2 when it is detected that the output circuit 2c outputs a voltage above a preset threshold to the node N2. The control circuit 6 turns on the switch SW2 when it is detected that the output circuit 2c does not output a voltage above the threshold to the node N2.

[0120] Fig.11 2 is a block diagram showing a specific example of the configuration of the output circuit 2c and the control circuit 6 according to the fourth embodiment. Fig.11 As shown, the output circuit 2c involved in the fourth embodiment replaces the non-inverting logic circuit 20 with an inverting logic circuit 20a relative to the output circuit 2 involved in the first embodiment. The voltage VDD and the ground voltage GND are applied to the inverting logic circuit 20a. The input signal terminal of the inverting logic circuit 20a is connected to the node N1, and the signal output terminal is connected to the gate of each of the transistors MP1 and MN1. The inverting logic circuit 20a detects the logic level of the node N1, inverts the detected logic level, and applies a voltage based on the inverted logic level to each of the gates of the transistors MP1 and MN1. For example, when an H-level voltage is applied to the node N1, the inverting logic circuit 20a outputs an L-level voltage. In addition, for example, when an L-level voltage is applied to the node N1, the inverting logic circuit 20a outputs an H-level voltage. The structure of the other output circuits 2c is the same as that of the output circuit 2 involved in the first embodiment.

[0121] Next, refer to Fig.11 , the structure of the control circuit 6 included in the pull-up circuit 5 is described. Fig.11 As shown, the control circuit 6 involved in the fourth embodiment includes a comparator 60 and a voltage source 61. The voltage source 61 outputs a voltage VREF5. The voltage VREF5 is a voltage higher than the ground voltage GND and lower than the voltage VDD. The voltage VREF5 is, for example, 1 / 2 of the voltage VDD. The positive output terminal of the voltage source 61 is connected to the non-inverting input terminal of the comparator 60. The negative output terminal of the voltage source 61 is grounded.

[0122] The inverting input terminal of the comparator 60 is connected to the node N2. The output terminal of the comparator 60 is connected to the switch SW2. The switch SW2 is controlled based on the output of the comparator 60. More specifically, when the output of the comparator 60 is at an H level, the switch SW2 is turned on. When the output of the comparator 60 is at an L level, the switch SW2 is turned off.

[0123] <4-2>Action

[0124] The operation of the semiconductor device 1 e according to the fourth embodiment will be described. Fig.12 is a timing chart showing an operation example of the semiconductor device 1e according to the fourth embodiment. Fig.12 , there are shown the operation when noise is applied to the terminal TEN, and the operation of the semiconductor device 1e is switched when an L-level signal is applied to the terminal TEN. Fig.12, the voltage VEN, the voltage VOUT, and the state of the switch SW2 are shown in order from the top.

[0125] exist Fig.12 In the state where the H level is applied to the terminal TEN by the device at the previous stage, the timing diagram starts when the state is switched to the high impedance state. In this state, the voltage VEN is the voltage VDD, the voltage VOUT is 0V, and the switch SW2 is in the on state. The switch SW2 is in the on state, so the node N1 is pulled up to the voltage VDD by the pull-up circuit 5. The voltage of the node N1 is the voltage VDD, that is, the H level, so the output circuit 2c is in the off state, and the voltage VOUT becomes 0V.

[0126] At time t41, noise is applied to the terminal TEN, and the voltage VEN drops sharply. For example, the peak value of the drop of the voltage VEN is lower than 1 / 2 of the voltage VDD. Then, the voltage VEN rises and reaches the voltage VDD at time t42. The period from time t41 to time t42 is, for example, several μsec. The period from time t41 to time t42 is shorter than the time for the output of the output circuit 2c to switch from 0V to the voltage VDD. Therefore, the output circuit 2c maintains an output of 0V. The voltage VOUT is maintained at 0V, so the switch SW2 also remains in the on state during the period from time t41 to time t42.

[0127] During the period from time t42 to time t43 , the situation does not change, so the voltage VEN is maintained at the voltage VDD, the voltage VOUT is maintained at 0 V, and the switch SW2 is maintained in the on state.

[0128] At time t43, the device at the previous stage connected to the terminal TEN outputs 0V as an L level, and the voltage VEN becomes 0V. After time t43, the voltage VEN is maintained at 0V. The voltage VEN becomes lower than 1 / 2 of the voltage VDD, so at time t43, the output circuit 2c starts the operation of outputting the voltage VDD. During the period from time t43 to time t45, the voltage VOUT rises from 0V to the voltage VDD in a state where the conversion rate is controlled by the output circuit 2c. In addition, at time t43, the voltage VOUT is lower than the voltage VREF5, so the switch SW2 remains in the on state.

[0129] At time t44, the voltage VOUT becomes greater than the voltage VREF5, and the switch SW2 changes from the on state to the off state. After time t44, the switch SW2 remains in the off state. The switch SW2 becomes in the off state, thereby reducing the power consumed by the pull-up circuit 5. Specifically, the power consumed by the resistor R5 is no longer consumed. In addition, the period from time t43 to time t44 is the time required for the voltage VOUT to rise from 0V to the final voltage, that is, 1 / 2 of the voltage VDD, and is therefore more than 30μsec.

[0130] At time t45, voltage VOUT reaches voltage VDD, and the rise of voltage VOUT stops. After time t45, voltage VOUT is maintained at voltage VDD.

[0131] <4-3>Effect

[0132] According to the semiconductor device 1e according to the fourth embodiment described above, malfunction due to noise can be suppressed and power consumption can be suppressed, similarly to the semiconductor device 1 according to the first embodiment. Next, the effects of the semiconductor device 1e according to the fourth embodiment will be described in detail.

[0133] The semiconductor device 1e according to the fourth embodiment controls the conversion rate of the output voltage of the output circuit 2c, similarly to the semiconductor device 1 according to the first embodiment. Therefore, even if the voltage of the node N1 drops momentarily due to noise, the pull-up circuit 5 maintains the state in which the node N1 is pulled up. In addition, if an L-level control signal is applied to the node N1 and the output circuit 2c makes the voltage of the node N2 higher than the threshold, the pull-up circuit 5 sets the switch SW2 to the off state, and the pull-up circuit 5 sets the node N1 to the state in which the node N1 is not pulled up. As a result, the semiconductor device 1e according to the fourth embodiment can suppress malfunctions caused by noise and suppress power consumption.

[0134] In addition, the semiconductor device 1e according to the fourth embodiment, like the semiconductor device 1 according to the first embodiment, waits for a period from when the control signal becomes L level until the output of the output circuit 2c actually exceeds the threshold value, and then cuts off the pull-up circuit 5. That is, the pull-up circuit 5 monitors the output of the output circuit 2c, thereby generating a waiting time. Thus, the waiting time can be set to match the operation timing of the circuit.

[0135] <5>Other modifications, etc.

[0136] In the above-mentioned embodiments and modified examples, the pull-down circuit and the pull-up circuit include resistors as an example. The pull-down circuit and the pull-up circuit are not limited to this. The pull-down circuit and the pull-up circuit may include a current source instead of a resistor.

[0137] Fig.13 This is a block diagram showing an example of the structure of a semiconductor device according to a second modification of the first embodiment. The semiconductor device 1f according to the second modification of the first embodiment is different from the semiconductor device 1 according to the first embodiment in that the pull-down circuit 3 is replaced by a pull-down circuit 3e.

[0138] The pull-down circuit 3e involved in the second variation of the first embodiment is different from the pull-down circuit 3 involved in the first embodiment in that the resistor R1 is replaced by a current source CS6. The current source CS6 is connected to the node N1. The current source CS6 is connected to one end of the switch SW1. The current source CS6 is configured to allow a current to flow from the node N1 toward one end of the switch SW1. The other structures are the same as the pull-down circuit 3 involved in the first embodiment.

[0139] As described above, even if a current source is used instead of a resistor, the pull-down circuit 3 e according to the second modification of the first embodiment functions in the same manner as the pull-down circuit 3 according to the first embodiment.

[0140] Fig.14 This is a block diagram showing an example of the structure of a semiconductor device according to a first modification of the fourth embodiment. A semiconductor device 1g according to the first modification of the fourth embodiment differs from a semiconductor device 1e according to the fourth embodiment in that the pull-up circuit 5 is replaced by a pull-up circuit 5a.

[0141] The pull-up circuit 5a involved in the first variant of the fourth embodiment is different from the pull-up circuit 5 involved in the fourth embodiment in that the resistor R5 is replaced by a current source CS7. The current source CS7 is connected to the node N1. The current source CS7 is connected to one end of the switch SW2. The current source CS7 is configured to allow a current to flow from one end of the switch SW2 toward the node N1. The other structures are the same as the pull-up circuit 5 involved in the fourth embodiment.

[0142] As described above, even if a current source is used instead of a resistor, the pull-up circuit 5 a according to the first modification of the fourth embodiment functions in the same manner as the pull-up circuit 5 according to the fourth embodiment.

[0143] In the above embodiment, the case where the pull-down circuit includes a switch is described as an example. In the first modified example of the first embodiment, the case where an N-channel transistor is used as a specific example of the switch is illustrated. The structure of the pull-down circuit is not limited to this. For example, the switch SW1 of the pull-down circuit can also be composed of a combination of an N-channel transistor and a P-channel transistor.

[0144] Fig.15 This is a block diagram showing an example of the structure of a semiconductor device according to a third modification of the first embodiment. The semiconductor device 1h according to the third modification of the first embodiment is different from the semiconductor device 1 according to the first embodiment in that the pull-down circuit 3 is replaced by a pull-down circuit 3f.

[0145] The pull-down circuit 3f involved in the third variant of the first embodiment includes a resistor R1, transistors MN9 and MP10, an inverter INV1, and a control circuit 4e. The transistor MN9 is an N-channel transistor. The transistor MP10 is a P-channel transistor. One end of the resistor R1 is connected to the node N1. The other end of the resistor R1, the drain of the transistor MN9, and the source of the transistor MP10 are connected. The source of the transistor MN9 and the drain of the transistor MP10 are grounded. The gate of the transistor MN9 and the input of the inverter INV1 are connected. The output of the inverter INV1 is connected to the gate of the transistor MP10. The input of the control circuit 4e is connected to the node N2. The output of the control circuit 4e is connected to the gate of the transistor MN9 and the input of the inverter INV1. The control circuit 4e controls the voltage of the gate of the transistor MN9 and the input of the inverter INV1 based on the voltage of the node N2. Specifically, the control circuit 4e sets the voltage at the gate of the transistor MN9 and the input terminal of the inverter INV1 to the L level when it is detected that the output circuit 2 outputs a voltage higher than a preset threshold value to the node N2. The control circuit 4e sets the voltage at the gate of the transistor MN9 and the input terminal of the inverter INV1 to the H level when it is detected that the output circuit 2 does not output a voltage higher than the threshold value to the node N2.

[0146] As described above, even if the N-channel transistor MN9 and the P-channel transistor MP10 are used in combination as the switch SW1 , the pull-down circuit 3 f according to the third modification of the first embodiment functions similarly to the pull-down circuit 3 according to the first embodiment.

[0147] In the above embodiment, the pull-up circuit includes a switch as an example. The pull-up circuit is not limited to this. For example, the switch SW2 of the pull-up circuit can be formed using a P-channel transistor, or a combination of an N-channel transistor and a P-channel transistor.

[0148] Fig.16 This is a block diagram showing an example of the structure of a semiconductor device according to the second modification of the fourth embodiment. The semiconductor device 1i according to the second modification of the fourth embodiment is different from the semiconductor device 1e according to the fourth embodiment in that the pull-up circuit 5 is replaced by a pull-up circuit 5b.

[0149] The pull-up circuit 5b involved in the second variant of the fourth embodiment includes a resistor R5, a transistor MP11 and a control circuit 6a. The transistor MP11 is a P-channel transistor. One end of the resistor R5 is connected to the node N1. The other end of the resistor R5 is connected to the drain of the transistor MP11. The voltage VDD is applied to the source of the transistor MP11. The input end of the control circuit 6a is connected to the node N2. The output end of the control circuit 6a is connected to the gate of the transistor MP11. The control circuit 6a controls the voltage of the gate of the transistor MP11 based on the voltage of the node N2. Specifically, the control circuit 6a sets the voltage of the gate of the transistor MP11 to the H level when it is detected that the output circuit 2c outputs a voltage above a preset threshold to the node N2. The control circuit 6a sets the voltage of the gate of the transistor MP11 to the L level when it is detected that the output circuit 2c does not output a voltage above the threshold to the node N2.

[0150] As described above, even if the P-channel transistor MP11 is used as the switch SW2 , the pull-up circuit 5 b according to the second modification of the fourth embodiment functions in the same manner as the pull-up circuit 5 according to the fourth embodiment.

[0151] Fig.17 This is a block diagram showing an example of the structure of a semiconductor device according to the third modification of the fourth embodiment. The semiconductor device 1j according to the third modification of the fourth embodiment is different from the semiconductor device 1e according to the fourth embodiment in that the pull-up circuit 5 is replaced by a pull-up circuit 5c.

[0152] The pull-up circuit 5c involved in the third variant of the fourth embodiment includes a resistor R5, transistors MN10 and MP12, an inverter INV2 and a control circuit 6b. The transistor MN10 is an N-channel transistor. The transistor MP12 is a P-channel transistor. One end of the resistor R5 is connected to the node N1. The other end of the resistor R5, the source of the transistor MN10 and the drain of the transistor MP12 are connected. The voltage VDD is applied to the drain of the transistor MN10 and the source of the transistor MP12. The gate of the transistor MN10 and the input of the inverter INV2 are connected. The output of the inverter INV2 and the gate of the transistor MP12 are connected. The input of the control circuit 6b is connected to the node N2. The output of the control circuit 6b is connected to the gate of the transistor MN10 and the input of the inverter INV2. The control circuit 6b controls the voltage of the gate of the transistor MN10 and the input of the inverter INV2 based on the voltage of the node N2. Specifically, when the control circuit 6b detects that the output circuit 2c outputs a voltage higher than a preset threshold value to the node N2, the control circuit 6b sets the voltage at the gate of the transistor MN10 and the input terminal of the inverter INV2 to the L level. When the control circuit 6b detects that the output circuit 2c does not output a voltage higher than the threshold value to the node N2, the control circuit 6b sets the voltage at the gate of the transistor MN10 and the input terminal of the inverter INV2 to the H level.

[0153] As described above, even if the N-channel transistor MN10 and the P-channel transistor MP12 are used in combination as the switch SW2 , the pull-up circuit 5 c according to the third modification of the fourth embodiment functions similarly to the pull-up circuit 5 according to the fourth embodiment.

[0154] In the above-mentioned embodiments and variations, the semiconductor device including the terminal TOUT is described as an example. The structure of the semiconductor device is not limited to this. The terminal TOUT may not be provided. Specifically, the output of the output circuit may be used only inside the semiconductor device.

[0155] In this specification, "connection" means electrical connection, and does not exclude the case where other elements are passed between them. In addition, regarding "electrical connection", if it can operate in the same way as electrical connection, it can also be passed through an insulator. In addition, in the specification, "on state" means that a voltage greater than the threshold voltage of the transistor is applied to the gate of the corresponding transistor. "Off state" means that a voltage less than the threshold voltage of the transistor is applied to the gate of the corresponding transistor, and does not exclude the case where a small current such as the leakage current of the transistor flows.

[0156] In addition, part or all of the above-mentioned embodiment and the above-mentioned modification examples may be described as the following supplementary notes, but are not limited to the following contents.

[0157] [Note 1]

[0158] A semiconductor device, comprising:

[0159] The first terminal is connected to the first node and receives a control signal from the outside;

[0160] a first circuit connected to the first node, switching between a first state in which the first voltage is not output to the second node and a second state in which the first voltage is output to the second node based on a logic level of the first node, and controlling a conversion rate of the output voltage when switching from the first state to the second state; and

[0161] The second circuit includes a switch having one end connected to the first node and having a second voltage applied to the other end, and the switch is controlled based on the voltage of the second node.

[0162] [Note 2]

[0163] A semiconductor device as described in Supplementary Note 1, wherein:

[0164] The second voltage is a ground voltage,

[0165] The second circuit sets the switch to a non-connected state when the voltage at the second node is higher than a third voltage, and sets the switch to a connected state when the voltage at the second node is lower than the third voltage.

[0166] [Note 3]

[0167] A semiconductor device as described in Supplementary Note 1, wherein:

[0168] The second voltage is a power supply voltage,

[0169] The second circuit sets the switch to a non-connected state when the voltage at the second node is higher than a third voltage, and sets the switch to a connected state when the voltage at the second node is lower than the third voltage.

[0170] [Note 4]

[0171] A semiconductor device as described in Supplementary Note 1, wherein:

[0172] The second voltage is a ground voltage,

[0173] The second circuit further includes an inverter having an input terminal connected to the second node.

[0174] The switch is a first transistor, and the output end of the inverter is connected to the gate of the first transistor.

[0175] [Note 5]

[0176] A semiconductor device as described in any one of Appendixes 1 to 4, wherein:

[0177] The first voltage is equal to a power supply voltage applied to the first circuit.

[0178] [Note 6]

[0179] A semiconductor device as described in any one of Appendixes 1 to 4, wherein:

[0180] The first voltage is lower than a power supply voltage applied to the first circuit.

[0181] [Note 7]

[0182] A semiconductor device, comprising:

[0183] The first terminal is connected to the first node and receives a control signal from the outside;

[0184] a first circuit that switches between a first state in which the first signal is not output to the second node and a second state in which the first signal is output to the second node based on a logic level of the first node; and

[0185] The second circuit includes a switch having one end connected to the first node and having the second voltage applied to the other end, and the switch is controlled based on the first signal applied to the second node.

[0186] [Note 8]

[0187] A semiconductor device as described in Supplementary Note 7, wherein:

[0188] The second circuit counts the number of times the first signal is applied to the second node, and controls the switch based on the counted number of times.

[0189] [Note 9]

[0190] A semiconductor device as described in Supplementary Note 1, wherein:

[0191] The second circuit further includes a low-pass filter having an input terminal connected to the second node, and the switch is controlled based on an output of the low-pass filter.

[0192] [Note 10]

[0193] A semiconductor device as described in any one of Appendixes 1 to 9, wherein:

[0194] The second circuit further includes a resistance element connected in series with the one end of the switch.

[0195] [Note 11]

[0196] A semiconductor device as described in any one of Appendixes 1 to 9, wherein:

[0197] The second circuit further includes a current source connected in series with the one end of the switch.

[0198] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and their equivalents.

[0199] Description of Reference Numerals

[0200] 1…semiconductor device, 2…output circuit, 3…pull-down circuit, 4…control circuit, TEN, TOUT…terminals, R1…resistor, SW1…switch.

Claims

1. A semiconductor device, wherein: have: The first terminal is connected to the first node and receives a control signal from the outside; a first circuit connected to the first node, switching between a first state in which the first voltage is not output to the second node and a second state in which the first voltage is output to the second node based on a logic level of the first node, and controlling a conversion rate of the output voltage when switching from the first state to the second state; as well as The second circuit includes a switch having one end connected to the first node and having a second voltage applied to the other end, and the switch is controlled based on the voltage of the second node.

2. The semiconductor device according to claim 1, wherein: The second voltage is a ground voltage, When the voltage at the second node is higher than a third voltage, the second circuit sets the switch to a non-connected state, and when the voltage at the second node is lower than the third voltage, the second circuit sets the switch to a connected state.

3. The semiconductor device according to claim 1, wherein: The second voltage is a power supply voltage, When the voltage at the second node is higher than a third voltage, the second circuit sets the switch to a non-connected state, and when the voltage at the second node is lower than the third voltage, the second circuit sets the switch to a connected state.

4. The semiconductor device according to claim 1, wherein: The second voltage is a ground voltage, The second circuit further includes an inverter having an input terminal connected to the second node. The switch is a first transistor, and the output end of the inverter is connected to the gate of the first transistor.

5. The semiconductor device according to claim 1, wherein: The first voltage is equal to a power supply voltage applied to the first circuit.

6. The semiconductor device according to claim 1, wherein: The first voltage is lower than a power supply voltage applied to the first circuit.

7. A semiconductor device, wherein: have: The first terminal is connected to the first node and receives a control signal from the outside; a first circuit that switches between a first state in which the first signal is not output to the second node and a second state in which the first signal is output to the second node based on a logic level of the first node; as well as The second circuit includes a switch having one end connected to the first node and having the second voltage applied to the other end, and the switch is controlled based on the first signal applied to the second node.

8. The semiconductor device according to claim 7, wherein: The second circuit counts the number of times the first signal is applied to the second node, and controls the switch based on the counted number of times.

9. The semiconductor device according to claim 7, wherein: The second circuit further includes a low-pass filter having an input terminal connected to the second node, and the switch is controlled based on an output of the low-pass filter.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The second circuit further includes a resistance element connected in series with the one end of the switch.

11. The semiconductor device according to any one of claims 1 to 9, wherein: The second circuit further includes a current source connected in series with the one end of the switch.

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