BUCK circuit with superaudio mode and electronic device

Abstract

The invention provides a BUCK circuit with a superaudio mode and an electronic device, and relates to the technical field of electronic power, a mode control unit in the BUCK circuit is internally provided with a feedback signal end connected with the output end of an inductor and is configured to respond to the superaudio mode triggered by the BUCK circuit, and the feedback signal end is connected with the output end of the inductor. Based on real-time voltage signals VOUT at the two ends of an output capacitor in the BUCK circuit, the voltage detection threshold value of a feedback signal VFB at the feedback signal end is increased by a set proportion, so that fluctuation of the real-time voltage signals VOUT is reduced in the mode that the starting time of a low-side power tube in the superaudio frequency mode is shortened; the duration of the BUCK circuit in the sleep mode between the pulse frequency modulation mode and the superaudio frequency mode is controlled to reach the set threshold time all the time, and the feedback signal VFB is configured to be related to the real-time voltage signal VOUT. The BUCK circuit is switched back and forth between the USM mode and the PFM mode, and stable output can be achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic power technology, and in particular to a BUCK circuit and an electronic device with an ultra-high frequency mode. Background Art

[0002] For a traditional buck chopper circuit (BUCK circuit) with dual working modes of pulse width modulation (PWM) mode and pulse frequency modulation (PFM) mode, after entering the PFM mode at light load, the switching frequency will decrease as the external load becomes smaller until it drops to the lowest frequency (less than 1kHz) at no load, resulting in audible noise (20Hz-20KHz), which needs to be avoided in audio applications.

[0003] Ultra-sound frequency (USM) mode is achieved by limiting the switching frequency above 30KHz. Figure 1 As shown, the problem of audible noise can be solved. The specific structure of the BUCK circuit with USM mode can be found in the records of Chinese patent CN 103701323 B, etc. However, in the existing BUCK circuit, the switching between USM mode and PFM mode has the following problems: in the stage of triggering USM mode, due to the insufficient response speed of the comparator used for feedback signal detection, limited comparator accuracy, and low-side power tube (LSD) shutdown delay, the low-side power tube in USM mode is turned on for a long time, and the output voltage is V OUT When the high-side power tube is turned off, the output voltage V OUT The switching time is not large enough, resulting in the sleep mode duration from USM mode to PFM mode being less than 29 μs. In the case of frequent switching between USM mode and PFM mode, unstable switching frequency is caused. In particular, frequent switching between USM and PFM under critical external load will cause large fluctuations in switching frequency, seriously affecting the output voltage of the BUCK circuit. V OUT stability. Summary of the invention

[0004] The main purpose of the present disclosure is to provide a BUCK circuit and an electronic device with an ultra-high frequency mode to solve the technical problem of unstable switching frequency caused by detection delay during switching between USM mode and PFM mode in the related art.

[0005] In order to achieve the above-mentioned object, the first aspect of the present disclosure provides a BUCK circuit with an ultra-high frequency mode, comprising a mode control unit, a high-side power tube, a low-side power tube, an inductor, and an output capacitor connected in parallel with an external load; wherein, The input end of the mode control unit is connected to the output end of the inductor, the output end 1 of the mode control unit is connected to the gate of the high-side power tube, the output end 2 of the mode control unit is connected to the gate of the low-side power tube, and the source of the high-side power tube is divided into two paths, one path is connected to the drain of the low-side power tube, and the other path is connected to the ground after passing through the inductor and the output capacitor in sequence; The mode control unit has a built-in feedback signal terminal connected to the output terminal of the inductor, and the mode control unit is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal at both ends of the output capacitor in the BUCK circuit. V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the new voltage detection threshold after the increase is combined with the feedback signal V FB The comparison result controls the state of the low-side power tube to reduce the real-time voltage signal by shortening the opening time of the low-side power tube in the super audio mode. V OUT The feedback signal V FB is configured with the real-time voltage signal V OUT Related.

[0006] Further, the setting ratio is configured to be obtained based on the estimated delay of the mode control unit, the parameters of the output capacitor, and the parameters of the inductor, wherein the estimated delay is configured to be equal to the time length between the theoretical shutdown time and the actual shutdown time of the low-side power tube, and the estimated delay is configured to be equal to the real-time voltage signal V OUT Related.

[0007] Furthermore, the operating frequency of the BUCK circuit in the super audio mode is a fixed frequency; and, The mode control unit is also configured to, when the BUCK circuit is in the pulse frequency modulation mode, control the low-side power tube to shut down in response to the current of the inductor dropping to 0, and automatically trigger the sleep mode, and, in response to the duration of the sleep mode reaching the set threshold time, automatically trigger the super audio mode.

[0008] Furthermore, the switchable working modes provided in the mode control unit include pulse width modulation mode, pulse frequency modulation mode, and ultrasonic mode; and, The mode control unit is further configured to periodically monitor the real-time voltage signal when the BUCK circuit is in the pulse width modulation mode. V OUT , identify the real-time voltage signal V OUT When the voltage is lower than the first reference voltage, the BUCK circuit is controlled to switch from the pulse width modulation mode to the pulse frequency modulation mode, and when the BUCK circuit is in the pulse frequency modulation mode, the feedback signal is monitored. V FB , and based on the feedback signal V FB The comparison result with the voltage detection threshold controls the switching frequency of the BUCK circuit.

[0009] Furthermore, the mode control unit comprises: A feedback signal acquisition module is configured to obtain a feedback signal based on the real-time voltage signal V OUT Generate the feedback signal V FB ; The preprocessing module is configured to convert the feedback signal V FB Compare with the voltage detection threshold, and generate a PFM clock signal based on the comparison result and send it to the logic control module; and, A logic control module is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor in the BUCK circuit V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the state of the low-side power tube is controlled based on the level conversion of the PFM clock signal, and the sleep mode start signal built into the logic control module is reset.

[0010] Furthermore, the feedback signal acquisition module includes a voltage divider circuit; and, The preprocessing module includes an error amplifier, a PFM judgment circuit, a PFM clock generating circuit and a multiplexer, wherein the first input terminal of the multiplexer is connected to a first reference voltage, the second input terminal of the multiplexer is connected to a second reference voltage, the control terminal of the multiplexer is connected to a first output terminal of the logic control module, the output terminal of the multiplexer is connected to a positive input terminal of the PFM clock generating circuit, and the positive input terminal of the error amplifier is connected to a voltage detection threshold V REF , the negative input terminal of the error amplifier is connected to the output terminal of the voltage divider circuit, the output terminal of the error amplifier is connected to the negative input terminal of the PFM judgment circuit, and the positive input terminal of the PFM judgment circuit is connected to the first reference voltage, the output terminal of the PFM judgment circuit is connected to the enable terminal of the PFM clock generation circuit, and the output terminal of the PFM clock generation circuit is connected to the first input terminal of the logic control module, wherein the first reference voltage and the second reference voltage are respectively configured as the voltage detection threshold V REF The value of the first reference voltage is smaller than the value of the second reference voltage according to different setting ratios; and The PFM determination circuit is configured to respond to the output signal of the error amplifier V comp When the voltage is lower than the first reference voltage, an enable signal is sent to the PFM clock generating circuit; The PFM clock generating circuit is configured to generate the PFM clock signal in response to the enable signal and send the PFM clock signal to the logic control module.

[0011] Furthermore, the pre-processing module is also configured with an RC filter circuit, a PWM comparator, a PFM oscillator, a voltage subtractor, and the BUCK circuit also includes a high-side power tube driver and a low-side power tube driver; wherein, The RC filter circuit is arranged between the error amplifier and the PFM judgment circuit, and the positive input terminal of the PWM comparator is connected to the output terminal of the voltage subtractor, and the negative input terminal of the PWM comparator is connected to the current of the inductor through the sampling circuit. I L , and the positive input terminal of the voltage subtractor is connected to the output signal of the error amplifier V comp , the negative input end of the voltage subtractor is connected to the output end of the PFM judgment circuit via the PFM oscillator, and the output end of the PFM oscillator is also connected to the second input end of the logic control module; The PWM comparator is configured to respond to the current of the inductor collected by the sampling circuit.I L When the set peak value is reached, the output signal of the PWM comparator is controlled to change from a low level to a high level; The high-side power tube driver is arranged between the logic control module and the high-side power tube, and is configured to control the high-side power tube to be turned off in response to the received output signal of the PWM comparator changing from a low level to a high level, and to control the high-side power tube to be turned on in response to the received signal of the second output terminal of the logic control module changing from a low level to a high level; The low-side power tube driver is arranged between the logic control module and the low-side power tube, and is configured to control the low-side power tube to turn on in response to the signal received from the third output terminal of the logic control module changing from a low level to a high level, and to control the low-side power tube to turn off in response to the signal received from the third output terminal of the logic control module changing from a high level to a low level.

[0012] Furthermore, the logic control module performs the following steps to complete the switching frequency control functions of the pulse frequency modulation mode and the super audio mode and the mode switching function from the pulse frequency modulation mode to the super audio mode: In the pulse frequency modulation mode, the output of the multiplexer is set to the first reference voltage so that when the feedback signal V FB When the voltage is lower than or equal to the first reference voltage, the PFM clock signal received by the first input terminal of the logic control module changes from a low level to a high level; In response to the PFM clock signal changing from a low level to a high level, controlling the signal at the second output terminal of the logic control module to change from a low level to a high level, so that the high-side power tube is turned on, and at the same time, the sleep mode start signal is reset; In response to the inductor current rising to reach the set peak I peak , controlling the signal at the second output terminal of the logic control module to change from a high level to a low level, so as to turn off the high-side power tube; In response to the output signal of the high-side power tube driver changing from a high level to a low level, controlling the signal of the third output terminal of the logic control module to change from a low level to a high level, so that the low-side power tube is turned on; In response to the current of the inductor dropping to 0, controlling the signal of the third output terminal of the logic control module to change from a high level to a low level, so as to turn off the low-side power tube and trigger a sleep mode; Starting a timer of the sleep mode until the timer reaches the set threshold time, triggering the super audio mode; placing the output of the multiplexer at the second reference voltage; The output signal of the third output terminal of the logic control module is controlled to change from a low level to a high level, so that the low-side power tube is turned on, and the feedback signal V FB To lower blood pressure; Control the third output terminal of the logic control module to output the real-time voltage signal V OUT and limiting the frequency of the same-frequency signal to a preset fixed frequency until the ultrasonic audio mode corresponding to this working cycle ends.

[0013] Furthermore, the threshold time is set to 29 μs, and the first reference voltage V REF-1 is configured as the voltage detection threshold V REF 1.01 times the second reference voltage V REF-2 is configured to be 1.015 times the voltage detection threshold; and the logic control module further performs the following steps to complete the switching function from the pulse width modulation mode to the pulse frequency modulation mode: When the BUCK circuit is in the pulse width modulation mode, the output signal of the error amplifier is obtained regularly. V comp ; Identify the error amplifier output signal V comp Is it lower than the third reference voltage? V ref_comp If so, control the BUCK circuit to switch from the pulse width modulation mode to the pulse frequency modulation mode; otherwise, continue with the pulse width modulation mode.

[0014] A second aspect of the present disclosure provides an electronic device, wherein the electronic device is provided with the BUCK circuit described in any one of the first aspects of the present disclosure.

[0015] In the BUCK circuit provided in the embodiment of the present disclosure, a threshold hysteresis control strategy is introduced to switch the feedback signal when the USM mode is triggered. V FB The voltage detection threshold will feedback the signal V FB The voltage detection threshold is appropriately increased to shorten the opening time of the low-side power tube, achieving the goal of reducing the real-time voltage signal V OUT The purpose of fluctuation is to achieve stable output when switching between USM mode and PFM mode.V OUT The technical effect is achieved, thereby solving the technical problem of unstable switching frequency caused by detection delay during the switching process between USM mode and PFM mode in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram showing a comparison of switching frequencies of BUCK circuits with and without USM mode functions in the related art; Figure 2 A block diagram of a BUCK circuit provided in an embodiment of the present disclosure; Figure 3 A block diagram of the composition of a mode control unit provided in an embodiment of the present disclosure; Figure 4 An example schematic diagram of a BUCK circuit provided in an embodiment of the present disclosure; Figure 5 The core control logic of the PFM mode of the BUCK circuit provided in the embodiment of the present disclosure; Figure 6 A state diagram of each signal of a BUCK circuit in PFM mode provided by an embodiment of the present disclosure; Figure 7 A state diagram of each signal of a BUCK circuit in USM mode provided by an embodiment of the present disclosure; Figure 8 A block diagram of an electronic device provided in accordance with an embodiment of the present disclosure.

[0018] Reference numerals F sw - switching frequency; F sw_min- Minimum switching frequency; EA- Error amplifier; LSD- Low-side power tube; LSDRV- Low-side power tube driver; HSD- High-side power tube; HSDRV- High-side power tube driver; AMUX- Multiplexer; Timer- Timer; VDD- Power supply; PFM_CLK- PFM clock signal; USM Mode-; Multiplexer control signal; LSON- Signal at the third output end (inside the logic control module); HSON- Signal at the second output end (inside the logic control module); LSON- Signal at the third output end; HSON- Signal at the second output end; HS OFF- Output signal of PWM comparator; HSGT- Control signal of high-side power tube; LSGT- Control signal of low-side power tube; Sleep- Sleep mode start signal; Sleep time- Duration of sleep mode; ZC- Zero crossing detection signal; SW- Switch signal; R C1 , R C2 , R F1 , R F2 , R L -resistance; L -inductance; V IN - Constant voltage; V OUT - Real-time voltage signal; V REF - Voltage detection threshold; V FB - Feedback signal; V comp - Output signal of the error amplifier; V REF_1 - a first reference voltage; V REF_2 - Second reference voltage; V slope - The output signal of the PFM oscillator; C C -capacitance; C OUT - Output capacitor; I L - the current of the inductor; I peak- peak value; 10- BUCK circuit; 11- mode control unit; 12- high-side power tube; 13- low-side power tube; 14- inductor; 15- output capacitor; 111- feedback signal acquisition module; 112- preprocessing module; 113- logic control module; 1- electronic device. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the scheme of the present disclosure, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present disclosure.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] In the present disclosure, the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", etc. are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0022] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this disclosure can be understood according to specific circumstances.

[0023] The term "Pulse Code Modulation Mode", abbreviated as PCM mode, is the full name of Peak Current Mode in English. It is a widely used DC-DC converter control method, mainly used to convert analog signals into digital signals.

[0024] The term "Pulse Width Modulation Mode", referred to as PWM mode, PWM's full name in English is Pulse Width Modulation, which is a technology that modulates the width of a series of pulses to equivalently obtain the required waveform (including shape and amplitude).

[0025] The term "Pulse Frequency Modulation Mode", referred to as PFM mode, is a modulation technology that controls the circuit by adjusting the frequency of pulses, rather than adjusting the width of the pulses like PWM. This modulation method is more efficient under light external load conditions, but less efficient under heavy load conditions.

[0026] The term "ultra-sonic mode", abbreviated as USM mode, is the full name of Ultrasonic Mode in English. It is a specific mode that is widely used in various electronic devices, especially in application scenarios that require efficient energy conversion and control.

[0027] The term "switching frequency" refers to the switching frequency of the high-side power tube and the low-side power tube in the BUCK circuit, where the high-side power tube and the low-side power tube are switched at a fixed frequency, so that the inductor element generates uninterrupted current during the working cycle and forms a stable voltage at the output end.

[0028] The term "step-down chopper circuit", referred to as BUCK circuit, is one of the basic DC-DC circuits used for DC to DC step-down conversion.

[0029] The term "variable resistor", abbreviated as RV, is the full name of Potentiometer in English. It is a precision electronic circuit that can adjust power and current. Its structure has a built-in variable resistance element.

[0030] The term "PFM oscillator" is an electronic device that can generate an AC signal. It can generate a sine wave or other waveform output voltage by self-oscillating the circuit without an external input signal. The full name of the oscillator is Oscillator.

[0031] The term "multiplexer", referred to as AMUX, is the full name of Analog Multiplexer in English. It can connect multiple analog signals to a common analog signal, or not connect analog signals.

[0032] The term "PWM comparator" refers to an electronic circuit whose main function is to generate a pulse width modulation (PWM) signal by comparing two voltage signals (usually a DC wave and a triangle wave).

[0033] The term “PFM determination circuit” refers to a circuit device that compares an input signal with a first reference voltage and generates an electrical signal based on the comparison result, and can be implemented by a comparator.

[0034] The term "PFM clock generation circuit" refers to a circuit that modulates the clock frequency by adjusting the pulse width.

[0035] The term "sampling circuit" refers to a current I L The circuit that performs sampling.

[0036] The term "error amplifier", referred to as EA, has the main function of amplifying differential signals and suppressing common-mode signals.

[0037] The term "critical USM mode" is a switching power supply operating mode designed to provide higher efficiency and lower losses. In this mode, the power switch device will be turned on when the inductor current reaches a critical value, which is determined by the relationship between the inductor and the output voltage. Once the inductor current drops to zero, the switch device will be turned off.

[0038] The term "sleep mode" refers to a mode in which both the high-side power transistor and the low-side power transistor of the BUCK circuit are turned off at the same time.

[0039] The term "sleep mode duration" refers to the time period that the BUCK circuit is in the sleep mode. For the BUCK circuit, properly setting the sleep mode duration can not only reduce the overall energy consumption, but also extend the service life of the corresponding electronic device.

[0040] In addition, the terms "installed", "set", "provided with", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] The related technology has a technical problem of unstable switching frequency due to detection delay during the switching process between USM mode and PFM mode.

[0043] In order to solve the above technical problems, the embodiment of the present disclosure provides a BUCK circuit with an ultra-high frequency mode, such as Figure 2As shown, the BUCK circuit 10 includes a mode control unit 11, a high-side power tube 12, a low-side power tube 13, an inductor 14, and an output capacitor 15 connected in parallel with an external load.

[0044] The input end of the mode control unit 11 is connected to the output end of the inductor 14, the output end 1 of the mode control unit 11 is connected to the gate of the high-side power tube 12, and the output end 2 of the mode control unit 11 is connected to the gate of the low-side power tube 13. The source of the high-side power tube 12 is divided into two paths, one path is connected to the drain of the low-side power tube 13, and the other path is connected to the ground after passing through the inductor 14 and the output capacitor 15 in sequence.

[0045] The mode control unit 11 has a built-in feedback signal terminal connected to the output terminal of the inductor 14. The mode control unit 11 is configured to trigger an ultra-high frequency mode (USM mode) in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor 15 in the BUCK circuit. V OUT The feedback signal at the feedback signal end V FB The voltage detection threshold is increased by a set ratio, and based on the increased new voltage detection threshold and the feedback signal V FB The comparison result controls the state of the low-side power tube to reduce the real-time voltage signal by shortening the opening time of the low-side power tube 13 in the super audio mode. V OUT The fluctuation of the feedback signal is controlled to ensure that the duration of the sleep mode between the pulse frequency modulation mode (PFM mode) and the USM mode of the BUCK circuit always reaches the set threshold time. V FB is configured with real-time voltage signals V OUT Related.

[0046] It should be noted that the related technology is that in the USM mode, the mode control unit 11 is based on the feedback signal V FB The difference between the voltage detection threshold and the unchanged voltage detection threshold controls the state of the low-side power tube 13. The embodiment of the present disclosure is based on the real-time voltage signal V OUT The voltage detection threshold is adjusted to shorten the opening time of the low-side power tube 13 in the super audio mode, and the real-time voltage signal V OUT The drain of the high-side power tube 12 can be connected to a power supply or a constant voltage. V IN The source of the low-side power tube 13 is grounded or set to a low voltage, which is not limited in the present disclosure.

[0047] Some embodiments of the present disclosure also provide an electronic device corresponding to the above-mentioned BUCK circuit.

[0048] The BUCK circuit provided in the embodiment of the present disclosure is applicable to any existing occasions where a BUCK circuit is required. Compared with the prior art, the BUCK circuit provided in the embodiment of the present disclosure adopts a threshold hysteresis control strategy, by switching the feedback signal when the USM mode is triggered. V FB The voltage detection threshold will feedback the signal V FB The voltage detection threshold is appropriately increased to shorten the opening time of the low-side power tube, achieving the goal of reducing the real-time voltage signal V OUT The purpose of fluctuation is to achieve stable output when switching between USM mode and PFM mode. V OUT The technical effect is achieved, thereby solving the technical problem of unstable switching frequency in the switching process between USM mode and PFM mode in the related technology.

[0049] Specifically, the setting ratio is configured to be obtained based on the estimated delay of the mode control unit 11, the parameters of the output capacitor 15, and the parameters of the inductor 14, wherein the estimated delay is configured to be equal to the time length between the theoretical shutdown moment and the actual shutdown moment of the low-side power tube 13, and the estimated delay is configured to be consistent with the real-time voltage signal V OUT For example, the setting ratio can obtain an optimal value through a deep learning network.

[0050] The switchable working modes provided in the mode control unit 11 include PFM mode and USM mode. Preferably, the switchable working modes provided in the mode control unit 11 also include pulse width modulation mode (PWM mode), so that the working modes of the mode control unit 11 include PFM mode, USM mode and PWM mode.

[0051] exist Figure 2 Based on the method shown, preferably, the operating frequency of the BUCK circuit in the USM mode is a fixed frequency. In addition, the mode control unit 11 is also configured to control the low-side power tube 13 to turn off in response to the current of the inductor 14 dropping to 0 when the BUCK circuit is in the PFM mode, and automatically trigger the sleep mode, and in response to the duration of the sleep mode reaching the set threshold time, trigger the USM mode. Through this configuration, automatic switching from the PFM mode to the USM mode is achieved.

[0052] exist Figure 2Based on the method shown in the figure, preferably, the mode control unit 11 is also configured to monitor the real-time voltage signal at regular intervals when the BUCK circuit is in the PWM mode. V OUT , identify real-time voltage signals V OUT When the voltage is lower than the first reference voltage, the BUCK circuit is controlled to switch from the PWM mode to the PFM mode, and when the BUCK circuit is in the PFM mode, the feedback signal is monitored. V FB , and based on the feedback signal V FB The comparison result with the voltage detection threshold controls the switching frequency of the BUCK circuit. With this configuration, automatic switching from PWM mode to PFM mode is achieved.

[0053] Figure 3 FIG. 1 is a block diagram of a mode control unit provided in an embodiment of the present disclosure. Figure 3 As shown, in order to achieve a better mode control effect, preferably, the mode control unit 11 includes a feedback signal acquisition module 111, a preprocessing module 112, and a logic control module 113 which are connected in sequence.

[0054] The feedback signal acquisition module 111 is configured to obtain the feedback signal based on the real-time voltage signal. V OUT Generate feedback signal V FB The feedback signal acquisition module 111 may be implemented in a software or hardware manner.

[0055] The preprocessing module 112 is configured to convert the feedback signal V FB The voltage detection threshold is compared, and a PFM clock signal is generated based on the comparison result and sent to the logic control module 113. The pre-processing module 112 can also be implemented in software or hardware.

[0056] The logic control module 113 is configured to trigger the USM mode in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor 15 in the BUCK circuit. V OUT The feedback signal at the feedback signal end V FB The voltage detection threshold is increased by a set ratio, and the state of the low-side power tube 13 is controlled based on the level conversion of the PFM clock signal, and the sleep mode start signal built into the logic control module 113 is reset.

[0057] exist Figure 3On the basis of the mode control unit shown, preferably, the feedback signal acquisition module 111 is configured to include a voltage divider circuit to reduce the voltage detection threshold.

[0058] exist Figure 3 Based on the mode control unit shown, preferably, the preprocessing module 112 includes an error amplifier, a PFM judgment circuit, a PFM clock generation circuit and a multiplexer. Among them, the first input terminal of the multiplexer is connected to the first reference voltage, the second input terminal of the multiplexer is connected to the second reference voltage, the control terminal of the multiplexer is connected to the first output terminal of the logic control module 113, and the output terminal of the multiplexer is connected to the positive input terminal of the PFM clock generation circuit. The positive input terminal of the error amplifier is connected to the voltage detection threshold V REF The negative input terminal of the error amplifier is connected to the output terminal of the voltage divider circuit, and the output terminal of the error amplifier is connected to the negative input terminal of the PFM judgment circuit. The positive input terminal of the PFM judgment circuit is connected to the first reference voltage, and the output terminal of the PFM judgment circuit is connected to the enable terminal of the PFM clock generation circuit. The output terminal of the PFM clock generation circuit is connected to the first input terminal of the logic control module 113. The first reference voltage and the second reference voltage are respectively configured as voltage detection thresholds V REF According to different setting ratios, the value of the first reference voltage is smaller than the value of the second reference voltage.

[0059] The PFM determination circuit is configured to respond to the output signal of the error amplifier V comp When the voltage is lower than the first reference voltage, an enable signal is sent to the PFM clock generating circuit.

[0060] The PFM clock generation circuit is configured to generate a PFM clock signal in response to the enable signal and send the PFM clock signal to the logic control module 113 .

[0061] Based on the configuration of the preprocessing module 112, preferably, the preprocessing module 112 is further configured with an RC filter circuit, a PWM comparator, a PFM oscillator and a voltage subtractor. The RC filter circuit is arranged between the error amplifier and the PFM judgment circuit. The positive input terminal of the PWM comparator is connected to the output terminal of the voltage subtractor, and the negative input terminal of the PWM comparator is connected to the current of the inductor 14 through the sampling circuit. I L The positive input of the voltage subtractor is connected to the output signal of the error amplifier. V comp The negative input terminal of the voltage subtractor is connected to the output terminal of the PFM judgment circuit via the PFM oscillator. The output terminal of the PFM oscillator is also connected to the second input terminal of the logic control module 113.

[0062] The PWM comparator is configured to respond to the current of the inductor 14 collected by the sampling circuit I L When the set peak value is reached, the output signal of the PWM comparator is controlled to change from low level to high level.

[0063] exist Figure 3 On the basis of the mode control unit shown, preferably, the BUCK circuit further includes a high-side power tube driver and a low-side power tube driver.

[0064] The high-side power tube driver is arranged between the logic control module 113 and the high-side power tube 12, and is configured to control the high-side power tube 12 to be turned off in response to the received output signal of the PWM comparator changing from a low level to a high level, and to control the high-side power tube 12 to be turned on in response to the received signal at the second output end of the logic control module 113 changing from a low level to a high level.

[0065] The low-side power tube driver is arranged between the logic control module 113 and the low-side power tube 13, and is configured to control the low-side power tube 13 to turn on in response to the signal received from the third output terminal of the logic control module 113 changing from a low level to a high level, and to control the low-side power tube 13 to turn off in response to the signal received from the third output terminal of the logic control module 113 changing from a high level to a low level.

[0066] As a preferred implementation, the logic control module 113 executes the following steps S11 to S12 to complete the switching function from the PWM mode to the PFM mode and the mode switching function from the PFM mode to the USM mode: Step S11: When the BUCK circuit is in PWM mode, the output signal of the error amplifier is obtained regularly. V comp .

[0067] Step S12: Identify the output signal of the error amplifier V comp Is it lower than the third reference voltage? V ref_comp , if so, control the BUCK circuit to switch from PWM mode to PFM mode, otherwise, continue with PWM mode.

[0068] Through the above steps S11-S12, when V comp <Third reference voltage V ref_comp When the system switches from PWM mode to PFM mode, the PFM mode is detected by V FB Lower voltage limit (1.01 V REF) to control the switching frequency, while the peak I peak Fixed, that is, the control in PFM mode can be implemented based on the ripple control principle.

[0069] As a preferred implementation, the logic control module 113 executes the following steps S21 to S26 to complete the switching frequency control function of the PFM mode: Step S21: In the PFM mode, the output of the multiplexer is set to a first reference voltage so that when the feedback signal V FB When the voltage is lower than or equal to the first reference voltage, the PFM clock signal received by the first input terminal of the logic control module 113 changes from a low level to a high level.

[0070] Step S22: in response to the PFM clock signal changing from low level to high level, the signal at the second output terminal of the control logic control module 113 changes from low level to high level, so that the high-side power tube 12 is turned on, and at the same time, the sleep mode start signal Sleep is reset.

[0071] Step S23: In response to the current of the inductor 14 rising to a set peak value I peak , the signal at the second output terminal of the control logic control module 113 changes from a high level to a low level, so that the high-side power tube 12 is turned off.

[0072] Step S24 : in response to the output signal of the high-side power transistor driver changing from high level to low level, the signal of the third output terminal of the control logic control module 113 changes from low level to high level, so that the low-side power transistor 13 is turned on.

[0073] Step S25: in response to the current of the inductor 14 dropping to 0, the signal at the third output terminal of the control logic control module 113 changes from a high level to a low level, so that the low-side power tube 13 is turned off and the sleep mode is triggered.

[0074] Step S26: Start the sleep mode timer until the timer reaches the set threshold time, triggering the USM mode.

[0075] Through the above steps S21 to S26, when V FB ≤ 1.01 V REF When the PFM clock signal is output, the high-side power tube 12 is turned on and the sleep mode signal is reset. I peak When the high-side power tube 12 is turned off, and when the voltage of the high-side power tube driver is detected to be low (the high-side power tube 12 is turned off), Figure 4 The output signal HSOFF of the PWM comparator in the circuit sets the LSON signal to 1, and the low-side power tube 13 is turned on. When the current of the inductor 14 drops to zero, the LSON signal is reset to 0, and the low-side power tube 13 is turned off. At this time, the sleep mode is triggered and the 29μs timer is enabled. If the duration of the sleep mode is less than 29μs, the USM mode will not be triggered, and the circuit continues to work in the PFM mode.

[0076] As a preferred implementation, the logic control module 113 performs the following steps S31 to S33 to complete the switching frequency control function of the USM mode: Step S31: setting the output of the multiplexer to a second reference voltage.

[0077] Step S32: The output signal of the third output terminal of the control logic control module 113 changes from a low level to a high level, so that the low-side power tube 13 is turned on, and the feedback signal V FB To reduce blood pressure.

[0078] Step S33: The third output terminal of the control logic control module 113 outputs a real-time voltage signal V OUT The same-frequency signal is transmitted and the frequency of the same-frequency signal is limited to a preset fixed frequency until the USM mode corresponding to this working cycle ends.

[0079] Through the above steps S31 to S33, when the duration of the sleep mode reaches 29 μs, the USM mode is triggered. Figure 4 The LSON signal in the output is set to 1, the low-side power tube 13 is turned on, and the inductor current flows in the reverse direction from the low-side power tube 13, which is used to output the real-time signal. V OUT Rapid discharge forces V FB Lower than the reference voltage, the PFM clock signal is outputted. At this time, the low-side power tube 13 is turned off and the high-side power tube 12 is turned on. This cycle is repeated to limit the frequency to 30kHz.

[0080] Figure 4 FIG. 1 is a schematic diagram of an example of a BUCK circuit provided in an embodiment of the present disclosure. The functions of each component have been described in detail above and will not be repeated here. The core control logic of the PFM mode is as follows: Figure 5 As shown in Figure 2, the signal states of the BUCK circuit in PFM mode are as follows: Figure 6 As shown in Figure 2, the signal states of the BUCK circuit in USM mode are as follows: Figure 7 It can be seen that the output of the BUCK circuit provided by the embodiment of the present disclosure has better switching stability than the related art.

[0081] In some embodiments of the present disclosure, preferably, the threshold time is set to 29 μs, and the first reference voltage V REF-1 is configured as a voltage detection threshold V REF 1.01 times the second reference voltage V REF-2 Configured as 1.015 times the voltage detection threshold.

[0082] From the above description, it can be seen that the present disclosure achieves the following technical effects: 1. Provides a control strategy for switching between USM mode and PFM mode. In order to solve the problem of the chip switching back and forth between USM mode and PFM mode when in critical USM mode, a threshold hysteresis control strategy is introduced, that is, when triggering USM mode, switch V FB The voltage detection threshold, V FB The voltage detection threshold is increased by about 0.005% to trigger the PFM clock signal in advance, making V OUT The ripple is raised by 0.005% in USM mode, so that the duration of sleep mode can reach 29μs in each cycle, thus avoiding switching back and forth between USM mode and PFM mode, and also resisting the shutdown delay of the low-side power tube.

[0083] 2. Prevent the switching frequency from being unstable due to the chip switching back and forth between USM mode and PFM mode. The switching frequency is stabilized at 30 kHz, eliminating audible noise.

[0084] 3. Output signal V OUT的 The ripple is lower, the voltage ripple is reduced by 20%, and the system efficiency is increased by 10%. Especially in critical load scenarios, the output stability is significantly improved.

[0085] 4. Compatible with small inductor design, expanding application scenarios.

[0086] It should be noted that the above steps can be executed in a computer system such as a set of computer executable instructions, and although the above steps show a logical order, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0087] The present disclosure also provides an electronic device for implementing the above-mentioned BUCK circuit embodiment. Figure 8 As shown, the electronic device 1 includes the BUCK circuit 10 of the above embodiment.

[0088] The specific manner in which the BUCK circuit in the above device embodiment performs the operation has been described in detail in the embodiment of the BUCK circuit, and will not be elaborated here.

[0089] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A BUCK circuit with an ultra-high frequency mode, characterized in that: It includes a mode control unit, a high-side power tube, a low-side power tube, an inductor, and an output capacitor connected in parallel with an external load; wherein, The input end of the mode control unit is connected to the output end of the inductor, the output end 1 of the mode control unit is connected to the gate of the high-side power tube, the output end 2 of the mode control unit is connected to the gate of the low-side power tube, and the source of the high-side power tube is divided into two paths, one path is connected to the drain of the low-side power tube, and the other path is connected to the ground after passing through the inductor and the output capacitor in sequence; The mode control unit has a built-in feedback signal terminal connected to the output terminal of the inductor, and the mode control unit is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal at both ends of the output capacitor in the BUCK circuit. V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the new voltage detection threshold after the increase is combined with the feedback signal V FB The comparison result controls the state of the low-side power tube to reduce the real-time voltage signal by shortening the opening time of the low-side power tube in the super audio mode. V OUT The feedback signal V FB is configured with the real-time voltage signal V OUT Related.

2. The BUCK circuit according to claim 1, characterized in that: The setting ratio is configured to be obtained based on the estimated delay of the mode control unit, the parameters of the output capacitor, and the parameters of the inductor, wherein the estimated delay is configured to be equal to the time length between the theoretical shutdown time and the actual shutdown time of the low-side power tube, and the estimated delay is configured to be equal to the real-time voltage signal V OUT Related.

3. The BUCK circuit according to claim 1 or 2, characterized in that: The operating frequency of the BUCK circuit in the super audio mode is a fixed frequency; and The mode control unit is also configured to, when the BUCK circuit is in the pulse frequency modulation mode, control the low-side power tube to shut down in response to the current of the inductor dropping to 0, and automatically trigger the sleep mode, and, in response to the duration of the sleep mode reaching the set threshold time, automatically trigger the super audio mode.

4. The BUCK circuit according to claim 3, characterized in that: The switchable working modes provided in the mode control unit include pulse width modulation mode, pulse frequency modulation mode, and ultrasonic mode; and, The mode control unit is further configured to periodically monitor the real-time voltage signal when the BUCK circuit is in the pulse width modulation mode. V OUT , identify the real-time voltage signal V OUT When the voltage is lower than the first reference voltage, the BUCK circuit is controlled to switch from the pulse width modulation mode to the pulse frequency modulation mode, and when the BUCK circuit is in the pulse frequency modulation mode, the feedback signal is monitored. V FB , and based on the feedback signal V FB The comparison result with the voltage detection threshold controls the switching frequency of the BUCK circuit.

5. The BUCK circuit according to claim 4, characterized in that: The mode control unit comprises: A feedback signal acquisition module is configured to obtain a feedback signal based on the real-time voltage signal V OUT Generate the feedback signal V FB ; The preprocessing module is configured to convert the feedback signal V FB Compare with the voltage detection threshold, and generate a PFM clock signal based on the comparison result and send it to the logic control module; and, The logic control module is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor in the BUCK circuit. V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the state of the low-side power tube is controlled based on the level conversion of the PFM clock signal, and the sleep mode start signal built into the logic control module is reset.

6. The BUCK circuit according to claim 5, characterized in that: The feedback signal acquisition module includes a voltage divider circuit; and, The preprocessing module includes an error amplifier, a PFM judgment circuit, a PFM clock generating circuit and a multiplexer, wherein the first input terminal of the multiplexer is connected to a first reference voltage, the second input terminal of the multiplexer is connected to a second reference voltage, the control terminal of the multiplexer is connected to a first output terminal of the logic control module, the output terminal of the multiplexer is connected to a positive input terminal of the PFM clock generating circuit, and the positive input terminal of the error amplifier is connected to a voltage detection threshold V REF , the negative input terminal of the error amplifier is connected to the output terminal of the voltage divider circuit, the output terminal of the error amplifier is connected to the negative input terminal of the PFM judgment circuit, and the positive input terminal of the PFM judgment circuit is connected to the first reference voltage, the output terminal of the PFM judgment circuit is connected to the enable terminal of the PFM clock generation circuit, and the output terminal of the PFM clock generation circuit is connected to the first input terminal of the logic control module, wherein the first reference voltage and the second reference voltage are respectively configured as the voltage detection threshold V REF The value of the first reference voltage is smaller than the value of the second reference voltage according to different setting ratios; and The PFM determination circuit is configured to respond to the output signal of the error amplifier V comp When the voltage is lower than the first reference voltage, an enable signal is sent to the PFM clock generating circuit; The PFM clock generating circuit is configured to generate the PFM clock signal in response to the enable signal and send the PFM clock signal to the logic control module.

7. The BUCK circuit according to claim 6, characterized in that: The pre-processing module is also configured with an RC filter circuit, a PWM comparator, a PFM oscillator, a voltage subtractor, and the BUCK circuit also includes a high-side power tube driver and a low-side power tube driver; wherein, The RC filter circuit is arranged between the error amplifier and the PFM judgment circuit, and the positive input terminal of the PWM comparator is connected to the output terminal of the voltage subtractor, and the negative input terminal of the PWM comparator is connected to the current of the inductor through the sampling circuit. I L , and the positive input terminal of the voltage subtractor is connected to the output signal of the error amplifier V comp , the negative input end of the voltage subtractor is connected to the output end of the PFM judgment circuit via the PFM oscillator, and the output end of the PFM oscillator is also connected to the second input end of the logic control module; The PWM comparator is configured to respond to the current of the inductor collected by the sampling circuit. I L When the set peak value is reached, the output signal of the PWM comparator is controlled to change from a low level to a high level; The high-side power tube driver is arranged between the logic control module and the high-side power tube, and is configured to control the high-side power tube to be turned off in response to the received output signal of the PWM comparator changing from a low level to a high level, and to control the high-side power tube to be turned on in response to the received signal of the second output terminal of the logic control module changing from a low level to a high level; The low-side power tube driver is arranged between the logic control module and the low-side power tube, and is configured to control the low-side power tube to turn on in response to the signal received from the third output terminal of the logic control module changing from a low level to a high level, and to control the low-side power tube to turn off in response to the signal received from the third output terminal of the logic control module changing from a high level to a low level.

8. The BUCK circuit according to claim 7, characterized in that: The logic control module performs the following steps to complete the switching frequency control functions of the pulse frequency modulation mode and the super audio mode and the mode switching function from the pulse frequency modulation mode to the super audio mode: In the pulse frequency modulation mode, the output of the multiplexer is set to the first reference voltage so that when the feedback signal V FB When the voltage is lower than or equal to the first reference voltage, the PFM clock signal received by the first input terminal of the logic control module changes from a low level to a high level; In response to the PFM clock signal changing from a low level to a high level, controlling the signal at the second output terminal of the logic control module to change from a low level to a high level, so that the high-side power tube is turned on, and at the same time, the sleep mode start signal is reset; In response to the inductor current rising to reach the set peak I peak , controlling the signal at the second output terminal of the logic control module to change from a high level to a low level, so as to turn off the high-side power tube; In response to the output signal of the high-side power tube driver changing from a high level to a low level, controlling the signal of the third output terminal of the logic control module to change from a low level to a high level, so that the low-side power tube is turned on; In response to the current of the inductor dropping to 0, controlling the signal of the third output terminal of the logic control module to change from a high level to a low level, so as to turn off the low-side power tube and trigger a sleep mode; Starting a timer of the sleep mode until the timer reaches the set threshold time, triggering the super audio mode; placing the output of the multiplexer at the second reference voltage; The output signal of the third output terminal of the logic control module is controlled to change from a low level to a high level, so that the low-side power tube is turned on, and the feedback signal V FB Performing blood pressure reduction; and, Control the third output terminal of the logic control module to output the real-time voltage signal V OUT and limiting the frequency of the same-frequency signal to a preset fixed frequency until the ultrasonic audio mode corresponding to this working cycle ends.

9. The BUCK circuit according to any one of claims 6 to 8, characterized in that: The threshold time is set to 29 μs, and the first reference voltage V REF-1 is configured as the voltage detection threshold V REF 1.01 times the second reference voltage V REF-2 is configured to be 1.015 times the voltage detection threshold; and the logic control module further performs the following steps to complete the switching function from the pulse width modulation mode to the pulse frequency modulation mode: When the BUCK circuit is in the pulse width modulation mode, the output signal of the error amplifier is obtained regularly. V comp ; Identify the error amplifier output signal V comp Is it lower than the third reference voltage? V ref_comp If so, control the BUCK circuit to switch from the pulse width modulation mode to the pulse frequency modulation mode; otherwise, continue with the pulse width modulation mode.

10. An electronic device, characterized in that: The electronic device is provided with the BUCK circuit described in any one of claims 1 to 9.

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