A BUCK circuit and an electronic device with a super audio mode

Abstract

The present disclosure provides a BUCK circuit and an electronic device with a super audio mode, relating to the field of electronic power technology. A mode control unit in the BUCK circuit has a feedback signal terminal connected to the output end of an inductor, and is configured to respond to the BUCK circuit triggering the super audio mode, and based on a real-time voltage signal across an output capacitor in the BUCK circuit V OUT increase the voltage detection threshold of the feedback signal of the feedback signal terminal by a set ratio, so as to reduce the fluctuation of the real-time voltage signal by shortening the turn-on time of the low-side power transistor in the super audio mode, and, control the duration of the sleep mode of the BUCK circuit between the pulse frequency modulation mode and the super audio mode to always reach a set threshold time, wherein the feedback signal V FB is configured to be related to the real-time voltage signal V OUT . The BUCK circuit can achieve stable output when switching back and forth between the USM mode and the PFM mode V FB . V OUT The BUCK circuit can achieve stable output when switching back and forth between the USM mode and the PFM mode

Description

Technical Field

[0001] The present disclosure relates to the field of electronic power technology, and particularly to a BUCK circuit with an ultra-audio mode and an electronic device. Background Art

[0002] For a traditional buck chopper circuit (BUCK circuit) with dual operating modes of pulse width modulation (PWM) mode and pulse frequency modulation (PFM) mode, after entering the PFM mode under light load, the switching frequency will decrease as the external load becomes smaller, and will drop to the lowest frequency (less than 1 kHz) when the load is no-load, resulting in audible noise (20 Hz - 20 KHz), which is a situation that needs to be avoided in audio applications.

[0003] The ultra-audio (USM) mode can solve the problem of audible noise by restricting the switching frequency above 30 KHz, as Figure 1 shown. The specific structure of the BUCK circuit with the USM mode can be referred to the records of Chinese Patent CN 103701323 B and the like. However, in the existing BUCK circuit, there are the following problems in the switching between the USM mode and the PFM mode: in the stage of triggering the USM mode, due to the insufficient response speed of the comparator for feedback signal detection, the limited accuracy of the comparator, and the turn-off delay of the low-side power transistor (LSD), the turn-on time of the low-side power transistor in the USM mode is relatively long, and the output voltage V OUT will be over-discharged. When the high-side power transistor is turned off, the output voltage V OUT is not large enough, resulting in the duration of the sleep mode when switching from the USM mode to the PFM mode being less than 29 μs. In the case of frequent switching between the USM mode and the PFM mode, it causes an unstable switching frequency. Especially when the USM and PFM are frequently switched under the critical external load, it will cause a large fluctuation in the switching frequency, seriously affecting the stability of the output voltage V OUT of the BUCK circuit. Summary of the Invention

[0004] The main object of the present disclosure is to provide a BUCK circuit with an ultra-audio mode and an electronic device, so as to solve the technical problem of unstable switching frequency caused by detection delay in the switching process between the USM mode and the PFM mode in the related art.

[0005] To achieve the above object, the first aspect of the present disclosure provides a BUCK circuit with an ultra-audio mode, including a mode control unit, a high-side power transistor, a low-side power transistor, an inductor, and an output capacitor connected in parallel with an external load; wherein,

[0006] The input end of the mode control unit is connected to the output end of the inductor. One output end of the mode control unit is connected to the gate of the high-side power transistor, and the second output of the mode control unit is connected to the gate of the low-side power transistor. Moreover, the source of the high-side power transistor is divided into two paths. One path is connected to the drain of the low-side power transistor, and the other path is grounded through the inductor and the output capacitor in sequence.

[0007] The mode control unit has a feedback signal terminal connected to the output end of the inductor. The mode control unit is configured to respond to the BUCK circuit triggering the super-audio mode, and based on the real-time voltage signal across the output capacitor in the BUCK circuit V OUT increase the voltage detection threshold of the feedback signal at the feedback signal terminal by a set ratio, and based on the comparison result between the new increased voltage detection threshold and the feedback signal V FB control the state of the low-side power transistor, so as to reduce the fluctuation of the real-time voltage signal by shortening the on-time of the low-side power transistor in the super-audio mode. Moreover, control the duration of the sleep mode of the BUCK circuit between the pulse frequency modulation mode and the super-audio mode to always reach the set threshold time, where the feedback signal V FB is configured to be related to the real-time voltage signal V OUT V FB is configured to be related to the real-time voltage signal V OUT

[0008] Further, the set ratio is configured to be obtained based on the estimated delay of the mode control unit, the parameters of the output capacitor, and the parameters of the inductor, where the estimated delay is configured to be equal to the time length between the theoretical turn-off moment and the actual turn-off moment of the low-side power transistor, and the estimated delay is configured to be related to the real-time voltage signal V OUT

[0009] Further, the operating frequency of the BUCK circuit in the super-audio mode is a fixed frequency; and

[0010] the mode control unit is further configured to, when the BUCK circuit is in the pulse frequency modulation mode, control the low-side power transistor to turn off in response to the current of the inductor dropping to 0, and at the same time automatically trigger the sleep mode, and in response to the duration of the sleep mode reaching the set threshold time, automatically trigger the super-audio mode.

[0011] ​​​Furthermore, the switchable working modes provided in the mode control unit include pulse width modulation mode, pulse frequency modulation mode, and ultrasonic mode; and,

[0012] The mode control unit is further configured to periodically monitor the real-time voltage signal when the BUCK circuit is in the pulse width modulation mode. V OUT , identify the real-time voltage signal V OUT When the voltage is lower than the first reference voltage, the BUCK circuit is controlled to switch from the pulse width modulation mode to the pulse frequency modulation mode, and when the BUCK circuit is in the pulse frequency modulation mode, the feedback signal is monitored. V FB , and based on the feedback signal V FB The comparison result with the voltage detection threshold controls the switching frequency of the BUCK circuit.

[0013] Furthermore, the mode control unit comprises:

[0014] A feedback signal acquisition module is configured to obtain a feedback signal based on the real-time voltage signal V OUT Generate the feedback signal V FB ;

[0015] The preprocessing module is configured to convert the feedback signal V FB Compare with the voltage detection threshold, and generate a PFM clock signal based on the comparison result and send it to the logic control module; and,

[0016] A logic control module is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor in the BUCK circuit V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the state of the low-side power tube is controlled based on the level conversion of the PFM clock signal, and the sleep mode start signal built into the logic control module is reset.

[0017] Furthermore, the feedback signal acquisition module includes a voltage divider circuit; and,

[0018] The preprocessing module includes an error amplifier, a PFM judgment circuit, a PFM clock generation circuit, and a multiplexer. Among them, the first input terminal of the multiplexer is connected to a first reference voltage, the second input terminal of the multiplexer is connected to a second reference voltage, the control terminal of the multiplexer is connected to the first output terminal of the logic control module, the output terminal of the multiplexer is connected to the positive input terminal of the PFM clock generation circuit, and the positive input terminal of the error amplifier is connected to a voltage detection threshold V REF , the negative input terminal of the error amplifier is connected to the output terminal of the voltage division circuit, the output terminal of the error amplifier is connected to the negative input terminal of the PFM judgment circuit, and the positive input terminal of the PFM judgment circuit is connected to the first reference voltage, the output terminal of the PFM judgment circuit is connected to the enable terminal of the PFM clock generation circuit, and the output terminal of the PFM clock generation circuit is connected to the first input terminal of the logic control module. Among them, the first reference voltage and the second reference voltage are respectively configured as different setting ratios of the voltage detection threshold V REF , and the value of the first reference voltage is less than the value of the second reference voltage; and,

[0019] The PFM judgment circuit is configured to respond to the output signal of the error amplifier V comp When it is lower than the first reference voltage, an enable signal is sent to the PFM clock generation circuit;

[0020] The PFM clock generation circuit is configured to generate the PFM clock signal in response to the enable signal and send it to the logic control module.

[0021] Furthermore, the preprocessing module is also configured with an RC filter circuit, a PWM comparator, a PFM oscillator, a voltage subtractor, and the BUCK circuit further includes a high-side power transistor driver and a low-side power transistor driver; among them,

[0022] The RC filter circuit is arranged between the error amplifier and the PFM judgment circuit, and the positive input terminal of the PWM comparator is connected to the output terminal of the voltage subtractor, and the negative input terminal of the PWM comparator is connected to the current of the inductor through a sampling circuit I L , and the positive input terminal of the voltage subtractor is connected to the output signal of the error amplifier V comp , the negative input terminal of the voltage subtractor is connected to the output terminal of the PFM judgment circuit through the PFM oscillator, and the output terminal of the PFM oscillator is also connected to the second input terminal of the logic control module;

[0023] The PWM comparator is configured to respond to the current of the inductor collected by the sampling circuit I L When it reaches the set peak value, control the output signal of the PWM comparator to change from low level to high level;

[0024] The high-side power transistor driver is arranged between the logic control module and the high-side power transistor, and is configured to respond to the output signal of the PWM comparator received to change from low level to high level, control the high-side power transistor to turn off, and respond to the signal received from the second output terminal of the logic control module to change from low level to high level, control the high-side power transistor to turn on;

[0025] The low-side power transistor driver is arranged between the logic control module and the low-side power transistor, and is configured to respond to the signal received from the third output terminal of the logic control module to change from low level to high level, control the low-side power transistor to turn on, and respond to the signal received from the third output terminal of the logic control module to change from high level to low level, control the low-side power transistor to turn off.

[0026] Further, the logic control module performs the following steps to complete the switching frequency control functions of the pulse frequency modulation mode and the supersonic mode respectively, and the mode switching function from the pulse frequency modulation mode to the supersonic mode:

[0027] In the pulse frequency modulation mode, place the output of the multiplexer at the first reference voltage, so that when the feedback signal V FB Is lower than or equal to the first reference voltage, the PFM clock signal received by the first input terminal of the logic control module changes from low level to high level;

[0028] In response to the PFM clock signal changing from low level to high level, control the signal of the second output terminal of the logic control module to change from low level to high level, so that the high-side power transistor turns on, and at the same time, reset the sleep mode start signal;

[0029] In response to the current of the inductor rising to reach the set peak value I peak , control the signal of the second output terminal of the logic control module to change from high level to low level, so that the high-side power transistor turns off;

[0030] In response to the output signal of the high-side power transistor driver changing from high level to low level, control the signal of the third output terminal of the logic control module to change from low level to high level, so that the low-side power transistor turns on;

[0031] When the current in the inductor drops to 0, control the signal at the third output terminal of the logic control module to change from high level to low level, so as to turn off the low-side power transistor and trigger the sleep mode;

[0032] Start the timer for the sleep mode until the designed time of the timer reaches the set threshold time, and trigger the ultra-audio frequency mode;

[0033] Place the output of the multiplexer at the second reference voltage;

[0034] Control the output signal at the third output terminal of the logic control module to change from low level to high level, so as to turn on the low-side power transistor and step down the feedback signal V FB ;

[0035] Control the third output terminal of the logic control module to output the in-phase signal of the real-time voltage signal V OUT and limit the frequency of the in-phase signal to a preset fixed frequency until the ultra-audio frequency mode corresponding to the current working cycle ends.

[0036] Further, the set threshold time is 29 μs, the first reference voltage V REF-1 is configured as 1.01 times the voltage detection threshold V REF , the second reference voltage V REF-2 is configured as 1.015 times the voltage detection threshold; and, the logic control module also performs the following steps to complete the switching function from the pulse width modulation mode to the pulse frequency modulation mode:

[0037] When the BUCK circuit is in the pulse width modulation mode, regularly obtain the output signal of the error amplifier V comp ;

[0038] Identify whether the output signal of the error amplifier V comp is lower than the third reference voltage V ref_comp , if so, control the BUCK circuit to switch from the pulse width modulation mode to the pulse frequency modulation mode, otherwise, continue the pulse width modulation mode.

[0039] The second aspect of the present disclosure provides an electronic device, and the electronic device is provided with the BUCK circuit according to any one of the first aspects of the present disclosure.

[0040] In the BUCK circuit provided by the embodiments of the present disclosure, a threshold hysteresis control strategy is introduced. When triggering the USM mode, the voltage detection threshold of the feedback signal is switched V FB to appropriately increase the voltage detection threshold of the feedback signal V FB so as to shorten the turn-on time of the low-side power transistor, achieving the purpose of reducing the fluctuation of the real-time voltage signal V OUT . Thus, the technical effect that a stable V OUT can be output during the back-and-forth switching between the USM mode and the PFM mode is realized, and further, the technical problem of unstable switching frequency caused by detection delay during the switching between the USM mode and the PFM mode in the related art is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a comparison schematic diagram of the switching frequencies of the BUCK circuits with and without the USM mode function in the related art;

[0043] Figure 2 It is a block diagram of the BUCK circuit provided by the embodiments of the present disclosure;

[0044] Figure 3 It is a block diagram of the composition of the mode control unit provided by the embodiments of the present disclosure;

[0045] Figure 4 It is an example schematic diagram of the BUCK circuit provided by the embodiments of the present disclosure;

[0046] Figure 5 It is the PFM mode core control logic of the BUCK circuit provided by the embodiments of the present disclosure;

[0047] Figure 6 It is the signal state diagram of the BUCK circuit in the PFM mode provided by the embodiments of the present disclosure;

[0048] Figure 7 It is the signal state diagram of the BUCK circuit in the USM mode provided by the embodiments of the present disclosure;

[0049] Figure 8 It is a block diagram of the electronic device provided by the embodiments of the present disclosure.

[0050] Reference numeral

[0051] F sw - Switching frequency; F sw_min - Minimum switching frequency; EA - Error amplifier; LSD - Low-side power transistor; LSDRV - Low-side power transistor driver; HSD - High-side power transistor; HSDRV - High-side power transistor driver; AMUX - Multiplexer; Timer - Timer; VDD - Power supply; PFM_CLK - PFM clock signal; USM Mode -; Control signal of the multiplexer; LSON - Signal at the third output terminal (within the logic control module); HSON - Signal at the second output terminal (within the logic control module); LSON - Signal at the third output terminal; HSON - Signal at the second output terminal; HS OFF - Output signal of the PWM comparator; HSGT - Control signal of the high-side power transistor; LSGT - Control signal of the low-side power transistor; Sleep - Sleep mode start signal; Sleep time - Duration of the sleep mode; ZC - Zero-crossing detection signal; SW - Switching signal; R C1 , R C2 , R F1 , R F2 , R L - Resistor; L - Inductor; V IN - Constant voltage; V OUT - Real-time voltage signal; V REF - Voltage detection threshold; V FB - Feedback signal; V comp - Output signal of the error amplifier; V REF_1 - First reference voltage; V REF_2 - Second reference voltage; V slope - Output signal of the PFM oscillator; C C - Capacitor; C OUT - Output capacitor; I L - Current of the inductor; Ipeak - Peak; 10 - BUCK circuit; 11 - Mode control unit; 12 - High-side power transistor; 13 - Low-side power transistor; 14 - Inductor; 15 - Output capacitor; 111 - Feedback signal acquisition module; 112 - Preprocessing module; 113 - Logic control module; 1 - Electronic device. Detailed implementation manners

[0052] To enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0054] In the present disclosure, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", etc. is based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit that the indicated device, element or component must have a specific orientation, or be constructed and operated in a specific orientation.

[0055] Moreover, in addition to being able to represent an orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present disclosure can be understood according to specific circumstances.

[0056] The term "pulse code modulation mode", abbreviated as PCM mode, and its full English name is Peak Current Mode, is a widely used DC-DC converter control method, mainly used to convert analog signals into digital signals.

[0057] The term "pulse width modulation mode", abbreviated as PWM mode, the full English name of PWM is Pulse Width Modulation, which is a technology that equivalently obtains the required waveform (including shape and amplitude) by modulating the widths of a series of pulses.

[0058] The term "pulse frequency modulation mode", abbreviated as PFM mode, the full English name of PFM is Pulse Frequency Modulation, which is a modulation technology that controls a circuit by adjusting the frequency at which pulses occur, rather than adjusting the width of the pulses as in PWM. This modulation method has higher efficiency under light external load conditions, but lower efficiency under heavy load conditions.

[0059] The term "ultrasonic mode", abbreviated as USM mode, the full English name is Ultrasonic Mode, which is a specific mode widely used in a variety of electronic devices, especially in application scenarios that require efficient energy conversion and control.

[0060] The term "switching frequency", that is, the switching frequencies of the high-side power transistor and the low-side power transistor in the BUCK circuit, where the high-side power transistor and the low-side power transistor switch at a fixed frequency, causing the inductor element to generate an uninterrupted current during the working cycle and forming a stable voltage at the output terminal.

[0061] The term "buck chopper circuit", abbreviated as BUCK circuit, is one of the basic DC-DC circuits used for DC-to-DC buck conversion.

[0062] The term "rheostat", abbreviated as RV, the full English name is Potentiometer, a precision electronic circuit that can adjust power and current, and its structure has a built-in variable resistance element.

[0063] The term "PFM oscillator" is an electronic device that can generate an alternating current signal. It can generate an output voltage of a sine wave or other waveforms by relying on self-excited oscillation of the circuit without an external input signal. The full English name of oscillator is Oscillator.

[0064] The term "multiplexer", abbreviated as AMUX, the full English name is Analog Multiplexer, which can connect multiple analog signals to a common analog signal or not connect analog signals.

[0065] The term "PWM comparator" is an electronic circuit whose main function is to generate a pulse width modulation PWM signal by comparing two voltage signals (usually a DC wave and a triangular wave).

[0066] The term "PFM judgment circuit" is a circuit device that compares an input signal with a first reference voltage and generates an electrical signal based on the comparison result, which can be implemented by a comparator.

[0067] The term "PFM clock generation circuit" is a circuit that modulates the clock frequency by adjusting the pulse width.

[0068] The term "sampling circuit" is a circuit that samples the current of an inductor I L for sampling.

[0069] The term "error amplifier", abbreviated as EA, mainly functions to amplify differential signals and suppress common-mode signals.

[0070] The term "critical USM mode" is an operating mode of a switching power supply, aiming to provide higher efficiency and lower losses. In this mode, the power switch device conducts when the inductor current reaches a critical value, which is determined by the relationship between the inductor and the output voltage. Once the inductor current drops to zero, the switch device turns off.

[0071] The term "sleep mode" is a mode in which the high-side power transistor and the low-side power transistor of the BUCK circuit are both turned off.

[0072] The term "duration of sleep mode" is the time period of the BUCK circuit in the sleep mode. For the BUCK circuit, reasonably setting the duration of the sleep mode can not only reduce the overall energy consumption but also extend the service life of the corresponding electronic device.

[0073] In addition, the terms "mount", "set", "provided with", "connected", "connected to" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there is internal communication between two devices, components or parts. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific situations.

[0074] It should be noted that, without conflict, the embodiments in this disclosure and the features in the embodiments can be combined with each other. The following will detail this disclosure with reference to the drawings and in combination with the embodiments.

[0075] In the related art, there is a technical problem of unstable switching frequency due to detection delay during the switching process between the USM mode and the PFM mode.

[0076] To solve the above technical problem, the embodiments of this disclosure provide a BUCK circuit with an ultra-audio frequency mode, such as Figure 2As shown, the BUCK circuit 10 includes a mode control unit 11, a high-side power transistor 12, a low-side power transistor 13, an inductor 14, and an output capacitor 15 connected in parallel with an external load.

[0077] The input terminal of the mode control unit 11 is connected to the output terminal of the inductor 14. One output terminal of the mode control unit 11 is connected to the gate of the high-side power transistor 12, and the second output of the mode control unit 11 is connected to the gate of the low-side power transistor 13. The source of the high-side power transistor 12 is divided into two paths. One path is connected to the drain of the low-side power transistor 13, and the other path is grounded after passing through the inductor 14 and the output capacitor 15 in sequence.

[0078] The mode control unit 11 has a feedback signal terminal connected to the output terminal of the inductor 14. The mode control unit 11 is configured to respond to the BUCK circuit triggering the ultra-audio frequency mode (USM mode), and based on the real-time voltage signal across the output capacitor 15 in the BUCK circuit V OUT increase the voltage detection threshold of the feedback signal at the feedback signal terminal by a set ratio, and based on the comparison result between the increased new voltage detection threshold and the feedback signal V FB control the state of the low-side power transistor, so as to reduce the fluctuation of the real-time voltage signal by shortening the on-time of the low-side power transistor 13 in the ultra-audio frequency mode V FB and, control the duration of the sleep mode of the BUCK circuit between the pulse frequency modulation mode (PFM mode) and the USM mode to always reach the set threshold time, where the feedback signal V OUT is configured to be related to the real-time voltage signal V FB V OUT .

[0079] It should be noted that in the related technology, in the USM mode, the mode control unit 11 controls the state of the low-side power transistor 13 based on the difference between the feedback signal V FB and the unchanged voltage detection threshold. In the embodiment of the present disclosure, the voltage detection threshold is adjusted based on the real-time voltage signal V OUT so that the on-time of the low-side power transistor 13 in the ultra-audio frequency mode is shortened, and the fluctuation of the real-time voltage signal V OUT becomes smaller. The drain of the high-side power transistor 12 can be connected to a power supply or a constant voltage V IN , and the source of the low-side power transistor 13 is grounded or set to a low voltage. The present disclosure does not limit this.

[0080] ​Some embodiments of the present disclosure also provide an electronic device corresponding to the above BUCK circuit.

[0081] The BUCK circuit provided by the embodiments of the present disclosure is applicable to any existing occasion that requires a BUCK circuit. Compared with the prior art, by applying the BUCK circuit provided by the embodiments of the present disclosure, a threshold hysteresis control strategy is introduced. When triggering the USM mode, the voltage detection threshold of the feedback signal is switched, and the voltage detection threshold of the feedback signal is appropriately increased to shorten the turn-on time of the low-side power transistor, achieving the purpose of reducing the fluctuation of the real-time voltage signal, thereby realizing the technical effect that stable output can be achieved when switching back and forth between the USM mode and the PFM mode, and further solving the technical problem of unstable switching frequency in the process of switching between the USM mode and the PFM mode in the related art. V FB wherein, specifically, the set ratio is configured to be obtained based on the estimated delay of the mode control unit 11, the parameters of the output capacitor 15, and the parameters of the inductor 14. The estimated delay is configured to be equal to the time length between the theoretical turn-off moment and the actual turn-off moment of the low-side power transistor 13, and the estimated delay is related to the real-time voltage signal. Exemplarily, the set ratio can obtain the optimal value through a deep learning network. V FB The switchable operating modes equipped in the mode control unit 11 include the PFM mode and the USM mode. Preferably, the switchable operating modes equipped in the mode control unit 11 further include the pulse width modulation mode (PWM mode), so that the mode control unit 11 has three operating modes: the PFM mode, the USM mode, and the PWM mode. V OUT On the basis of the method shown, preferably, the operating frequency of the BUCK circuit in the USM mode is a fixed frequency. And the mode control unit 11 is further configured to, when the BUCK circuit is in the PFM mode, in response to the current of the inductor 14 dropping to 0, control the low-side power transistor 13 to turn off, and at the same time automatically trigger the sleep mode, and in response to the duration of the sleep mode reaching the set threshold time, trigger the USM mode. Through this configuration, automatic switching from the PFM mode to the USM mode is achieved. V OUT In the process of switching between the USM mode and the PFM mode, the technical problem of unstable switching frequency is solved.

[0082] wherein, specifically, the set ratio is configured to be obtained based on the estimated delay of the mode control unit 11, the parameters of the output capacitor 15, and the parameters of the inductor 14. The estimated delay is configured to be equal to the time length between the theoretical turn-off moment and the actual turn-off moment of the low-side power transistor 13, and the estimated delay is related to the real-time voltage signal. Exemplarily, the set ratio can obtain the optimal value through a deep learning network. V OUT Exemplarily, the set ratio can obtain the optimal value through a deep learning network.

[0083] The switchable operating modes equipped in the mode control unit 11 include the PFM mode and the USM mode. Preferably, the switchable operating modes equipped in the mode control unit 11 further include the pulse width modulation mode (PWM mode), so that the mode control unit 11 has three operating modes: the PFM mode, the USM mode, and the PWM mode.

[0084] In Figure 2 Based on the method shown, preferably, the operating frequency of the BUCK circuit in the USM mode is a fixed frequency. And the mode control unit 11 is further configured to, when the BUCK circuit is in the PFM mode, in response to the current of the inductor 14 dropping to 0, control the low-side power transistor 13 to turn off, and at the same time automatically trigger the sleep mode, and in response to the duration of the sleep mode reaching the set threshold time, trigger the USM mode. Through this configuration, automatic switching from the PFM mode to the USM mode is achieved.

[0085] In Figure 2Based on the method shown in the figure, preferably, the mode control unit 11 is also configured to monitor the real-time voltage signal at regular intervals when the BUCK circuit is in the PWM mode. V OUT , identify real-time voltage signals V OUT When the voltage is lower than the first reference voltage, the BUCK circuit is controlled to switch from the PWM mode to the PFM mode, and when the BUCK circuit is in the PFM mode, the feedback signal is monitored. V FB , and based on the feedback signal V FB The comparison result with the voltage detection threshold controls the switching frequency of the BUCK circuit. With this configuration, automatic switching from PWM mode to PFM mode is achieved.

[0086] Figure 3 FIG. 1 is a block diagram of a mode control unit provided in an embodiment of the present disclosure. Figure 3 As shown, in order to achieve a better mode control effect, preferably, the mode control unit 11 includes a feedback signal acquisition module 111, a preprocessing module 112, and a logic control module 113 which are connected in sequence.

[0087] The feedback signal acquisition module 111 is configured to obtain the feedback signal based on the real-time voltage signal. V OUT Generate feedback signal V FB The feedback signal acquisition module 111 may be implemented in a software or hardware manner.

[0088] The preprocessing module 112 is configured to convert the feedback signal V FB The voltage detection threshold is compared, and a PFM clock signal is generated based on the comparison result and sent to the logic control module 113. The pre-processing module 112 can also be implemented in software or hardware.

[0089] The logic control module 113 is configured to trigger the USM mode in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor 15 in the BUCK circuit. V OUT The feedback signal at the feedback signal end V FB The voltage detection threshold is increased by a set ratio, and the state of the low-side power tube 13 is controlled based on the level conversion of the PFM clock signal, and the sleep mode start signal built into the logic control module 113 is reset.

[0090] exist Figure 3Based on the pattern control unit shown, preferably, the feedback signal acquisition module 111 is configured to include a voltage dividing circuit. The voltage detection threshold is reduced through the voltage dividing circuit.

[0091] On Figure 3 Based on the pattern control unit shown, preferably, the preprocessing module 112 includes an error amplifier, a PFM judgment circuit, a PFM clock generation circuit, and a multiplexer. Among them, the first input terminal of the multiplexer is connected to a first reference voltage, the second input terminal of the multiplexer is connected to a second reference voltage, the control terminal of the multiplexer is connected to the first output terminal of the logic control module 113, and the output terminal of the multiplexer is connected to the positive input terminal of the PFM clock generation circuit. The positive input terminal of the error amplifier is connected to the voltage detection threshold V REF , the negative input terminal of the error amplifier is connected to the output terminal of the voltage dividing circuit, and the output terminal of the error amplifier is connected to the negative input terminal of the PFM judgment circuit. The positive input terminal of the PFM judgment circuit is connected to the first reference voltage, and the output terminal of the PFM judgment circuit is connected to the enable terminal of the PFM clock generation circuit. The output terminal of the PFM clock generation circuit is connected to the first input terminal of the logic control module 113. Among them, the first reference voltage and the second reference voltage are respectively configured as different setting ratios of the voltage detection threshold V REF , and the value of the first reference voltage is less than the value of the second reference voltage.

[0092] The PFM judgment circuit is configured to respond to the output signal of the error amplifier V comp When it is lower than the first reference voltage, an enable signal is sent to the PFM clock generation circuit.

[0093] The PFM clock generation circuit is configured to generate a PFM clock signal in response to the above enable signal and send it to the logic control module 113.

[0094] Based on the configuration of the above preprocessing module 112, preferably, the preprocessing module 112 is further configured with an RC filter circuit, a PWM comparator, a PFM oscillator, and a voltage subtractor. Among them, the RC filter circuit is arranged between the error amplifier and the PFM judgment circuit. The positive input terminal of the PWM comparator is connected to the output terminal of the voltage subtractor, and the negative input terminal of the PWM comparator is connected to the current of the inductor 14 through a sampling circuit I L . The positive input terminal of the voltage subtractor is connected to the output signal of the error amplifier V comp , the negative input terminal of the voltage subtractor is connected to the output terminal of the PFM judgment circuit through the PFM oscillator. The output terminal of the PFM oscillator is also connected to the second input terminal of the logic control module 113.

[0095] The PWM comparator is configured to respond to the current of inductor 14 collected by the sampling circuit I L When reaching the set peak value, control the output signal of the PWM comparator to change from low level to high level.

[0096] Based on the mode control unit shown in Figure 3 Preferably, the BUCK circuit further includes a high-side power transistor driver and a low-side power transistor driver.

[0097] The high-side power transistor driver is arranged between the logic control module 113 and the high-side power transistor 12, and is configured to control the high-side power transistor 12 to turn off in response to the output signal of the received PWM comparator changing from low level to high level, and to control the high-side power transistor 12 to turn on in response to the signal at the second output terminal of the received logic control module 113 changing from low level to high level.

[0098] The low-side power transistor driver is arranged between the logic control module 113 and the low-side power transistor 13, and is configured to control the low-side power transistor 13 to turn on in response to the signal at the third output terminal of the received logic control module 113 changing from low level to high level, and to control the low-side power transistor 13 to turn off in response to the signal at the third output terminal of the received logic control module 113 changing from high level to low level.

[0099] As a preferred implementation manner, the logic control module 113 executes the following steps S11 - step S12 to complete the switching function from PWM mode to PFM mode and the mode switching function from PFM mode to USM mode:

[0100] Step S11: When the BUCK circuit is in PWM mode, periodically obtain the output signal of the error amplifier V comp .

[0101] Step S12: Identify the output signal of the error amplifier V comp Whether it is lower than the third reference voltage V ref_comp , if so, control the BUCK circuit to switch from PWM mode to PFM mode, otherwise, continue with the PWM mode.

[0102] Through the above steps S11 - step S12, when V comp <the third reference voltage V ref_comp , the system will switch from PWM mode to PFM operating mode. This PFM mode detects V FB the lower limit voltage (1.01 VREF ) to control the switching frequency, while the peak value I peak is fixed, that is, the control in the PFM mode can be realized based on the ripple control principle.

[0103] As a preferred implementation manner, the logic control module 113 executes the following steps S21 - step S26 to complete the switching frequency control function of the PFM mode:

[0104] Step S21: In the PFM mode, set the output of the multiplexer to the first reference voltage, so that when the feedback signal V FB is lower than or equal to the first reference voltage, the PFM clock signal received by the first input end of the logic control module 113 changes from low level to high level.

[0105] Step S22: In response to the PFM clock signal changing from low level to high level, control the signal at the second output end of the logic control module 113 to change from low level to high level, so that the high-side power transistor 12 is turned on, and at the same time, reset the sleep mode start signal Sleep.

[0106] Step S23: In response to the current of the inductor 14 rising to the set peak value I peak , control the signal at the second output end of the logic control module 113 to change from high level to low level, so that the high-side power transistor 12 is turned off.

[0107] Step S24: In response to the output signal of the high-side power transistor driver changing from high level to low level, control the signal at the third output end of the logic control module 113 to change from low level to high level, so that the low-side power transistor 13 is turned on.

[0108] Step S25: In response to the current of the inductor 14 dropping to 0, control the signal at the third output end of the logic control module 113 to change from high level to low level, so that the low-side power transistor 13 is turned off and trigger the sleep mode.

[0109] Step S26: Start the timer of the sleep mode until the design of the timer reaches the set threshold time, and trigger the USM mode.

[0110] Through the above steps S21 - step S26, when V FB ≤ 1.01 V REF is reached, output the PFM clock signal, turn on the high-side power transistor 12 and reset the sleep mode signal at the same time. When the peak value is triggered I peakTurn off the high-side power transistor 12 at the right time. At the same time, when it is detected that the voltage of the high-side power transistor driver is low (the high-side power transistor 12 is turned off), the output signal HSOFF of the PWM comparator in Figure 4 will set the LSON signal to 1, turn on the low-side power transistor 13. Until the current of the inductor 14 drops to zero, reset the LSON signal to 0, turn off the low-side power transistor 13. At this time, trigger the sleep mode and enable the 29 μs timer. If the duration of the sleep mode is less than 29 μs, the USM mode will not be triggered, and at this time, continue to work in the PFM mode.

[0111] As a preferred implementation, the logic control module 113 executes the following steps S31 - step S33 to complete the switching frequency control function of the USM mode:

[0112] Step S31: Set the output of the multiplexer to the second reference voltage.

[0113] Step S32: Control the output signal of the third output terminal of the logic control module 113 to change from low level to high level, so as to turn on the low-side power transistor 13 and step down the feedback signal V FB

[0114] Step S33: Control the third output terminal of the logic control module 113 to output a signal with the same frequency as the real-time voltage signal V OUT and limit the frequency of the signal with the same frequency to a preset fixed frequency until the USM mode corresponding to the current working cycle ends.

[0115] Through the above steps S31 - step S33, when the duration of the sleep mode reaches 29 μs, the USM mode is triggered at this time. Figure 4 The LSON signal in V OUT is set to 1, the low-side power transistor 13 is turned on, and the inductor current flows in from the low-side power transistor 13 in the reverse direction, quickly discharging the real-time output signal V FB forcing

[0116] Figure 4 to be lower than the reference voltage, thereby outputting a PFM clock signal. At this time, turn off the low-side power transistor 13 and turn on the high-side power transistor 12, and repeat this cycle to limit the frequency to 30 kHz. Figure 5 This is a schematic diagram of an example of the BUCK circuit provided by the embodiment of the present disclosure. The functions of each component have been described in detail above and will not be repeated. The core control logic of its PFM mode is as Figure 6 shown, and the signal states of each component of the BUCK circuit in the PFM mode are as Figure 7 ​As shown, it can be seen that the output of the BUCK circuit provided by the embodiments of the present disclosure has better switching stability compared with the related art.

[0117] In some embodiments of the present disclosure, preferably, the threshold time is set to 29 μs, and the first reference voltage V REF-1 is configured to be 1.01 times the voltage detection threshold V REF , and the second reference voltage V REF-2 is configured to be 1.015 times the voltage detection threshold.

[0118] From the above description, it can be seen that the present disclosure achieves the following technical effects:

[0119] 1. Provide a control strategy for switching between the USM mode and the PFM mode. To solve the problem that the chip switches back and forth between the USM mode and the PFM mode in the critical USM mode, a threshold hysteresis control strategy is introduced, that is, when triggering the USM mode, the voltage detection threshold of V FB is switched, and the voltage detection threshold of V FB is increased by about 0.005% to trigger the PFM clock signal in advance, so that V OUT the ripple is increased by 0.005% in the USM mode, so that the duration of the sleep mode can reach 29 μs in each cycle, thereby avoiding the back-and-forth switching between the USM mode and the PFM mode, and at the same time being able to resist the turn-off delay of the low-side power transistor.

[0120] 2. Prevent the switching frequency instability phenomenon caused by the chip switching back and forth between the USM mode and the PFM mode. The switching frequency is stabilized at 30 kHz, and audible noise is eliminated.

[0121] 3. The output signal V OUT的 has lower ripple, the voltage ripple is reduced by 20%, and the system efficiency is increased by 10%. Especially in the critical load scenario, the output stability is significantly improved.

[0122] 4. It can be compatible with small inductor designs, expanding the application scenarios.

[0123] It should be noted that the above steps can be executed in a computer system such as a set of computer-executable instructions, and although the above steps show a logical order, in some cases, the steps shown or described can be executed in a different order than here.

[0124] The embodiments of the present disclosure also provide an electronic device for implementing the above BUCK circuit embodiments. As Figure 8 shown, the electronic device 1 includes the BUCK circuit 10 of the above embodiments.

[0125] The specific manner of the execution operation of the BUCK circuit in the above device embodiment has been described in detail in the embodiment related to the BUCK circuit, and will not be elaborated here.

[0126] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A BUCK circuit with an ultra-high frequency mode, characterized in that: It includes a mode control unit, a high-side power tube, a low-side power tube, an inductor, and an output capacitor connected in parallel with an external load; wherein, The input end of the mode control unit is connected to the output end of the inductor, the output end 1 of the mode control unit is connected to the gate of the high-side power tube, the output end 2 of the mode control unit is connected to the gate of the low-side power tube, and the source of the high-side power tube is divided into two paths, one path is connected to the drain of the low-side power tube, and the other path is connected to the ground after passing through the inductor and the output capacitor in sequence; The mode control unit has a built-in feedback signal terminal connected to the output terminal of the inductor, and the mode control unit is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal at both ends of the output capacitor in the BUCK circuit. V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the new voltage detection threshold after the increase is combined with the feedback signal V FB The comparison result controls the state of the low-side power tube to reduce the real-time voltage signal by shortening the opening time of the low-side power tube in the super audio mode. V OUT The feedback signal V FB is configured with the real-time voltage signal V OUT The setting ratio is configured to be obtained based on the estimated delay of the mode control unit, the parameters of the output capacitor, and the parameters of the inductor. The estimated delay is configured to be equal to the time length between the theoretical shutdown time and the actual shutdown time of the low-side power tube, and the estimated delay is configured to be equal to the real-time voltage signal V OUT Related.

2. The BUCK circuit according to claim 1, characterized in that: The operating frequency of the BUCK circuit in the super audio mode is a fixed frequency; and The mode control unit is also configured to, when the BUCK circuit is in the pulse frequency modulation mode, control the low-side power tube to shut down in response to the current of the inductor dropping to 0, and automatically trigger the sleep mode, and, in response to the duration of the sleep mode reaching the set threshold time, automatically trigger the super audio mode.

3. The BUCK circuit according to claim 2, characterized in that: The switchable working modes provided in the mode control unit include pulse width modulation mode, pulse frequency modulation mode, and ultrasonic mode; and, The mode control unit is further configured to periodically monitor the real-time voltage signal when the BUCK circuit is in the pulse width modulation mode. V OUT , identify the real-time voltage signal V OUT When the voltage is lower than the first reference voltage, the BUCK circuit is controlled to switch from the pulse width modulation mode to the pulse frequency modulation mode, and when the BUCK circuit is in the pulse frequency modulation mode, the feedback signal is monitored. V FB , and based on the feedback signal V FB The comparison result with the voltage detection threshold controls the switching frequency of the BUCK circuit.

4. The BUCK circuit according to claim 3, characterized in that: The mode control unit comprises: A feedback signal acquisition module is configured to obtain a feedback signal based on the real-time voltage signal V OUT Generate the feedback signal V FB ; The preprocessing module is configured to convert the feedback signal V FB Compare with the voltage detection threshold, and generate a PFM clock signal based on the comparison result and send it to the logic control module; and, The logic control module is configured to trigger the super audio mode in response to the BUCK circuit, based on the real-time voltage signal across the output capacitor in the BUCK circuit. V OUT The feedback signal at the feedback signal terminal V FB The voltage detection threshold is increased by a set ratio, and the state of the low-side power tube is controlled based on the level conversion of the PFM clock signal, and the sleep mode start signal built into the logic control module is reset.

5. The BUCK circuit according to claim 4, characterized in that: The feedback signal acquisition module includes a voltage divider circuit; and, The preprocessing module includes an error amplifier, a PFM judgment circuit, a PFM clock generating circuit and a multiplexer, wherein the first input terminal of the multiplexer is connected to a first reference voltage, the second input terminal of the multiplexer is connected to a second reference voltage, the control terminal of the multiplexer is connected to a first output terminal of the logic control module, the output terminal of the multiplexer is connected to a positive input terminal of the PFM clock generating circuit, and the positive input terminal of the error amplifier is connected to a voltage detection threshold V REF , the negative input terminal of the error amplifier is connected to the output terminal of the voltage divider circuit, the output terminal of the error amplifier is connected to the negative input terminal of the PFM judgment circuit, and the positive input terminal of the PFM judgment circuit is connected to the first reference voltage, the output terminal of the PFM judgment circuit is connected to the enable terminal of the PFM clock generation circuit, and the output terminal of the PFM clock generation circuit is connected to the first input terminal of the logic control module, wherein the first reference voltage and the second reference voltage are respectively configured as the voltage detection threshold V REF The value of the first reference voltage is smaller than the value of the second reference voltage according to different setting ratios; and The PFM determination circuit is configured to respond to the output signal of the error amplifier V comp When the voltage is lower than the first reference voltage, an enable signal is sent to the PFM clock generating circuit; The PFM clock generating circuit is configured to generate the PFM clock signal in response to the enable signal and send the PFM clock signal to the logic control module.

6. The BUCK circuit according to claim 5, characterized in that: The pre-processing module is also configured with an RC filter circuit, a PWM comparator, a PFM oscillator, a voltage subtractor, and the BUCK circuit also includes a high-side power tube driver and a low-side power tube driver; wherein, The RC filter circuit is arranged between the error amplifier and the PFM judgment circuit, and the positive input terminal of the PWM comparator is connected to the output terminal of the voltage subtractor, and the negative input terminal of the PWM comparator is connected to the current of the inductor through the sampling circuit. I L , and the positive input terminal of the voltage subtractor is connected to the output signal of the error amplifier V comp , the negative input end of the voltage subtractor is connected to the output end of the PFM judgment circuit via the PFM oscillator, and the output end of the PFM oscillator is also connected to the second input end of the logic control module; The PWM comparator is configured to respond to the current of the inductor collected by the sampling circuit. I L When the set peak value is reached, the output signal of the PWM comparator is controlled to change from a low level to a high level; The high-side power tube driver is arranged between the logic control module and the high-side power tube, and is configured to control the high-side power tube to be turned off in response to the received output signal of the PWM comparator changing from a low level to a high level, and to control the high-side power tube to be turned on in response to the received signal of the second output terminal of the logic control module changing from a low level to a high level; The low-side power tube driver is arranged between the logic control module and the low-side power tube, and is configured to control the low-side power tube to turn on in response to the signal received from the third output terminal of the logic control module changing from a low level to a high level, and to control the low-side power tube to turn off in response to the signal received from the third output terminal of the logic control module changing from a high level to a low level.

7. The BUCK circuit according to claim 6, characterized in that: The logic control module performs the following steps to complete the switching frequency control functions of the pulse frequency modulation mode and the super audio mode and the mode switching function from the pulse frequency modulation mode to the super audio mode: In the pulse frequency modulation mode, the output of the multiplexer is set to the first reference voltage so that when the feedback signal V FB When the voltage is lower than or equal to the first reference voltage, the PFM clock signal received by the first input terminal of the logic control module changes from a low level to a high level; In response to the PFM clock signal changing from a low level to a high level, controlling the signal at the second output terminal of the logic control module to change from a low level to a high level, so that the high-side power tube is turned on, and at the same time, the sleep mode start signal is reset; In response to the inductor current rising to reach the set peak I peak , controlling the signal at the second output terminal of the logic control module to change from a high level to a low level, so as to turn off the high-side power tube; In response to the output signal of the high-side power tube driver changing from a high level to a low level, controlling the signal of the third output terminal of the logic control module to change from a low level to a high level, so that the low-side power tube is turned on; In response to the current of the inductor dropping to 0, controlling the signal of the third output terminal of the logic control module to change from a high level to a low level, so as to turn off the low-side power tube and trigger a sleep mode; Starting a timer of the sleep mode until the timer reaches the set threshold time, triggering the super audio mode; placing the output of the multiplexer at the second reference voltage; The output signal of the third output terminal of the logic control module is controlled to change from a low level to a high level, so that the low-side power tube is turned on, and the feedback signal V FB Performing blood pressure reduction; and, Control the third output terminal of the logic control module to output the real-time voltage signal V OUT and limiting the frequency of the same-frequency signal to a preset fixed frequency until the ultrasonic audio mode corresponding to this working cycle ends.

8. The BUCK circuit according to any one of claims 5 to 7, characterized in that: The threshold time is set to 29 μs, and the first reference voltage V REF-1 is configured as the voltage detection threshold V REF 1.01 times the second reference voltage V REF-2 is configured to be 1.015 times the voltage detection threshold; and the logic control module further performs the following steps to complete the switching function from the pulse width modulation mode to the pulse frequency modulation mode: When the BUCK circuit is in the pulse width modulation mode, the output signal of the error amplifier is obtained regularly. V comp ; Identify the error amplifier output signal V comp Is it lower than the third reference voltage? V ref_comp If so, control the BUCK circuit to switch from the pulse width modulation mode to the pulse frequency modulation mode; otherwise, continue with the pulse width modulation mode.

9. An electronic device, characterized in that: The electronic device is provided with the BUCK circuit described in any one of claims 1 to 8.

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