A global soft-switching DAB topology and control method suitable for a wide voltage range

Abstract

The present application provides a global soft-switching DAB topology suitable for a wide voltage range, including: an input side bridge arm group, a transformer group and an output side bridge arm group; a control method implemented by the topology, including during a half switching cycle, under different working stages, under the control of different current paths, under the premise of ensuring a wide voltage gain, not only expanding the ZVS range, but also by optimizing current stress, further reducing current-related losses, thereby improving the operating efficiency of the entire converter.

Description

Technical Field

[0001] The present application relates to the technical field of power systems, and in particular to a global soft-switch DAB topology and control method applicable to a wide voltage range. Background Art

[0002] Bidirectional DC-DC converters are important power interfaces in many power applications, such as energy storage systems, electric vehicle chargers, and power distribution systems. Among them, the dual active bridge (DAB) DC-DC converter has become an ideal choice for the above applications since it was first proposed due to its advantages such as zero voltage switching (ZVS), high power density, bidirectional power transmission, electrical isolation, and symmetrical structure.

[0003] At present, power transmission is achieved by adjusting the phase shift angle between the high-frequency voltages generated by the two bridges of DAB. The commonly used single-phase shift (SPS) control method is simple and can achieve full-range zero voltage switching (ZVS), low peak current and low circulating current at the optimal operating point, but it will lead to high peak current, large RMS current and reduced ZVS range under non-optimal gain conditions. Dual-phase shift (DPS) and three-phase shift (TPS) control use two duty cycles to further optimize performance. Although these methods can achieve performance improvements, they often require complex power calculations and are highly dependent on system parameters. To simplify control and extend the ZVS range, boundary trapezoidal modulation and a general model based on the basic optimal strategy have been proposed, but their effectiveness in a wide voltage gain range has not been fully verified. For applications such as photovoltaic and energy storage systems, the battery voltage varies widely, making control over a wide voltage gain range a key challenge. The traditional DAB topology has a contradiction between a wide ZVS range and simplified control. The improved dual-transformer structure can achieve a wider ZVS range and reduce the filter size, but complexity and power unidirectionality are still limitations. Optimizing control strategies over a wide voltage gain range is critical for high-performance energy storage and charging applications.

[0004] In view of this, it is difficult for existing DAB converters to simultaneously achieve a wide ZVS range and low loss over a wide voltage gain range. Summary of the invention

[0005] In order to overcome the above technical defects, the present application provides a global soft-switching DAB topology and control method applicable to a wide voltage range. To achieve the above purpose, the present application is implemented according to the following technical solutions:

[0006] In a first aspect, the present application provides a global soft-switching DAB topology applicable to a wide voltage range, comprising: an input-side bridge arm group, a transformer group, and an output-side bridge arm group;

[0007] The input side bridge arm group includes an input capacitor bridge arm, a main power bridge arm and an auxiliary power bridge arm. The input voltage V 1The positive and negative electrodes are connected to the two ends of the input capacitor bridge arm and the auxiliary power bridge arm in sequence, wherein the input capacitor bridge arm includes a series-connected input split filter capacitor C 1 and input split filter capacitors C 2 , C 1 The negative electrode and C 2 The node formed by connecting the positive electrodes is C, and the main power bridge arm includes a MOSFET connected in series S 5 and S 6 ,and S 5 and S 6 Contains anti-parallel diodes, S 6 The direction of the anti-parallel diode in is from source to drain, S 5 The direction of the anti-parallel diode in is from drain to source, S 5 The drains of C 1 The negative electrode and C 2 At the positive pole of the secondary power bridge arm, the secondary power bridge arm includes a MOSFET connected in series S 1 and S 2 , MOSFETs in series S 3 and S 4 ,and S 1 , S 2 , S 3 and S 4 They all contain anti-parallel diodes. S 1 The source and S 2 The node formed by connecting the drain of S 3 The source of S 4 The drain and S 5 The node formed by connecting the source of is B;

[0008] The transformer group includes the main power transformer T r1 , Auxiliary power transformerT r2 , AC inductance L k and DC blocking capacitors C dc , T r1 Primary negative electrode and DC blocking capacitor C dc One end of the capacitor is connected to the C dc The other end of is connected to node B. T r2 Primary positive and T r1 The positive pole of the primary side is connected to node A respectively. T r2 The primary negative electrode is connected to node C. T r1 Secondary positive pole and AC inductor L k One end is connected to T r1 The secondary negative electrode and T r2 The secondary side positive pole is connected;

[0009] The output side bridge arm group includes two MOSFETs connected in series Q 1 and Q 2 , two split filter capacitors in series C 3 and C 4 ,and Q 1 and Q 2 They all contain anti-parallel diodes. Q 1 The source and Q 2 The node formed by connecting the drain of L k The other end is connected to C 3 Negative electrode and C 4 The node formed by connecting the positive electrodes is G, and the node G is connected to T r2 The negative pole of the secondary side is connected, V 2 The positive electrode is Q 1 Drain and C 3 Positive pole connected, V 2 The negative electrode is Q2 The source and C 4 Negative pole connected.

[0010] Optionally, in the input side bridge arm, the input voltage V 1 The positive pole of the split filter capacitor is C 1 positive electrode, S 1 The drain and S 3 The drain is connected to the input voltage V 1 The negative pole of the split filter capacitor C 2 The negative electrode, S 2 The source and S 4 The source is connected.

[0011] In a second aspect, the present application provides a control method for a global soft switching DAB topology applicable to a wide voltage range, applying the global soft switching DAB topology applicable to a wide voltage range as described in any one of the first aspects, including: a PWM signal is symmetrical during two half switching cycles, and during one half switching cycle, it is divided into 9 working stages:

[0012] Phase 1: t 0 - t 1 ],exist t 0 Moment, switch S 1 On, switch tube S 1 , S 4 , S 5 , Q 2 Work, at this stage, v AB equal V 1 , v AC equal V 1 / 2, total voltage on the secondary side of the dual transformer v DE for n 1 V 1 + n 2 V 1 / 2, the high-frequency voltage generated by the secondary half-bridge v FG = -V 2 / 2, transformer current i k Start increasing at a first constant rate, t 0 The moment is the moment when the current half switching cycle starts. v DE is the series voltage of the secondary sides of the two transformers, v FG is the voltage generated by the secondary full bridge;

[0013] Phase 2: t 1 - t 2 ],exist t 1 Moment, switch Q 2 The transformer current starts to Q 1 The junction capacitor is discharged and Q 2 The junction capacitor is charged; when Q 2 The junction capacitor is charged to V 2 When the switch Q 1 The drain-source voltage is discharged to 0, then Q 1 The body diode will conduct, and the next stage Q 1 The conduction creates the zero voltage turn-on condition;

[0014] Phase 3: t 2 - t 3 ],exist t 2 Moment, switch Q 1 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE equal n 1 V 1 + n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG for V2 / 2, transformer current i k increasing at a second constant rate, wherein the second constant rate is less than the first constant rate;

[0015] Phase 4: t 3 - t 4 ],exist t 3 Moment, switch S 4 The transformer current starts to S 3 and S 6 The junction capacitor is discharged and S 4 The junction capacitor is charged; when the switch S 4 The junction capacitor is charged to V 2 After / 2, S 3 The junction capacitor is discharged to V 2 / 2, S 6 The junction capacitor discharges to 0, the switch S 6 The body diode will conduct, and the next stage S 6 The conduction creates the zero voltage turn-on condition;

[0016] Phase 5: t 4 - t 5 ],exist t 4 Moment, switch S 6 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE Change to n 1 V 1 / 2+ n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG Same as stage 3, transformer current i k beginning to decrease at a third constant rate;

[0017] Phase 6: t 5 - t 6 ],exist t 5 Moment, switch S 5 The transformer current starts to S 3 The junction capacitor is discharged and S 5 and S 4 The junction capacitor is charged; when S 4 The junction capacitor is charged to V 2 , S 5 The junction capacitor is charged to V 2 / 2, switch S 3 The drain-source voltage is discharged to 0, then S 3 The body diode will conduct, and the next stage S 3 The conduction creates the zero voltage turn-on condition;

[0018] Phase 7: t 6 - t 7 ],exist t 6 Moment, switch S 3 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE equal n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG equal V 2 / 2, transformer current i k decreasing at a fourth constant rate, wherein the fourth constant rate is less than the third constant rate;

[0019] Phase 8: t 7 - t 8 ],exist t 7 Moment, switch S 1The transformer current starts to S 2 The junction capacitor is discharged and S 1 The junction capacitor is charged; when S 2 The junction capacitor is charged to V 2 When the switch S 1 The drain-source voltage is discharged to 0, then S 1 The body diode will conduct, and the next stage S 2 The conduction creates the zero voltage turn-on condition;

[0020] Stage 9: t 8 After the time], t 8 Moment, switch S 2 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE becomes - n 1 V 1 - n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG Same as stage 8, transformer current i k The fifth constant rate is decreased at a fifth constant rate, the fifth constant rate is equal to the first constant rate, and the fifth constant rate is greater than the fourth rate.

[0021] Optionally, the transformer current i k The relationship for increasing at the first constant rate is:

[0022] .

[0023] Optionally, the Q 1 The zero voltage switching condition is:

[0024] .

[0025] Optionally, the transformer current i k The relationship for increasing at the second constant rate is:

[0026] .

[0027] Optionally, the S 6 The zero voltage switching condition is:

[0028] .

[0029] Optionally, the transformer current i k The relationship for decreasing at the third constant rate is:

[0030] .

[0031] Optionally, the S 3 The zero voltage switching condition is:

[0032] .

[0033] Optionally, the transformer current i k The relationship for decreasing at the fourth constant rate is:

[0034] .

[0035] Optionally, the S 2 The zero voltage switching condition is:

[0036] .

[0037] Optionally, the transformer current i k The relationship for decreasing at the fifth constant rate is:

[0038] .

[0039] This application has the following beneficial effects:

[0040] Compared with other DAB converters with the same number of switches and control freedom, the proposed topology for a global soft-switching DAB topology suitable for a wide voltage range not only expands the ZVS range under the premise of ensuring a wide voltage gain, but also further reduces the current-related losses by optimizing the current stress, thereby improving the operating efficiency of the entire converter. The proposed topology shows excellent performance in dynamic response and can quickly adapt to input voltage fluctuations and load changes. With its fast response speed and high regulation accuracy, the stability and reliability of the system are effectively improved. The control method for a global soft-switching DAB topology suitable for a wide voltage range proposed in this application only relies on the input voltage and output voltage, without the need for operating area classification, thereby significantly reducing the dependence on converter parameters. This design improves the reliability of control.

[0041] In addition to the above-described purposes, features and advantages, the present application has other purposes, features and advantages. The present application will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0043] Figure 1 This is a schematic diagram of a global soft-switch DAB topology structure applicable to a wide voltage range provided in an embodiment of the present application;

[0044] Figure 2 In a half cycle provided by the embodiment of the present application, when 0< D φ < D 1 < D 2 <0.5, schematic diagram of DAB converter working waveform;

[0045] FIG. 3 (a) is a diagram of an embodiment of the present application. t 0 - t 1 Schematic diagram of the current path at the moment;

[0046] FIG. 3( b ) is a diagram of an embodiment of the present application. t 1 - t 2 Schematic diagram of the current path at the moment;

[0047] FIG. 3 (c) is provided in an embodiment of the present application t 2 - t3 Schematic diagram of the current path at the moment;

[0048] FIG. 3( d ) is provided in an embodiment of the present application. t 3 - t 4 Schematic diagram of the current path at the moment;

[0049] FIG. 3 (e) is provided in an embodiment of the present application t 4 - t 5 Schematic diagram of the current path at the moment;

[0050] FIG. 3( f ) is provided in an embodiment of the present application. t 5 - t 6 Schematic diagram of the current path at the moment;

[0051] FIG. 3( g ) is provided in the embodiment of the present application. t 6 - t 7 Schematic diagram of the current path at the moment;

[0052] FIG. 3 (h) is provided in an embodiment of the present application t 7 - t 8 Schematic diagram of the current path at the moment;

[0053] FIG. 3 (i) is provided in an embodiment of the present application t 8 Schematic diagram of the current path after time;

[0054] Figure 4 is a closed-loop control block diagram within one and a half cycles provided for an embodiment of the present application;

[0055] FIG5(a) is a diagram of an embodiment of the present application. V 1 = Experimental waveform at 120V;

[0056] FIG5(b) is a diagram of the embodiment of the present application. V 1 = Experimental waveform at 160V;

[0057] FIG5(c) is a diagram of the embodiment of the present application. V 1 = Experimental waveform at 200V;

[0058] FIG5(d) is a diagram of the embodiment of the present application. V1 = Experimental waveform at 240V;

[0059] Figure 6 is the input voltage provided in the embodiment of the present application V 1 =180V, the experimental waveform when the load is switched from 1kW to 500W. DETAILED DESCRIPTION

[0060] The embodiments of the present application are described in detail below with reference to the accompanying drawings; however, the present application can be implemented in many different ways as defined and covered by the claims.

[0061] In order to solve the problems raised in the background technology, such as Figure 1 As shown, the present application proposes a global soft switch DAB topology suitable for a wide voltage range, including: an input side bridge arm group, a transformer group and an output side bridge arm group; the input side bridge arm group includes an input capacitor bridge arm, a main power bridge arm and an auxiliary power bridge arm, and the input voltage V 1 The positive and negative electrodes are connected to the two ends of the input capacitor bridge arm and the auxiliary power bridge arm in sequence, wherein the input capacitor bridge arm includes a series-connected input split filter capacitor C 1 and input split filter capacitors C 2 , C 1 The negative electrode and C 2 The node formed by connecting the positive electrodes is C, and the main power bridge arm includes a MOSFET connected in series S 5 and S 6 ,and S 5 and S 6 Contains anti-parallel diodes, S 6 The direction of the anti-parallel diode in is from source to drain, S 5 The direction of the anti-parallel diode in is from drain to source, S 5 The drains of C 1 The negative electrode and C 2 At the positive pole of the secondary power bridge arm, the secondary power bridge arm includes a MOSFET connected in series S 1 and S 2 , MOSFETs in series S 3 and S4 , S 1 The source and S 2 The node formed by connecting the drain of S 3 The source of S 4 The drain and S 5 The node formed by connecting the source of is B;

[0062] The transformer group includes the main power transformer T r1 , Auxiliary power transformer T r2 , AC inductance L k and DC blocking capacitors C dc , T r1 Primary negative electrode and DC blocking capacitor C dc One end of the capacitor is connected to the C dc The other end of is connected to node B. T r2 Primary positive and T r1 The positive pole of the primary side is connected to node A respectively. T r2 The primary negative electrode is connected to node C. T r1 Secondary positive pole and AC inductor L k One end is connected to T r1 The secondary negative electrode and T r2 The secondary side positive pole is connected;

[0063] The output side bridge arm group includes two MOSFETs connected in series Q 1 and Q 2 , two split filter capacitors in series C 3 and C 4 , Q 1 The source and Q 2 The node formed by connecting the drain of L k The other end is connected to C 3 Negative electrode andC 4 The node formed by connecting the positive electrodes is G, and the node G is connected to T r2 The negative pole of the secondary side is connected, V 2 The positive electrode is Q 1 Drain and C 3 Positive pole connected, V 2 The negative electrode is Q 2 The source and C 4 Negative pole connected.

[0064] Among them, in the input side bridge arm, the input voltage V 1 The positive pole of the split filter capacitor is C 1 positive electrode, S 1 The drain and S 3 The drain is connected to the input voltage V 1 The negative pole of the split filter capacitor C 2 The negative electrode, S 2 The source and S 4 The source is connected.

[0065] Simple Figure 1 The topological structure is summarized as follows: C 1 , C 2 is the input split filter capacitor, C 3 , C 4 is the output filter capacitor. V 1 and V 2 Indicates the voltage switch tubes on both sides of the converter S 1 ~ S 6 and Q 1 ~ Q 2 It forms the active switch branches on both sides, and the AC inductor L k represents the sum of the transformer leakage inductance and external AC inductance reflected to the secondary side, C dc It is a DC blocking capacitor. The two sides are connected in parallel by the primary side and in series by the secondary side. Tr1 and T r2 The turns ratios of the two are n 1 = N 1.Tr1 / N 2.Tr1 , n 2 = N 1.Tr2 / N 2.Tr2 ,in N 1.Trx , N 2.Trx ( x =1 or 2) respectively T r1 and T r2 The number of turns on the primary and secondary sides. The positive direction of current flow is already in Figure 1 Winning bid.

[0066] based on Figure 1 A global soft-switching DAB topology applicable to a wide voltage range is shown. The present application also proposes a control method for a global soft-switching DAB topology applicable to a wide voltage range.

[0067] In addition, before the specific analysis, the following assumptions are made:

[0068] 1) All switches, inductors, capacitors and transformers are ideal.

[0069] 2) Filter capacitor C j ( j =1,2,3,4) are large enough so that the input voltage and output voltage are considered constant.

[0070] 3) The impact of dead time can be ignored.

[0071] like Figure 2 As shown, the DAB topology works in buck mode. Figure 2 shows the key waveforms in buck mode. In this figure, T s represents the switching cycle, D 1 Indicates switch S 1 , S 4 as well as S 5 The common on-time duty cycle, D 2 Indicates switchS 1 , S 5 as well as S 6 The common on-time duty cycle, D φ It means switch S 1 and Q 1 compared to the shift. v DE is the series voltage of the secondary sides of the two transformers, v FG is the voltage generated by the secondary full bridge. i k is the leakage inductance current. It should be noted that Figure 2 When 0< D φ < D 1 < D 2 <0.5, schematic diagram of the DAB converter operating waveform.

[0072] It should be noted that, since the PWM signal is symmetrical during the two half switching cycles, this application only applies to t 0 arrive t 8 The detailed working process is analyzed in one and a half cycles. The equivalent circuits corresponding to each stage are shown in Figure 3 (a) to Figure 3 (i).

[0073] Phase 1: t 0 - t 1 ], as shown in Figure 3(a), t 0 Moment, switch S 1 On, switch tube S 1 , S 4 , S 5 , Q 2 Work, at this stage, v AB equal V 1 , v AC equal V 1 / 2, so the total voltage on the secondary side of the dual transformer is v DE forn 1 V 1 + n 2 V 1 / 2, the high-frequency voltage generated by the secondary half-bridge v FG = -V 2 / 2. Transformer current i k Start increasing at the first constant rate, the relationship is as follows:

[0074] (1)

[0075] Phase 2: t 1 - t 2 ], as shown in Figure 3(b), t 1 Moment, switch Q 2 The transformer current starts to Q 1 The junction capacitor is discharged and Q 2 The junction capacitor is charged. Q 2 The junction capacitor is charged to V 2 When the switch Q 1 When the drain-source voltage is discharged to 0, the body diode of Q1 will be turned on, which is the beginning of the next stage. Q 1 conduction creates a zero voltage turn-on condition, so Q 1 The zero voltage switching condition is:

[0076] (2)

[0077] Phase 3: t 2 - t 3 ], as shown in Figure 3(c), t 2 Moment, switch Q 1 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE equal n 1 V 1 +n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG for V 2 / 2, transformer current i k Increase at a second constant rate (relatively lower than the first constant rate), that is, the relationship between the second constant rate is:

[0078] (3)

[0079] Phase 4: t 3 - t 4 ], as shown in Figure 3(d), t 3 Moment, switch S 4 The transformer current starts to S 3 and S 6 The junction capacitor is discharged and S 4 The junction capacitor is charged; when the switch S 4 The junction capacitor is charged to V 2 After / 2, S 3 The junction capacitor is discharged to V 2 / 2, S 6 The junction capacitor is discharged to 0. Switch S 6 The body diode will conduct, and the next stage S 6 Since the leakage inductance of the DAB converter is relatively large, the current required to charge / discharge the two drain-source capacitors is small and can be neglected to simplify the zero voltage turn-on analysis. S 6 The zero voltage switching condition is:

[0080] (4)

[0081] Phase 5: t 4 - t 5 ], as shown in Figure 3(e), t4 Moment, switch S 6 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE Change to n 1 V 1 / 2+ n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG As in phase 3, the transformer current begins to decrease at a third constant rate, and the relationship is as follows:

[0082] (5)

[0083] Phase 6: t 5 - t 6 ], as shown in Figure 3(f), t 5 Moment, switch S 5 The transformer current starts to S 3 The junction capacitor is discharged and S 5 and S 4 The junction capacitor is charged; when S 4 The junction capacitor is charged to V 2 , S 5 The junction capacitor is charged to V 2 / 2, switch S 3 The drain-source voltage discharges to 0, and the body diode will conduct, which is the next stage. S 3 conduction creates a zero voltage turn-on condition, so S 3 The zero voltage switching condition is:

[0084] (6)

[0085] Phase 7: t 6 - t 7 ], as shown in Figure 3(g), t 6Moment, switch S 3 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE equal n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG equal V 2 / 2, transformer current i k Decrease at a fourth constant rate, the fourth constant rate is less than the third constant rate, and the relationship of the fourth constant rate is as follows:

[0086] (7)

[0087] Phase 8: t 7 - t 8 ], as shown in Figure 3(h), t 7 Moment, switch S 1 The transformer current starts to S 2 The junction capacitor discharges and S 1 The junction capacitor is charged. S 2 The junction capacitor is charged to V 2 When the switch S 1 The drain-source voltage discharges to 0, and the body diode will conduct, which is the next stage. S 2 conduction creates a zero voltage turn-on condition, so S 2 The zero voltage switching condition is:

[0088] (8)

[0089] Stage 9: t 8 After the moment], as shown in Figure 3(i), t 8 Moment, switch S 2 It is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE becomes - n 1V 1 - n 2 V 1 / 2, the high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG Same as stage 8, transformer current i k Decrease at the fifth constant rate. Based on symmetry, the fifth constant rate is equal to the first constant rate, and the fifth constant rate is greater than the fourth constant rate. The relationship between the fifth constant rate is as follows:

[0090] (9)

[0091] In summary, the PWM signal controls the block diagram during one and a half switching cycles, as shown in Figure 4 As shown, a single regulator can be used to adjust V 2 The side voltage is used to decouple the three power control variables and obtain the required parameters based on simple calculations. D 1 The PI controller adjusts the D φ pass D 1 Multiply by gain k (0.3~0.8) is obtained, while the shift D 2 By sampling and shifting two voltages D 1 Then, the PWM unit is based on D φ , D 1 and D 2 The value of Figure 2 , generating the corresponding driving signal.

[0092] Experimental simulation stage

[0093] The proposed global soft-switching dual-transformer DAB topology is built in MATLAB / Simulink, and the proposed control method is used to verify its working performance. The specific circuit simulation parameters are shown in Table 1.

[0094] Table 1 Main circuit simulation parameters

[0095]

[0096] Figure 5 shows the rated power P N =1 kW experimental waveform. Among them,v DE and v FG They represent the series voltage on the secondary sides of the two transformers and the voltage generated by the secondary full bridge. i k Leakage Inductance L k The current, whose polarity at the moment of switch-on determines the realization of zero voltage switching. As shown in Figure 5(a), when V 1 =120 V, v FG Square wave and shift phase D 2 The maximum value is 0.5. From the current polarity when the switch is turned on, it can be inferred that zero voltage turn-on is easy to achieve and lower conduction loss can also be obtained. V 1 When the voltage increases to 160V, 200V and 240V as shown in Figure 5(b)-(d), the shift ratio gradually decreases, thus achieving volt-second balance across the leakage inductance. i k It can be seen from the polarity that zero voltage switching is achieved in both cases. D φ , D 1 as well as D 2 , achieving wide input voltage range operation and ensuring zero voltage turn-on of all switches.

[0097] like Figure 6 As shown, in V 1 =180V, when the load changes from full load (1kW) to half load (500W), the recovery time is about 0.5ms, which indicates a fast response speed. The voltage overshoot is also acceptable for many industrial applications. It can be seen that the proposed converter topology and control method have good dynamic response capability.

[0098] As described above, compared with other DAB converters with the same number of switches and control freedom, the proposed topology for a global soft-switching DAB topology suitable for a wide voltage range not only expands the ZVS range under the premise of ensuring a wide voltage gain, but also further reduces the current-related losses by optimizing the current stress, thereby improving the operating efficiency of the entire converter. The proposed topology exhibits excellent performance in dynamic response and can quickly adapt to input voltage fluctuations and load changes. With its fast response speed and high regulation accuracy, the stability and reliability of the system are effectively improved. The control method for a global soft-switching DAB topology suitable for a wide voltage range proposed in this application relies only on the input voltage and output voltage, without the need for operating area classification, thereby significantly reducing the dependence on converter parameters. This design improves the reliability of control.

[0099] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A global soft-switching DAB topology suitable for a wide voltage range, characterized in that: include: Input side bridge arm group, transformer group and output side bridge arm group; The input side bridge arm group includes an input capacitor bridge arm, a main power bridge arm and an auxiliary power bridge arm, and the positive and negative electrodes of the input voltage V1 are connected to the two ends of the input capacitor bridge arm and the auxiliary power bridge arm in sequence, wherein the input capacitor bridge arm includes an input split filter capacitor connected in series C 1 and input split filter capacitor C 2. C 1 negative electrode and C 2 is connected to form a node C, and the main power bridge arm includes a MOSFET connected in series S 5 and S 6, and S 5 and S 6 contains an anti-parallel diode, S The direction of the anti-parallel diode in 6 is from source to drain. S The direction of the anti-parallel diode in 5 is from drain to source. S The drain of 5 is connected to C 1 negative electrode and C At the positive pole of 2, the secondary power bridge arm includes a MOSFET in series S 1 and S 2. MOSFETs in series S 3 and S 4, and S 1. S 2. S 3 and S 4 all contain anti-parallel diodes. S 1 source and S The node formed by connecting the drain of 2 is A, S 3 source, S 4 drain and S The node formed by connecting the source of 5 is B; The transformer group includes the main power transformer T r1 , Auxiliary power transformer T r2 , AC inductance L k and DC blocking capacitors C dc , T r1 Primary negative electrode and DC blocking capacitor C dc One end of the capacitor is connected to the C dc The other end of is connected to node B. T r2 Primary positive and T r1 The positive pole of the primary side is connected to node A respectively. T r2 The primary negative electrode is connected to node C. T r1 Secondary positive pole and AC inductor L k One end is connected to T r1 The secondary negative electrode and T r2 The secondary side positive pole is connected; The output side bridge arm group includes two MOSFETs connected in series Q 1 and Q 2. Two split filter capacitors in series C 3 and C 4, and Q 1 and Q 2 both contain anti-parallel diodes. Q 1 source and Q The node formed by connecting the drain of 2 is F, and the node F and the AC inductor L k The other end is connected to C 3 negative electrode and C 4 The positive electrodes are connected to form a node called G. T r2 The negative pole of the secondary side is connected to the positive pole of V2. Q 1 drain and C 3 positive pole is connected, and the negative pole of V2 is connected to Q 2 source and C 4 Negative poles are connected.

2. A global soft-switching DAB topology applicable to a wide voltage range according to claim 1, characterized in that: In the input side bridge arm, the positive electrode of the input voltage V1 is connected to the split filter capacitor C 1 positive electrode, S 1 drain and S 3, the negative electrode of the input voltage V1, and the split filter capacitor C 2 negative electrode, S 2 source and S 4 are connected to the source.

3. A control method for a global soft-switching DAB topology applicable to a wide voltage range, applying the global soft-switching DAB topology applicable to a wide voltage range as claimed in any one of claims 1 to 2, characterized in that: include: The PWM signal is symmetrical during the two half-switching cycles. During one half-switching cycle, it is divided into 9 working stages: Phase 1: t 0- t 1], in t 0 time, switch S 1 is on, switch tube S 1, S 4. S 5. Q 2 work, at this stage, v AB equal V 1, v AC equal V 1 / 2, total voltage on the secondary side of the dual transformer v DE for n 1 V 1+ n 2 V 1 / 2, high frequency voltage generated by the secondary half bridge v FG = -V 2 / 2, transformer current i k Start increasing at a first constant rate, t Time 0 is the time when the current half switching cycle starts. v DE is the series voltage of the secondary sides of the two transformers, v FG is the voltage generated by the secondary full bridge; Phase 2: t 1- t 2], in t 1 moment, switch Q 2 is turned off, and the transformer current starts to Q 1 discharges the junction capacitor and Q 2 The junction capacitor is charged; when Q 2 The junction capacitor is charged to V 2 o'clock, switch Q 1 discharges to 0, then Q 1's body diode will conduct, providing the next stage Q 1 conduction creates zero voltage turn-on condition; Phase 3: t 2- t 3], in t 2 moments, switch Q 1 is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer v DE equal n 1 V 1+ n 2 V 1 / 2, high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG for V 2 / 2, transformer current i k increasing at a second constant rate, wherein the second constant rate is less than the first constant rate; Phase 4: t 3- t 4], in t 3 moments, switch S 4 is turned off, and the transformer current starts to S 3 and S 6, the junction capacitor is discharged and S 4 The junction capacitor is charged; when the switch S 4 The junction capacitor is charged to V After 2 / 2, S 3 The junction capacitor is discharged to V 2 / 2, S 6 The junction capacitor is discharged to 0, the switch S The body diode of 6 will conduct, providing the next stage S 6. Turn on to create zero voltage turn-on condition; Phase 5: t 4- t 5], in t 4 Moments, switch S 6 is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE Change to n 1 V 1 / 2+ n 2 V 1 / 2, high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG Same as stage 3, transformer current i k beginning to decrease at a third constant rate; Phase 6: t 5- t 6], in t 5 moments, switch S 5 is turned off, and the transformer current starts to S 3 The junction capacitor is discharged and S 5 and S 4 junction capacitor is charged; when S 4 The junction capacitor is charged to V 2, S 5 The junction capacitor is charged to V 2 / 2, switch S 3 discharges to 0, then S 3's body diode will conduct, providing the next stage S 3. Turn on to create zero voltage turn-on condition; Phase 7: t 6- t 7], in t 6 moments, switch S 3 is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer is v DE equal n 2 V 1 / 2, high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG equal V 2 / 2, transformer current i k decreasing at a fourth constant rate, wherein the fourth constant rate is less than the third constant rate; Stage 8: t 7- t 8], in t 7 Moments, Switch S 1 is turned off, and the transformer current starts to S 2, the junction capacitor is discharged and S 1 junction capacitor is charged; when S 2 The junction capacitor is charged to V 2 o'clock, switch S 1 discharges to 0, then S 1's body diode will conduct, providing the next stage S 2. Turn on to create zero voltage turn-on condition; Stage 9: t 8 o'clock later], in t 8 Moments, switch S 2 is turned on under zero voltage switching conditions. At this stage, the total voltage on the secondary side of the transformer v DE becomes - n 1 V 1- n 2 V 1 / 2, high-frequency voltage generated by the half-bridge on the secondary side of the transformer v FG Same as stage 8, transformer current i k The fifth constant rate is decreased at a fifth constant rate, the fifth constant rate is equal to the first constant rate, and the fifth constant rate is greater than the fourth constant rate.

4. The method according to claim 3, characterized in that The transformer current i k The relationship for increasing at the first constant rate is: 。 5. The method according to claim 3, characterized in that: Said Q The zero voltage turn-on condition of 1 is: 。 6. The method according to claim 3, characterized in that The transformer current i k The relationship for increasing at the second constant rate is: 。 7. The method according to claim 3, characterized in that Said S The zero voltage switching condition of 6 is: 。 8. The method according to claim 3, characterized in that The transformer current i k The relationship for decreasing at the third constant rate is: 。 9. The method according to claim 3, characterized in that: Said S The zero voltage switching condition of 3 is: 。 10. The method according to claim 3, characterized in that The transformer current i k The relationship for decreasing at the fourth constant rate is: 。 11. The method according to claim 3, characterized in that Said S The zero voltage switching condition of 2 is: 。 12. The method according to claim 3, characterized in that The transformer current i k The relationship for decreasing at the fifth constant rate is: 。

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