Dual three-phase motor current harmonic suppression method and device

Abstract

The invention discloses a dual three-phase motor current harmonic suppression method and device, and the method comprises the steps: employing two three-phase half-bridge inverters for control in a dual three-phase motor system, and enabling the voltage harmonic distribution of two-level space vector pulse width modulation to comprise the fundamental frequency of a switching frequency and the frequency multiplication of the fundamental frequency; determining proportional-integral parameters of the dual three-phase motor system and analyzing and calculating disturbance loop impedance, in a dual three-phase current loop first-order system, connecting a first-order low-pass filter with a motor in series, the first-order low-pass filter being located between a three-phase half-bridge inverter and the motor; and a proportional-differential controller is added in front of the proportional-integral controller to counteract the first-order low-pass filter added on the d-axis current loop so as to control the transfer function of the dual three-phase motor system to be unchanged.

Description

Technical Field

[0001] The present application relates to the field of electric power transmission, and more specifically, to a method and device for suppressing current harmonics of a dual three-phase motor. Background Art

[0002] The vector control technology of dual three-phase permanent magnet synchronous motor has been widely used due to its advantages such as low cost and high reliability. By constructing a traditional PI controller through the vector space decoupling mathematical model of the motor, efficient control of the motor can be achieved. However, when the motor works under light load conditions, due to the small amplitude of the stator current, the influence of low-frequency harmonics and switching frequency multiple harmonics is aggravated, resulting in a significant increase in the harmonic content of the motor current and a significant increase in torque pulsation. For current harmonics of specific orders, such as the 5th and 7th current harmonics projected in the z1-z2 subspace, relevant literature has proposed a control strategy based on the PR controller. However, the above control technology does not effectively attenuate the main components of the current harmonics. Summary of the invention

[0003] In response to at least one defect or improvement need in the prior art, the present invention provides a method and device for suppressing current harmonics of a dual three-phase motor, which solves the problem that when the existing dual three-phase motor operates under light load conditions, the stator current amplitude is small, the influence of low-frequency harmonics and switching frequency multiple harmonics is aggravated, resulting in a significant increase in the harmonic content of the motor current and a significant increase in the torque pulsation. Through the current harmonic suppression method, the motor current harmonic content and torque pulsation content are greatly reduced without changing the system control parameters.

[0004] To achieve the above-mentioned purpose, according to the first aspect of the present invention, a method for suppressing current harmonics of a dual three-phase motor is provided, the method comprising: using two three-phase half-bridge inverters for control in a dual three-phase motor system, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiples of the switching frequency; determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, and using a first-order low-pass filter in series with the motor in the first-order system of the dual three-phase current loop, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; adding a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system unchanged.

[0005] In an exemplary embodiment, after determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, the method further includes: determining the first-order low-pass filter as,

[0006]

[0007] Among them, T s represents the switching cycle, P is a first-order low-pass filter;

[0008] The proportional-derivative controller is determined as,

[0009]

[0010] Where PD(s) is the proportional-derivative controller, T is the first-order filter inertia time constant, and N is the filter coefficient of the proportional-derivative controller.

[0011] In an exemplary embodiment, determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance includes: the loop impedance of the d-axis current loop includes a proportional-integral controller, a delay module, a motor inductance and a resistor, and calculating the disturbance loop impedance as follows:

[0012]

[0013] Among them, Z s(d) represents the d-axis disturbance loop impedance, T s represents the switching cycle, K pd ,K id are the P parameter and I parameter of the d-axis PI controller respectively, and R is the resistance.

[0014] In an exemplary embodiment, the method of determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, in the dual three-phase current loop first-order system, using a first-order low-pass filter in series with the motor includes: adding a first-order low-pass filter between the three-phase half-bridge inverter and the motor, cascading to form a second-order filter; selecting and determining the cutoff frequency and time constant of the first-order filter to suppress high-order harmonic components.

[0015] According to the second aspect of the present invention, a dual three-phase motor current harmonic suppression device is also provided, which includes: a control unit, used to use two three-phase half-bridge inverters for control in the dual three-phase motor system, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiple of the switching frequency; a first determination unit, used to determine the proportional-integral parameters of the dual three-phase motor system and analyze and calculate the disturbance loop impedance, and in the dual three-phase current loop first-order system, a first-order low-pass filter is used in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; an offset unit, used to add a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

[0016] According to a third aspect of the present invention, there is further provided a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the above-mentioned dual three-phase motor current harmonic suppression method when running.

[0017] According to a fourth aspect of the present invention, there is also provided an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the dual three-phase motor current harmonic suppression method through the computer program.

[0018] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0019] The present application provides a method for suppressing current harmonics of a dual three-phase motor, which is achieved by using two three-phase half-bridge inverters in a dual three-phase motor system for control, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and multiples of the fundamental frequency of the switching frequency; determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, and using a first-order low-pass filter in series with the motor in the first-order system of the dual three-phase current loop, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; adding a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged, and greatly reducing the motor current harmonic content and torque pulsation content without changing the system control parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic flow chart of an optional dual three-phase motor current harmonic suppression method provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of an optional dual three-phase motor control system provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of a d-axis current loop under an optional PI controller provided in an embodiment of the present application;

[0024] Figure 4A schematic diagram of voltage harmonic distribution under an optional two-level SVPWM provided in an embodiment of the present application;

[0025] Figure 5 An optional disturbance loop impedance amplitude-frequency curve diagram provided in an embodiment of the present application;

[0026] Figure 6 An optional dual three-phase permanent magnet synchronous motor current and its FFT analysis schematic diagram provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of an optional second-order filter provided in an embodiment of the present application;

[0028] Figure 8 A schematic diagram of an optional d-axis current loop provided in an embodiment of the present application;

[0029] Fig. 9 A schematic diagram of an optional first-order filter structure provided in an embodiment of the present application;

[0030] Fig.10 A schematic diagram of another optional first-order filter structure provided in an embodiment of the present application;

[0031] Fig.11 Another optional dual three-phase permanent magnet synchronous motor current and its FFT analysis schematic diagram provided in an embodiment of the present application;

[0032] Fig.12 A schematic diagram of the structure of an optional dual three-phase motor current harmonic suppression device provided in an embodiment of the present application;

[0033] Fig.13 A schematic diagram of the structure of an optional electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0036] According to one aspect of the embodiments of the present application, a method for suppressing current harmonics of a dual three-phase motor is provided. Figure 1 The present invention describes a method for suppressing current harmonics of a dual three-phase motor provided in an embodiment of the present application.

[0037] Figure 1 is a flow chart of an optional dual three-phase motor current harmonic suppression method provided in an embodiment of the present application, such as Figure 1 As shown, the process of the method may include the following steps:

[0038] S102, using two three-phase half-bridge inverters to control the dual three-phase motor system, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and multiple frequencies of the fundamental frequency of the switching frequency;

[0039] S104, determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, in the dual three-phase current loop first-order system, using a first-order low-pass filter connected in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor;

[0040] S106, adding a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

[0041] A method for suppressing current harmonics of a dual three-phase motor provided in an embodiment of the present application can be used to suppress current harmonics in a scenario where a dual three-phase motor operates under light load conditions.

[0042] Optionally, in order to solve the problem of large overall current harmonics of dual three-phase permanent magnet synchronous motors under light load conditions, the present invention proposes a method for suppressing current harmonics of dual three-phase motors. For the first-order system of the dual three-phase motor current loop, an RC first-order low-pass filter can be used in series with the motor; at the same time, in order to keep the motor control parameters unchanged, a PD controller and an RC first-order low-pass filter can be used to cancel each other.

[0043] See also Figure 2, analyze the causes of current harmonics and then determine the corresponding current harmonic suppression methods. Figure 2 The block diagram of a dual three-phase permanent magnet synchronous motor (PMSM) control system using a traditional proportional-integral (PI) controller and a space vector pulse width modulation (SVPWM) control strategy is presented. However, in actual operation, the d-axis current control loop may cause current ripple due to various factors, such as system nonlinear characteristics, digital control delay, and harmonic components introduced during the SVPWM modulation process.

[0044] In order to further analyze the ripple current generation mechanism of the system, this application takes the d-axis current loop as an example to deeply explore the dynamic response characteristics and potential influencing factors of the control system. Figure 3 , describes the characteristics of ripple current and its formation process. The current harmonic distribution can be analyzed from two perspectives: harmonic voltage distribution and the frequency characteristics of loop impedance. Figure 4 As shown in the figure, the dual three-phase motor control system is controlled by two three-phase half-bridge inverters. The voltage harmonics of the two-level SVPWM are mainly distributed near the fundamental frequency and multiples of the fundamental frequency of the switching frequency. When the switching frequency is selected as 10kHz, the harmonic voltage is mainly distributed near the frequencies of 10kHz, 20kHz, 30kHz, and 40kHz.

[0045] Through the above steps S102 to S106, two three-phase half-bridge inverters are used in the dual three-phase motor system for control, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiple of the switching frequency; the proportional-integral parameters of the dual three-phase motor system are determined and the disturbance loop impedance is analyzed and calculated, and in the dual three-phase current loop first-order system, a first-order low-pass filter is used in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; a proportional-differential controller is added before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system unchanged, and greatly reduce the motor current harmonic content and torque pulsation content without changing the system control parameters.

[0046] For ease of understanding, the parameters and physical quantities involved in this application are described as follows:

[0047] R represents the stator resistance;

[0048] L D ,L Q They are d-axis inductance and q-axis inductance respectively;

[0049] T s represents the switching cycle;

[0050] K pd ,Kid are the P and I parameters of the d-axis PI controller respectively;

[0051] u h Indicates harmonic voltage;

[0052] i d ,i q are d-axis current and q-axis current respectively;

[0053] Z s(d) represents the d-axis disturbance loop impedance;

[0054] T represents the inertia time constant of the first-order filter;

[0055] f c Represents the cutoff frequency of the first-order filter;

[0056] N represents the filter coefficient of the PD controller.

[0057] In an exemplary embodiment, after determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, the method further includes:

[0058] S11, determining the first-order low-pass filter as,

[0059]

[0060] Among them, T s represents the switching cycle, P is a first-order low-pass filter;

[0061] S12, determining the proportional-differential controller as,

[0062]

[0063] Where PD(s) is the proportional-derivative controller, T is the first-order filter inertia time constant, and N is the filter coefficient of the proportional-derivative controller.

[0064] In an exemplary embodiment, determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance includes:

[0065] S21, the loop impedance of the d-axis current loop includes a proportional-integral controller, a delay module, a motor inductance and a resistor. The disturbance loop impedance is calculated as follows:

[0066]

[0067] Among them, Z s(d) represents the d-axis disturbance loop impedance, T s represents the switching cycle, K pd ,Kid are the P parameter and I parameter of the d-axis PI controller respectively, and R is the resistance.

[0068] In the embodiment of the present application, according to the traditional PI design method, it can be obtained that:

[0069]

[0070] Combined with the disturbance loop impedance calculation formula, we can get:

[0071]

[0072] From this, we can draw the amplitude-frequency curve characteristic diagram of the disturbance loop impedance changing with frequency, such as Figure 5 As shown, the disturbance loop impedance Z s(d) There is a minimum point within the range of 0 to 100 Hz, and within the frequency range of 0 to 50 kHz, the disturbance loop impedance is generally small. The above formula can be simplified to:

[0073]

[0074] In the range of 0~1.6kHz, Play a major role, but Z s2 The larger value It decays rapidly as the frequency increases, and decays to less than 2500L when it approaches 100Hz. D Smaller values, and Z s1 =L D The value of s+R has not yet increased to 2500L D Therefore, between 100Hz and 1.6kHz, it is basically 2500L D In effect, after 1.6kHz, Z s2 The effect of Z decreases with the increase of frequency. s1 Play a major role.

[0075] See also Figure 6 , describes the current, torque waveform and current harmonic distribution of a dual three-phase permanent magnet synchronous motor at 500rpm and 7Nm. Since the harmonic voltage is large at the multiple of 10kHz, the loop impedance is only determined by the first-order system Z s1 =L Ds+R will lead to larger harmonic currents; because the four-vector SVPWM algorithm in the digital system cannot achieve the theoretical z1-z2 harmonic subspace synthesis voltage vector of 0, there will be a certain number of 5th, 7th, 11th, and 13th voltage harmonics. When the motor speed is below 320Hz, these harmonic voltages will act on the smaller harmonic impedance in the range of 0 to 1.6kHz, and will also generate a certain amount of harmonic current. These harmonic currents cause current waveform distortion and larger torque pulsation under light load conditions, that is, conditions with small fundamental current amplitudes.

[0076] In an exemplary embodiment, the determining of the proportional-integral parameters of the dual three-phase motor system and the analysis and calculation of the disturbance loop impedance, in the dual three-phase current loop first-order system, using a first-order low-pass filter in series with the motor includes:

[0077] S31, adding a first-order low-pass filter between the three-phase half-bridge inverter and the motor, and cascading to form a second-order filter;

[0078] S32, selecting and determining the cutoff frequency and time constant of the first-order filter to suppress high-order harmonic components.

[0079] In the embodiment of the present application, after analyzing the causes of current harmonics, the corresponding current harmonic suppression method can be determined. Specifically, Figure 7 As shown, according to Figure 3 After designing PI parameters and analyzing the disturbance loop impedance, in order to further strengthen Z after 1.6kHz s1 The role of adding a first-order low-pass filter between the inverter and the motor is to make it Cascaded to form a second-order filter, the new Z s1 It can be expressed as

[0080]

[0081] In order to prevent the system control parameters from changing, a PD controller is added before the PI controller to offset the first-order filter newly added to the d-axis current loop so that the overall transfer function of the system does not change, thereby ensuring that the system control parameters remain unchanged, such as Figure 8 As shown, the PD controller expression can be expressed as,

[0082] PD(s)=1+Ts

[0083] Since the mains frequency is 50Hz, the corresponding speed is 1000rpm. In order to suppress the high-order harmonic components as much as possible, the cutoff frequency and time constant of the first-order filter are selected as follows:

[0084]

[0085] The first-order filter is realized by connecting capacitors and resistors in series, such as Fig. 9 As shown, in order to minimize the power loss on the resistor, the resistor and capacitor values ​​are selected as follows:

[0086]

[0087] The implementation form of the PD controller is: In the formula, N is 106.

[0088] After the improvement, the disturbance loop impedance becomes,

[0089]

[0090] According to the above formula, the amplitude-frequency curve characteristic diagram of the disturbance loop impedance changing with frequency can be drawn, such as Fig.10 As shown. Figure 5 and Fig.10 It can be found that after the improvement, the disturbance loop impedance has been improved in the whole frequency band, especially after 1.6kHz, the disturbance loop impedance has increased greatly. After the improvement, the current, torque waveform and current harmonic distribution of the dual three-phase permanent magnet synchronous motor at 500rpm and 7Nm are shown in the figure below. Fig.11 As shown in the figure, it can be found that the current harmonics at 10kHz multiples are almost attenuated to 0, the current harmonics within 0-1000Hz are also suppressed to a certain extent, and the torque pulsation is significantly reduced, which proves the effectiveness of the proposed method.

[0091] Through this embodiment, the motor current harmonic content and torque ripple content are greatly reduced without changing the system control parameters.

[0092] According to another aspect of the embodiments of the present application, a current harmonic suppression device for implementing the above-mentioned dual three-phase motor current harmonic suppression method is also provided. Fig.12 is a schematic diagram of the structure of an optional dual three-phase motor current harmonic suppression device according to an embodiment of the present application, such as Fig.12 As shown, the device may include:

[0093] A control unit 1202, for controlling a dual three-phase motor system using two three-phase half-bridge inverters, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes a fundamental frequency and a multiple of the fundamental frequency of the switching frequency;

[0094] The first determination unit 1204 is used to determine the proportional-integral parameters of the dual three-phase motor system and analyze and calculate the disturbance loop impedance, and in the dual three-phase current loop first-order system, a first-order low-pass filter is connected in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor;

[0095] The offset unit 1206 is used to add a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

[0096] It should be noted that the control unit 1202 in this embodiment can be used to execute the above step S102, the first determination unit 1204 in this embodiment can be used to execute the above step S104, and the offset unit 1206 in this embodiment can be used to execute the above step S106.

[0097] Through the above module, two three-phase half-bridge inverters are used in the dual three-phase motor system for control, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiple of the switching frequency; the proportional-integral parameters of the dual three-phase motor system are determined and the disturbance loop impedance is analyzed and calculated, and in the dual three-phase electric current loop first-order system, a first-order low-pass filter is used in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; a proportional-differential controller is added before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system unchanged, and greatly reduce the motor current harmonic content and torque pulsation content without changing the system control parameters.

[0098] In an exemplary embodiment, the apparatus further comprises:

[0099] The second determining unit is used to determine that the first-order low-pass filter is,

[0100]

[0101] Among them, T s represents the switching cycle, P is a first-order low-pass filter;

[0102] The third determining unit is used to determine the proportional-derivative controller as follows:

[0103]

[0104] Where PD(s) is the proportional-derivative controller, T is the first-order filter inertia time constant, and N is the filter coefficient of the proportional-derivative controller.

[0105] In an exemplary embodiment, the first determining unit includes:

[0106] The calculation module, the loop impedance of the d-axis current loop includes a proportional-integral controller, a delay module, a motor inductance and a resistor, and is used to calculate the disturbance loop impedance as follows:

[0107]

[0108] Among them, Z s(d) represents the d-axis disturbance loop impedance, T s represents the switching cycle, K pd ,K id are the P parameter and I parameter of the d-axis PI controller respectively, and R is the resistance.

[0109] In an exemplary embodiment, the first determining unit includes:

[0110] A cascade module, used for adding a first-order low-pass filter between the three-phase half-bridge inverter and the motor, and cascading to form a second-order filter;

[0111] Select the module, select and determine the cutoff frequency and time constant of the first-order filter to suppress high-order harmonic components.

[0112] It should be noted here that the examples and scenarios implemented by the above-mentioned modules and corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned embodiments. It should be noted that the above-mentioned modules as part of the device can run in a hardware environment and can be implemented by software or hardware, wherein the hardware environment includes a network environment.

[0113] According to another aspect of the embodiments of the present application, a storage medium is further provided. Optionally, in this embodiment, the storage medium can be used to execute the program code of any of the above-mentioned dual three-phase motor current harmonic suppression methods in the embodiments of the present application.

[0114] Optionally, in this embodiment, the storage medium is configured to store program codes for executing the following steps:

[0115] S1, two three-phase half-bridge inverters are used for control in a dual three-phase motor system, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiples of the switching frequency;

[0116] S2, determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, in the dual three-phase current loop first-order system, using a first-order low-pass filter in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor;

[0117] S3, adding a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

[0118] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, which will not be described in detail in this embodiment.

[0119] Among them, computer-readable storage media may include, but are not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0120] According to another aspect of the embodiment of the present application, an electronic device for implementing the above-mentioned dual three-phase motor current harmonic suppression method is also provided. The electronic device can be a server, a terminal, or a combination thereof.

[0121] Fig.13 is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application, such as Fig.13 As shown, it includes a processor 1302, a communication interface 1304, a memory 1306 and a communication bus 1308, wherein the processor 1302, the communication interface 1304, and the memory 1306 communicate with each other through the communication bus 1308, wherein:

[0122] Memory 1306, used for storing computer programs;

[0123] The processor 1302 is used to execute the computer program stored in the memory 1306 to implement the following steps:

[0124] S1, two three-phase half-bridge inverters are used for control in a dual three-phase motor system, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiples of the switching frequency;

[0125] S2, determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, in the dual three-phase current loop first-order system, using a first-order low-pass filter in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor;

[0126] S3, adding a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

[0127] Optionally, the communication bus may be a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.13 The communication interface is used for communication between the electronic device and other devices.

[0128] The memory may include RAM, or may include non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0129] As an example, the memory 1306 may include, but is not limited to, the control unit 1202, the first determination unit 1204, and the offset unit 1206 in the dual three-phase motor current harmonic suppression device. In addition, it may also include, but is not limited to, other module units in the dual three-phase motor current harmonic suppression device, which will not be repeated in this example.

[0130] The above-mentioned processor can be a general-purpose processor, which can include but not be limited to: CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be DSP (Digital Signal Processing), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0131] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0132] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0133] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0134] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0135] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0136] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0137] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.

[0138] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0139] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0140] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for suppressing current harmonics of a dual three-phase motor, characterized in that: include: Two three-phase half-bridge inverters are used for control in a dual three-phase motor system, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes the fundamental frequency and the fundamental frequency multiple of the switching frequency; Determine the proportional-integral parameters of the dual three-phase motor system and analyze and calculate the disturbance loop impedance, and use a first-order low-pass filter in series with the motor in the dual three-phase current loop first-order system, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; A proportional-differential controller is added before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

2. The method for suppressing current harmonics of a dual three-phase motor according to claim 1, characterized in that: After determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, the method further includes: Determine the first-order low-pass filter as, Among them, T s represents the switching cycle, P is a first-order low-pass filter; The proportional-derivative controller is determined as, Where PD(s) is the proportional-derivative controller, T is the first-order filter inertia time constant, and N is the filter coefficient of the proportional-derivative controller.

3. The method for suppressing current harmonics of a dual three-phase motor according to claim 1, characterized in that: Determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance includes: The loop impedance of the d-axis current loop includes a proportional-integral controller, a delay module, a motor inductance and a resistor. The disturbance loop impedance is calculated as follows: Among them, Z s(d) represents the d-axis disturbance loop impedance, T s represents the switching cycle, K pd ,K id are the P parameter and I parameter of the d-axis PI controller respectively, and R is the resistance.

4. The method for suppressing current harmonics of a dual three-phase motor according to claim 1, characterized in that: Determining the proportional-integral parameters of the dual three-phase motor system and analyzing and calculating the disturbance loop impedance, in the dual three-phase current loop first-order system, using a first-order low-pass filter in series with the motor includes: Adding a first-order low-pass filter between the three-phase half-bridge inverter and the motor, cascading to form a second-order filter; Select and determine the cutoff frequency and time constant of the first-order filter to suppress high-order harmonic components.

5. A dual three-phase motor current harmonic suppression device, characterized in that: include: A control unit for controlling a dual three-phase motor system using two three-phase half-bridge inverters, wherein the voltage harmonic distribution of the two-level space vector pulse width modulation includes a fundamental frequency and multiples of the fundamental frequency of the switching frequency; A first determination unit is used to determine the proportional-integral parameters of the dual three-phase motor system and analyze and calculate the disturbance loop impedance, and in the dual three-phase current loop first-order system, a first-order low-pass filter is connected in series with the motor, wherein the first-order low-pass filter is located between the three-phase half-bridge inverter and the motor; The offset unit is used to add a proportional-differential controller before the proportional-integral controller to offset the first-order low-pass filter added to the d-axis current loop, so as to control the transfer function of the dual three-phase motor system to remain unchanged.

6. The dual three-phase motor current harmonic suppression device according to claim 5, characterized in that: The device also includes: The second determining unit is used to determine that the first-order low-pass filter is, Among them, T s represents the switching cycle, P is a first-order low-pass filter; The third determining unit is used to determine the proportional-derivative controller as follows: Where PD(s) is the proportional-derivative controller, T is the first-order filter inertia time constant, and N is the filter coefficient of the proportional-derivative controller.

7. The dual three-phase motor current harmonic suppression device according to claim 5, characterized in that: The first determining unit includes: The calculation module, the loop impedance of the d-axis current loop includes a proportional-integral controller, a delay module, a motor inductance and a resistor, and is used to calculate the disturbance loop impedance as follows: Among them, Z s(d) represents the d-axis disturbance loop impedance, T s represents the switching cycle, K pd ,K id are the P parameter and I parameter of the d-axis PI controller respectively, and R is the resistance.

8. The method for suppressing current harmonics of dual three-phase motors according to claim 5, characterized in that: The first determining unit includes: A cascade module, used for adding a first-order low-pass filter between the three-phase half-bridge inverter and the motor, and cascading to form a second-order filter; Select the module, select and determine the cutoff frequency and time constant of the first-order filter to suppress high-order harmonic components.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 5 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the method according to any one of claims 1 to 5 through the computer program.

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