Oscillation circuit

Abstract

Embodiments provide an oscillation circuit capable of generating a rectangular wave AC signal having a duty cycle of approximately 50%. An oscillation circuit according to an embodiment includes: a ring oscillator; a first transistor having a gate terminal connected to the output terminal of the ring oscillator and a drain terminal connected to the first node; a second transistor having a drain terminal and a gate terminal connected to the first node; a third transistor having a gate terminal connected to the first node and a drain terminal connected to the second node; a fourth transistor having a gate terminal connected to the first node and a drain terminal connected to the third node; a fifth transistor having a drain terminal connected to the second node and a source terminal connected to the third node; and a buffer having an input terminal connected to the second node.

Description

[0001] This application claims the priority of Japanese Patent Application No. 2023-158937 (filing date: September 22, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] Embodiments relate to an oscillation circuit. Background Art

[0003] As an oscillator for driving a charge pump circuit, an oscillation circuit using a ring oscillator is known. Summary of the invention

[0004] An object of the present invention is to provide an oscillation circuit capable of generating a rectangular wave AC signal having a duty ratio of approximately 50%.

[0005] An oscillation circuit according to an embodiment includes: a ring oscillator; a first transistor having a gate terminal connected to an output terminal of the ring oscillator and a drain terminal connected to a first node; a second transistor having a drain terminal and a gate terminal connected to the first node; a third transistor having a gate terminal connected to the first node and a drain terminal connected to the second node; a fourth transistor having a gate terminal connected to the first node and a drain terminal connected to a third node; a fifth transistor having a drain terminal connected to the second node and a source terminal connected to the third node; and a buffer having an input terminal connected to the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing an example of the configuration of a semiconductor device using the oscillation circuit according to the embodiment.

[0007] Figure 2 2 is a circuit diagram showing an example of the configuration of an oscillation circuit according to the embodiment.

[0008] Figure 3 This is a waveform diagram showing an example of time variation of a voltage applied to each node and a current flowing through each transistor when the oscillation circuit according to the embodiment operates.

[0009] Description of symbols

[0010] 1 oscillation circuit; 2 charge pump circuit; 11, 21, 22, 23, 24, 25, 31, 32, 33, 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b, 45a, 45b, 51, 52, 53, 54, 61, 62, 63, 64, 71a, 71b, 72a, 72b transistors; 12 current source; 13 resistor; 14 capacitor; 20 transistor group; 40 converter group; 41, 42, 43, 44, 45, 71, 72 converters; 50 capacitor group; 70 buffer; 100 semiconductor device; RO ring oscillator. DETAILED DESCRIPTION

[0011] The following is an explanation of the embodiments with reference to the accompanying drawings. In the following description, the same reference numerals are used for components having substantially the same function and configuration. In the case where it is not necessary to distinguish between components represented by reference numerals containing the same characters, these components are each referred to by reference numerals containing only characters.

[0012] In the following description, “connection” between a first element and another second element includes that the first element is always or selectively connected to the second element indirectly via an intermediate element that is conductive, or is directly connected to the second element without an intermediate element.

[0013] 1. Composition

[0014] 1.1 Overall composition

[0015] First, use Figure 1 , the structure of a semiconductor device using the oscillation circuit involved in the embodiment is described. Figure 1 This is a block diagram showing an example of the configuration of a semiconductor device using the oscillation circuit according to the embodiment.

[0016] like Figure 1 As shown, the semiconductor device 100 includes an oscillation circuit 1 and a charge pump circuit 2. The oscillation circuit 1 outputs a rectangular wave AC signal Fr to the charge pump circuit 2. The charge pump circuit 2 operates using the input rectangular wave AC signal Fr as a clock signal. The charge pump circuit 2 outputs a boost signal Vout that boosts the input voltage to a predetermined voltage to the outside of the semiconductor device 100. The semiconductor device 100 is used, for example, in a motor control driver (MCD: Motor Control Driver).

[0017] 1.2 Structure of oscillation circuit

[0018] Next, use Figure 2 , the structure of the oscillation circuit involved in the implementation method is described. Figure 2 2 is a circuit diagram showing an example of the configuration of an oscillation circuit according to the embodiment.

[0019] The oscillation circuit 1 includes transistors 11, 31, 32, 33, 61, 62, 63 and 64, a current source 12, a resistor 13, a capacitor 14, a transistor group 20, an inverter group 40, a capacitor group 50 and a buffer 70. The oscillation circuit 1 generates and outputs an AC signal using a delay of an inverter.

[0020] The transistors 11, 31, 32, 33, 61, 62, 63 and 64 include, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The transistors 11, 31, 32 and 33 include, for example, P-type MOSFETs. The transistors 61, 62, 63 and 64 include, for example, N-type MOSFETs.

[0021] The transistor 11 has a drain terminal and a gate terminal connected to the node N1 , and a source terminal and a back gate terminal to which a voltage VCC is supplied. The voltage VCC is a power supply voltage for driving the oscillation circuit 1 .

[0022] The current source 12 has an input terminal connected to the node N1 and an output terminal supplied with a voltage GND. The voltage GND is a ground voltage, for example, 0V.

[0023] The resistor 13 has a first end connected to the node N1 and a second end connected to the node N2 .

[0024] The capacitor 14 has a first end to which the voltage VCC is supplied and a second end connected to the node N2 .

[0025] The resistor 13 and the capacitor 14 function together as a low-pass filter. That is, they gradually reduce signals with a frequency higher than a certain frequency. The resistor 13 and the capacitor 14 prevent high-frequency noise from the current source from being superimposed on the inverter group 40 .

[0026] The transistor group 20 supplies current to each inverter of the inverter group 40. The transistor group 20 includes n transistors. n is an odd number greater than 3. Figure 2 2 shows the case where n=5. Hereinafter, the case where n=5 will be described.

[0027] The transistor group 20 includes transistors 21, 22, 23, 24, and 25. The transistors 21, 22, 23, 24, and 25 include, for example, P-type MOSFETs.

[0028] The transistor 21 has a drain terminal connected to the node N11 , a source terminal and a back gate terminal to which the voltage VCC is supplied, and a gate terminal connected to the node N2 .

[0029] The transistor 22 has a drain terminal connected to the node N12 , a source terminal and a back gate terminal to which the voltage VCC is supplied, and a gate terminal connected to the node N2 .

[0030] The transistor 23 has a drain terminal connected to the node N13 , a source terminal and a back gate terminal to which the voltage VCC is supplied, and a gate terminal connected to the node N2 .

[0031] The transistor 24 has a drain terminal connected to the node N14 , a source terminal and a back gate terminal to which the voltage VCC is supplied, and a gate terminal connected to the node N2 .

[0032] The transistor 25 has a drain terminal connected to the node N15 , a source terminal and a back gate terminal to which the voltage VCC is supplied, and a gate terminal connected to the node N2 .

[0033] The transistor 31 has a drain terminal connected to the node N3 , a source terminal and a back gate terminal to which the voltage VCC is supplied, and a gate terminal connected to the node N2 .

[0034] The transistor 32 has a drain terminal connected to the node N4 , a source terminal supplied with the voltage VCC, and a gate terminal connected to the node N2 .

[0035] The transistor 33 has a drain terminal connected to the node N5 , a source terminal connected to the node N4 , a gate terminal connected to the node N2 , and a back gate terminal to which the voltage VCC is supplied.

[0036] The transistors 11, 21, 22, 23, 24, 25, 31, 32, and 33 form a current mirror CMC1. The current mirror CMC1 mirrors the current flowing through the transistor 11, and determines the current flowing through the transistors 21, 22, 23, 24, 25, 31, 32, and 33.

[0037] The inverter group 40 includes the same number of inverters as the number n of transistors included in the transistor group 20. Figure 2 In the example shown, five converters are included. This case will be described below.

[0038] The converter group 40 includes converters 41, 42, 43, 44, and 45. The outputs of the converters 41, 42, 43, 44, and 45 are input to other converters, and the converters are connected in this order to form a ring. Hereinafter, for a certain converter, the converter that will be the input source of the signal is referred to as the "previous stage" converter, and the converter that will be the output destination of the signal is referred to as the "latter stage" converter.

[0039] The converter 41 includes, for example, transistors 41a and 41b. The transistors 41a and 41b include, for example, N-type MOSFETs. The transistor 41a includes a drain terminal and a gate terminal connected to the node N11, a source terminal connected to the node N12, and a back gate terminal supplied with a voltage GND. The transistor 41b includes a drain terminal connected to the node N12, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N11.

[0040] The converter 42 includes, for example, transistors 42a and 42b. The transistors 42a and 42b include, for example, N-type MOSFETs. The transistor 42a includes a drain terminal and a gate terminal connected to the node N12, a source terminal connected to the node N13, and a back gate terminal supplied with a voltage GND. The transistor 42b includes a drain terminal connected to the node N13, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N12.

[0041] The converter 43 includes, for example, transistors 43a and 43b. The transistors 43a and 43b include, for example, N-type MOSFETs. The transistor 43a includes a drain terminal and a gate terminal connected to the node N13, a source terminal connected to the node N14, and a back gate terminal supplied with a voltage GND. The transistor 43b includes a drain terminal connected to the node N14, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N13.

[0042] The converter 44 includes, for example, transistors 44a and 44b. The transistors 44a and 44b include, for example, N-type MOSFETs. The transistor 44a includes a drain terminal and a gate terminal connected to the node N14, a source terminal connected to the node N15, and a back gate terminal supplied with a voltage GND. The transistor 44b includes a drain terminal connected to the node N15, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N14.

[0043] The converter 45 includes, for example, transistors 45a and 45b. The transistors 45a and 45b include, for example, N-type MOSFETs. The transistor 45a includes a drain terminal and a gate terminal connected to the node N15, a source terminal connected to the node N11, and a back gate terminal supplied with a voltage GND. The transistor 45b includes a drain terminal connected to the node N11, a source terminal and a back gate terminal supplied with a voltage GND, and a gate terminal connected to the node N15.

[0044] Among the transistors included in the inverter group 40, the transistors 41a, 42a, 43a, 44a, and 45a function as pull-up resistors, and the transistors 41b, 42b, 43b, 44b, and 45b function as switches that determine the output of the inverter.

[0045] Each of the converters 41, 42, 43, 44, and 45 inverts the signal input from the converter at the previous stage and outputs it to the converter at the next stage. That is, when a voltage of "H" (High) level is input from the converter at the previous stage, a voltage of "L" (Low) level is output to the converter at the next stage. When a voltage of "L" level is input from the converter at the previous stage, a voltage of "H" level is output to the converter at the next stage.

[0046] The capacitor group 50 includes transistors whose number is one less than the number n of transistors included in the transistor group 20. Figure 2 In the example shown, four transistors are included. This case will be described below.

[0047] The capacitor group 50 includes, for example, transistors 51, 52, 53, and 54. The transistors 51, 52, 53, and 54 include, for example, MOSFETs.

[0048] The transistor 51 is a replica transistor with a drain terminal and a source terminal short-circuited. The transistor 51 has a drain terminal, a source terminal, and a back gate terminal to which a voltage GND is supplied, and a gate terminal connected to the node N12. The transistor 51 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of the transistor 51 is substantially equal to the gate-drain capacitance of the transistor 61 described later. The gate-source capacitance of the transistor 51 is substantially equal to the gate-source capacitance of the transistor 61 described later.

[0049] The transistor 52 is a replica transistor with a drain terminal and a source terminal short-circuited. The transistor 52 has a drain terminal, a source terminal, and a back gate terminal to which a voltage GND is supplied, and a gate terminal connected to the node N13. The transistor 52 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of the transistor 52 is substantially equal to the gate-drain capacitance of the transistor 61 described later. The gate-source capacitance of the transistor 52 is substantially equal to the gate-source capacitance of the transistor 61 described later.

[0050] Transistor 53 is a replica transistor with a drain terminal and a source terminal short-circuited. Transistor 53 has a drain terminal, a source terminal and a back gate terminal to which voltage GND is supplied, and a gate terminal connected to node N14. Transistor 53 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of transistor 53 is substantially equal to the gate-drain capacitance of transistor 61 described later. The gate-source capacitance of transistor 53 is substantially equal to the gate-source capacitance of transistor 61 described later.

[0051] Transistor 54 is a replica transistor with a drain terminal and a source terminal short-circuited. Transistor 54 has a drain terminal, a source terminal and a back gate terminal to which voltage GND is supplied, and a gate terminal connected to node N15. Transistor 54 functions as a capacitor having capacitance between the gate terminal and the drain terminal, and between the gate terminal and the source terminal. The gate-drain capacitance of transistor 54 is substantially equal to the gate-drain capacitance of transistor 61 described later. The gate-source capacitance of transistor 54 is substantially equal to the gate-source capacitance of transistor 61 described later.

[0052] The inverter group 40 and the capacitor group 50 function together as a ring oscillator RO. The ring oscillator RO outputs a clock signal having an amplitude voltage of V0. The voltage V0 is a voltage obtained by subtracting a voltage drop caused by a load capacitance inside the ring oscillator RO from the voltage VCC.

[0053] The transistor 61 has a drain terminal connected to the node N3, a source terminal supplied with the voltage GND, and a gate terminal connected to the node N11. The threshold voltage of the transistor 61 is expressed as α×V0 using a constant α satisfying 0<α<1 and an amplitude voltage V0 of the ring oscillator RO. For example, α=0.8.

[0054] The transistor 62 has a drain terminal and a gate terminal connected to the node N3 , and a source terminal and a back gate terminal to which the voltage GND is supplied.

[0055] The transistor 63 has a drain terminal connected to the node N4 , a source terminal and a back gate terminal to which the voltage GND is supplied, and a gate terminal connected to the node N3 .

[0056] The transistor 64 has a drain terminal connected to the node N5 , a source terminal and a back gate terminal to which the voltage GND is supplied, and a gate terminal connected to the node N3 .

[0057] The transistors 62 , 63 , and 64 form a current mirror CMC2 . The current mirror CMS2 mirrors the current flowing through the transistor 62 , and determines the current flowing through the transistors 63 and 64 .

[0058] The buffer 70 has an input terminal connected to the node N5 and an output terminal connected to the node N7 . The buffer 70 shapes the input AC signal (eg, a trapezoidal wave) and outputs a rectangular wave AC signal Fr to the charge pump circuit 2 .

[0059] Buffer 70 includes, for example, converters 71 and 72. Converters 71 and 72 each invert and output an input signal. That is, converters 71 and 72 each output an "L" level voltage when an "H" level voltage is input. Converters 71 and 72 each output an "H" level voltage when an "L" level voltage is input.

[0060] Converter 71 includes, for example, transistors 71a and 71b. Transistor 71a includes, for example, a P-type MOSFET. Transistor 71a includes a drain terminal connected to node N6, a source terminal and a back-gate terminal supplied with voltage VCC, and a gate terminal connected to node N5. Transistor 71b includes, for example, an N-type MOSFET. Transistor 71b includes a drain terminal connected to node N6, a source terminal and a back-gate terminal supplied with voltage GND, and a gate terminal connected to node N5.

[0061] Converter 72 includes, for example, transistors 72a and 72b. Transistor 72a includes, for example, a P-type MOSFET. Transistor 72a includes a drain terminal connected to node N7, a source terminal and a back-gate terminal supplied with voltage VCC, and a gate terminal connected to node N6. Transistor 72b includes, for example, an N-type MOSFET. Transistor 72b includes a drain terminal connected to node N7, a source terminal supplied with voltage GND, and a gate terminal and a back-gate terminal connected to node N6.

[0062] The buffer 70 sets the threshold voltage to VCC / 2, which is half the power supply voltage VCC. That is, when the voltage at the node N5 is higher than VCC / 2, the buffer 70 outputs VCC, and when the voltage at the node N5 is lower than VCC / 2, the buffer 70 outputs GND.

[0063] 2. Work

[0064] use Figure 3 , the operation of the oscillation circuit involved in the implementation scheme is explained. Figure 3 It is a waveform diagram showing an example of time variation of the voltage applied to each node and the current flowing through each transistor when the oscillation circuit according to the embodiment operates. Figure 3 Part (a) shows the temporal variation of the voltage applied to the node N11 as the output signal of the ring oscillator RO. Figure 3 Part (b) shows the temporal variation of the voltage applied to the node N3. Figure 3 Part (c) shows the temporal variation of the voltage applied to the node N4. Figure 3 Part (d) shows the temporal variation of the voltage applied to the node N6. Figure 3 Part (e) shows the temporal variation of the voltage applied to the node N7. Figure 3 Part (f) shows the time variation of the drain current flowing in the transistor 33. Figure 3 Part (g) shows the time variation of the drain current flowing in the transistor 64.

[0065] When current flows through the converter group 40, each converter alternately outputs a voltage of "H" level and a voltage of "L" level at a certain period T. That is, the ring oscillator RO generates a clock output. The voltage applied to the node N11 as the output terminal of the ring oscillator RO is as follows: Figure 3 Change as shown in part (a).

[0066] like Figure 3 As shown in part (a), the waveform of the voltage applied to the node N11 shows an asymmetric shape when the voltage rises and when the voltage drops. Specifically, when it rises, the voltage rises gently, and when it drops, the voltage drops rapidly. This is because, when it rises, the parasitic capacitance of the capacitor group 50 and the transistor 61 is charged in each stage of the converter group 40, so the rise of the voltage slows down.

[0067] like Figure 3 As shown in part (a), in the same oscillation cycle, the time when the voltage applied to the node N11 rises to α×V0 is t1. In addition, the time when the voltage applied to the node N11 drops to GND is t3.

[0068] In the period before time t1, if Figure 3 As shown in parts (b), (c) and (d), voltage VCC is applied to node N3, voltage V1 is applied to node N4, and GND is applied to node N5. In addition, at this time, transistor 32 is in a pinch-off state due to the large potential difference between the drain and the source, and voltage V1 is a voltage that is lower than the power supply voltage VCC by the pinch-off voltage of transistor 32 (for example, 0.4V).

[0069] At time t1, if Figure 3 As shown in part (b) of FIG. 1 , the voltage of node N3 drops rapidly to GND. At this time, the pinch-off state of transistor 32 is eliminated, as shown in FIG. Figure 3 As shown in part (c) of FIG. 1 , the voltage of node N4 rises rapidly to VCC. As a result, at time t1, the voltage of node N5 is GND. Since a potential difference VCC is generated between the drain and source of transistor 33, Figure 3 As shown in part (f) of FIG. 1 , a drain current with a magnitude of ICC flows through transistor 33. The drain current of transistor 33 becomes a source current for the input terminal of buffer 70, as shown in FIG. Figure 3 As shown in part (d) of FIG. 1 , the voltage of the node N5 gradually increases from time t1 .

[0070] In the same oscillation cycle, the time when the voltage of the node N5 first rises to VCC after the time t1 is set to t2. At the time t2, since the potential difference between the drain and the source of the transistor 33 disappears, Figure 3 As shown in part (f) of , the drain current flowing in the transistor 33 stops.

[0071] During the period from time t2 to time t3, if Figure 3 As shown in parts (b), (c) and (d) of FIG. 1 , GND is applied to the node N3, and voltage VCC is applied to the node N4 and the node N5.

[0072] At time t3, since the drain terminal and the source terminal of the transistor 61 are insulated, Figure 3 As shown in part (b), the voltage of node N3 gradually starts to rise. Since transistors 62, 63, and 64 form a current mirror CMC2, a current corresponding to the voltage change of node N3 flows through each transistor. As a result, Figure 3 As shown in part (c) of FIG. 1 , the voltage of node N4 gradually decreases. In addition, at time t3, the voltage of node N5 is VCC. Since a potential difference VCC is generated between the drain and source of transistor 64, Figure 3 As shown in part (f) of FIG. 1 , a drain current with a magnitude of ICC flows through transistor 64. The drain current of transistor 64 becomes a sink current for the input terminal of buffer 70, as shown in FIG. Figure 3 As shown in part (d) of FIG. 1 , the voltage of the node N5 gradually decreases from time t3.

[0073] In the same oscillation cycle, the time when the voltage of the node N5 first drops to GND after the time t3 is set to t4. At the time t4, since the potential difference between the drain and the source of the transistor 64 disappears, Figure 3 As shown in part (f) of FIG. 6 , the drain current flowing in the transistor 64 stops. Figure 3 As shown in part (b) of FIG. 1 , around time t4, the voltage of node N3 rises to VCC. Figure 3 As shown in part (c) of FIG. 1 , before time t4, the voltage of the node N4 drops to V1 and then maintains the voltage V1. Thus, the potential state of each node is reset to the state before the voltage of the node N11 starts to rise.

[0074] The magnitude of the drain current ICC flowing in the transistor 33 from time t1 to t2 and the potential difference between the drain and the source are equal to the magnitude of the drain current ICC flowing in the transistor 64 from time t3 to t4 and the potential difference between the drain and the source. Therefore, the length of the period from time t1 to t2 is equal to the length of the period from time t3 to t4. Therefore, Figure 3In the portion (d) of FIG. 5 , a slew rate when the voltage rises from time t1 to t2 and a slew rate when the voltage drops from time t3 to t4 are consistent with each other.

[0075] When the general Figure 3 When the voltage variation of the node N5 shown in part (d) is input to the buffer 70, the output Figure 3 The period T' of the output rectangular wave signal is substantially equal to the output period T of the converter group 40. Figure 3 The length of the period (A) during which the output voltage is VCC and the length of the period (B) during which the output voltage is GND shown in part (e) are substantially equal.

[0076] 3. Effect

[0077] According to the configuration of this embodiment, it is possible to provide an oscillation circuit that can generate a rectangular wave AC signal having a duty ratio of approximately 50% without using a frequency divider etc. This effect will be described in detail.

[0078] The structure involved in this embodiment is to connect a current mirror circuit to the clock output, and receive the output of the current mirror circuit upstream and downstream of the node N5. With this structure, since the source current flowing in the transistor 33 connected to the upstream of the node N5 and the sink current flowing in the transistor 64 connected to the downstream of the node N5 become the same size, the conversion rate when the voltage rises and the conversion rate when the voltage drops in the output clock signal become approximately equal. Therefore, the duty cycle of the rectangular wave AC signal Fr obtained by shaping the clock signal is unified to approximately 50%. As a result, the characteristics of a system such as a charge pump, in which the behavior of the system depends on the duty cycle of the input clock signal, can be met. In addition, since the duty cycle of the clock signal can be unified to approximately 50% without adding a frequency divider, etc., it is possible to suppress the increase in power consumption and the increase in chip area.

[0079] Furthermore, according to the configuration involved in this embodiment, the output end of the current mirror connected to the upstream of the node N5 is connected to the middle part of the two-stage stacked transistors 32 and 33 to control so that when the voltage of the node N5 drops, the voltage drops to GND. Thus, the phenomenon that the duty ratio is not uniformly approximately 50% due to the fact that the voltage of the node N5 is not completely dropped to GND is suppressed.

[0080] In addition, in a configuration in which the duty cycle is unified to 50% without using a frequency divider, it is expected that the duty cycle of the clock signal output from the ring oscillator is 50%. In the configuration involved in this embodiment, transistors 51, 52, 53, and 54 having the same capacitance as the gate-drain capacitance and gate-source capacitance of the transistor 61 connected to the output end of the converter group are connected to each stage of the converter group 40 as replicas. With this configuration, since the load capacitance is consistent in each stage of the converter group 40, the duty cycle of the signal output from the ring oscillator RO can be corrected to approximately 50%.

[0081] 4. Modifications

[0082] The oscillation circuit 1 according to the embodiment described above can be modified in various ways. Modifications are described below.

[0083] The configuration of inverters 41, 42, 43, 44, 45, 71, and 72 in oscillation circuit 1 is not limited to the configuration described in this embodiment. For example, inverters 41, 42, 43, 44, and 45 may be configured by P-type MOSFETs and N-type MOSFETs.

[0084] 5. Others

[0085] Several embodiments of the present invention have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and can be omitted, replaced, and changed in various ways without departing from the scope of the purpose of the invention. These embodiments and / or their variations are included in the scope and / or purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. An oscillator circuit, comprising: Ring oscillator; a first transistor having a gate terminal connected to the output terminal of the ring oscillator and a drain terminal connected to the first node; a second transistor having a drain terminal and a gate terminal connected to the first node; a third transistor having a gate terminal connected to the first node and a drain terminal connected to the second node; a fourth transistor having a gate terminal connected to the first node and a drain terminal connected to the third node; a fifth transistor having a drain terminal connected to the second node and a source terminal connected to the third node; and The buffer has an input terminal connected to the second node.

2. The oscillation circuit according to claim 1, A sixth transistor is further provided, and the sixth transistor has a drain terminal connected to the third node.

3. The oscillation circuit according to claim 2, further comprising: a seventh transistor having a drain terminal and a gate terminal connected to the fourth node; and a current source having a first terminal connected to the fourth node, A gate terminal of the fifth transistor and a gate terminal of the sixth transistor are connected to the fourth node.

4. The oscillation circuit according to claim 3, The first transistor, the second transistor, the third transistor, and the fourth transistor have a first conductivity type, The fifth transistor, the sixth transistor, and the seventh transistor have a second conductivity type different from the first conductivity type.

5. The oscillation circuit according to claim 1, The ring oscillator comprises: A first converter, a second converter and a third converter; as well as The first capacitor and the second capacitor, The first converter has an input terminal connected to the fifth node and an output terminal connected to the sixth node. The second converter has an input terminal connected to the sixth node and an output terminal connected to the seventh node. The third converter has an input terminal connected to the seventh node and an output terminal connected to the fifth node. The first capacitor has a first end connected to the sixth node and a second end connected to the ground. The second capacitor has a first end connected to the seventh node and a second end connected to the ground. The first transistor has a gate terminal connected to the fifth node.

6. The oscillation circuit according to claim 5, The first capacitor includes an eighth transistor having a gate terminal connected to the sixth node, and a drain terminal and a source terminal connected to the ground. The second capacitor includes a ninth transistor having a gate terminal connected to the sixth node, and a drain terminal and a source terminal connected to the ground.

7. The oscillation circuit according to claim 6, The gate-source capacitance of the eighth transistor and the gate-source capacitance of the ninth transistor are each substantially equal to the gate-source capacitance of the first transistor, The gate-drain capacitance of the eighth transistor and the gate-drain capacitance of the ninth transistor are each substantially equal to the gate-drain capacitance of the first transistor.

8. The oscillation circuit according to claim 5, The second converter includes an odd number of converters.

9. An oscillator circuit comprising: Ring oscillator; a current mirror circuit having an input terminal connected to the output terminal of the ring oscillator, a first output terminal and a second output terminal; and a buffer having an input terminal for inputting a source current and a sink current, wherein the source current is a current based on a first current flowing to the first output terminal of the current mirror circuit, and the sink current is a current based on a second current flowing to the second output terminal of the current mirror circuit, The magnitude of the source current is substantially equal to the magnitude of the sink current.

10. The oscillation circuit according to claim 9, The first output terminal of the current mirror circuit is connected between two transistors connected in series.

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