Interface circuit and signal processing method
By using a combination of FPGA, driver circuit, comparator, transformer and network interface in the E1/2MHz interface circuit, the problems of high cost and large space occupancy of traditional interface circuits are solved, and a lower cost and more compact interface circuit design is achieved.
Patent Information
- Application Number
- CN202411751126.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-30
- Publication Date
- 2025-03-25
AI Technical Summary
Traditional E1/2MHz interface circuits require the use of dedicated LIU/FRAMER chips and complex level conversion and switching circuits, resulting in high costs, large PCB layout space and FPGA pins.
The interface circuit of the field programmable gate array FPGA, driver circuit, comparator, transformer and network interface is adopted to select and convert signals through the LIU module, 2M module and MUX module in the FPGA, eliminating the special LIU/FRAMER chip and complex level conversion and switching circuits.
There is no need to use dedicated LIU/FRAMER chips and complex level switching and switching circuits, saving FPGA pins and reducing product costs and PCB layout space.
Smart Images
Figure CN119696569A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to an interface circuit and a method for processing a signal. Background Art
[0002] In communication systems, E1 / 2MHz interfaces are often used for clock frequency measurement and clock synchronization. Traditional E1 / 2MHz interface circuits require the use of dedicated LIU / FRAMER chips + complex level conversion and switching circuits, which puts enormous pressure on PCB layout space and cost, and also occupies a large number of FPGA pins. Summary of the invention
[0003] To overcome the problems existing in the related art, this specification provides an interface circuit and a method for processing a signal.
[0004] According to a first aspect of an embodiment of this specification, an interface circuit is provided, the interface circuit comprising: a field programmable gate array FPGA, a driving circuit, a comparator, a transformer and a network interface;
[0005] The FPGA is connected to the driving circuit and the comparator respectively, the driving circuit and the comparator are connected to each other through a transformer, and the transformer is connected to the network interface;
[0006] The FPGA includes: a LIU module, a 2M module and a MUX module. The LIU module and the 2M module are respectively connected to the MUX module, and the MUX module is respectively connected to the driving circuit and the comparator.
[0007] Wherein, the MUX module is connected to the driving circuit and the comparator respectively, including:
[0008] The MUX module is connected to the driving circuit via FPGA_TX_P and FPGA_TX_N signals;
[0009] The MUX module is connected to the comparator through FPGA_TX_P and FPGA_TX_N signals.
[0010] Wherein, the network interface includes: an RJ45 interface.
[0011] According to a second aspect of an embodiment of this specification, a method for processing a signal is provided, the method being applied to an interface circuit, the interface circuit comprising: a field programmable gate array FPGA, a drive circuit, a comparator, a transformer and a network interface, the FPGA being connected to the drive circuit and the comparator respectively, the drive circuit and the comparator being connected to the transformer respectively, the transformer being connected to the network interface, wherein the FPGA comprises: a LIU module, a 2M module and a MUX module, the LIU module and the 2M module being connected to the MUX module respectively, the MUX module being connected to the drive circuit and the comparator respectively, the method comprising:
[0012] The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or 2M signal to be transmitted;
[0013] Sending the E1 signal or 2M signal to be transmitted to the driving circuit, so that the driving circuit sends the E1 signal or 2M signal to the network interface through the transformer; or,
[0014] The MUX module selects and receives the E1 signal or the 2M signal sent by the comparator, and sends the E1 signal to the LIU module or sends the 2M signal to the 2M module.
[0015] The step of sending the E1 signal or 2M signal to be transmitted to the driving circuit includes:
[0016] The E1 signal or 2M signal to be transmitted is sent to the driving circuit through the FPGA_TX_P signal and / or the FPGA_TX_N signal.
[0017] The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or the 2M signal to be transmitted, including:
[0018] When the MUX module selects the E1 signal, the high and low level phases of the output FPGA_TX_P and FPGA_TX_N unipolar signals are staggered, and the unipolar level is converted into a bipolar level through a transformer.
[0019] The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or the 2M signal to be transmitted, including:
[0020] When the MUX module selects the 2M signal, the output FPGA_TX_P signal is a valid signal, and the output FPGA_TX_N signal is an invalid signal.
[0021] The MUX module selects to receive the E1 signal or the 2M signal sent by the comparator, including:
[0022] When the MUX module selects the E1 signal, it receives a unipolar FPGA_RX_P signal and / or a FPGA_RX_N signal from the comparator.
[0023] The MUX module selects to receive the E1 signal or the 2M signal sent by the comparator, including:
[0024] When the MUX module selects the E1 signal, it receives a unipolar FPGA_RX_P signal or FPGA_RX_N signal from the comparator.
[0025] It can be seen from the above embodiments that, by using the technology disclosed in the present invention, whether for E1 signals or 2MHz signals, the conversion of FPGA signals and interface signals can be achieved through the same circuit, without the need for additional selection circuits. In particular, for E1 signals, there is no need to use a dedicated LIU / FRAMER chip + complex level conversion and switching circuits, which saves PCB layout space and FPGA pins and reduces costs.
[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.
[0028] Figure 1 This is a schematic diagram of an interface circuit according to an exemplary embodiment of the present specification.
[0029] Figure 2 This is a schematic diagram of an interface circuit according to an exemplary embodiment of the present specification.
[0030] Figure 3 It is a flowchart of a method for processing a signal according to an exemplary embodiment of the present specification. DETAILED DESCRIPTION
[0031] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this specification. Instead, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.
[0032] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the" and "the" used in this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0033] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0034] like Figure 1 As shown, the current E1 / 2MHz interface circuit is implemented using a dedicated LIU / FRAMER chip and a complex level conversion and switch circuit. For example, when the port selects the E1 interface form, in the sending direction, the LIU_TXD / TXCLK output by the LIU module inside the FPGA is converted into the HDB3 signal E1_TX_P / N with a bias level through the dedicated LIU / FRAMER chip, and the software controls the analog switch to select the E1_TX_P / N signal to be sent to the input of the transformer; in the receiving direction, the analog switch selects the RX_A_P / N signal output by the transformer, outputs the E1_RX_P / N signal to the dedicated LIU / FRAMER chip, and the LIU / FRAMER chip outputs LIU_RXD / RXCLK to the LIU module inside the FPGA. The input and output signals of the transformer on the E1 interface path are both HDB3 bipolar levels.
[0035] For another example, when the port selects the 2MHz interface form, in the sending direction, the 2M_TX_A_P / N signal output by the 2M module inside the FPGA is converted into a 2M_TX_B_P / N signal through the driving circuit, and the analog switch selects to send the 2M_TX_B_P / N signal to the transformer; in the receiving direction, the analog switch selects the RX_A_P signal output by the transformer, and the output 2M_RX_B signal is converted to a 2M_RX_A signal through level conversion to the FPGA. The input and output of the transformer on the 2MHz interface path are both unipolar levels.
[0036] In the current solution, there are the following problems:
[0037] 1. Dedicated LIU / FRAMER chips are required, which increases costs;
[0038] 2. Complex level conversion and switching circuits are required, which may lead to PCB layout and cost risks;
[0039] 3. It takes up a lot of FPGA pins.
[0040] In order to solve the above technical problems, an embodiment of the present disclosure provides an interface circuit, which includes: a field programmable gate array FPGA, a driving circuit, a comparator, a transformer and a network interface;
[0041] The FPGA is connected to the driving circuit and the comparator respectively, the driving circuit and the comparator are connected to each other through a transformer, and the transformer is connected to the network interface;
[0042] The FPGA includes: a LIU module, a 2M module and a MUX module. The LIU module and the 2M module are respectively connected to the MUX module, and the MUX module is respectively connected to the driving circuit and the comparator.
[0043] In this embodiment, the LIU module is used to output E1 signals, and the 2M module is used to output 2M signals.
[0044] like Figure 2 As shown, the LIU module and the 2M module are configured in the FPGA, and the administrator can configure the MUX module through commands. The MUX module can be understood as a selector for selecting E1 or 2M signals.
[0045] In this embodiment, the LIU module and the 2M module are respectively connected to the MUX module, and the MUX module is connected to the driving circuit and the comparator. In this embodiment, the driving module is used to send E1 or 2M signals to the network interface (RJ45), and the comparator is used to receive the E1 or 2M signals sent by the network interface.
[0046] In this embodiment, the MUX module is connected to the driving circuit through FPGA_TX_P and FPGA_TX_N signals, and the MUX module is connected to the comparator through FPGA_TX_P and FPGA_TX_N signals.
[0047] from Figure 2 It can be seen that compared with the existing technology, the use of LIU / FRAMER chips can be omitted, while the PCB layout space is optimized, effectively reducing product costs.
[0048] Based on the above-mentioned interface circuit, an embodiment of the present disclosure provides a method for processing a signal, which is applied to the interface circuit, wherein the interface circuit includes: a field programmable gate array FPGA, a driving circuit, a comparator, a transformer and a network interface, wherein the FPGA is connected to the driving circuit and the comparator respectively, the driving circuit and the comparator are connected to the transformer respectively, and the transformer is connected to the network interface, wherein the FPGA includes: a LIU module, a 2M module and a MUX module, wherein the LIU module and the 2M module are connected to the MUX module respectively, and the MUX module is connected to the driving circuit and the comparator respectively, such as Figure 3 As shown, the method includes:
[0049] The S301MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or 2M signal to be transmitted;
[0050] S302 sends the E1 signal or 2M signal to be transmitted to the driving circuit, so that the driving circuit sends the E1 signal or 2M signal to the network interface through the transformer; or, the MUX module selects to receive the E1 signal or 2M signal sent by the comparator, and sends the E1 signal to the LIU module or sends the 2M signal to the 2M module.
[0051] In this embodiment, the MUX module selects the E1 signal or 2M signal to be sent, and sends the E1 signal or 2M signal to be transmitted to the driving circuit through the FPGA_TX_P signal and / or the FPGA_TX_N signal.
[0052] The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or the 2M signal to be transmitted, including:
[0053] When the MUX module selects the E1 signal, the high and low level phases of the output FPGA_TX_P and FPGA_TX_N unipolar signals are staggered, and the unipolar level is converted into a bipolar level through a transformer.
[0054] The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or the 2M signal to be transmitted, including:
[0055] When the MUX module selects the 2M signal, the output FPGA_TX_P signal is a valid signal, and the output FPGA_TX_N signal is an invalid signal.
[0056] The MUX module selects to receive the E1 signal or the 2M signal sent by the comparator, including:
[0057] When the MUX module selects the E1 signal, it receives a unipolar FPGA_RX_P signal and / or a FPGA_RX_N signal from the comparator.
[0058] The MUX module selects to receive the E1 signal or the 2M signal sent by the comparator, including:
[0059] When the MUX module selects the E1 signal, it receives a unipolar FPGA_RX_P signal or FPGA_RX_N signal from the comparator.
[0060] Specifically, Figure 2 As shown, in the sending direction, the FPGA selects to output the E1 signal or the 2MHz signal according to the software configuration. After the E1 signal and the 2MHz signal are selected inside the FPGA, they are output to the external drive circuit through the FPGA's FPGA_TX_P / N signal, and the drive circuit relays the signal to the transformer. For the E1 signal, the high and low levels of the FPGA_TX_P / N unipolar signal output by the FPGA are staggered in phase. After passing through the transformer, the unipolar level becomes a bipolar level; for the 2MHz signal, the FPGA_TX_P signal is valid, and the FPGA_TX_N signal is always at a low level. After passing through the transformer, the level polarity remains unchanged.
[0061] In the receiving direction, the FPGA chooses to send the received signal to the LIU module or the 2M module according to the software configuration. The E1 signal or 2MHz signal of the panel port outputs the RX_A_P / N signal after passing through the transformer. After the RX_A_P / N signal passes through the comparator, it generates the FPGA_RX_P / N signal to the FPGA. For the E1 signal, the RX_B_P / N input of the transformer is a bipolar level, and the transformer output RX_A_P / N is also a bipolar level. After passing through the comparator, the RX_A_P / N generates a unipolar FPGA_RX_P / N signal, and the high and low levels of the two are phase-shifted; for the 2MHz signal, the transformer input and output are both unipolar levels, and the RX_A_P generates a unipolar FPGA_RX_P signal after passing through the comparator.
[0062] The processing of E1 signal and 2MHz signal is selected inside FPGA without the need of peripheral analog switch circuit.
[0063] It can be seen from the above embodiments that, compared with the prior art, the interface circuit provided by the present invention does not require the use of dedicated LIU / FRAMER chips, peripheral complex level conversion and switching circuits, while saving FPGA pins and reducing R&D and product costs.
[0064] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. A person of ordinary skill in the art can understand and implement it without paying creative labor.
[0065] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0066] Those skilled in the art will readily appreciate other embodiments of the specification after considering the specification and practicing the invention claimed herein. The specification is intended to cover any variations, uses or adaptations of the specification that follow the general principles of the specification and include common knowledge or customary techniques in the art that are not claimed in the specification. The specification and examples are to be considered exemplary only, and the true scope and spirit of the specification are indicated by the following claims.
[0067] It should be understood that the present description is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
[0068] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.
Claims
1. An interface circuit, characterized in that: The interface circuit includes: a field programmable gate array FPGA, a driving circuit, a comparator, a transformer and a network interface; The FPGA is connected to the driving circuit and the comparator respectively, the driving circuit and the comparator are connected to each other through a transformer, and the transformer is connected to the network interface; The FPGA includes: a LIU module, a 2M module and a MUX module. The LIU module and the 2M module are respectively connected to the MUX module, and the MUX module is respectively connected to the driving circuit and the comparator.
2. The interface circuit according to claim 1, characterized in that: The MUX module is connected to the driving circuit and the comparator respectively, and includes: The MUX module is connected to the driving circuit via FPGA_TX_P and FPGA_TX_N signals; The MUX module is connected to the comparator through FPGA_TX_P and FPGA_TX_N signals.
3. The interface circuit according to claim 1, characterized in that: The network interface includes: an RJ45 interface.
4. A method for processing a signal, characterized in that The method is applied to an interface circuit, which includes: a field programmable gate array FPGA, a driving circuit, a comparator, a transformer and a network interface, wherein the FPGA is connected to the driving circuit and the comparator respectively, the driving circuit and the comparator are connected to the transformer respectively, and the transformer is connected to the network interface, wherein the FPGA includes: a LIU module, a 2M module and a MUX module, the LIU module and the 2M module are connected to the MUX module respectively, and the MUX module is connected to the driving circuit and the comparator respectively, and the method includes: The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or 2M signal to be transmitted; Sending the E1 signal or 2M signal to be transmitted to the driving circuit, so that the driving circuit sends the E1 signal or 2M signal to the network interface through the transformer; or, The MUX module selects and receives the E1 signal or the 2M signal sent by the comparator, and sends the E1 signal to the LIU module or sends the 2M signal to the 2M module.
5. The method according to claim 4, characterized in that The step of sending the E1 signal or 2M signal to be transmitted to the driving circuit includes: The E1 signal or 2M signal to be transmitted is sent to the driving circuit through the FPGA_TX_P signal and / or the FPGA_TX_N signal.
6. The method according to claim 5, characterized in that The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or the 2M signal to be transmitted, including: When the MUX module selects the E1 signal, the high and low level phases of the output FPGA_TX_P and FPGA_TX_N unipolar signals are staggered, and the unipolar level is converted into a bipolar level through a transformer.
7. The method according to claim 5, characterized in that The MUX module receives the signals sent by the LIU module and the 2M module, and selects the E1 signal or the 2M signal to be transmitted, including: When the MUX module selects the 2M signal, the output FPGA_TX_P signal is a valid signal, and the output FPGA_TX_N signal is an invalid signal.
8. The method according to claim 4, characterized in that The MUX module selects to receive the E1 signal or the 2M signal sent by the comparator, including: When the MUX module selects the E1 signal, it receives a unipolar FPGA_RX_P signal and / or a FPGA_RX_N signal from the comparator.
9. The method according to claim 4, characterized in that The MUX module selects to receive the E1 signal or the 2M signal sent by the comparator, including: When the MUX module selects the E1 signal, it receives a unipolar FPGA_RX_P signal or FPGA_RX_N signal from the comparator.