Logic chip, image sensor, electronic device and vehicle

Abstract

The invention discloses a logic chip, an image sensor, electronic equipment and a vehicle, the image sensor comprises a pixel array, the pixel array comprises N columns of pixel units, N is greater than or equal to 1, and the logic chip comprises a logic wafer; the N first column-level ADC circuits are located on the logic wafer, the nth first column-level ADC circuit is used for converting a first gain signal output by the nth column of pixel units, and n is smaller than or equal to N; the N second column-level ADC circuits are located on the logic wafer, the nth second column-level ADC circuit is used for converting a second gain signal output by the nth column of pixel units, and the conversion gain of the second gain signal is different from that of the first gain signal. According to the logic chip and the image sensor, the data conversion time of the column-level ADC circuit can be shortened, the conversion speed of the column-level ADC circuit is increased, and the imaging frame frequency is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a logic chip, and an image sensor, electronic equipment and a vehicle comprising the logic chip. Background Art

[0002] In the related art, the logic chip of the image sensor uses a single column-level ADC (analog to digital converter) circuit, which reduces the area of ​​the logic circuit, but requires a high processing speed of the circuit and a higher operating frequency. Based on the current technological level, it is difficult to further increase the frame rate, and it is impossible to further reduce the operating frequency of the column-level ADC circuit, thereby limiting the conversion speed of the column ADC circuit and the frame rate of imaging. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a logic chip that can reduce the data conversion time of the column-level analog-to-digital conversion circuit, increase the conversion speed of the column-level analog-to-digital conversion circuit, and increase the imaging frame rate.

[0004] A second aspect of the present invention provides an image sensor;

[0005] A third aspect of the present invention provides an electronic device;

[0006] A fourth aspect of the present invention provides a vehicle.

[0007] In order to achieve the above-mentioned purpose, the logic chip of the first aspect of the present invention is used for an image sensor, the image sensor includes a pixel array, the pixel array includes N columns of pixel units, N≥1, and the logic chip includes: a logic wafer; N first column-level analog-to-digital conversion circuits, the N first column-level analog-to-digital conversion circuits are located on the logic wafer, and the nth first column-level analog-to-digital conversion circuit is used to convert a first gain signal output by the nth column of pixel units, n≤N; N second column-level analog-to-digital conversion circuits, the N second column-level analog-to-digital conversion circuits are located on the logic wafer, and the nth second column-level analog-to-digital conversion circuit is used to convert a second gain signal output by the nth column of pixel units, wherein the second gain signal has a different conversion gain from the first gain signal.

[0008] The logic chip of the embodiment of the present invention has two column-level analog-to-digital conversion circuits corresponding to one column of pixel units, so that the operating frequency of the analog-to-digital conversion circuit when the chip is running can be reduced by half compared with the single-column-level analog-to-digital conversion circuit in the prior art. Therefore, under the same operating frequency conditions, the logic chip of the embodiment of the present invention can process more pixel signals, improve the conversion speed of the column-level analog-to-digital conversion circuit, reduce the data conversion time of the column-level analog-to-digital conversion circuit, and improve the frame rate of image processing.

[0009] In some embodiments, the N first column-level analog-to-digital conversion circuits are arranged along the direction of the pixel unit columns of the pixel array, and the N second column-level analog-to-digital conversion circuits are arranged along the direction of the pixel unit columns of the pixel array.

[0010] In some embodiments, the logic wafer includes a central area and a peripheral area, N of the first column-level analog-to-digital conversion circuits form a first column-level analog-to-digital conversion circuit group, and N of the second column-level analog-to-digital conversion circuits form a second column-level analog-to-digital conversion circuit group, and the first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group are located in the central area of ​​the logic wafer.

[0011] In some embodiments, the first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group are both located in a first logic area of ​​the central region, and the first logic area is offset from the center of the central region.

[0012] In some embodiments, the logic chip also includes: a first tail current source, the first tail current source is located in the logic wafer, the first tail current source is located between the first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group, and the first tail current source is respectively connected to the column bus of the image sensor, the first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group.

[0013] In some embodiments, the first column-level analog-to-digital conversion circuit group is located in the second logic area of ​​the central area, the second column-level analog-to-digital conversion circuit group is located in the third logic area of ​​the central area, the second logic area and the third logic area are both offset from the center of the central area, and the second logic area is arranged opposite to the third logic area.

[0014] In some embodiments, the logic chip further includes: a second tail current source, the second tail current source is located in the second logic area, and the second tail current source is respectively connected to the column bus of the image sensor and the first column-level analog-to-digital conversion circuit group.

[0015] In some embodiments, the second tail current source is located outside the first column-level analog-to-digital conversion circuit group, and the outside is a side away from the center of the central area of ​​the logic wafer.

[0016] In some embodiments, the logic chip further includes: a third tail current source, the third tail current source is located in the third logic area, and the third tail current source is respectively connected to the column bus of the image sensor and the second column-level analog-to-digital conversion circuit group.

[0017] In some embodiments, the third tail current source is located outside the second column-level analog-to-digital conversion circuit group, and the outside is a side away from the center of the central area of ​​the logic wafer.

[0018] In some embodiments, each of the first ADC circuits includes: a first switch, the first switch is connected to a column line of a corresponding column of pixel units; a second switch, the second switch is connected to an output end of a ramp generating circuit of the image sensor; a first capacitor, a first end of the first capacitor is connected to the first switch; a second capacitor, a first end of the second capacitor is connected to the second switch; a first comparator, a first input end of the first comparator is connected to a second end of the first capacitor, and a second input end of the first comparator is connected to a second end of the second capacitor; a second comparator, an input end of the second comparator is connected to an output end of the first comparator; and a first counter, the first counter is connected to an output end of the second comparator, and is used to obtain a quantized value of the first gain signal according to a comparison result of the second comparator.

[0019] In some embodiments, each of the second column-level analog-to-digital conversion circuits includes: a third switch, the third switch is connected to the column line of the corresponding column pixel unit; a fourth switch, the fourth switch is connected to the output end of the ramp generating circuit of the image sensor; a third capacitor, the first end of the third capacitor is connected to the third switch; a fourth capacitor, the first end of the fourth capacitor is connected to the fourth switch; a third comparator, the first input end of the third comparator is connected to the second end of the third capacitor, and the second input end of the third comparator is connected to the second end of the fourth capacitor; a fourth comparator, the input end of the fourth comparator is connected to the output end of the third comparator; a second counter, the second counter is connected to the output end of the fourth comparator, and is used to obtain the quantization value of the second gain signal according to the comparison result of the fourth comparator.

[0020] In some embodiments, the logic chip also includes: a first column switching circuit group, the first column switching circuit group is located on the logic wafer, one end of the first column switching circuit group is connected to the column line of the pixel array, and the other end of the first column switching circuit group is connected to N first column-level analog-to-digital conversion circuits, for switching the output of the first gain signal on the column line of the pixel array.

[0021] In some embodiments, the logic chip also includes: a second column switching circuit group, the second column switching circuit group is located on the logic wafer, one end of the second column switching circuit group is connected to the column line of the pixel array, and the other end of the second column switching circuit group is connected to N second column-level analog-to-digital conversion circuits, for switching the output of the second gain signal on the column line of the pixel array.

[0022] In some embodiments, the logic chip further includes: a peripheral circuit, which is arranged in a peripheral area of ​​the logic wafer and is located around the first column-level analog-to-digital conversion circuit group and / or the second column-level analog-to-digital conversion circuit group.

[0023] In some embodiments, the logic chip further includes: electrical interconnection contacts, the electrical interconnection contacts are arranged in a peripheral area of ​​the logic wafer, and the electrical interconnection contacts are used to connect to a pixel chip of the image sensor.

[0024] In order to achieve the above-mentioned purpose, the image sensor of the second aspect of the embodiment of the present invention includes: a pixel chip, the pixel chip includes a pixel wafer and a pixel array arranged on the pixel wafer, the pixel array includes N columns of pixel units; the logic chip, the logic chip is stacked with the pixel chip.

[0025] The image sensor according to the embodiment of the present invention can reduce the conversion time of the column-level analog-to-digital conversion circuit and greatly improve the image processing frame rate by adopting the logic chip of the above embodiment under the condition of the same working frequency.

[0026] In some embodiments, the pixel chip is electrically connected to the logic chip through silicon through-via routing.

[0027] In some embodiments, the column lines of the column pixel units are electrically connected to the corresponding column-level analog-to-digital conversion circuits through silicon through-via routing.

[0028] In some embodiments, each of the pixel units includes: a first photoelectric conversion unit, the first end of the first photoelectric conversion unit is grounded; a first transmission tube, the first end of the first transmission tube is connected to the second end of the first photoelectric conversion unit; a first storage node, the first storage node is connected to the second end of the first transmission tube; a source follower tube, the first end of the source follower tube is connected to the power supply, and the control end of the source follower tube is connected to the first storage node; a selection tube, the first end of the selection tube is connected to the second end of the source follower tube, and the second end of the selection tube is output to the corresponding column line.

[0029] In some embodiments, the pixel unit also includes: a second photoelectric conversion unit, a first end of the second photoelectric conversion unit is grounded, and a photosensitive area of ​​the second photoelectric conversion unit is smaller than a photosensitive area of ​​the first photoelectric conversion unit; a second transmission tube, a first end of the second transmission tube is connected to a second end of the second photoelectric conversion unit; a third storage node, the third storage node is connected to a storage capacitor; a third transmission tube, a first end of the third transmission tube is connected to the third storage node; a second storage node, the second storage node is connected to a second end of the third transmission tube; a reset tube, a first end of the reset tube is connected to a power supply, and a second end of the reset tube is connected to the second storage node; a gain conversion tube, a first end of the gain conversion tube is connected to the second storage node, and a second end of the gain conversion tube is connected to the first storage node.

[0030] In order to achieve the above objective, a third aspect of the present invention further provides an electronic device, which includes the image sensor of the above embodiment.

[0031] The electronic device according to the embodiment of the present invention can improve the conversion speed of the column-level analog-to-digital conversion circuit, reduce the data conversion time of the column-level analog-to-digital conversion circuit, increase the frame rate of image processing, and improve the imaging quality by adopting the image sensor of the above embodiment.

[0032] In order to achieve the above objective, a fourth aspect of the present invention provides a vehicle, which includes the image sensor of the above embodiment.

[0033] According to the vehicle of the embodiment of the present invention, by adopting the image sensor of the above embodiment, the conversion speed of the column-level analog-to-digital conversion circuit can be improved, the data conversion time of the column-level analog-to-digital conversion circuit can be reduced, the frame rate of image processing can be improved, data support can be provided for the control strategy based on the image processing results in the vehicle, and the vehicle performance can be improved.

[0034] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0036] Figure 1 is a block diagram of a logic chip according to an embodiment of the present invention;

[0037] Figure 2 is a schematic diagram of a chip architecture of an image sensor according to an embodiment of the present invention;

[0038] Figure 3is a schematic diagram of a chip architecture of an image sensor according to another embodiment of the present invention;

[0039] Figure 4 is a schematic structural diagram of a pixel array and an analog-to-digital converter according to an embodiment of the present invention;

[0040] Figure 5 is a block diagram of an electronic device according to an embodiment of the present invention;

[0041] Figure 6 is a block diagram of a vehicle according to one embodiment of the present invention.

[0042] Reference numerals:

[0043] Vehicle 1;

[0044] Electronic equipment 1000;

[0045] Image sensor 100;

[0046] Logic chip 10 and pixel chip 20;

[0047] Pixel wafer 21; pixel array 22;

[0048] Central area P1; peripheral area P2;

[0049] Logic wafer 11; first column-level analog-to-digital conversion circuit 12; N second column-level analog-to-digital conversion circuits 13; first column-level analog-to-digital conversion circuit group 121; second column-level analog-to-digital conversion circuit group 131; central area P1; first tail current source 14, second tail current source 15 and third tail current source 16; electrical interconnection contact 17; first column switching circuit group 18 and second column switching circuit group 19;

[0050] The first switch SW11, the second switch SW12, the first capacitor C01, the second capacitor C02, the first comparator A1, the second comparator A2 and the first counter CNT1; the third switch SW21, the fourth switch SW22, the third capacitor C03, the fourth capacitor C04, the third comparator A3, the fourth comparator A4 and the second counter CNT2. DETAILED DESCRIPTION

[0051] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0052] Reference below Figure 1-Figure 4 A logic chip according to an embodiment of the present invention is described.

[0053] The logic chip of the embodiment of the present invention is used for an image sensor. The image sensor includes a pixel chip. A pixel array can be prepared on the pixel chip to convert light signals into electrical signals. The pixel array can be a two-dimensional array. In an embodiment, the pixel array can include M rows × N columns of pixel units, M≥1, N≥1.

[0054] The logic chip is interconnected with the pixel chip to convert the signal output by the pixel array to obtain an image signal. In some embodiments, the pixel chip and the logic chip can be stacked using a three-dimensional stacking technology.

[0055] Figure 1 is a block diagram of a logic chip according to an embodiment of the present invention, such as Figure 1 As shown, the logic chip 10 includes a logic wafer 11 , N first column-level analog-to-digital conversion circuits 12 , and N second column-level analog-to-digital conversion circuits 13 .

[0056] Among them, N first column-level analog-to-digital conversion circuits 12 are located on the logic wafer 11, and the nth first column-level analog-to-digital conversion circuit 12 is used to convert the first gain signal output by the nth column pixel unit, n≤N; N second analog-to-digital conversion circuits 13 are located on the logic wafer 11, and the nth second column-level analog-to-digital conversion circuit 13 is used to convert the second gain signal output by the nth column pixel unit. Among them, the conversion gain of the second gain signal is different from that of the first gain signal. The conversion gain is the photoelectric conversion gain. Different conversion gains mean that the amount of charge accumulated in the storage node and / or capacitor in the pixel circuit of the image sensor is different. The use of dual conversion gains can increase the dynamic range of the image sensor.

[0057] In an embodiment, the first gain signal may be a low conversion gain signal, i.e., an image signal of the image sensor in a low conversion gain mode, and the second gain signal may be a high conversion gain signal, i.e., an image signal of the image sensor in a high conversion gain mode, or the first gain signal may be a high conversion gain signal, and the second gain signal may be a low conversion gain signal. For example, in a low light scene, the pixel circuit of the image sensor operates in a high conversion gain mode; in a high light scene, the pixel circuit of the image sensor operates in a low conversion gain mode.

[0058] That is, the logic chip 10 of the embodiment of the present invention has two column-level ADC circuits corresponding to one column of pixel units, which can reduce the operating frequency of the circuit by half compared with the prior art during operation. Therefore, under the same operating frequency conditions, the logic chip 10 of the embodiment of the present invention can process more pixel signals and perform more complex operations, that is, improve the frame rate of image processing.

[0059] In the embodiment, N first column-level analog-to-digital conversion circuits 12 are arranged along the direction of the pixel unit columns of the pixel array, and N second column-level analog-to-digital conversion circuits 13 are arranged along the direction of the pixel unit columns of the pixel array, which facilitates the interconnection between the logic chip 10 and the pixel chip, and the design is reasonable.

[0060] Specifically, the pixel array includes a plurality of pixel unit columns, each pixel unit column includes a plurality of pixel units, and the plurality of pixel unit columns are arranged along one direction. Figure 2 FIG. 1 is a schematic diagram of a chip architecture of an image sensor according to an embodiment of the present invention. Figure 2 The plurality of pixel unit columns are arranged along the pixel unit column arrangement direction as shown in the figure. In an embodiment, the pixel chip is interconnected with the logic chip, wherein the column-level analog-to-digital conversion circuit is electrically connected to the corresponding pixel unit column. In an embodiment of the present invention, the N first column-level analog-to-digital conversion circuits and the N second column-level analog-to-digital conversion circuits are arranged along the pixel unit column arrangement direction, making the electrical connection between the upper and lower chips simpler and more reasonable, and reducing the crossing of the lines.

[0061] Furthermore, in some embodiments, Figure 2 As shown, the logic wafer 11 includes a central area P1 and a peripheral area P2, wherein the peripheral area P2 is located outside the central area P1. The central area P1 may be used to arrange a main logic circuit.

[0062] N first column-level analog-to-digital conversion circuits 12 form a first column-level analog-to-digital conversion circuit group 121, and N second column-level analog-to-digital conversion circuits 13 form a second column-level analog-to-digital conversion circuit group 131. Modularization can make it easier for professional and technical personnel to understand and improve. Among them, the first column-level analog-to-digital conversion circuit group 121 and the second column-level analog-to-digital conversion circuit group 131 are located in the central area P1 of the logic wafer 11, corresponding to the pixel array of the pixel chip, which is convenient for the interconnection between the two.

[0063] In some embodiments, the first column-level analog-to-digital conversion circuit group 121 and the second column-level analog-to-digital conversion circuit group 131 are both arranged in the first logic area of ​​the central area P1, and the first logic area is offset from the center of the central area, such as Figure 2 As shown, the first column-level analog-to-digital conversion circuit group 121 and the second column-level analog-to-digital conversion circuit group 131 are located in the upper half of the central area P1 of the logic chip 10, so that other idle parts such as the lower half can be used to meet more diverse needs, increasing the flexibility of logic circuit design.

[0064] like Figure 2As shown, the logic chip 10 also includes a first tail current source 14, which is arranged on the logic wafer 11 and located between the first column-level analog-to-digital conversion circuit group 121 and the second column-level analog-to-digital conversion circuit group 131. The first tail current source 14 is respectively connected to the column bus of the image sensor, the first column-level analog-to-digital conversion circuit group 121 and the second column-level analog-to-digital conversion circuit group 131, so that a more stable signal can be obtained.

[0065] Specifically, Figure 2 As shown, the first column-level analog-to-digital conversion circuit group 121 located at the top simultaneously converts the LCG (low gain) signal output by the pixel, and the second column-level analog-to-digital conversion circuit group 131 located at the bottom converts the HCG (high gain) signal output by the pixel. The column bus output signal of the pixel chip is uniformly output from one side of the chip to the column-level readout circuit. For example, the column bus is vertically interconnected from the edge of the pixel chip to the logic chip 10 downward to the first tail current source 14, and then symmetrically routed up and down to connect to the first column-level analog-to-digital conversion circuit group 121 and the second column-level analog-to-digital conversion circuit group 131.

[0066] In other embodiments, Figure 3 FIG. 1 is a schematic diagram of a chip structure of an image sensor according to another embodiment of the present invention. Figure 3 As shown, the first column-level analog-to-digital conversion circuit group 121 is set in the second logic area of ​​the central area P1, and the second column-level analog-to-digital conversion circuit group 131 is set in the third logic area of ​​the central area P1. The second logic area and the third logic area are both offset from the center of the central area P1, and the second logic area and the third logic area are relative areas. In this way, other logic circuits can be set in the center of the logic wafer 11.

[0067] like Figure 3 As shown, the logic chip 10 further includes a second tail current source 15 and a third tail current source 16 .

[0068] The second tail current source 15 is disposed in the second logic area and is located outside the first column-level analog-to-digital conversion circuit group 121, which is a side away from the center of the central area P1 of the logic wafer 11. The second tail current source 15 is respectively connected to the column bus of the image sensor and the first column-level analog-to-digital conversion circuit group 121. Specifically, the column bus of the image sensor is vertically interconnected downward from the edge of the pixel chip to the logic chip 10 to the second tail current source 15 and then routed to the first column-level analog-to-digital conversion circuit group 121.

[0069] The third tail current source 16 is disposed in the third logic area and is located outside the second column-level analog-to-digital conversion circuit group 131, which is a side away from the center of the central area P1 of the logic wafer 11. The third tail current source 16 is respectively connected to the column bus of the image sensor and the second column-level analog-to-digital conversion circuit group 131. Specifically, the column bus of the image sensor is vertically interconnected from the edge of the pixel chip to the logic chip 10 downward to the third tail current source 16 and then routed to the second column-level analog-to-digital conversion circuit group 131, so that a more stable signal can be obtained.

[0070] In some embodiments, peripheral circuits may be disposed on the logic wafer 11 and around the first column-level analog-to-digital conversion circuit group 121 and / or the second column-level analog-to-digital conversion circuit group 131 to meet other circuit requirements of the image sensor.

[0071] The logic chip 10 may further include electrical interconnection contacts 17, which are disposed in a peripheral region P2 of the logic wafer 11, and the peripheral region P2 is located outside the central region P1. The electrical interconnection contacts 17 are used to connect the pixel chip of the image sensor to realize the interconnection between the pixel chip and the logic chip, so that the two are electrically coupled to each other.

[0072] Figure 4 is a schematic diagram of the structure of a pixel array and an analog-to-digital converter according to an embodiment of the present invention. Figure 4 As shown, each first column-level analog-to-digital conversion circuit 12 includes a first switch SW11, a second switch SW12, a first capacitor C01, a second capacitor C02, a first comparator A1, a second comparator A2 and a first counter CNT1.

[0073] Among them, the first switch SW11 is connected to the column line COL of the corresponding column pixel unit, and the column line COL is used to transmit the pixel signal of the corresponding column pixel unit; the second switch SW12 is connected to the output end (middle black dotted line) of the ramp generating circuit of the image sensor to obtain the ramp signal; the first end of the first capacitor C01 is connected to the first switch SW11; the first end of the second capacitor C02 is connected to the second switch SW12; the first input end of the first comparator A1 is connected to the second end of the first capacitor C01, and the second input end of the second comparator A2 is connected to the second end of the second capacitor C02; the input end of the second comparator A2 is connected to the output end of the first comparator A1; the first counter CNT1 is connected to the output end of the second comparator A2, and the first counter CNT11 is used to obtain the quantized value of the first gain signal according to the comparison result of the second comparator A2. Thus, the conversion of the first gain signal output by the corresponding column pixel unit is realized.

[0074] like Figure 4As shown, each second column-level analog-to-digital conversion circuit 13 includes a third switch SW21, a fourth switch SW22, a third capacitor C03, a fourth capacitor C04, a third comparator A3, a fourth comparator A4 and a second counter CNT2.

[0075] Among them, the third switch SW21 is connected to the column line COL of the corresponding column pixel unit, and the column line COL is used to transmit the pixel signal of the corresponding column pixel unit; the fourth switch SW22 is connected to the output end of the ramp generating circuit of the image sensor to obtain the ramp signal; the first end of the third capacitor C03 is connected to the third switch W21; the first end of the fourth capacitor C04 is connected to the fourth switch SW22; the first input end of the third comparator A3 is connected to the second end of the third capacitor C03, and the second input end of the third comparator A3 is connected to the second end of the fourth capacitor C04; the input end of the fourth comparator A4 is connected to the output end of the third comparator A3; the second counter CNT2 is connected to the output end of the fourth comparator A4, and is used to obtain the quantized value of the second gain signal according to the comparison result of the fourth comparator A4. Thus, the conversion of the second gain signal output by the corresponding column pixel unit is realized.

[0076] like Figure 4 As shown, the logic chip 10 of the embodiment of the present invention further includes a first column switching circuit group 18 and a second column switching circuit group 19 .

[0077] The first column switching circuit group 18 is arranged on the logic wafer 11, one end of the first column switching circuit group 18 is connected to the column line of the pixel array, and the other end of the first column switching circuit group 18 is connected to N first column-level analog-to-digital conversion circuits 12, which is used to switch the output of the first gain signal on the column line of the pixel array; the second column switching circuit group 19 is arranged on the logic wafer 11, one end of the second column switching circuit group 19 is connected to the column line of the pixel array, and the other end of the second column switching circuit group 19 is connected to N second column-level analog-to-digital conversion circuits 13, which is used to switch the output of the second gain signal on the column line of the pixel array.

[0078] In summary, the logic chip 10 of the embodiment of the present invention uses a dual-column analog-to-digital conversion circuit in the column readout circuit, which can greatly improve the circuit processing frame rate and reduce the conversion time of column analog-to-digital conversion under the condition of the same operating frequency. This means that the logic chip 10 of the embodiment of the present invention breaks through the technical bottleneck of the prior art, achieves a higher frame rate by reducing the operating frequency, and has better working characteristics.

[0079] Based on the logic chip of the above embodiment, a second embodiment of the present invention provides an image sensor.

[0080] like Figure 2As shown in FIG. 3 , the image sensor 100 according to the embodiment of the present invention includes a pixel chip 20 and the logic chip 10 according to the above embodiment.

[0081] The pixel chip 20 includes a pixel wafer 21 and a pixel array 22 disposed on the pixel wafer 21 . The pixel array 22 includes M rows×N columns of pixel units.

[0082] In an embodiment, the logic chip 10 and the pixel chip 20 may be stacked.

[0083] In some embodiments, the pixel array 22 in the pixel wafer 21 and the column-level analog-to-digital conversion circuit of the logic wafer 11 can be located at the center of the pixel wafer 21 and the center of the logic wafer 11, respectively, and related peripheral circuits can be further arranged around the pixel array 22 and the surrounding areas of the column-level analog-to-digital conversion circuit. In the pixel array 22 on the pixel wafer 21, the photoelectric conversion element and the pixel circuit can be designed into a two-dimensional matrix structure. The logic circuit of the logic chip 10 is arranged in the logic area of ​​the logic wafer 11. And, the vertical contacts for connecting the two chips can be arranged in the peripheral area so that the pixel chip 20 and the logic chip 10 can be electrically coupled to each other.

[0084] The image sensor 100 according to the embodiment of the present invention can reduce the conversion time of the column-level ADC circuit and greatly improve the image processing frame rate by adopting the logic chip 10 of the above embodiment under the condition of the same working frequency.

[0085] In an embodiment, the pixel chip 20 may be electrically connected to the logic chip 10 through silicon vias, so that the logic chip 10 may obtain pixel signals of pixel units of the pixel chip 20 , and then quantize and read out the pixel signals.

[0086] In an embodiment, the column lines of the column pixel units are electrically connected to the corresponding column-level analog-to-digital conversion circuits through silicon vias, so that the column-level analog-to-digital conversion circuits obtain pixel signals of the column pixel units through the correspondingly connected column lines, and then quantize and convert the pixel signals.

[0087] Furthermore, in some embodiments, Figure 4 As shown, each pixel unit includes a first photoelectric conversion unit LPD, a first transmission tube M1, a first storage node FD1, a source follower tube M2 and a selection tube M3.

[0088] The first end of the first photoelectric conversion unit LPD is grounded; the first end of the first transmission tube M1 is connected to the second end of the first photoelectric conversion unit LPD; the first storage node FD1 is connected to the second end of the first transmission tube M1; the first end of the source follower tube M2 is connected to the power supply VDDp, and the control end of the source follower tube M2 is connected to the first storage node FD1; the first end of the selection tube M3 is connected to the second end of the source follower tube M2, and the second end of the selection tube M3 is output to the corresponding column line COL. Through the first photoelectric conversion unit LPD and its transmission storage and readout circuit, the weak light signal can be collected.

[0089] like Figure 4 As shown, the pixel unit further includes a second photoelectric conversion unit SPD, a second transmission tube M4, a third storage node FD3, a third transmission tube M5, a second storage node FD2, a reset tube M6 and a gain conversion tube M7.

[0090] The first end of the second photoelectric conversion unit SPD is grounded, and the photosensitive area of ​​the second photoelectric conversion unit SPD is smaller than the photosensitive area of ​​the first photoelectric conversion unit LPD; the first end of the second transmission tube M4 is connected to the second end of the second photoelectric conversion unit SPD; the third storage node FD3 is connected to the storage capacitor; the first end of the third transmission tube M5 is connected to the third storage node FD3; the second storage node FD2 is connected to the second end of the third transmission tube M5; the first end of the reset tube M6 is connected to the power supply VDDp, and the second end of the reset tube M6 is connected to the second storage node FD2; the first end of the gain conversion tube M7 is connected to the second storage node FD2, and the second end of the gain conversion tube M7 is connected to the first storage node FD1. Through the second photoelectric conversion unit SPD and its transmission storage readout circuit, the collection of strong light signals can be realized.

[0091] Specifically, reset signal pulse RST, switch pulse signals FCG, DCG and RS; pulse control signals TXS and TXL. The transistor controlled by the RST reset signal resets the voltage at the FD1 point to VDDp. The DCG pulse control signal enables the pixel circuit to operate in low gain mode or high gain mode. The RS pulse signal controls the signal output of a certain row of selected pixels. The pulse control signals TXL and TXS control the image signal transmission of the large photodiode LPD and the small photodiode SPD respectively. The photodiodes SPD and LPD convert the incident light signal into an electrical signal, and the output pixel signal is Vpix.

[0092] The switches SW11, SW12 and SW21, SW22 control the pixel signals to be transmitted to the high and low gain analog-to-digital converters (ADCE and ADCO). AZ_CMPT1 and AZ_CMPB1 are reset signals of the analog-to-digital converters, respectively.

[0093] Furthermore, the signal transmission path and delay between the pixel column bus output and the column-level readout circuit sampling and holding capacitors (C01-C04) are analyzed. Figure 2 As shown, the delay T0 caused by the parasitic resistance R1 and the capacitance C1 on the column bus of the pixel chip 20 is considered. Therefore, for the Nth row of pixels, the delay of converting LCG is τ0=N×T0. Next, the signal transmission enters the second part of the delay, which takes into account the delay τ1=T1 caused by the interconnection between the pixel wafer 21 and the logic wafer 11. Finally, the delay τ2 introduced by the wiring from the peripheral area of ​​the logic wafer 11 to the column-level readout circuit of the LCG (or HCG). In the chip architecture scheme of the image sensor of an embodiment of the present invention, taking the transmission of the first row of pixels as an example, the delay and voltage drop of the LCG signal and the HCG signal output by the column pixels are analyzed respectively. According to the above analysis, combined with Figure 4 It can be seen that on the logic chip, the distance from the tail current source Pixel_Iload to the column sampling and holding capacitor C01 of the upper column-level ADC circuit in the figure is approximately equal to the distance to the column sampling and holding capacitor C03 of the lower column-level ADC circuit, and the delay of converting LCG on the logic chip is equal to the delay of converting HCG on the logic chip. For the same row of pixels, the delay caused by the parasitic resistance R1 and capacitor C1 on the column bus of the pixel chip 20 is equal, and the delay caused by the interconnection between the pixel chip 20 and the logic chip 10 is a fixed value T1. Therefore, the total delay of converting LCG is equal to the total delay of converting HCG.

[0094] From the perspective of voltage drop, the line resistance of the signals of the odd and even columns in the same row reaching the ADC is the same, and the total capacitance can also be kept consistent. In this way, the total voltage drop and delay of the odd and even column pixel signals when reaching the column sampling and protection capacitors are consistent, thereby improving the consistency between columns. Since the odd and even columns of each row reach the output point on the same side, the consistency of the odd and even columns within each row can be ensured (compatible with the original design scheme).

[0095] For Figure 3 The solution of placing the analog-to-digital conversion circuit groups on the upper and lower sides, although it looks symmetrical, is actually highly related to the position of the readout row in the array. Taking the first row of pixels as an example, assuming that the odd columns are upward and the even columns are downward, then the resistance R1 of the even column bus is N times that of the odd column R1. Although the parasitic capacitance is the same, there will be obvious differences in delay and voltage drop. When the readout row is located in the center of the array, the odd and even columns are consistent. The other non-middle rows will also have inconsistencies in the odd and even columns.

[0096] However, for Figure 2 and Figure 3 The arrangement of the column-level ADC circuit shown can reduce the conversion time of the column-level ADC by corresponding one column of pixel units to two column-level ADC circuits, thereby achieving the effect of improving the circuit processing frame rate.

[0097] Based on the image sensor of the above embodiment, the third aspect of the present invention further provides an electronic device.

[0098] Figure 5 is a block diagram of an electronic device according to an embodiment of the present invention, such as Figure 5 As shown, the electronic device 1000 of the embodiment of the present invention includes the image sensor 100 of the above embodiment. The specific structure of the image sensor 100 can refer to the description of the above embodiment, which will not be described again.

[0099] In an embodiment, the electronic device 1000 may include but is not limited to a smart phone, a tablet, or a vehicle-mounted image acquisition device and other devices with an image acquisition function.

[0100] According to the electronic device 1000 of the embodiment of the present invention, by adopting the image sensor 100 of the above embodiment, the conversion speed of the column-level analog-to-digital conversion circuit can be improved, the data conversion time of the column-level analog-to-digital conversion circuit can be reduced, the frame rate of image processing can be increased, and the imaging quality can be improved.

[0101] Based on the image sensor of the above embodiment, a fourth aspect of the present invention further provides a vehicle.

[0102] Figure 6 is a block diagram of a vehicle according to an embodiment of the present invention, such as Figure 6 As shown, the vehicle 1 includes the image sensor 100 of the above embodiment.

[0103] In an embodiment, the image sensor 100 may be an image sensor on a vehicle-mounted camera or a vehicle-mounted tablet, or an image sensor 100 of a vehicle-mounted device having an image acquisition function.

[0104] According to the vehicle 1 of the embodiment of the present invention, by adopting the image sensor 100 of the above embodiment, the conversion speed of the column-level analog-to-digital conversion circuit can be improved, the data conversion time of the column-level analog-to-digital conversion circuit can be reduced, the frame rate of image processing can be improved, data support can be provided for the control strategy based on the image processing results in the vehicle, and the vehicle performance can be improved.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0106] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A logic chip for an image sensor, characterized in that: The image sensor includes a pixel array, the pixel array includes N columns of pixel units, N≥1, and the logic chip includes: Logic wafers; N first column-level analog-to-digital conversion circuits, the N first column-level analog-to-digital conversion circuits are located on the logic wafer, the nth first column-level analog-to-digital conversion circuit is used to convert a first gain signal output by an nth column of pixel units, n≤N; N second column-level analog-to-digital conversion circuits, the N second column-level analog-to-digital conversion circuits are located on the logic wafer, and the nth second column-level analog-to-digital conversion circuit is used to convert the second gain signal output by the nth column pixel unit, wherein the conversion gain of the second gain signal is different from that of the first gain signal.

2. The logic chip according to claim 1, characterized in that: The N first column-level analog-to-digital conversion circuits are arranged along the direction in which the pixel unit columns of the pixel array are arranged, and the N second column-level analog-to-digital conversion circuits are arranged along the direction in which the pixel unit columns of the pixel array are arranged.

3. The logic chip according to claim 1, characterized in that: The logic wafer includes a central area and a peripheral area, the N first column-level analog-to-digital conversion circuits form a first column-level analog-to-digital conversion circuit group, the N second column-level analog-to-digital conversion circuits form a second column-level analog-to-digital conversion circuit group, and the first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group are located in the central area of ​​the logic wafer.

4. The logic chip according to claim 3, characterized in that: The first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group are both located in a first logic area of ​​the central region, and the first logic area deviates from the center of the central region.

5. The logic chip according to claim 4, characterized in that: The logic chip further includes: A first tail current source, the first tail current source is located in the logic wafer, the first tail current source is located between the first column-level analog-to-digital conversion circuit group and the second column-level analog-to-digital conversion circuit group, and the first tail current source is respectively connected to the column bus of the image sensor, the first column-level analog-to-digital conversion circuit group, and the second column-level analog-to-digital conversion circuit group.

6. The logic chip according to claim 3, characterized in that: The first column-level analog-to-digital conversion circuit group is located in the second logic area of ​​the central area, and the second column-level analog-to-digital conversion circuit group is located in the third logic area of ​​the central area. The second logic area and the third logic area are both offset from the center of the central area, and the second logic area is arranged opposite to the third logic area.

7. The logic chip according to claim 6, characterized in that: The logic chip further includes: A second tail current source is provided in the second logic area, and the second tail current source is respectively connected to the column bus of the image sensor and the first column-level analog-to-digital conversion circuit group.

8. The logic chip according to claim 7, characterized in that: The second tail current source is located outside the first column-level analog-to-digital conversion circuit group, and the outside is a side away from the center of the central area of ​​the logic wafer.

9. The logic chip according to claim 6, characterized in that: The logic chip further includes: A third tail current source is located in the third logic area and is connected to the column bus of the image sensor and the second column-level analog-to-digital conversion circuit group respectively.

10. The logic chip according to claim 9, characterized in that: The third tail current source is located outside the second column-level analog-to-digital conversion circuit group, and the outside is a side away from the center of the central area of ​​the logic wafer.

11. The logic chip according to claim 1, characterized in that: Each of the first column-level analog-to-digital conversion circuits comprises: A first switch connected to a column line of a corresponding column of pixel units; a second switch connected to an output terminal of a ramp generating circuit of the image sensor; a first capacitor, wherein a first end of the first capacitor is connected to the first switch; a second capacitor, wherein a first end of the second capacitor is connected to the second switch; A first comparator, wherein a first input terminal of the first comparator is connected to a second terminal of the first capacitor, and a second input terminal of the first comparator is connected to a second terminal of the second capacitor; a second comparator, wherein an input terminal of the second comparator is connected to an output terminal of the first comparator; A first counter is connected to the output end of the second comparator and is used to obtain a quantized value of the first gain signal according to a comparison result of the second comparator.

12. The logic chip according to claim 11, characterized in that: Each of the second column-level analog-to-digital conversion circuits comprises: A third switch, wherein the third switch is connected to a column line of a corresponding column of pixel units; a fourth switch connected to an output end of a ramp generating circuit of the image sensor; a third capacitor, a first end of the third capacitor being connected to the third switch; a fourth capacitor, a first end of the fourth capacitor being connected to the fourth switch; a third comparator, wherein a first input terminal of the third comparator is connected to the second terminal of the third capacitor, and a second input terminal of the third comparator is connected to the second terminal of the fourth capacitor; a fourth comparator, wherein an input terminal of the fourth comparator is connected to an output terminal of the third comparator; A second counter, wherein the second counter is connected to the output end of the fourth comparator and is used to obtain a quantized value of the second gain signal according to a comparison result of the fourth comparator.

13. The logic chip according to claim 1, characterized in that: The logic chip further includes: A first column switching circuit group, wherein the first column switching circuit group is located on the logic wafer, one end of the first column switching circuit group is connected to the column line of the pixel array, and the other end of the first column switching circuit group is connected to N first column-level analog-to-digital conversion circuits, for switching the output of the first gain signal on the column line of the pixel array.

14. The logic chip according to claim 13, characterized in that: The logic chip further includes: A second column switching circuit group, the second column switching circuit group is located on the logic wafer, one end of the second column switching circuit group is connected to the column line of the pixel array, and the other end of the second column switching circuit group is connected to N second-column-level analog-to-digital conversion circuits, for switching the output of the second gain signal on the column line of the pixel array.

15. The logic chip according to claim 3, characterized in that: The logic chip further includes: The peripheral circuit is arranged in the peripheral area of ​​the logic wafer and is located around the first column-level analog-to-digital conversion circuit group and / or the second column-level analog-to-digital conversion circuit group.

16. The logic chip according to claim 3, characterized in that: The logic chip further includes: The electrical interconnection contacts are arranged in the peripheral area of ​​the logic wafer, and the electrical interconnection contacts are used to connect the pixel chip of the image sensor.

17. An image sensor, characterized in that: include: A pixel chip, the pixel chip comprising a pixel wafer and a pixel array arranged on the pixel wafer, the pixel array comprising M rows×N columns of pixel units; The logic chip according to any one of claims 1 to 16, wherein the logic chip is stacked with the pixel chip.

18. The image sensor according to claim 17, characterized in that: The pixel chip is electrically connected to the logic chip through silicon via routing.

19. The image sensor according to claim 17, characterized in that: The column lines of the column pixel units are electrically connected to the corresponding column-level analog-to-digital conversion circuits through silicon vias.

20. The image sensor according to claim 17, wherein: Each of the pixel units comprises: A first photoelectric conversion unit, wherein a first terminal of the first photoelectric conversion unit is grounded; a first transmission tube, wherein a first end of the first transmission tube is connected to a second end of the first photoelectric conversion unit; a first storage node, the first storage node being connected to the second end of the first transmission tube; A source follower tube, wherein a first end of the source follower tube is connected to a power source, and a control end of the source follower tube is connected to the first storage node; A selection tube, wherein the first end of the selection tube is connected to the second end of the source follower tube, and the second end of the selection tube is output to the corresponding column line.

21. The image sensor according to claim 20, characterized in that The pixel unit also includes: a second photoelectric conversion unit, wherein a first end of the second photoelectric conversion unit is grounded, and a photosensitive area of ​​the second photoelectric conversion unit is smaller than a photosensitive area of ​​the first photoelectric conversion unit; a second transmission tube, wherein a first end of the second transmission tube is connected to a second end of the second photoelectric conversion unit; a third storage node, wherein the third storage node is connected to the storage capacitor; a second switch tube, wherein a second end of the second switch tube is connected to the second storage node; A second storage node, wherein the second storage node is connected to a second end of the gain conversion tube; A reset tube, wherein a first end of the reset tube is connected to a power source, and a second end of the reset tube is connected to the second storage node; A gain conversion tube, wherein a first end of the gain conversion tube is connected to the second storage node, and a second end of the gain conversion tube is connected to the first storage node.

22. An electronic device, characterized in that: The image sensor comprises any one of claims 17-21.

23. A vehicle, characterized in that: The image sensor comprises any one of claims 17-21.

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