Manufacturing method of IC carrier plate
By pre-made circuit layers and conducting columns of the IC carrier plate on the bearing plate, and using the combination of dielectric layer and riveting layer, the problems of large equipment investment, complex processes and insufficient line binding force in the existing IC carrier plate process are solved, and higher process capabilities and yields are achieved, reducing costs.
Patent Information
- Application Number
- CN202411905266.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-03-25
AI Technical Summary
The existing IC carrier plate production process has problems such as large equipment investment, complex process, increased copper thickness on through hole filling electroplating, insufficient line binding force, difficulty in controlling interlayer alignment, material shrinkage deformation and graphics consistency.
The circuit layer and conducting column are pre-made on the bearing plate. The electrical connection between the conducting column and the circuit layer is achieved through the combination of the dielectric layer and the rivet layer, and the accurate alignment between the layers is ensured through the alignment method between the PIN hole and the PIN needle.
It improves process capabilities and product yields, reduces equipment investment costs, enhances line reliability and alignment accuracy, simplifies processes, and reduces costs.
Smart Images
Figure CN119697908A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of IC carrier boards, and in particular to a method for manufacturing an IC carrier board. Background Art
[0002] The mainstream process for existing IC substrates is mSAP, or semi-additive process. The main technical features of this process are: 1) First, a very thin metal base layer is formed, and the required circuit pattern is added through this metal base layer, and then the metal layer of the non-patterned part is etched away; 2) Vias are first made between circuit layers, and then the vias are metallized; 3) The alignment between circuit layers and between circuit layers and vias depends on the CCD optical alignment of the equipment.
[0003] The process equipment investment is large, the process is complex, and it faces several bottlenecks that affect the process capability and mass production yield: 1) The thickness of the surface copper will increase when the via is filled with electroplating, which is not conducive to the production of fine circuits; 2) The circuit is attached to the surface of the dielectric layer, and insufficient bonding will lead to flying wires, gaps and other defects, especially for fine circuits, where this defect is more obvious; 3) As the multi-layer boards are stacked layer by layer, the deviation between the layers is difficult to control, resulting in deviation between the micro-holes and the target pads and between the layers, resulting in defective products; 3) The expansion and contraction of the material and the consistency of the pattern are difficult to control.
[0004] Therefore, the prior art has defects and needs to be improved. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing an IC substrate, improve process capability, increase product yield, and reduce equipment investment costs.
[0006] The technical solution of the present invention is as follows: a method for manufacturing an IC carrier is provided, comprising the following steps.
[0007] S1: manufacturing a first circuit layer on a first carrier board, and manufacturing a second circuit layer on a second carrier board.
[0008] S2: Making conductive pillars on the first circuit layer.
[0009] S3: filling a dielectric layer between the first circuit layer and the second circuit layer and pressing them together so that the conductive pillar is electrically connected to the second circuit layer; wherein the second circuit layer is provided with a docking interface that cooperates with the conductive pillar.
[0010] Furthermore, the manufacturing method of the IC carrier board also includes: S4: removing the second carrier board; S5: manufacturing a riveting layer on the second circuit layer, and the conductive column passes through the docking interface to connect with the riveting layer.
[0011] Furthermore, a pre-opening is preliminarily made at a position of the dielectric layer corresponding to the conducting column; a release layer is arranged on the first carrier board and the second carrier board, and the first carrier board and the second circuit layer are arranged on the release layer.
[0012] Furthermore, the first supporting plate and the second supporting plate are metal substrates or non-metal substrates with a metal layer attached thereto.
[0013] Furthermore, the manufacturing method of the first circuit layer is: coating a photosensitive layer on the first carrier plate, removing the photosensitive layer in the area with the first circuit layer image through exposure and development, generating the first circuit layer by electroplating, and removing the photosensitive layer in other positions to obtain the first circuit layer.
[0014] Furthermore, the manufacturing method of the second circuit layer is: coating a photosensitive layer on the second carrier plate, removing the photosensitive layer in the area with the second circuit layer image through exposure and development, electroplating to generate the second circuit layer, and removing the photosensitive layer in other positions to obtain the second circuit layer.
[0015] Furthermore, the method for making the conductive column is: coating a photosensitive layer on the first carrier board on which the first circuit layer is made, removing the photosensitive layer in the area with the conductive column image through exposure and development, generating the conductive column by electroplating, and removing the photosensitive layer in other positions to obtain the conductive column.
[0016] Furthermore, the preparation method of the riveted layer is as follows: after removing the second carrier board, the second circuit layer and the conductive column position are exposed, the residual substances at the conductive column position are cleaned, and one end of the conductive column is exposed; a photosensitive layer is coated on the second circuit layer and the dielectric layer, and the photosensitive layer in the area with the riveted layer image is removed through exposure and development, the riveted layer is generated by electroplating, and the photosensitive layer at other positions is removed to obtain the riveted layer; the riveted layer is directly generated by electroplating on the surface of the conductive column.
[0017] Furthermore, the riveting layer is a mushroom head structure.
[0018] Furthermore, the dielectric layer is: epoxy resin, polyimide, ABF insulating material, one or more superpositions thereof.
[0019] Furthermore, during pressing, the first carrier plate, the second carrier plate and the dielectric layer are pressed together, and PIN holes are reserved on the first carrier plate and the second carrier plate, and the PIN pins are used to align and fix the layers during pressing.
[0020] Furthermore, for the production of multiple layers, the above steps S1-S5 are repeated.
[0021] Compared with the existing carrier board manufacturing process, the present invention: all circuit layers are pre-fabricated on the carrier board, which is not affected by the change of copper thickness and surface conditions in the subsequent process, and it is easier to manufacture fine circuits; each layer of the circuit is embedded in the dielectric layer, and the conductive column can form a "mushroom head" with a riveted structure between the circuit layer, which is better in terms of reliability such as heat shock resistance; by forming the alignment between the layers while pressing the preset openings and PIN columns on the carrier board, the process is simple and controllable, which not only reduces costs but also can better control the yield.
[0022] By adopting the above scheme, the present invention provides a method for manufacturing an IC carrier, wherein a first circuit layer and a conductive column on the first circuit are manufactured on a first carrier, and a second circuit layer is manufactured on a second carrier, wherein the second circuit layer is provided with a docking interface that cooperates with the conductive column, and then a dielectric layer is filled and pressed between the first circuit layer and the second circuit layer, so that the conductive column is electrically connected to the second circuit layer; compared with the existing carrier manufacturing process: all circuit layers are pre-manufactured on the carrier, which is not affected by the change in copper thickness and surface conditions in the later process, and it is easier to manufacture fine circuits; each layer of the circuit is embedded in the dielectric layer, and the conductive column can form a "mushroom head" with a riveted structure between the circuit layer, which is more excellent in terms of reliability such as heat resistance and shock resistance; by forming the alignment between the layers while pressing the openings preset on the carrier and the PIN column, the process is simple and controllable, which not only reduces costs but also can better control the yield. Furthermore, the alignment method of the PIN hole and the PIN needle is adopted to fully ensure the accurate docking of the conductive column and the docking interface. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a structural schematic diagram of the first carrier board, the release layer and the first circuit layer of the present invention;
[0024] Figure 2 It is a schematic structural diagram of the second carrier board, the release layer and the second circuit layer of the present invention;
[0025] Figure 3 A schematic diagram of the structure of a conductive column produced in the first circuit layer;
[0026] Figure 4 It is a structural schematic diagram when step S3 is performed;
[0027] Figure 5 A structural schematic diagram of a riveting layer is produced after removing the second carrier plate and the release layer. DETAILED DESCRIPTION
[0028] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0029] The invention provides a method for manufacturing an IC carrier, comprising the following steps.
[0030] S1: Fabricate a first circuit layer 11 on a first carrier board 10, and fabricate a second circuit layer 13 on a second carrier board 12. Figure 1 The specific steps of making the first circuit layer 11 on the first carrier board 10 are: select the first carrier board 10, pre-treat the surface of the first carrier board 10 to facilitate peeling; then coat the first carrier board 10 with a photosensitive material, then illuminate the non-first circuit layer area to solidify the non-first circuit layer area, then remove the photosensitive material in the first circuit layer area, and then make the first circuit layer by electroplating addition method and remove the photosensitive material in the non-first circuit layer area. Similarly, please participate Figure 2 The specific steps of making the second circuit layer 13 on the second carrier board 12 are: select the second carrier board 12, pre-treat the surface of the second carrier board 12 to facilitate peeling; then coat the photosensitive material on the second carrier board 12, and then illuminate the non-second circuit layer area to make the non-second circuit layer area solidified (i.e., exposed and developed), then remove the photosensitive material in the second circuit layer area, and then make the second circuit layer by electroplating addition method and remove the photosensitive material in the non-second circuit layer area.
[0031] S2: Make a conductive column 14 on the first circuit layer. Figure 3 The specific steps are as follows: coating the photosensitive material on the first carrier board 10 and the first circuit layer, then curing the photosensitive material in the non-conducting column area by light, then removing the photosensitive material in the non-conducting column area, and finally forming the conducting column 14 by electroplating and removing the excess photosensitive material. The formation of the conducting column 14 may require repeating step S3 several times so that the conducting column 14 meets the designed thickness. In practical applications, the thickness of the conducting column 14 is generally the thickness of the dielectric layer and the second circuit layer.
[0032] S3: Fill the dielectric layer 15 between the first circuit layer and the second circuit layer and press them together, so that the conductive pillar 14 is electrically connected to the second circuit layer; wherein the second circuit layer is provided with a docking port 16 that cooperates with the conductive pillar 14. Figure 4 , the first carrier board 10 loaded with the first circuit layer and the conductive pillar 14, the dielectric layer 15, and the second carrier board 12 containing the second circuit layer are assembled by PIN alignment to achieve lamination. In practical applications, for example, the dielectric layer 15 can be made of a prepreg, and the prepreg is provided with a hole that matches the conductive pillar 14, so as to prevent the dielectric of the dielectric layer 15 from squeezing into the docking interface 16 during the lamination process, thereby affecting the conduction performance.
[0033] S4: removing the second carrying plate 12.
[0034] S5: Make a riveting layer 17 on the second circuit layer, and the conductive pillar 14 passes through the docking interface 16 to connect with the riveting layer 17. The riveting layer 17 can further strengthen the connection between the conductive pillar 14 and the second circuit layer to prevent the conductive pillar 14 from being separated from the docking interface 16. Figure 5 .
[0035] In this embodiment, a pre-opening is preliminarily performed at a position of the dielectric layer 15 corresponding to the conductive pillar 14; a release layer 20 is provided on the first carrier board 10 and the second carrier board 12, and the first carrier board 10 and the second circuit layer are provided on the release layer 20. The release layer can facilitate the removal of the first carrier board 10 and the second carrier board 12 according to actual application requirements.
[0036] In this embodiment, the first carrier plate 10 and the second carrier plate 12 are both non-metallic substrates with a metal layer attached thereon, such as a copper clad laminate.
[0037] In this embodiment, the manufacturing method of the first circuit layer is: coating a photosensitive layer on the first carrier board 10, removing the photosensitive layer in the area with the first circuit layer image through exposure and development, generating the first circuit layer by electroplating, and removing the photosensitive layer in other positions to obtain the first circuit layer.
[0038] In this embodiment, the manufacturing method of the second circuit layer is: coating a photosensitive layer on the second carrier board 12, removing the photosensitive layer in the area with the second circuit layer image through exposure and development, generating the second circuit layer by electroplating, and removing the photosensitive layer in other positions to obtain the second circuit layer.
[0039] In this embodiment, the manufacturing method of the conductive column 14 is as follows: a photosensitive layer is coated on the first carrier board 10 on which the first circuit layer is manufactured, the photosensitive layer in the area with the conductive column image is removed through exposure and development, the conductive column 14 is generated by electroplating, and the photosensitive layer in other positions is removed to obtain the conductive column 14.
[0040] In this embodiment, the preparation method of the riveted layer 17 is as follows: after removing the second carrier plate 12, the second circuit layer 13 and the position of the conductive column 14 are exposed, the residual substances at the position of the conductive column 14 are cleaned, and one end of the conductive column 14 is exposed; a photosensitive layer is coated on the second circuit layer 13 and the dielectric layer 15, and the photosensitive layer in the area with the riveted layer image is removed through exposure and development, and the riveted layer 17 is generated by electroplating, and the photosensitive layer at other positions is removed to obtain the riveted layer 17; the riveted layer 17 is directly generated by electroplating on the surface of the conductive column 14.
[0041] The preparation method of the riveted layer 17 is as follows: a photosensitive layer is coated on the surface of the second carrier plate 12, the photosensitive layer in the area with the riveted layer 17 image is removed through exposure and development, the riveted layer 17 is generated by electroplating, and the photosensitive layer in other positions is removed to obtain the riveted layer 17; the riveted layer 17 is directly generated by electroplating on the surface of the conductive column 14.
[0042] In this embodiment, the riveting layer 17 is a mushroom head structure. The mushroom head structure can improve the connection strength.
[0043] In this embodiment, the dielectric layer 15 is: epoxy resin, polyimide, ABF insulating material, or a combination of the two.
[0044] In this embodiment, during the pressing, the first carrier plate 10, the second carrier plate 12, and the dielectric layer 15 are pressed together, and there are reserved PIN holes on the first carrier plate 10 and the second carrier plate 12, and the PIN pins are used to align and fix each layer during the pressing. The PIN hole and PIN pin alignment method is adopted to fully ensure the accurate docking of the conductive column 14 and the docking interface 16.
[0045] In summary, the present invention provides a method for manufacturing an IC carrier, by manufacturing a first circuit layer and a conductive column on the first circuit on a first carrier, and manufacturing a second circuit layer on a second carrier, wherein the second circuit layer is provided with a docking interface that cooperates with the conductive column, and then a dielectric layer is filled and pressed between the first circuit layer and the second circuit layer, and then the conductive column is electrically connected to the second circuit layer by electroplating growth; compared with the existing carrier manufacturing process: all circuit layers are pre-made on the carrier, which is not affected by the change of copper thickness and surface conditions in the later process, and it is easier to manufacture fine circuits; each layer of the circuit is embedded in the dielectric layer, and the conductive column can form a "mushroom head" with a riveted structure between the circuit layer, which is more excellent in terms of reliability such as heat resistance and shock resistance; by forming the alignment between the layers while pressing the preset openings and PIN columns on the carrier, the process is simple and controllable, which not only reduces costs but also can better control the yield. Furthermore, the alignment method of the PIN hole and the PIN needle is adopted to fully ensure the accurate docking of the conductive column and the docking interface.
[0046] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the rules, processes and process methods of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for manufacturing an IC substrate, characterized in that: The following steps are involved: S1: manufacturing a first circuit layer on a first carrier board, and manufacturing a second circuit layer on a second carrier board; S2: Making conductive pillars on the first circuit layer; S3: filling a dielectric layer between the first circuit layer and the second circuit layer and pressing them together so that the conductive pillar is electrically connected to the second circuit layer; wherein the second circuit layer is provided with a docking interface that cooperates with the conductive pillar.
2. The method for manufacturing an IC substrate according to claim 1, characterized in that: Also includes: S4: removing the second carrying plate; S5: manufacturing a riveting layer on the second circuit layer, and the conducting column passes through the docking interface and is connected to the riveting layer.
3. The method for manufacturing an IC substrate according to claim 1, characterized in that: A pre-opening is preliminarily performed at a position of the dielectric layer corresponding to the conducting column; a release layer is arranged on the first carrier board and the second carrier board, and the first carrier board and the second circuit layer are arranged on the release layer.
4. The method for manufacturing an IC substrate according to claim 1, characterized in that: The first carrier plate and the second carrier plate are a metal substrate or a non-metal substrate with a metal layer attached thereon; the dielectric layer is: epoxy resin, polyimide, ABF insulating material, one or more superpositions thereof.
5. The method for manufacturing an IC substrate according to claim 1, characterized in that: The manufacturing method of the first circuit layer is as follows: coating a photosensitive layer on a first carrier plate, removing the photosensitive layer in the area with the first circuit layer image through exposure and development, electroplating to generate the first circuit layer, and removing the photosensitive layer in other positions to obtain the first circuit layer; The manufacturing method of the second circuit layer is: coating a photosensitive layer on the second carrier plate, removing the photosensitive layer in the area with the second circuit layer image through exposure and development, electroplating to generate the second circuit layer, and removing the photosensitive layer in other positions to obtain the second circuit layer.
6. The method for manufacturing an IC substrate according to claim 1, characterized in that: The manufacturing method of the conductive column is as follows: coating a photosensitive layer on a first carrier board on which a first circuit layer is manufactured, removing the photosensitive layer in the area with the conductive column image through exposure and development, generating the conductive column by electroplating, and removing the photosensitive layer in other positions to obtain the conductive column.
7. The method for manufacturing an IC substrate according to claim 2, characterized in that: The preparation method of the riveted layer is as follows: after removing the second carrier plate, the second circuit layer and the position of the conductive column are exposed, the residual substances at the position of the conductive column are cleaned, and one end of the conductive column is exposed; a photosensitive layer is coated on the second circuit layer and the dielectric layer, and the photosensitive layer in the area with the riveted layer image is removed through exposure and development, the riveted layer is generated by electroplating, and the photosensitive layer at other positions is removed to obtain the riveted layer; the riveted layer is directly generated by electroplating on the surface of the conductive column.
8. The method for manufacturing an IC substrate according to claim 2, characterized in that: The riveting layer is a mushroom head structure.
9. The method for manufacturing an IC substrate according to claim 1, characterized in that: During the pressing process, the first carrier plate, the second carrier plate and the dielectric layer are pressed together. There are reserved PIN hole positions on the first carrier plate and the second carrier plate. During the pressing process, the PIN pins are used to align and fix each layer.
10. The method for manufacturing an IC substrate according to claim 1, characterized in that: For multiple layers, repeat the above steps.