Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a wire stacking structure, the wire stacking structure comprises a plurality of wire layers which are arranged at intervals in the vertical direction, each wire layer comprises a first wire part and a second wire part, and the wire layers extend in the first direction; the storage structure is located on one side of the wire stacking structure in the second direction, and the storage structure is electrically connected with the first wire part; the contact plug is located on the other side of the wire stacking structure in the second direction, and the contact plug is electrically connected with the first wire part; and the shielding structure is at least clamped between the adjacent second wire parts in the vertical direction. The semiconductor structure can reduce parasitic capacitance in the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures based on existing structures is a favorable means to break through existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal memory cells (MHC), which usually includes bit lines, transistors and capacitors stacked on a substrate, meets the above needs. As the integration of semiconductor structures increases, the number of memory cells that can be accommodated increases, and the performance of semiconductor structures is also better.

[0004] However, as the number of stacked layers increases, the parasitic capacitance within the semiconductor structure becomes larger and larger. Therefore, a semiconductor structure with a new architecture is urgently needed to improve the integration of the semiconductor structure and reduce the parasitic capacitance within the semiconductor structure. Summary of the invention

[0005] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a wire stacking structure, the wire stacking structure comprising a plurality of wire layers spaced apart in a vertical direction, the wire layers comprising a first wire portion and a second wire portion, the wire layers extending along a first direction; a storage structure located on one side of the wire stacking structure along the second direction, the storage structure being electrically connected to the wire layer; a contact plug located on the other side of the wire stacking structure along the second direction, the contact plug being electrically connected to the first wire portion; and a shielding structure, the shielding structure being sandwiched at least between adjacent second wire portions in the vertical direction.

[0006] In some embodiments, the semiconductor structure also includes a substrate; the projection of the wire layer on the substrate is a ring shape, the wire layer includes two first wire portions arranged in parallel along a second direction, and the two second wire portions are respectively connected to the two ends of the two first wire portions; the storage structure includes a first storage structure and a second storage structure, and the first storage structure and the second storage structure are respectively located on opposite sides of the wire stacking structure.

[0007] In some embodiments, the second conductor portion includes a first sub-portion, a second sub-portion, and a third sub-portion connected in sequence, the first sub-portion and the third sub-portion are respectively connected to two first conductor portions, and the first sub-portion, the second sub-portion, and the third sub-portion surround a first groove; the shielding structure includes a vertical shielding portion and a horizontal shielding portion, the vertical shielding portion is located in the first groove and extends in the vertical direction, and the horizontal shielding portion is located between adjacent second conductor portions in the vertical direction.

[0008] In some embodiments, the shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second conductor portion, and the dielectric shielding layer conformally covers a surface of the second conductor portion.

[0009] In some embodiments, a plurality of contact plugs are arranged at intervals along a first direction, and the plurality of contact plugs are electrically connected to a plurality of first wire portions one by one; the contact plugs include a vertical conductive portion and a conductive connecting portion, the conductive connecting portion is in contact with the corresponding first wire portion, and a dimension of the conductive connecting portion in a second direction is greater than a dimension of the vertical conductive portion in the second direction; the semiconductor structure also includes: a spacer layer surrounding the side wall of the vertical conductive portion, the spacer layer being in contact with the wire stacking structure.

[0010] In some embodiments, the storage structure includes a storage layer located at the same layer as each conductor layer, the storage layer includes a plurality of storage cells arranged at intervals along a first direction, each storage cell includes a transistor structure and a capacitor structure, one end of the transistor structure along a second direction is electrically connected to the corresponding first conductor portion, and the other end is electrically connected to the capacitor structure.

[0011] According to a second aspect of an embodiment of the present disclosure, another semiconductor structure is provided, including: a substrate; a wire stacking structure, the wire stacking structure including a plurality of wire layers spaced apart in a vertical direction, the wire layers extending along a first direction, the wire layers including a first wire layer and a second wire layer spaced apart in a second direction, the projections of the first wire layer and the second wire layer on the substrate being a ring; a first storage structure and a second storage structure located on both sides of the wire stacking structure along the second direction, the first storage structure being electrically connected to the first wire layer, and the second storage structure being electrically connected to the second wire layer; a contact plug located between the first wire layer and the second wire layer, the contact plug being electrically connected to both the first wire layer and the second wire layer; and a shielding structure, the shielding structure being at least sandwiched between adjacent wire layers in the vertical direction.

[0012] In some embodiments, the first wire layer and the second wire layer both include a first wire portion and a second wire portion located at both ends of the first wire portion, and the first wire portion and the second wire portion surround a strip groove; the shielding structure includes a vertical shielding portion and a horizontal shielding portion, the vertical shielding portion is located in the strip groove and extends in the vertical direction, and the horizontal shielding portion is located between adjacent second wire portions in the vertical direction.

[0013] In some embodiments, a plurality of contact plugs are arranged at intervals along a first direction, and the plurality of contact plugs are electrically connected to a first wire layer and a second wire layer located in corresponding layers, respectively; the contact plugs include a vertical conductive portion and a conductive connecting portion, the conductive connecting portion is in contact with both the first wire layer and the second wire layer located in the corresponding layer, and a dimension of the conductive connecting portion in the second direction is greater than a dimension of the vertical conductive portion in the second direction; the semiconductor structure also includes: a spacer layer surrounding the side wall of the vertical conductive portion, the spacer layer being in contact with the wire stacking structure.

[0014] According to a third aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: forming a wire stacking structure, the wire stacking structure comprising a plurality of wire layers spaced apart in a vertical direction, the wire layers comprising a first wire portion and a second wire portion, and the wire layers extending in a first direction; forming a storage structure located on one side of the wire stacking structure along the second direction, the storage structure being electrically connected to the wire layer; forming a contact plug located on the other side of the wire stacking structure along the second direction, the contact plug being electrically connected to the first wire portion; and forming a shielding structure, the shielding structure being sandwiched at least between adjacent second wire portions in the vertical direction.

[0015] In some embodiments, the semiconductor structure also includes a substrate; the projection of the wire layer on the substrate is a ring; a contact plug is formed on the other side of the wire stacking structure along the second direction, including: forming a filling dielectric layer in the strip groove enclosed by the wire layer, the filling dielectric layer penetrates the wire stacking structure along the vertical direction; forming a plurality of vertical plug holes arranged at intervals along the first direction in the filling dielectric layer, and each vertical plug hole has a different depth; forming a spacing layer on the side wall of the vertical plug hole; forming a connecting hole connected to the bottom of the vertical plug hole, the connecting hole exposing a portion of the side wall of the corresponding first wire portion; filling the contact plug in the vertical plug hole and in the connecting hole.

[0016] In some embodiments, a first dielectric layer is sandwiched between adjacent wire layers in the vertical direction, and the wire layer includes two first wire portions arranged in parallel along a second direction, and the two second wire portions are respectively connected to two ends of the two first wire portions; a shielding structure is formed, including: forming a first groove in the filling dielectric layer to expose the second wire portion; removing the first dielectric layer between adjacent second wire portions in the vertical direction along the first groove to form a wire gap; forming a shielding structure in the wire gap and the first groove, the shielding structure including a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second wire portion, and the dielectric shielding layer conformally covers the surface of the second wire portion.

[0017] In the embodiment of the present disclosure, by providing a contact plug electrically connected to the wire layer in the second direction, it is possible to avoid additionally forming a step structure region for connecting each layer of the wire layer, thereby effectively improving the integration of the semiconductor structure. In addition, by providing a shielding structure coupled to the wire layer, it is possible to effectively reduce the parasitic capacitance between the wire layers, reduce the signal interference between adjacent wire layers, and thus improve the overall electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0020] Figure 2 is a three-dimensional schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0021] Figure 3A is based on Figure 2 A schematic top view of the structure of the semiconductor shown;

[0022] Figure 3B is a schematic top view of a semiconductor structure according to another exemplary embodiment;

[0023] Figure 3C is a schematic top view of a semiconductor structure according to another exemplary embodiment;

[0024] Figure 3D is a schematic top view of a semiconductor structure according to another exemplary embodiment;

[0025] Figure 4 is a three-dimensional schematic diagram of a semiconductor structure according to yet another exemplary embodiment;

[0026] Figure 5 is based on Figure 4 A schematic top view of the structure of the semiconductor shown;

[0027] Figure 6 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 7-15 It is a top view schematic diagram and a cross-sectional view schematic diagram of a semiconductor structure during a preparation process of a semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0031] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0032] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0034] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0035] A three-dimensional dynamic random access memory generally includes bit lines, transistors, and capacitors stacked on a substrate. Taking a semiconductor structure including horizontal bit lines and vertical word lines as an example, there is parasitic capacitance between the stacked bit lines in the vertical direction. When the number of stacked bits is large, the presence of parasitic capacitance is likely to affect the overall electrical performance of the semiconductor structure, and even cause the semiconductor structure to fail to work. Therefore, how to improve the integration of semiconductor structures and eliminate parasitic capacitance in stacked structures has always been a problem that needs to be solved in the field.

[0036] Based on this, in order to solve the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same.

[0037] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 2 is a three-dimensional schematic diagram of a semiconductor structure according to another exemplary embodiment. Figure 3A is based on Figure 2 A schematic top view of a semiconductor structure is shown. Figure 3B is a schematic top view of a semiconductor structure according to another exemplary embodiment, Figure 3C is a schematic top view of a semiconductor structure according to another exemplary embodiment, Figure 3D is a schematic top view of a semiconductor structure according to another exemplary embodiment, Figure 4 is a three-dimensional schematic diagram of a semiconductor structure according to another exemplary embodiment. Figure 5 is based on Figure 4 A schematic diagram of a semiconductor structure shown in FIG. Figures 1 to 5 The semiconductor structure will be described.

[0038] Reference Figure 1 As shown, the semiconductor structure includes a wire stacking structure CL, the wire stacking structure CL includes a plurality of wire layers 110 spaced apart along a vertical direction D3, the wire layer 110 includes a first wire portion 110a and a second wire portion 110b, and the wire layer 110 extends along a first direction D1; a storage structure MG located on one side of the wire stacking structure CL along a second direction D2, the storage structure MG being electrically connected to the first wire portion 110a; a contact plug 210 located on the other side of the wire stacking structure CL along the second direction D2, the contact plug 210 being electrically connected to the first wire portion 110a; and a shielding structure 310, the shielding structure 310 being at least sandwiched between adjacent second wire portions 110b in the vertical direction D3.

[0039] In the semiconductor structure provided by the present disclosure, on the first hand, by providing a contact plug electrically connected to the first wire portion along the second direction, it is possible to avoid the formation of an additional step structure region for connecting each layer of wire layers, thereby effectively improving the integration of the semiconductor structure. On the second hand, by providing a shielding structure coupled to the second wire portion, it is possible to effectively reduce the parasitic capacitance between the wire layers and reduce the signal interference between adjacent wire layers, thereby improving the overall electrical performance of the semiconductor structure. On the third hand, by integrating both the contact plug and the shielding structure in the area where the wire layer is located, it is possible to further improve the integration of the semiconductor structure and ensure the reliability of the semiconductor structure.

[0040] In some embodiments, the semiconductor structure is formed on a substrate 100, and the material of the substrate 100 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art.

[0041] In some embodiments, the plurality of wire layers 110 included in the wire stack structure CL can be used as bit lines in a three-dimensional dynamic random access memory. In other examples, the wire layer 110 can be a word line in a three-dimensional dynamic random access memory. The wire layer 110 extends along a first direction D1 parallel to the plane where the substrate 100 is located, and the plurality of wire layers 110 are arranged at intervals along a third direction D3 perpendicular to the plane where the substrate 100 is located. The material of the wire layer 110 can be a conductive material including a semiconductor material (e.g., doped polysilicon), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The wire layer 110 can also be a multilayer structure, for example, the wire layer 110 can be a double-layer structure composed of a metal semiconductor compound and a conductive metal nitride.

[0042] In some embodiments, the wire layer 110 includes a first wire portion 110a and a second wire portion 110b, wherein the second wire portion 110b may be located at at least one end of the first wire portion 110a along the first direction D1, for example, the second wire portion 110b may be located at both ends of the first wire portion 110a along the first direction. The projection of the first wire portion 110a along the second direction D2 coincides with the projection of the storage structure MG along the second direction, the size of the first wire portion 110a along the first direction D1 is less than or equal to the size of the storage structure MG along the first direction D1, and the projection of the second wire portion 110b along the second direction D2 does not coincide with or only partially coincides with the projection of the storage structure MG along the second direction D2.

[0043] In one example, the projection of the second wire portion 110b along the second direction D2 only overlaps with the projections of two columns of memory cells MC located at both ends of the first direction D1 in the memory structure MG along the second direction D2, but does not at least partially overlap with the projections of the memory cells MC located in the middle column in the memory structure MG along the second direction D2, wherein a column of memory cells MC refers to a plurality of memory cells MC stacked in the vertical direction D3.

[0044] In some embodiments, the first wire portion 110a can be located at both ends of the second wire portion 110b along the first direction D1, and the projection of the second wire portion 110b along the second direction D2 falls into the projection of the storage structure MG along the second direction D2, that is, the size of the second wire portion 110b along the first direction D1 is smaller than the size of the storage structure MG along the first direction D1.

[0045] In some embodiments, the storage structure MG includes a storage layer ML located at the same layer as each wire layer 110, the storage layer ML includes a plurality of storage cells MC arranged at intervals along the first direction D1, each storage cell MC includes a transistor structure 120 and a capacitor structure 130, and one end of the transistor structure 120 along the second direction D2 is electrically connected to the corresponding first wire portion 110a, and the other end is electrically connected to the capacitor structure 130.

[0046] The transistor structure 120 includes a first source and drain 122, a second source and drain 124, and a channel layer 123 located between the first source and drain 122 and the second source and drain 124. The transistor structure 120 also includes a word line structure 121. The first source and drain 122, the channel layer 123, and the second source and drain 124 may be arranged in sequence along the second direction D2, and the word line structure 121 may extend along the vertical direction D3 and be coupled to the channel layer 123. The word line structure 121 includes a word line dielectric layer and a word line conductive layer, the word line dielectric layer is located between the word line conductive layer and the channel layer 123, and the word line structure 121 may cover at least one sidewall of the channel layer 123 to form a single-gate transistor, a double-gate transistor, or a full-ring gate transistor. The conductive layer 110 is electrically connected to one of the first source and drain 122 and the second source and drain 124 as a bit line, and the capacitor structure 130 is electrically connected to the other of the first source and drain 122 and the second source and drain 124. The capacitor structure may be a columnar capacitor structure or a cylindrical capacitor structure, wherein the capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode. The materials of the lower electrode and the upper electrode include metal materials, for example, Ti, Ta, W, Cu, Al, TiN, TaN, or a combination thereof, and the capacitor dielectric layer may be a high dielectric constant material, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. In other examples, the memory cell MC may also be other types of memory cells, such as a phase change memory cell, a resistive memory cell, and the like.

[0047] In some embodiments, the contact plugs 210 and the memory structure MG are respectively located on both sides of the conductive line stack structure CL along the second direction D2. The number of the contact plugs 210 is proportional to the number of layers of the memory structure MG. For example, if a plurality of contact plugs 210 are coupled to a plurality of memory layers ML in a one-to-one correspondence, the number of the contact plugs 210 is the same as the number of layers of the memory structure MG. Figure 1In the figure, three contact plugs 210 and three memory layers ML are used as examples for illustration. The actual number of contact plugs 210 and the number of layers of the memory structure MG may be greater. A plurality of contact plugs 210 are arranged at intervals along the first direction D1, and the projection of each contact plug 210 along the second direction D2 may be staggered or only partially overlapped with the projection of each memory cell MC along the second direction D2 along the first direction D1. A plurality of contact plugs 210 are electrically connected to a plurality of first wire portions 110a in a one-to-one correspondence, that is, the first wire portion 110a of each wire layer 110 is electrically connected to a corresponding contact plug 210. The heights of the plurality of contact plugs 210 in the vertical direction D3 are all different. For example, the top surfaces of the plurality of contact plugs 210 are flush with each other, but the bottom surface of each contact plug 210 is flush with the wire layer 110 located at the same layer. The plurality of contact plugs 210 electrically connected to the conductive line stacking structure CL form a stepped structure without forming the conductive line stacking structure CL into a stepped structure, which can save the occupied area of ​​the semiconductor structure in the first direction D1 and improve the integration of the semiconductor structure.

[0048] In some embodiments, the contact plug 210 includes a vertical conductive portion 211 and a conductive connection portion 212, the conductive connection portion 212 contacts the corresponding first wire portion 110a, the size of the conductive connection portion 212 in the second direction D2 is larger than the size of the vertical conductive portion 211 in the second direction D2, and the vertical conductive portion 211 does not contact the first wire portion 110a. The size of the conductive connection portion 212 in the first direction D1 may also be larger than the size of the vertical conductive portion 211 in the first direction D1, that is, the projection of the vertical conductive portion 211 on the substrate 100 is located within the projection of the corresponding conductive connection portion 212 on the substrate 100. It can be understood that the wire layer 110 located at the same layer as the contact plug 210 refers to the wire layer 110 located at the same layer as the conductive connection portion 212 in the contact plug 210, that is, the wire layer 110 electrically connected to the contact plug 210. The material of the contact plug 210 includes a conductive material, and the material of the contact plug 210 may be the same as the material of the wire layer 110.

[0049] In some embodiments, the shielding structure 310 is located only between the second wire portions 110 b adjacent to each other in the vertical direction D3 and not between the first wire portions 110 a . The projection of the shielding structure 310 on the substrate 100 covers the projection of the second wire portions 110 b on the substrate 100 .

[0050] In some embodiments, the shielding structure 310 includes a conductive shielding layer 310a and a dielectric shielding layer 310b sandwiched between the conductive shielding layer 310a and the second wire portion 110b, and the dielectric shielding layer 310b conformally covers the surface of the second wire portion 110b. The dielectric shielding layer 310b at least covers the top and bottom surfaces of the second wire portion 110b, and the dielectric shielding layer 310b may also cover part of the side surface of the second wire portion 110b. The dielectric shielding layer 310b can prevent the conductive shielding layer 310a from short-circuiting with the second wire portion 110b.

[0051] In some embodiments, the material of the conductive shielding layer 310a includes a conductive material, and the material of the dielectric shielding layer 310b includes an insulating material, such as a low dielectric constant material such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride or silicon oxynitride. The shielding structure 310 and the second conductor portion 110b form a MIM (Metal-Insulator-Metal) shielding capacitor. Since the capacitance of the MIM shielding capacitor itself is relatively small, the parasitic capacitance between the second conductor portions 110b can be reduced.

[0052] In some embodiments, the shielding structure 310 may extend along the vertical direction D3, for example, the shielding structure 310 includes an integrally formed vertical shielding portion 311 and a horizontal shielding portion 312, wherein the vertical shielding portion 311 extends along the vertical direction D3, and the horizontal shielding portion 312 is protruded from the side wall of the vertical shielding portion 311 along the second direction D2 and is located between adjacent second wire portions 110b in the vertical direction D3. The parasitic capacitance between all wire layers 110 in the wire stacking structure CL is reduced by a shielding structure 310, thereby improving the control efficiency of the shielding structure 310.

[0053] In some embodiments, reference Figure 2 and Figure 3A and 3B As shown, the projection of the wire layer 110 on the substrate 100 is annular, and the wire layer 110 includes two first wire portions 110a arranged in parallel along the second direction D2, and two second wire portions 110b are respectively connected to the two ends of the two first wire portions 110a; the storage structure MG includes a first storage structure MG1 and a second storage structure MG2, and the first storage structure MG1 and the second storage structure MG2 are respectively located on the opposite sides of the two first wire portions 110a in the wire stacking structure CL and are mirror-symmetrical along the axis of the first direction D1. The storage structure MG and the contact plug 210 are respectively located on the outside and inside of the annular wire layer 110, and the shielding structure 310 is also located on the inside of the annular wire layer 110.

[0054] In some embodiments, the second conductor portion 110b includes a first sub-portion 110b1, a second sub-portion 110b2 and a third sub-portion 110b3 which are connected in sequence, the first sub-portion 110b1 and the third sub-portion 110b3 are respectively connected to the two first conductor portions 110a, and the first sub-portion 110b1, the second sub-portion 110b2 and the third sub-portion 110b3 surround a first groove C1; the vertical shielding portion 311 of the shielding structure 310 is located in the first groove C1 and extends along the vertical direction D3, and the horizontal shielding portion 312 is located between adjacent second conductor portions 110b in the vertical direction D3.

[0055] In some embodiments, the first wire portion 110a and the second wire portion 110b are alternately connected in sequence to form an annular structure, and the contact plug 210 is located in a strip-shaped groove enclosed by the annular structure, and is connected to the two first wire portions 110a on both sides of the same layer. The projection of the second wire portion 110b on the substrate 100 is U-shaped, so that the first wire portion 110a electrically connected to the first storage structure MG1 and the first wire portion 110a electrically connected to the second storage structure MG2 are electrically connected to each other, and the first storage structure MG1 and the second storage structure MG2 share the wire layer 110 to improve the control efficiency of the storage structure. The storage layers ML on both sides of it on the same layer can be controlled by one contact plug 210, so that the number of contact plugs 210 can be reduced. In addition, by disposing the second wire portions 110b at both ends of the first wire portion 110a, sufficient space is reserved for the contact plugs 210, and the contact plugs 210 can be evenly distributed along the first direction D1 to reduce parasitic capacitance between the contact plugs 210 and reduce parasitic capacitance between the contact plugs 210 and the second wire portions 110b.

[0056] In some embodiments, reference Figure 3A As shown, the projection of the first wire portion 110a along the second direction D2 coincides with the projection of the storage structure MG along the second direction, the size of the first wire portion 110a along the first direction D1 is greater than or equal to the size of the storage structure MG along the first direction D1, and the projection of the second wire portion 110b along the second direction D2 does not coincide with the projection of the storage structure MG along the second direction D2.

[0057] In some embodiments, reference Figure 3B As shown, the projections of the first wire portion 110a and the second wire portion 110b along the second direction D2 coincide with the projection of the storage structure MG along the second direction, wherein the size of the first wire portion 110a along the first direction D1 is smaller than the size of the storage structure MG along the first direction D1, and the projection of the second wire portion 110b along the second direction D2 only partially coincides with the projection of the storage structure MG along the second direction D2.

[0058] In some embodiments, reference Figure 3CAs shown, the first wire portion 110a and the second wire portion 110b are arranged along the first direction D1, for example, half of the wire layer 110 is used as the first wire portion 110a, and the other half is used as the second wire portion 110b. The size ratio of the first wire portion 110a and the second wire portion 110b along the first direction D1 can be 1:1 to 2:1. The projections of the first wire portion 110a and the second wire portion 110b on the substrate 100 are both U-shaped. The shielding structure 310 and the contact plug 210 are respectively arranged in two areas of the wire layer 110, which can facilitate the control of the occupied space ratio of the shielding structure 310 and the contact plug 210.

[0059] In some embodiments, reference Figure 3D As shown, the wire layer 110 includes two second wire portions 110b arranged in parallel along the second direction D2, and the two first wire portions 110a are respectively connected to the two ends of the two second wire portions 110b. The projections of the first wire portions 110a on the substrate 100 are both U-shaped, and the projections of the second wire portions 110b on the substrate 100 are strip-shaped. The shielding structure 310 is disposed in the middle of the wire layer 110, and the contact plugs 210 are disposed at both ends of the wire layer 110.

[0060] In some embodiments, the semiconductor structure further includes a spacer layer 220 surrounding the sidewalls of the vertical conductive portion 211 of the contact plug 210, the spacer layer 220 contacts the sidewalls of the conductive line stack structure CL, and the spacer layer 220 may also contact the upper surface of the conductive connection portion 212 of the contact plug 210. The spacer layer 220 contacts the conductive line layer 110 located on the upper layer of the corresponding guide layer 110 of the contact plug 210, that is, the spacer layer 220 is used to separate the contact plug 210 from the non-corresponding conductive line layer 110. The spacer layer 220 may be a low dielectric constant material.

[0061] Reference Figure 4 and Figure 5As shown, the present disclosure further provides a semiconductor structure, including: a substrate 100; a wire stacking structure CL, the wire stacking structure CL includes a plurality of wire layers 110 arranged at intervals along a vertical direction D3, the wire layer 110 extends along a first direction D1, the wire layer D1 includes a first wire layer 111 and a second wire layer 112 arranged at intervals along a second direction D2, and the projections of the first wire layer 111 and the second wire layer 112 on the substrate 100 are ring-shaped; a first storage structure MG1 and a second storage structure MG2 located on both sides of the wire stacking structure CL along the second direction D2, the first storage structure MG1 is electrically connected to the first wire layer 111, and the second storage structure MG2 is electrically connected to the second wire layer 112; a contact plug 210 located between the first wire layer 111 and the second wire layer 112, the contact plug 210 is electrically connected to both the first wire layer 111 and the second wire layer 112; a shielding structure 310, the shielding structure 310 is at least sandwiched between adjacent wire layers 110 in the vertical direction D3.

[0062] In the semiconductor structure provided by the present disclosure, on the first hand, by providing a contact plug electrically connected to the wire layer along the second direction, it is possible to avoid the formation of an additional step structure region for connecting each layer of the wire layer, thereby effectively improving the integration of the semiconductor structure. On the second hand, by providing a shielding structure coupled to the wire layer, it is possible to effectively reduce the parasitic capacitance between the wire layers and reduce the signal interference between adjacent wire layers, thereby improving the overall electrical performance of the semiconductor structure. On the third hand, by integrating both the contact plug and the shielding structure in the area where the wire layer is located, it is possible to further improve the integration of the semiconductor structure and ensure the reliability of the semiconductor structure.

[0063] In some embodiments, the first storage structure MG1 and the second storage structure MG2 are respectively connected to two separate wire layers 110, and the separate first wire layer 111 and the second wire layer 112 are coupled to each other through the contact plug 210, so that the first wire layer 111 and the second wire layer 112 of the same layer are electrically connected to each other, and the first wire layer 111 and the second wire layer 112 of different layers are electrically isolated from each other, thereby reducing the mutual interference between the two storage structures. The storage structure MG and the contact plug 210 are respectively located on both sides of the annular wire layer 110 along the second direction D2, and the shielding structure 310 is located on the inner side of the annular wire layer 110.

[0064] In some embodiments, the first memory structure MG1 and the first conductive line layer 111 , and the second memory structure MG2 and the second conductive line layer 112 , are respectively located on opposite sides of the contact plug 210 along the second direction and are mirror-symmetric along the axis of the first direction D1 .

[0065] In some embodiments, the first memory structure MG1 and the second memory structure MG2 respectively include a memory layer ML located at the same layer as each wire layer 110, the memory layer ML includes a plurality of memory cells MC arranged at intervals along the first direction D1, each memory cell MC includes a transistor structure 120 and a capacitor structure 130, one end of the transistor structure 120 along the second direction D2 is electrically connected to the corresponding first wire portion 110a, and the other end is electrically connected to the capacitor structure 130. The transistor structure 120 includes a first source and drain 122, a second source and drain 124, and a channel layer 123 located between the first source and drain 122 and the second source and drain 124, and the transistor structure 120 also includes a word line structure 121.

[0066] In some embodiments, the projection of the shielding structure 310 on the substrate 100 covers the projection of the wire layer 110 on the substrate 100. The first wire layer 111 includes a first wire portion 111a and a second wire portion 111b located at both ends of the first wire portion 111a along the first direction D1, and the second wire layer 112 includes a first wire portion 112a and a second wire portion 112b located at both ends of the first wire portion 112a along the first direction D1. The projection of the second wire portion 111b / 112b on the substrate 100 may be rectangular or U-shaped. When the projection of the second wire portion 111b / 112b on the substrate 100 is U-shaped, the second wire portion 111b of the first wire layer 111 includes a first sub-portion 111b1, a second sub-portion 111b2, and a third sub-portion 111b3 connected in sequence, and the second wire portion 112b of the second wire layer 112 includes a first sub-portion 112b1, a second sub-portion 112b2, and a third sub-portion 112b3 connected in sequence.

[0067] In some embodiments, the grooves enclosed by the second wire portions 111b / 112b and the gaps between the first wire portions 111a / 112a together form a strip groove. The shielding structure 310 is also filled in the strip groove and extends along the vertical direction D3. The plurality of first wire layers 111 are shielded by one shielding structure 310, and the plurality of second wire layers 112 are shielded by one shielding structure 310. In some examples, the shielding structure 310 corresponding to the first wire layer 111 and the shielding structure 310 corresponding to the second wire layer 112 are electrically connected to each other, so that the entire wire stacking structure CL is controlled by one shielding structure, further improving the control efficiency of the shielding structure 310.

[0068] In some embodiments, the contact plug 210 includes a vertical conductive portion 211 and a conductive connection portion 212, the conductive connection portion 212 contacts the corresponding first wire layer 111 and the second wire layer 112, the size of the conductive connection portion 212 in the second direction D2 is larger than the size of the vertical conductive portion 211 in the second direction D2, and the vertical conductive portion 211 does not contact the first wire layer 111 and the second wire layer 112. The semiconductor structure further includes a spacer layer 220 surrounding the sidewall of the vertical conductive portion 211 of the contact plug 210, and the spacer layer 220 contacts the sidewall of the wire stack structure CL. The spacer layer 220 is used to separate the contact plug 210 from the non-corresponding wire layer 110.

[0069] Figure 6 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure; Figures 7 to 15 This is a schematic diagram of a semiconductor structure preparation process according to an embodiment of the present disclosure. Figures 6 to 15 The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is described in detail, wherein: Figures 7 to 15 The middle left picture is a top view of the semiconductor structure during its preparation process. Figures 7 to 15 The middle right picture is a cross-sectional schematic diagram of the semiconductor structure during preparation. Figures 7 to 13 The right picture in the figure is a cross-sectional view along the AA' section in the left picture. Figure 14 to Figure 15 The right picture in the figure is a cross-sectional view along the BB' section in the left picture. Figure 6 As shown, the preparation method comprises at least the following steps:

[0070] S610: forming a wire stacking structure, the wire stacking structure comprising a plurality of wire layers spaced apart in a vertical direction, the wire layer comprising a first wire portion and a second wire portion, and the wire layer extending in a first direction;

[0071] S620: forming a storage structure located on one side of the conductive line stacking structure along the second direction, wherein the storage structure is electrically connected to the conductive line layer;

[0072] S630: forming a contact plug located at the other side of the conductive line stack structure along the second direction, wherein the contact plug is electrically connected to the first conductive line portion;

[0073] S640: forming a shielding structure, wherein the shielding structure is at least sandwiched between adjacent second wire portions in the vertical direction.

[0074] It should be understood that Figure 6 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 6The steps shown in the figure can be adjusted in order according to actual needs. For example, the storage structure can be formed first and then the wire stacking structure can be formed, or the wire stacking structure can be formed first and then the storage structure can be formed. For another example, the contact plug can be formed first and then the shielding structure can be formed, or the shielding structure can be formed first and then the contact plug can be formed.

[0075] It is understandable that Figures 7 to 15 The second wire portion 110b is located at both ends of the first wire portion 110a for example. Figure 3A The projection of the second wire portion 110b along the second direction D2 does not overlap with the projection of the memory structure MG along the second direction D2. Figure 3B The projection of the second wire portion 110b along the second direction D2 partially overlaps with the projection of the memory structure MG along the second direction D2. Figure 3C The second conductor portion 110b and the first conductor portion 110a are two halves of the conductor layer 110, or Figure 3D The first wire portion 110a is shown located at two ends of the second wire portion 110b.

[0076] Reference Figure 7 As shown, the semiconductor structure also includes a substrate 100, and a storage structure MG is formed on the substrate 100. The storage structure MG includes a storage layer ML stacked in the vertical direction D3, and the storage layer ML includes a plurality of storage cells MC arranged at intervals along the first direction D1. Each storage cell MC includes a transistor structure 120 and a capacitor structure 130. The transistor structure 120 includes a first source and drain 122, a second source and drain 124, and a channel layer 123 located between the first source and drain 122 and the second source and drain 124. The transistor structure 120 also includes a word line structure 121. One end of the transistor structure 120 along the second direction D2 is electrically connected to the corresponding first semiconductor layer 101, and the other end is electrically connected to the capacitor structure 130. The two storage structures MG can also be arranged along the second direction D2 and are mirror-symmetrical along the axis of the first direction D1. The two storage structures MG are connected through a stacked structure composed of a first semiconductor layer 101 and a first dielectric layer 102. The first semiconductor layer 101 and the storage layer ML are located in the same layer. The material of the first semiconductor layer 101 may be single crystal silicon, and the material of the first dielectric layer 102 may be an insulating material. After forming a stacked layer formed by alternating single crystal silicon layers and silicon germanium layers by an epitaxial process, the silicon germanium layers are removed and filled with the first dielectric layer 102 .

[0077] Reference Figure 8As shown, the stacked structure composed of the first semiconductor layer 101 and the first dielectric layer 102 is etched to form a strip groove T1. The size of the strip groove T1 along the first direction D1 and the second direction D2 are both smaller than the size of the stacked structure along the first direction D1 and the second direction D2, and the projection of the remaining stacked structure on the substrate 100 is annular. The size of the strip groove T1 along the first direction D1 is larger than the size of the storage structure MG along the first direction D1, and the projection of the strip groove T1 along the second direction D2 covers the projection of the storage structure MG along the second direction D2. In other examples, the projection of the remaining stacked structure on the substrate 100 may be U-shaped.

[0078] Reference Fig. 9 As shown, the first semiconductor layer 101 exposed by the strip groove T1 is removed and replaced by a wire layer 110. The multiple wire layers 110 are stacked in a vertical direction D3 to form a wire stacking structure. The wire layer 110 includes a first wire portion 110a and a second wire portion 110b. The first semiconductor layer 101 can be removed by a wet etching process to form a gap between the remaining first dielectric layer 102, and the gap and the strip groove T1 are filled with a wire material layer. The wire material layer located in the strip groove T1 is removed, and the wire material layer located in the gap is retained as the wire layer 110. The wire layer 110 can be a double-layer structure, including a metal semiconductor compound covering the surface of the first source and drain 122 and a conductive metal nitride covering the surface of the metal semiconductor compound and filling the gap. The metal semiconductor compound can be a metal silicide such as cobalt silicide to reduce the contact resistance between the first source and drain 122 and the wire layer 110.

[0079] In some embodiments, forming a contact plug located at the other side of the conductive line stack structure along the second direction includes: referring to Fig.10 As shown, a filling dielectric layer 103 is formed in the strip groove T1 enclosed by the conductor layer 110, and the filling dielectric layer 103 penetrates the conductor stacking structure along the vertical direction D3; Fig.11 As shown, a plurality of vertical plug holes T2 arranged at intervals along the first direction D1 are formed in the filling dielectric layer 103, and the depth of each vertical plug hole T2 is different; refer to Fig.12 As shown, a spacer layer 220 is formed on the side wall of the vertical plug hole T2; a connecting hole T3 connected to the bottom of the vertical plug hole T2 is formed, and the connecting hole T3 exposes a portion of the side wall of the corresponding first wire portion 110a; Fig.13 As shown, contact plugs 210 are filled in the vertical plug holes T2 and the through holes T3 .

[0080] In some embodiments, Fig.11Taking the three vertical plug holes T2 arranged at intervals along the first direction D1 as an example, the three vertical plug holes T2 are used to form three contact plugs corresponding to the three storage layers ML respectively, and the bottom surfaces of the vertical plug holes T2 are flush with the top surfaces of the wire layers 110 corresponding to each storage layer ML. The depths of the three vertical plug holes T2 arranged in the first direction D1 can be deepened sequentially or can be discontinuously changed. The projection of the vertical plug hole T2 in the second direction D2 can be staggered or only partially overlapped with the projection of each storage cell MC in the second direction D2 along the first direction D1.

[0081] In some embodiments, a spacer material layer that conformally covers the inner wall of the vertical plug hole T2 can be formed by an atomic layer deposition process to improve the step coverage of the vertical plug hole T2 with a high aspect ratio. After forming the spacer material layer that conformally covers the inner wall of the vertical plug hole T2, the spacer material layer at the bottom of the vertical plug hole T2 is removed to retain the spacer material layer at the side wall of the vertical plug hole T2 as a spacer layer 220. The spacer layer 220 can be an insulating material and can be a double-layer structure composed of a silicon oxide layer and a silicon nitride layer. The bottom of the vertical plug hole T2 exposes the top surface of the remaining filling dielectric layer 103, and wet etching is performed along the vertical plug hole T2 to deepen the vertical plug hole T2 to form a connecting hole T3 that exposes part of the side wall of the corresponding first wire portion 110a. The material of the filling dielectric layer 103 is a low dielectric constant material.

[0082] In some embodiments, for a semiconductor structure including N storage layers ML, N-1 vertical plug holes T2 are first formed, and then N connecting holes T3 are formed, wherein the N-1 connecting holes T3 are connected to the N-1 vertical plug holes T2 in a one-to-one correspondence to jointly form a contact plug, and another connecting hole T3 is used alone to form a contact plug.

[0083] In some embodiments, a first dielectric layer 102 is sandwiched between adjacent wire layers 110 in the vertical direction D3, and the wire layer 110 includes two first wire portions 110a arranged in parallel along the second direction D2, and two second wire portions 110b are respectively connected to the two ends of the two first wire portions 110a; forming a shielding structure 310, including: Fig.14 As shown, a first groove C1 exposing the second wire portion 110b is formed in the filling dielectric layer 103; the first dielectric layer 102 between the adjacent second wire portions 110b in the vertical direction D3 is removed along the first groove C1 to form a wire gap; Fig.15 As shown, a shielding structure 310 is formed in the wire gap and the first groove C1. The shielding structure 310 includes a conductive shielding layer 310a and a dielectric shielding layer 310b sandwiched between the conductive shielding layer 310a and the second wire portion 110b. The dielectric shielding layer 310b conformally covers the surface of the second wire portion 110b.

[0084] After removing the first dielectric layer 102, a conductor gap projected as a ring is formed, and each conductor layer 110 exposes its top surface, bottom surface and inner wall. First, a dielectric shielding layer 310b is deposited to conformally cover the exposed surface of the second conductor portion 110b, and the thickness of the dielectric shielding layer 310b is less than half of the spacing between the conductor layers 110, and then the conductive shielding layer 310a is filled in the remaining conductor gap and the space of the first groove C1. The end surface of the dielectric shielding layer 310b along the second direction D2 is flush with the end surface of the conductor layer 110 along the second direction D2.

[0085] In some embodiments, the projection of each contact plug 210 along the second direction D2 may be staggered with the projection of each memory cell MC along the second direction D2 along the first direction D1. After removing the first dielectric layer 102 between the adjacent second wire portions 110b in the vertical direction D3, the dielectric layer between the memory cells MC exposed in the wire gap is further etched to widen the wire gap.

[0086] It should be noted that the first direction D1 and the second direction D2 used in the present disclosure are horizontal directions parallel to the plane where the substrate 100 is located, and the first direction D1 intersects with the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2, and the vertical direction D3 is a direction intersecting with the plane where the substrate 100 is located, for example, the vertical direction D3 is perpendicular to the plane where the substrate 101 is located. That is, the first direction D1, the second direction D2 and the vertical direction D3 are perpendicular to each other.

[0087] In some embodiments, the semiconductor structure includes: a memory, which may be a dynamic random access memory, or a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0088] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM).

[0089] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A wire stacking structure, the wire stacking structure comprising a plurality of wire layers spaced apart in a vertical direction, the wire layer comprising a first wire portion and a second wire portion, and the wire layer extending in a first direction; A storage structure located on one side of the wire stacking structure along the second direction, the storage structure being electrically connected to the wire layer; a contact plug located at the other side of the conductive line stack structure along the second direction, the contact plug being electrically connected to the first conductive line portion; A shielding structure is at least sandwiched between the second wire portions adjacent to each other in the vertical direction.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure also includes a substrate; The projection of the wire layer on the substrate is annular, the wire layer comprises two first wire portions arranged in parallel along a second direction, and the two second wire portions respectively connect two ends of the two first wire portions; The storage structure includes a first storage structure and a second storage structure, wherein the first storage structure and the second storage structure are respectively located at two opposite sides of the conductive line stacking structure.

3. The semiconductor structure according to claim 2, characterized in that: The second wire portion includes a first sub-portion, a second sub-portion and a third sub-portion connected in sequence, the first sub-portion and the third sub-portion are respectively connected to two first wire portions, and the first sub-portion, the second sub-portion and the third sub-portion surround a first groove; The shielding structure includes a vertical shielding portion and a horizontal shielding portion. The vertical shielding portion is located in the first groove and extends along the vertical direction. The horizontal shielding portion is located between the second conductive line portions adjacent to each other in the vertical direction.

4. The semiconductor structure according to claim 1, characterized in that The shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second wire portion, and the dielectric shielding layer conformally covers a surface of the second wire portion.

5. The semiconductor structure according to claim 1, characterized in that: The plurality of contact plugs are arranged at intervals along the first direction, and the plurality of contact plugs are electrically connected to the plurality of first wire portions one by one; the contact plugs include a vertical conductive portion and a conductive connecting portion, the conductive connecting portion is in contact with the corresponding first wire portion, and the size of the conductive connecting portion in the second direction is greater than the size of the vertical conductive portion in the second direction; The semiconductor structure further comprises: A spacer layer surrounds the sidewall of the vertical conductive portion, and the spacer layer is in contact with the conductive line stack structure.

6. The semiconductor structure according to claim 1, characterized in that The storage structure includes a storage layer located at the same layer as each of the conductive line layers, the storage layer includes a plurality of storage cells arranged at intervals along a first direction, each of the storage cells includes a transistor structure and a capacitor structure, one end of the transistor structure along the second direction is electrically connected to the corresponding first conductive line portion, and the other end is electrically connected to the capacitor structure.

7. A semiconductor structure, characterized in that: include: substrate; A wire stacking structure, the wire stacking structure comprising a plurality of wire layers spaced apart in a vertical direction, the wire layers extending along a first direction, the wire layers comprising a first wire layer and a second wire layer spaced apart in a second direction, the projections of the first wire layer and the second wire layer on the substrate being annular; A first storage structure and a second storage structure located at two sides of the wire stacking structure along the second direction, the first storage structure is electrically connected to the first wire layer, and the second storage structure is electrically connected to the second wire layer; A contact plug located between the first conductive line layer and the second conductive line layer, the contact plug being electrically connected to both the first conductive line layer and the second conductive line layer; A shielding structure is at least sandwiched between the adjacent conductive line layers in the vertical direction.

8. The semiconductor structure according to claim 7, characterized in that: The first conductor layer and the second conductor layer each include a first conductor portion and second conductor portions located at two ends of the first conductor portion, and the first conductor portion and the second conductor portion surround a strip groove; The shielding structure includes a vertical shielding portion and a horizontal shielding portion. The vertical shielding portion is located in the strip-shaped slot and extends along the vertical direction. The horizontal shielding portion is located between adjacent second conductor portions in the vertical direction.

9. The semiconductor structure according to claim 7, characterized in that: The plurality of contact plugs are arranged at intervals along the first direction, and the plurality of contact plugs are electrically connected to the first wire layer and the second wire layer located at the corresponding layer, respectively; the contact plug comprises a vertical conductive portion and a conductive connecting portion, the conductive connecting portion is in contact with both the first wire layer and the second wire layer located at the corresponding layer, and the size of the conductive connecting portion in the second direction is larger than the size of the vertical conductive portion in the second direction; The semiconductor structure further comprises: A spacer layer surrounds the sidewall of the vertical conductive portion, and the spacer layer is in contact with the conductive line stack structure.

10. A method for preparing a semiconductor structure, characterized in that: include: forming a wire stacking structure, the wire stacking structure comprising a plurality of wire layers spaced apart in a vertical direction, the wire layer comprising a first wire portion and a second wire portion, and the wire layer extending in a first direction; forming a storage structure located on one side of the wire stacking structure along the second direction, wherein the storage structure is electrically connected to the wire layer; forming a contact plug located at the other side of the conductive line stack structure along the second direction, wherein the contact plug is electrically connected to the first conductive line portion; A shielding structure is formed, wherein the shielding structure is at least sandwiched between the second wire portions adjacent to each other in the vertical direction.

11. The preparation method according to claim 10, characterized in that: The semiconductor structure further includes a substrate; the projection of the wire layer on the substrate is a ring; forming a contact plug located on the other side of the wire stacking structure along the second direction, comprising: Forming a filling dielectric layer in the strip-shaped groove enclosed by the conductor layer, wherein the filling dielectric layer penetrates the conductor stacking structure along the vertical direction; forming a plurality of vertical plug holes arranged at intervals along the first direction in the filling dielectric layer, and each of the vertical plug holes has a different depth; forming a spacer layer on the side wall of the vertical plug hole; forming a communication hole connected to the bottom of the vertical plug hole, wherein the communication hole exposes a portion of the side wall of the corresponding first wire portion; Contact plugs are filled in the vertical plug holes and in the communication holes.

12. The preparation method according to claim 11, characterized in that: A first dielectric layer is sandwiched between the adjacent wire layers in the vertical direction, the wire layer comprises two first wire portions arranged in parallel along a second direction, and two second wire portions are respectively connected to two ends of the two first wire portions; A shielding structure is formed, comprising: forming a first groove in the filling dielectric layer to expose the second conductive line portion; removing the first dielectric layer between the second wire portions adjacent to each other in the vertical direction along the first groove to form a wire gap; The shielding structure is formed in the wire gap and the first groove, and the shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second wire portion, and the dielectric shielding layer conformally covers the surface of the second wire portion.

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