A memory chip structure and a method of fabrication

Abstract

The application discloses a kind of storage chip structure and preparation method, the structure includes the bottom metal is provided with dielectric layer, bottom via is opened in the dielectric layer, and the bottom via is filled with conductive material and forms bottom via structure;The storage bit is set on the bottom via structure, and the top metal is set on the storage bit;When preparing the storage bit, etching the dielectric layer first, and there is height difference between the dielectric layer after etching and bottom via structure;Depositing film on the dielectric layer and bottom via structure, then depositing dielectric material on the film on the top of dielectric layer and planarizing, so that the upper surface of dielectric material on the film on the top of dielectric layer is flush with the upper surface of the film on the top of bottom via structure;Photoetching film in the upper part of bottom via structure region is etched away, and storage bit is formed.The application obtains storage bit, reduces the exposed area of storage bit, and reduces the performance problem of storage bit caused by film back splash.

Description

Technical Field

[0001] This invention belongs to the field of memory chips, specifically relating to a memory chip structure and its fabrication method. Background Technology

[0002] The development of the Internet of Things (IoT) has placed higher demands on data storage. New types of memory, such as Magnetic Random Access Memory (MRAM), possess advantages such as non-volatility, high-speed read / write, and high reliability, making them highly promising new types of storage. The core of an MRAM chip is the Magnetic Tunnel Junction (MTJ), which, driven by current, can switch between high and low resistance to achieve the purpose of storing "0" and "1". In the manufacturing of new memory chips, the memory cells are integrated into the CMOS back-end process. The memory cells are electrically interconnected through bottom and top interconnects. In addition to the memory array, the memory chip also contains logic control circuitry; this area only has the back-end interconnect structure.

[0003] In traditional novel memory manufacturing processes, the thin film material required for memory cells is deposited on a flat substrate surface. During the patterning process of memory cells, especially the etching process, sputtering occurs between the memory cells during ion bombardment. Sputtered residues may adhere to the sidewalls of the memory cells, causing damage or short circuits. This problem is even more pronounced in high-density memory arrays. Summary of the Invention

[0004] To address the problems of existing technologies, this invention provides a memory chip structure and its fabrication method. By employing a novel bit fabrication process, the risk of memory bit failure caused by current process bottlenecks during chip fabrication is significantly reduced, thereby improving chip yield and reliability.

[0005] The technical solution adopted in this invention is as follows:

[0006] In a first aspect, the present invention discloses a memory chip structure, including a bottom metal, memory bits and a top metal;

[0007] A dielectric layer is provided on the bottom metal, and a bottom through hole is formed on the dielectric layer. The bottom through hole is filled with conductive material to form a bottom through hole structure.

[0008] The storage bit is disposed on the bottom through-hole structure, and the top metal is disposed above the storage bit;

[0009] In preparing the memory bit, the dielectric layer is first etched, resulting in a height difference between the etched dielectric layer and the bottom via structure. A thin film is deposited on the dielectric layer and the bottom via structure, and then a dielectric material is deposited and planarized on the thin film on top of the dielectric layer, so that the upper surface of the dielectric material on the thin film on top of the dielectric layer is flush with the upper surface of the thin film on top of the bottom via structure. The thin film in a portion of the area above the bottom via structure is etched away by photolithography to form the memory bit.

[0010] Furthermore, the memory chip structure also includes a bottom electrode, which is fabricated on the upper surface of the bottom via structure and is located below and in contact with the memory bit.

[0011] Secondly, this invention discloses a method for fabricating the aforementioned memory chip structure, comprising the following steps:

[0012] 1) Prepare a bottom metal layer composed of a bottom metal;

[0013] 2) A first dielectric material and a second dielectric material are deposited sequentially from bottom to top on the bottom metal layer, thus forming a first dielectric layer and a second dielectric layer in sequence. Holes are drilled in the first dielectric layer and the second dielectric layer above the bottom metal to form bottom vias. The bottom vias are filled with conductive material to form a bottom via structure. Using the bottom via structure as a mask, the second dielectric layer is etched using a self-aligned etching method to form a groove. There is a height difference between the bottom via structure and the etched second dielectric layer.

[0014] 3) Deposit a thin film on the groove and the bottom through-hole structure, the upper surface of the thin film on the second dielectric layer is lower than the upper surface of the bottom through-hole structure; then deposit a third dielectric material on the thin film on top of the second dielectric layer and planarize it so that the upper surface of the third dielectric material is flush with the upper surface of the thin film on top of the bottom through-hole structure.

[0015] 4) Photolithography is used to etch the thin film of the third dielectric material and the upper part of the bottom via structure. When the etching stops, the upper surface of the third dielectric material is not higher than the upper surface of the bottom via structure. When photolithography is used to etch the thin film of the partial area, the etching stops at the upper surface of the bottom via structure to form a storage bit.

[0016] 5) Deposit and planarize the fourth dielectric material, and then photolithographically etch all the fourth dielectric material, all the third dielectric material, and all the thin film on the second dielectric layer to expose the second dielectric layer;

[0017] 6) Deposit and planarize the fifth dielectric material. Use the damascus process to prepare the top metal on the fifth dielectric material above the memory bit, and finally form the memory chip structure.

[0018] The present invention also discloses a method for fabricating the memory chip structure, comprising the following steps:

[0019] 1) Prepare a bottom metal layer including a bottom metal;

[0020] 2) A first dielectric material and a second dielectric material are deposited sequentially from bottom to top on the bottom metal layer, thus forming a first dielectric layer and a second dielectric layer in sequence. A hole is drilled in the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom through-hole, and the bottom through-hole is filled with a conductive material to form a bottom through-hole structure. A bottom electrode is fabricated on the bottom through-hole structure, and the size of the bottom electrode is larger than the size of the bottom through-hole structure. The second dielectric layer is etched using a self-aligned etching method and the etching stops at the second dielectric layer.

[0021] 3) Deposit a thin film on the bottom electrode and the second dielectric layer, with the upper surface of the thin film on the second dielectric layer being lower than the lower surface of the bottom electrode; then deposit a third dielectric material on the thin film on top of the second dielectric layer and planarize it so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode.

[0022] 4) Photolithographically etch the thin film of the third dielectric material and the upper part of the bottom electrode. When the etching stops, the upper surface of the third dielectric material is not higher than the upper surface of the bottom electrode. When photolithographically etching the thin film of the upper part of the bottom electrode, the etching stops at the upper surface of the bottom electrode to form a storage bit.

[0023] 5) Deposit and planarize the fourth dielectric material, and then photolithographically etch the fourth dielectric material, the third dielectric material, and the thin film on the second dielectric layer to expose part or all of the current second dielectric layer;

[0024] 6) Deposit and planarize the fifth dielectric material. Use the damascus process to form the top metal on the fifth dielectric material above the memory bit, and finally form the memory chip structure.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] This invention employs a novel architecture and manufacturing technology, creating a step difference after the deposition of the memory bit thin film. This overcomes the device failure problem caused by backsplattering of the metal thin film during the etching process in existing memory chip manufacturing technologies, thereby improving chip yield and reliability. Simultaneously, the step difference formed after the deposition of the memory bit thin film facilitates photolithography alignment identification, reduces indirect alignment marks, and decreases process steps. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating the fabrication process of a memory chip structure according to a specific embodiment 1 of the present invention;

[0028] Figure 2 This is a flowchart illustrating the fabrication process of a memory chip structure according to a specific embodiment 2 of the present invention;

[0029] Figure 3 This is a flowchart illustrating the fabrication process of a memory chip structure according to a specific embodiment 3 of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of the present invention.

[0031] The component labels in the diagram are as follows: 100 - substrate; 201 - bottom metal layer; 202 - bottom via structure; 203 - bottom electrode; 204 - memory bit; 205 - top metal; 101 - sixth dielectric material; 102 - first dielectric material; 103 - second dielectric material; 104 - fourth dielectric material; 105 - fifth dielectric material. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0033] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0034] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0035] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection, an electrical connection, a physical connection, or a wireless communication connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two elements or the interaction between two elements, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings.

[0038] like Figure 4 As shown, this embodiment provides a memory chip structure, including: a substrate 100; a bottom metal 201 disposed on the substrate; a plurality of bottom via structures 202 fabricated on the bottom metal; bottom electrodes 203 fabricated on the bottom via structures; memory bits 204 fabricated on the bottom electrodes; a top metal 205 fabricated above the memory bits 204; and a top metal 205 fabricated above the bottom metal 201 in the logic region of the memory chip structure. The material of the memory bits includes MRAM, PCRAM, or RRAM; the bottom metal is a metal material such as copper or aluminum; the top metal is a metal material such as copper or aluminum; the substrate includes a CMOS layer and multiple metal layers arranged from bottom to top. Figure 4 The display provides a substrate, which also includes an array region and a logic region; the CMOS layer is a general structure in the art and has no special design; the metal layer is made of metal materials such as copper and aluminum.

[0039] like Figure 1 As shown, the method for fabricating the memory chip structure in this embodiment includes the following steps:

[0040] a) such as Figure 1 In steps (a)-(d), a bottom metal layer including a bottom metal is prepared, with a sixth dielectric material 101 filling the spaces between two adjacent bottom metal layers; a first dielectric material 102 and a second dielectric material 103 are deposited sequentially from bottom to top above the bottom metal layer, thus forming a first dielectric layer and a second dielectric layer in sequence; holes are drilled at the first and second dielectric layers above the bottom metal to form bottom vias, and the bottom vias are filled with conductive material to form a bottom via structure; a bottom electrode is prepared above the bottom via structure, the size of which is larger than the size of the bottom via structure; the second dielectric layer is etched using a self-aligned etching method and the etching stops at the second dielectric layer; wherein, the first dielectric material 102 and the second dielectric material 103 are different dielectric materials, and the dielectric material can be insulating dielectric materials such as silicon oxide, silicon nitride, or low-k; the self-aligned etching method is dry etching or wet etching; the conductive material includes, but is not limited to, copper, aluminum, titanium nitride, titanium, tantalum nitride, tantalum, tungsten, etc.

[0041] b) such as Figure 1 In steps (e)-(f), a thin film is deposited on the bottom electrode and the second dielectric layer, with the upper surface of the thin film on the second dielectric layer being lower than the lower surface of the bottom electrode; then, a third dielectric material is deposited on the thin film on top of the second dielectric layer and planarized, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode; the material of the thin film includes MRAM, PCRAM, or RRAM; the third dielectric material is an insulating dielectric material such as silicon oxide, silicon nitride, or low-k; the material of the bottom electrode includes, but is not limited to, copper, aluminum, titanium nitride, titanium, tantalum nitride, tantalum, tungsten, etc.

[0042] c) such as Figure 1 In step (g), the third dielectric material and the thin film on the upper part of the bottom electrode are photolithographically etched. When the etching stops, the upper surface of the third dielectric material is flush with the upper surface of the bottom electrode. When the thin film in the upper part of the area is photolithographically etched, the etching stops at the upper surface of the bottom electrode and exposes the bottom electrode, forming storage bit 204.

[0043] d) such as Figure 1 In (h)-(i), the fourth dielectric material 104 is deposited and planarized, and all the fourth dielectric material 104, all the third dielectric material and all the thin film on the second dielectric layer are photolithographically etched to expose the entire current second dielectric layer; the fourth dielectric material 104 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k.

[0044] e) such as Figure 1 In step (j), a fifth dielectric material 105 is deposited and planarized. A top metal 205 is formed on the fifth dielectric material 105 above the storage bit 204 using a damascus process. A top metal 205 is also formed on the bottom metal 201 of the array logic region using a damascus process. This forms the memory chip structure, ultimately producing the desired result. Figure 4 The memory chip structure shown is illustrated. The fifth dielectric material 105 is an insulating dielectric material such as silicon oxide, silicon nitride, or low-k.

[0045] like Figure 2 As shown, the method for fabricating the memory chip structure in this embodiment includes the following steps:

[0046] a) such as Figure 2In steps (a)-(d), a bottom metal layer including a bottom metal is prepared, with a sixth dielectric material 101 filling the spaces between two adjacent bottom metal layers; a first dielectric material 102 and a second dielectric material 103 are deposited sequentially from bottom to top above the bottom metal layer, thus forming a first dielectric layer and a second dielectric layer in sequence; holes are drilled in the first and second dielectric layers above the bottom metal to form bottom vias, and the bottom vias are filled with conductive material to form a bottom via structure; a bottom electrode is prepared above the bottom via structure, the size of which is larger than the size of the bottom via structure; the second dielectric layer is etched using a self-aligned etching method and the etching stops at the second dielectric layer; wherein, the first dielectric material 102 and the second dielectric material 103 are different dielectric materials, and the dielectric material can be an insulating dielectric material such as silicon oxide, silicon nitride, or low-k; the self-aligned etching method is a dry etching method or a wet etching method.

[0047] b) such as Figure 2 In steps (e)-(f), a thin film is deposited on the bottom electrode and the second dielectric layer, with the upper surface of the thin film on the third dielectric layer being lower than the lower surface of the bottom electrode; then, a third dielectric material is deposited on the thin film on top of the second dielectric layer and planarized, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode; the material of the thin film includes MRAM, PCRAM, or RRAM; the third dielectric material is an insulating dielectric material such as silicon oxide, silicon nitride, or low-k; the material of the bottom electrode includes, but is not limited to, copper, aluminum, titanium nitride, titanium, tantalum nitride, tantalum, tungsten, etc.

[0048] c) such as Figure 2 In step (g), the thin film on a portion of the third dielectric material and the bottom electrode is photolithographically etched. When the etching stops, the upper surface of the third dielectric material is flush with the upper surface of the bottom electrode. When the thin film on the portion of the material is photolithographically etched, the etching stops at the upper surface of the bottom electrode and exposes the bottom electrode, forming storage bit 204.

[0049] d) such as Figure 2 In (h)-(i), a fourth dielectric material 104 is deposited and planarized, and the fourth dielectric material 104, the third dielectric material and the thin film on the second dielectric layer are photolithographically etched to expose a portion of the current second dielectric layer; the fourth dielectric material 104 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k.

[0050] e) such as Figure 2In step (j), a fifth dielectric material 105 is deposited and planarized. A top metal 205 is formed on the fifth dielectric material 105 above the storage bit 204 using a damascus process. A top metal 205 is also formed on the bottom metal 201 of the array logic region using a damascus process. Finally, a memory chip structure is formed. The fifth dielectric material 105 is an insulating dielectric material such as silicon oxide, silicon nitride, or low-k.

[0051] This embodiment also provides a memory chip structure, including: a substrate 100; a bottom metal 201 disposed on the substrate; a plurality of bottom via structures 202 fabricated on the bottom metal; memory bits 204 fabricated on the bottom via structures 202; and a top metal 205 fabricated above the memory bits 204.

[0052] like Figure 3 As shown, the method for fabricating the memory chip structure in this embodiment includes the following steps:

[0053] a) such as Figure 3 In steps (a)-(b), a bottom metal layer is prepared, including a bottom metal layer, with a sixth dielectric material 101 filling the spaces between two adjacent bottom metal layers. A first dielectric material 102 and a second dielectric material 103 are deposited sequentially from bottom to top above the bottom metal layer, thus forming a first dielectric layer and a second dielectric layer. Holes are drilled in the first and second dielectric layers above the bottom metal layer to form bottom vias, and these vias are filled with conductive material to form a bottom via structure. Using the bottom via structure as a mask, the second dielectric layer is etched using a self-aligned etching method to form a groove. There is a height difference between the bottom via structure and the etched second dielectric layer, with the upper surface of the bottom via structure being higher than the upper surface of the etched second dielectric layer. The first dielectric material 102 and the second dielectric material 103 are different dielectric materials, which can be insulating dielectric materials such as silicon oxide, silicon nitride, or low-k dielectric materials. The self-aligned etching method can be dry or wet etching.

[0054] b) such as Figure 3 In steps (c)-(d), a thin film is deposited on the groove and the bottom via structure, with the upper surface of the thin film on the second dielectric layer being lower than the upper surface of the bottom via structure; then, a third dielectric material is deposited on the thin film on top of the second dielectric layer and planarized, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom via structure; wherein, the material of the thin film includes MRAM, PCRAM or RRAM; the third dielectric material is an insulating dielectric material such as silicon oxide, silicon nitride or low-k;

[0055] c) such as Figure 3In steps (d)-(e), the third dielectric material and the thin film on the upper part of the bottom via structure are photolithographically etched. When the etching stops, the upper surface of the third dielectric material is flush with the upper surface of the bottom via. When the thin film in the partial area is photolithographically etched, the etching stops at the upper surface of the bottom via structure to form the storage bit 204.

[0056] d) such as Figure 3 In steps (f)-(g), a fourth dielectric material 104 is deposited and planarized, and all the fourth dielectric material 104, all the third dielectric material and all the thin film on the second dielectric layer are photolithographically etched to expose the entire current second dielectric layer; the fourth dielectric material 104 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k.

[0057] e) such as Figure 3 In steps (h)-(i), a fifth dielectric material 105 is deposited and planarized. A top metal 205 is formed on the fifth dielectric material 105 above the storage bit 204 using a damascus process. A top metal 205 is also formed on the bottom metal 201 of the array logic region using a damascus process, ultimately forming a memory chip structure. The fifth dielectric material 105 is an insulating dielectric material such as silicon oxide, silicon nitride, or low-k.

[0058] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. Those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A memory chip structure, comprising: The bottom metal, the storage bit and the top metal are included. The bottom metal is provided with a dielectric layer, and a bottom via hole is formed in the dielectric layer and filled with conductive material to form a bottom via hole structure. The storage bit is arranged on the bottom via hole structure, and the top metal is arranged above the storage bit. In the preparation of the storage bit, the dielectric layer is etched first, and the etched dielectric layer has a height difference with the bottom via hole structure. A thin film is deposited on the dielectric layer and the bottom via hole structure, and a dielectric material is deposited on the thin film on the top of the dielectric layer and is planarized, so that the upper surface of the dielectric material on the thin film on the top of the dielectric layer is flush with the upper surface of the thin film on the top of the bottom via hole structure. The thin film in the partial region on the top of the bottom via hole structure is etched by photolithography to form the storage bit.

2. The memory chip structure of claim 1, wherein, The storage chip structure further includes a bottom electrode prepared on the upper surface of the bottom via hole structure and located below and in contact with the storage bit.

3. The memory chip structure of claim 1 or 2, wherein, The storage chip structure further includes a substrate located below and in contact with the bottom metal, and the substrate includes a CMOS layer and a multi-layer metal layer arranged from bottom to top.

4. A method of fabricating the memory chip structure of claim 1, wherein, The steps include: 1) preparing a bottom metal layer composed of a bottom metal; 2) sequentially depositing a first dielectric material and a second dielectric material on the bottom metal layer from bottom to top to form a first dielectric layer and a second dielectric layer, punching a bottom via hole in the first dielectric layer and the second dielectric layer above the bottom metal, filling the bottom via hole with conductive material to form a bottom via hole structure, etching the second dielectric layer using a self-aligned etching method with the bottom via hole structure as a mask to form a groove, and the bottom via hole structure having a height difference with the etched second dielectric layer; 3) depositing a thin film on the groove and the bottom via hole structure, and the upper surface of the thin film on the second dielectric layer being lower than the upper surface of the bottom via hole structure; depositing a third dielectric material on the thin film on the top of the second dielectric layer and planarizing, so that the upper surface of the third dielectric material is flush with the upper surface of the thin film on the top of the bottom via hole structure; 4) photolithography etching the third dielectric material and the thin film in the partial region on the top of the bottom via hole structure, and the upper surface of the third dielectric material being not higher than the upper surface of the bottom via hole structure when etching stops; when the thin film in the partial region is etched by photolithography, etching stops at the upper surface of the bottom via hole structure to form the storage bit; 5) depositing a fourth dielectric material and planarizing, and etching all the fourth dielectric material, all the third dielectric material and all the thin film on the second dielectric layer by photolithography to expose the second dielectric layer; 6) depositing a fifth dielectric material and planarizing, and preparing a top metal on the fifth dielectric material above the storage bit by damascene process to finally form the storage chip structure.

5. A method of fabricating the memory chip structure of claim 2, wherein, The steps include: 1) preparing a bottom metal layer including a bottom metal; 2) depositing first dielectric material and second dielectric material on the bottom metal layer from bottom to top, thus forming first dielectric layer and second dielectric layer in sequence, punching a hole at the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom via hole, filling the bottom via hole with conductive material to form a bottom via hole structure, preparing a bottom electrode on the bottom via hole structure, the size of the bottom electrode being larger than that of the bottom via hole structure, etching the second dielectric layer by self-aligned etching method and stopping etching at the second dielectric layer; 3) depositing a thin film on the bottom electrode and the second dielectric layer, the upper surface of the thin film on the second dielectric layer being lower than the lower surface of the bottom electrode; depositing third dielectric material on the thin film on the top of the second dielectric layer and planarizing, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on the top of the bottom electrode; 4) photoetching the third dielectric material and the thin film on the part of the area above the bottom electrode, the upper surface of the third dielectric material being not higher than the upper surface of the bottom electrode when etching stops; when photoetching the thin film on the part of the area, etching stops at the upper surface of the bottom electrode to form a storage bit; 5) depositing fourth dielectric material and planarizing, photoetching the fourth dielectric material, the third dielectric material and the thin film on the second dielectric layer to expose part or all of the current second dielectric layer; 6) depositing fifth dielectric material and planarizing, forming top metal on the fifth dielectric material on the storage bit by damascene process to finally form a storage chip structure.

6. The production method according to claim 4 or 5, characterized by, In step 2), the self-aligned etching method is dry etching or wet etching.

7. The production method according to claim 4 or 5, characterized by, The material of the storage bit includes MRAM, PCRAM or RRAM.

8. The production method according to claim 4 or 5, characterized by, The first dielectric material, the second dielectric material, the third dielectric material, the fourth dielectric material and the fifth dielectric material are silicon oxide, silicon nitride or low-k material; wherein the first dielectric material and the second dielectric material are different.

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