Semiconductor phase change memory and preparation method thereof

By etching the bottom anti-reflection layer in a lateral direction, heating electrodes of the target size are prepared, which solves the problems of unstable manufacturing of small and medium-sized devices in the prior art and high operating current, and reduces the power consumption of semiconductor phase change memory and simplifies the manufacturing process.

CN119697999APending Publication Date: 2025-03-25SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Patent Information

Application Number
CN202411735402.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-29
Publication Date
2025-03-25

AI Technical Summary

Technical Problem

In the process of increasing data storage density, the prior art mainly achieves performance improvement through device miniaturization. However, this method leads to increased manufacturing costs and unstable manufacturing process, making it difficult to simply and conveniently manufacture small-sized devices, which in turn affects the operating current of the devices.

Method used

Using a semiconductor phase change memory and its preparation method, the key size of the bottom anti-reflective layer is reduced by lateral etching, thereby achieving the target size preparation of the heating electrode. The method includes a multi-step lithography etching process, including a first step etching, a second step lateral etching, a third step etching and surface degreasing treatment, forming an L-shaped blade-shaped heating electrode structure.

Benefits of technology

By reducing the contact area between the heating electrode and the sulfur-based compound material, the power consumption of the semiconductor phase change memory is effectively reduced, and a simpler and more convenient manufacturing process is realized, reducing the device operating current.

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Abstract

The invention relates to a semiconductor phase change memory and a preparation method thereof. The semiconductor phase change memory comprises a logic circuit (201), a bottom electrode (202), a first dielectric layer (203), a second dielectric layer (204), a heating electrode (205), a barrier layer (206), a third dielectric layer (207), a chalcogenide material layer (208), a hard mask layer (209), a fourth dielectric layer (210), a fifth dielectric layer (211), a top electrode and a contact electrode. And the heating electrode (205) is an electrode with a target size, which is prepared by a method for reducing the size of the electrode of the semiconductor phase change memory. By reducing the contact area between the heating electrode (205) and the chalcogenide material layer (208), the power consumption of the semiconductor phase change memory is effectively reduced.
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Description

Technical Field

[0001] The invention belongs to the field of microelectronics, and in particular relates to a semiconductor phase change memory and a preparation method thereof. Background Art

[0002] With the emergence of emerging technologies such as cloud computing and big data, the scale and complexity of data storage have reached unprecedented levels. In the traditional process of increasing data storage density, better performance is mainly achieved through device miniaturization rather than optimizing storage structure. In order to reduce the size of devices at different nodes, it is usually achieved by remaking the mask template and adjusting the lithography conditions. However, the disadvantages of this method are the increase in manufacturing costs and the instability of the manufacturing process. Therefore, in order to solve the above problems, a simpler and more convenient method is needed to manufacture small-sized devices, thereby reducing the device operating current. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a semiconductor phase change memory and a preparation method thereof, so as to realize simpler and more convenient manufacture of small-sized devices, thereby reducing the device operating current.

[0004] The present invention provides a semiconductor phase change memory, which comprises a logic circuit, a bottom electrode, a first dielectric layer, a second dielectric layer, a heating electrode, a barrier layer, a third dielectric layer, a sulfur compound material layer, a hard mask layer, a fourth dielectric layer and a fifth dielectric layer, a top electrode, and a contact electrode; the heating electrode is an electrode of a target size obtained by reducing the size of an electrode of a semiconductor phase change memory.

[0005] Preferably, the heating electrode is an L-shaped blade-like structure arranged on the bottom electrode, the horizontal bottom edge of the blade-like structure is connected to the surface of the bottom electrode, and the upper end of the vertical side wall of the blade-like structure is connected to the lower end of the sulfur compound material layer.

[0006] Preferably, the bottom electrode may adopt a structure of multiple through holes.

[0007] More preferably, the bottom electrode is a structure of two through holes, and the two through holes are symmetrically distributed on two sides of the semiconductor phase change memory.

[0008] Preferably, the contact electrode is deposited in the loop contact hole and contacts the bottom electrode; the top electrode is deposited in the top electrode through hole and contacts the hard mask layer.

[0009] Preferably, the heating electrode is an electrode structure of target size made by the following method:

[0010] S1: First step of etching: after the photolithography is completed, the bottom anti-reflection layer in the photoresist layer is etched;

[0011] S2: second etching step: performing lateral etching on the bottom anti-reflection layer in step S1 to reduce the critical dimension of the bottom anti-reflection layer;

[0012] S3: The third step of etching: completely etching the photoresist layer and completing the patterning of the layer to be etched;

[0013] S4: Perform surface degumming and cleaning to obtain a heating electrode of target size.

[0014] Preferably, when the photoresist layer structure is two layers, it includes a photoresist layer and a bottom anti-reflection layer; when the photoresist layer structure is three layers, it includes a photoresist layer, a bottom anti-reflection layer and a hard mask layer; when the photoresist layer structure is three layers, it includes a photoresist layer, a bottom anti-reflection layer, a hard mask layer and a soft mask layer.

[0015] Preferably, the hard mask layer includes but is not limited to low-temperature silicon oxide, titanium nitride, silicon nitride, silicon oxynitride or silicon oxycarbide; the soft mask layer includes but is not limited to spin-on carbon, amorphous carbon, amorphous silicon or an organic dielectric layer; the layer structure to be etched is at least one layer, and the material of the layer to be etched includes at least one of metal, dielectric, and semiconductor materials.

[0016] Preferably, the conditions for the second etching in step S2 are: a high frequency power source of 300-500W, a pressure of 50-120mTorr, and a gas comprising a halogen gas and at least one auxiliary gas; wherein the halogen gas includes but is not limited to CF4 or C4F8, and the auxiliary gas includes but is not limited to oxygen, hydrogen, nitrogen, argon or helium.

[0017] Preferably, when the photoresist layer is a two-layer structure, the second etching step reduces the critical dimensions of the photoresist layer and the bottom anti-reflection layer; when the photoresist layer is a three-layer or four-layer structure, the second etching step reduces the critical dimensions of the bottom anti-reflection layer.

[0018] The present invention also provides a method for preparing the semiconductor phase change memory, comprising the following steps:

[0019] (1) depositing a first dielectric layer on the logic circuit, and then depositing a second dielectric layer;

[0020] (2) forming a groove above the bottom electrode by etching, and depositing a heating electrode on the surface of the groove to connect with the bottom electrode 202, and then depositing a barrier layer on the heating electrode;

[0021] (3) etching the barrier layer and the heating electrode at the bottom of the groove, and depositing a third dielectric layer to fill the groove;

[0022] (4) exposing the top of the heating electrode by chemical mechanical polishing;

[0023] (5) depositing a chalcogenide material layer and a hard mask layer on top of the heating electrode;

[0024] (6) etching the chalcogenide material layer and the hard mask layer to obtain a memory cell pattern;

[0025] (7) sequentially depositing a fourth dielectric layer and a fifth dielectric layer;

[0026] (8) forming a loop contact hole by etching and depositing a contact electrode to contact the bottom electrode;

[0027] (9) A top electrode through hole is formed by etching the fifth dielectric layer, and a top electrode is deposited to contact the hard mask layer.

[0028] Preferably, the material of the bottom electrode includes but is not limited to tungsten; the materials of the first dielectric layer and the second dielectric layer include but are not limited to SiN or SiO2; and the material of the hard mask layer includes TiN or TaN.

[0029] Preferably, the material of the heating electrode includes at least one of Ti, W, Ta, Cu, WCN, WN, TiSiN, TiN or TaN.

[0030] Preferably, the material of the sulfur-based compound material layer includes GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb system or GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb system containing doping elements; wherein the doping element includes at least one of Sc, Ag, In, Al, C, S, Se, N, Cu or W.

[0031] Preferably, the chalcogenide compound material layer is deposited by physical vapor deposition.

[0032] Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer are deposited by chemical vapor deposition.

[0033] Beneficial Effects

[0034] The invention can reduce the critical dimension by 80% by processing the lateral process dimension of the bottom anti-reflection layer. The method does not need to re-make the photolithography mask, which can reduce the cost of process manufacturing; the invention effectively reduces the power consumption of semiconductor phase change memory by reducing the contact area between the heating electrode and the sulfur compound material. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a device having a four-layer photoresist layer structure in Example 1 of the present invention;

[0036] Figure 2 This is a schematic diagram of the device after etching the bottom anti-reflection layer in Example 1 of the present invention;

[0037] Figure 3 This is a schematic diagram of a device after the bottom anti-reflection layer is laterally etched in Example 1 of the present invention;

[0038] Figure 4 This is a schematic diagram of the device after the third etching step in Example 1 of the present invention;

[0039] Figure 5 This is a schematic diagram of the device after surface degumming and cleaning in Example 1 of the present invention;

[0040] Figure 6 (a) SEM of etching results without using the method of the present invention, (b) SEM of etching results using the method of the present invention in Example 1;

[0041] Figure 7 This is a schematic diagram of a device after the first dielectric layer and the second dielectric layer are deposited in Example 1 of the present invention;

[0042] Figure 8 This is a schematic diagram of a device after etching to form a groove in Example 1 of the present invention;

[0043] Fig. 9 This is a schematic diagram of a device after the heating electrode and the barrier layer are deposited in Example 1 of the present invention;

[0044] Fig.10 It is a side view in the X direction of the device structure after the heating electrodes are separated by etching in Example 1 of the present invention;

[0045] Fig.11 It is a side view in the Y direction of the device structure after the heating electrodes are separated by etching in Example 1 of the present invention;

[0046] Fig.12 This is a schematic diagram of a device after the third dielectric layer is deposited in Example 1 of the present invention;

[0047] Fig.13 This is a schematic diagram of a device after chemical mechanical polishing of the heating electrode in Example 1 of the present invention;

[0048] Fig.14 It is a schematic diagram of a device after the chalcogenide compound material layer and the hard mask layer are deposited in Example 1 of the present invention;

[0049] Fig.15 A schematic diagram of obtaining a memory cell pattern by etching in Embodiment 1 of the present invention;

[0050] Fig.16This is a schematic diagram of a device after the fourth dielectric layer and the fifth dielectric layer are deposited in Example 1 of the present invention;

[0051] Fig.17 It is a schematic diagram of the device after etching to form a loop contact hole in Example 1 of the present invention;

[0052] Fig.18 This is a schematic diagram of the device after etching to form the top electrode through hole in Example 1 of the present invention.

[0053] Figure numerals: 101-photoresist layer, 102-bottom anti-reflective layer, 103-hard mask layer, 104-soft mask layer, 105-layer to be etched, 106-substrate, 201-logic circuit, 202-bottom electrode, 203-first dielectric layer, 203-second dielectric layer, 205-heating electrode, 206-blocking layer, 207-third dielectric layer, 208-phase change material, 209-hard mask layer, 210-fourth dielectric layer, 211-fifth dielectric layer, 212-loop contact hole, 213-top electrode through hole. DETAILED DESCRIPTION

[0054] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0055] Example

[0056] The present embodiment provides a semiconductor phase change memory, which includes a logic circuit 201, a bottom electrode 202, a first dielectric layer 203, a second dielectric layer 204, a heating electrode 205, a barrier layer 206, a third dielectric layer 207, a sulfur compound material layer 208, a hard mask layer 209, a fourth dielectric layer 210 and a fifth dielectric layer 211, a top electrode, and a contact electrode; the heating electrode 205 is an L-shaped blade-like structure arranged on the bottom electrode 202, the horizontal bottom edge of the blade-like structure is connected to the surface of the bottom electrode 202, and the upper end of the vertical side wall of the blade-like structure is connected to the lower end of the sulfur compound material layer 208. In this embodiment, the bottom electrode 202 is a structure of two through holes, and the two through holes are symmetrically distributed on both sides of the semiconductor phase change memory. The contact electrode is deposited in the loop contact hole 212 and contacts the bottom electrode 202; the top electrode is deposited in the top electrode through hole 213 and contacts the hard mask layer 209.

[0057] In this embodiment, the heating electrode 205 is a target size electrode structure prepared by the following method. Four photoresist film layers are used, including a photoresist layer 101, a bottom anti-reflection layer 102, a hard mask layer 103, and a soft mask layer 104. Figure 1 As shown, the hard mask 103 is low temperature silicon oxide, and the soft mask 104 is spin-coated organic carbon. The method comprises the following steps:

[0058] S1: First step of etching: After the photolithography is completed, the bottom anti-reflection layer 102 in the photoresist layer is etched, such as Figure 2 shown.

[0059] S2: Second etching step: Laterally etching the bottom anti-reflection layer 102, such as Figure 3 As shown, the etching conditions are high frequency power source 300-500W, pressure 50-120mTorr, gas CF4 and O2;

[0060] S3: The third step of etching: After the size is reduced to the target size, the etching of the hard mask layer 103 and the soft mask layer 104 is completed, and the pattern is transferred to the layer to be etched 105, such as Figure 4 As shown;

[0061] S4: Surface degumming and cleaning are performed to obtain the heating electrode 205 of the final target size, such as Figure 5 shown.

[0062] Figure 6 For comparison of etching results, (a) is the SEM of etching result without using the method of the present invention, and (b) is the SEM of etching result using the method of the present invention. It can be seen that Figure 6 The critical dimension of the line in (b) is significantly reduced.

[0063] The method for preparing a semiconductor phase change memory in this embodiment includes the following steps:

[0064] (1) A SiN first dielectric layer 203 is prepared on the logic circuit 201 by chemical vapor deposition; a tungsten bottom electrode 202 is located between the first dielectric layer 203 and the logic circuit 201, with the lower portion of the bottom electrode 202 located in the logic circuit 201 and the upper portion located in the first dielectric layer 203; then a SiO2 second dielectric layer 204 is deposited, such as Figure 7 As shown;

[0065] (2) A groove is formed above the bottom electrode 202 by etching, such as Figure 8 As shown, a TiN heating electrode 205 is deposited on the surface of the groove, connected to the bottom electrode 202, and then a barrier layer 206 is deposited on the heating electrode 205. Fig. 9 As shown;

[0066] (3) etching the barrier layer 206 and the heating electrode 205 at the bottom of the groove to separate the heating electrode 205; Fig.10 is the X-direction side view of the structure, Fig.11 is a side view in the Y direction; then a third dielectric layer 207 is deposited to fill the groove, such as Fig.12 As shown;

[0067] (4) Expose the flat top of the heating electrode 205 by chemical mechanical polishing, such as Fig.13 As shown, a heating electrode 205 with a blade-like structure is formed;

[0068] (5) Ge2Sb2Te5 chalcogenide material layer 208 and TiN hard mask layer 209 are prepared on top of the heating electrode 205 by physical vapor deposition, as shown in FIG. Fig.14 As shown;

[0069] (6) Etching the chalcogenide material layer 208 and the hard mask layer 209 to obtain a memory cell pattern, such as Fig.15 As shown;

[0070] (7) A fourth dielectric layer 210 and a fifth dielectric layer 211 are sequentially deposited on the chalcogenide material layer 208 and the hard mask layer 209, as shown in FIG. Fig.16 As shown;

[0071] (8) Forming loop contact hole 212 by plasma etching, such as Fig.17 As shown, a contact electrode is deposited to contact the bottom electrode 202;

[0072] (9) A top electrode through hole 213 is formed in the fifth dielectric layer 211 by plasma etching, such as Fig.18 As shown, a top electrode is deposited in contact with the hard mask layer 209 .

Claims

1. A semiconductor phase change memory, characterized in that: The semiconductor phase change memory comprises a logic circuit (201), a bottom electrode (202), a first dielectric layer (203), a second dielectric layer (204), a heating electrode (205), a barrier layer (206), a third dielectric layer (207), a sulfur compound material layer (208), a hard mask layer (209), a fourth dielectric layer (210), a fifth dielectric layer (211), a top electrode, and a contact electrode; the heating electrode (205) is an electrode of a target size obtained by a method of reducing the size of an electrode of a semiconductor phase change memory.

2. The semiconductor phase change memory according to claim 1, characterized in that: The heating electrode (205) is an L-shaped blade-like structure disposed on the bottom electrode (202), the horizontal bottom edge of the blade-like structure is connected to the surface of the bottom electrode (202), and the upper end of the vertical side wall of the blade-like structure is connected to the lower end of the sulfur compound material layer (208).

3. The semiconductor phase change memory according to claim 1, characterized in that: The contact electrode is deposited in the loop contact hole (212) and is in contact with the bottom electrode (202); the top electrode is deposited in the top electrode through hole (213) and is in contact with the hard mask layer (209).

4. The semiconductor phase change memory according to claim 1, characterized in that: The heating electrode (205) is an electrode structure of target size obtained by the following method: S1: First step of etching: after the photolithography is completed, the bottom anti-reflection layer (102) in the photoresist layer is etched; S2: second etching step: performing lateral etching on the bottom anti-reflection layer (102) in step S1 to reduce the critical dimension of the bottom anti-reflection layer (102); S3: the third etching step: completely etching the photoresist layer and completing the patterning of the layer to be etched (105); S4: performing surface degumming and cleaning treatment to obtain a heating electrode (205) of a target size.

5. The semiconductor phase change memory according to claim 4, characterized in that: When the photoresist layer structure is two layers, it comprises a photoresist layer (101) and a bottom anti-reflection layer (102); when the photoresist layer structure is three layers, it comprises a photoresist layer (101), a bottom anti-reflection layer (102) and a hard mask layer (103); when the photoresist layer structure is three layers, it comprises a photoresist layer (101), a bottom anti-reflection layer (102), a hard mask layer (103) and a soft mask layer (104).

6. The semiconductor phase change memory according to claim 4, characterized in that: The hard mask layer (103) comprises low-temperature silicon oxide, titanium nitride, silicon nitride, silicon oxynitride or silicon oxycarbide; the soft mask layer (104) comprises spin-on carbon, amorphous carbon, amorphous silicon or an organic dielectric layer; the structure of the layer to be etched (105) is at least one layer, and the material of the layer to be etched (105) comprises at least one of metal, dielectric and semiconductor materials.

7. A method for preparing a semiconductor phase change memory according to any one of claims 1 to 6, comprising the following steps: (1) depositing a first dielectric layer (203) on the logic circuit (201), and then depositing a second dielectric layer (204); (2) forming a groove above the bottom electrode (202) by etching, and depositing a heating electrode (205) on the surface of the groove to connect with the bottom electrode (202), and then depositing a barrier layer (206) on the heating electrode (205); (3) etching the barrier layer (206) and the heating electrode (205) at the bottom of the groove, and depositing a third dielectric layer (207) to fill the groove; (4) exposing the top of the heating electrode (205) by chemical mechanical polishing; (5) depositing a chalcogenide material layer (208) and a hard mask layer (209) on top of the heating electrode (205); (6) etching the chalcogenide material layer (208) and the hard mask layer (209) to obtain a memory cell pattern; (7) sequentially depositing a fourth dielectric layer (210) and a fifth dielectric layer (211); (8) forming a loop contact hole (212) by etching, and depositing a contact electrode to contact the bottom electrode (202); (9) A top electrode through hole (213) is formed by etching the fifth dielectric layer (211), and a top electrode is deposited to contact the hard mask layer (209).

8. The method for preparing a semiconductor phase change memory according to claim 7, characterized in that: The material of the bottom electrode (202) includes tungsten; the material of the first dielectric layer (203) and the second dielectric layer (204) includes SiN or SiO2; and the material of the hard mask layer (209) includes TiN or TaN.

9. The method for preparing a semiconductor phase change memory according to claim 7, characterized in that: The material of the heating electrode (205) includes at least one of Ti, W, Ta, Cu, WCN, WN, TiSiN, TiN or TaN.

10. The method for preparing a semiconductor phase change memory according to claim 7, characterized in that: The material of the sulfur compound material layer (208) includes GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb system or GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb system containing doping elements; wherein the doping element includes at least one of Sc, Ag, In, Al, C, S, Se, N, Cu or W.