Adaptive control method of phase change memory, phase change memory, medium and electronic device

Abstract

The application discloses a self-adaptive control method of a phase change memory, the phase change memory, a storage medium and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: writing a full 0 data mode into a storage unit within a minimum write-to-read time interval; performing a read operation on the storage unit to which the full 0 data mode is written, and obtaining detection data; obtaining at least one storage array bit error rate index according to the detection data; and based on a comparison result of the bit error rate index and a preset threshold, selecting a target voltage gear from a preconfigured voltage gear set to adjust the read voltage of the storage unit to a corresponding read voltage gear. The application realizes self-adaptive and accurate calibration of the read voltage through fast detection of the full 0 mode under the minimum write-to-read interval and global evaluation of the bit error rate, thereby guaranteeing the test efficiency and significantly improving the reliability and durability of the memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an adaptive control method for phase-change memory, a phase-change memory, a medium, and an electronic device. Background Technology

[0002] Phase-change memory (PCM) faces severe reliability challenges during long-term operation due to the irreversible aging characteristics of phase-change materials under cyclic write / erase operations. As the number of cycles increases, the threshold voltage (Vt) of the memory cell exhibits a significant non-linear drift: it drops rapidly in the early stages of its lifespan (BOL stage) and gradually saturates towards the end of its lifespan (EOL stage). This dynamic change leads to a severe mismatch between the preset read voltage (Vread) and actual requirements. Failure to adjust this accurately and promptly will directly cause two problems:

[0003] First, the uncorrectable bit error rate (UBER) rises sharply, potentially exceeding the fault tolerance capability of the error correction code (ECC); second, it accelerates material degradation and shortens device lifespan. Summary of the Invention

[0004] The main objective of this invention is to provide an adaptive control method for phase-change memory, a phase-change memory, a medium, and an electronic device, aiming to solve the read voltage mismatch problem caused by the nonlinear drift of the threshold voltage of the phase-change memory, and improve data reliability and device durability.

[0005] To achieve the above objectives, this invention proposes an adaptive control method for a phase-change memory, wherein the phase-change memory includes at least one memory array, the memory array includes a plurality of memory cells, and the method includes:

[0006] Write an all-zero data pattern to the storage unit within the minimum write-to-read interval;

[0007] A read operation is performed on the storage unit in the write all-zero data mode to obtain the detection data;

[0008] Based on the detection data, obtain the bit error rate index of the at least one storage array;

[0009] Based on the comparison result between the bit error rate index and the preset threshold, a target voltage level is selected from the pre-configured voltage level set to adjust the read voltage of the storage unit to the corresponding read voltage level.

[0010] The present invention also proposes a phase-change memory, comprising:

[0011] At least one storage array, each storage array comprising a plurality of storage units;

[0012] The data writing module is used to write all-zero data to the storage unit within the minimum write-to-read time interval;

[0013] The data reading module is used to perform a reading operation on the all-zero data mode to obtain detection data;

[0014] The bit error rate analysis module is used to obtain the bit error rate index of the at least one storage array based on the detection data.

[0015] The voltage adjustment module is used to select a target voltage level from a pre-configured voltage level set based on the comparison result between the bit error rate index and a preset threshold, so as to adjust the read voltage of the storage unit to the corresponding read voltage level.

[0016] The present invention also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the adaptive control method for phase change memory as described above.

[0017] The present invention also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the adaptive control method for phase-change memory as described above.

[0018] The technical solution of this invention obtains at least one bit error rate indicator (including bit error rate (RBER) and fault bit count (FBC)) of the storage array by writing all-zero mode to the storage cell under the condition of minimum write-to-read interval; and by comparing the bit error rate indicator with a preset threshold, it triggers the adaptive switching of multi-level read voltage levels (R1-Rn).

[0019] Therefore, this invention, based on the dynamic inspection mechanism inside the phase-change memory, accurately captures the nonlinear logarithmic drift characteristics of the threshold voltage (Vt) with the number of cycles through dual-index collaborative detection in the all-zero write mode (RBER assesses the overall bit error rate, and FBC locates local failure cells). This enables adaptive voltage level switching timing decisions, effectively avoiding the risks of premature switching (ECC redundancy waste) or delayed switching (bit error rate exceeding the standard) caused by traditional fixed thresholds. Thus, it accurately compensates for the Vt drift heterogeneity of the phase-change memory, extending the device's lifespan while ensuring data reliability. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 A schematic diagram showing the effects of changes in Vt and Vread in a phase-change memory and E3 loss.

[0022] Figure 2 A graph showing the relationship between the reset threshold voltage (Reset Vt) of a phase-change memory and the logarithm of the number of cycles.

[0023] Figure 3 This is a graph showing how the reference data of the phase-change memory changes with the number of cycles.

[0024] Figure 4 A graph showing the relationship between the bit error rate of a phase-change memory and the read voltage setting and cycle count limit;

[0025] Figure 5 This is a graph showing the relationship between the reset threshold voltage and the cycle count limit for a phase-change memory.

[0026] Figure 6 This is a flowchart of the adaptive control method for a phase-change memory according to the first embodiment of the present invention;

[0027] Figure 7 This is a durability-reading voltage correspondence table for the second embodiment of the present invention;

[0028] Figure 8 This is a flowchart of the adaptive control method for a phase-change memory according to a second embodiment of the present invention;

[0029] Figure 9 This is a schematic diagram of the structure of a phase-change memory provided in an embodiment of the present invention;

[0030] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0031] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0033] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0034] Please refer to Figure 1 , Figure 1 This diagram illustrates the changes in Vt and Vread voltages and the impact of E3 losses in a phase-change memory (PCM). The diagram shows the changes in the threshold voltage (Vt) and the adjustment requirements of the read voltage (Vread) during PCM endurance testing. Two sets of waveforms are presented, corresponding to the states of data "1" and "0" at the beginning and end of the lifespan (BOL) and end of the lifespan (EOL), respectively. Due to the inherent characteristics of PCM, the threshold voltage (Vt) shifts after endurance testing. Vt decreases more rapidly in the beginning of the lifespan (BOL) and then tends to saturate in the end of the lifespan (EOL). Furthermore, Vt does not change linearly with the number of cycles, but is approximately linearly related to the logarithm of the number of cycles. As can be seen in the diagram, the waveform positions corresponding to BOL and EOL are different in the "1" and "0" waveform sets, reflecting the changes in Vt. Simultaneously, due to E3 losses, if the read voltage (Vread) is not adjusted, a reset failure will be observed after cycling. To ensure that the bit error rate (UBER) meets the requirements at the end of the lifetime (EOL), the read voltage (Vread) needs to be adjusted. The figure shows the read voltages (Vread-EOL and Vread-BOL) corresponding to EOL and BOL, respectively, illustrating the changes in the required read voltage at different lifetime stages. This shows that as Vt changes, Vread needs to be changed accordingly to correctly read the stored data.

[0035] Please refer to Figure 2 , Figure 2This is a graph showing the relationship between the reset threshold voltage (Reset Vt) and the logarithm of the number of cycles in a phase-change memory (PCM). The horizontal axis represents the logarithm of the number of cycles (Log(Cycling)), indicating that the number of cycles is measured on a logarithmic scale. This is because the number of cycles in PCM endurance testing often ranges widely, and using a logarithmic scale can more effectively show the data trend. The vertical axis represents the reset threshold voltage (Reset Vt), which measures the threshold voltage value of the PCM when it is in the reset state. As can be seen from the diagonal line in the graph, the reset threshold voltage (Reset Vt) and the logarithm of the number of cycles (Log(Cycling)) are approximately linearly related; as the logarithm of the number of cycles increases, the reset threshold voltage (Reset Vt) gradually decreases. This reflects the characteristics of phase-change memory, namely that as the number of cycles in the endurance test increases, the reset threshold voltage gradually decreases. In other words, the threshold voltage does not change linearly with the number of cycles, but is approximately linearly related to the logarithm of the number of cycles.

[0036] Please refer to Figure 3 , Figure 3 This is a graph showing the variation of phase-change memory (PCM) reference data with the number of cycles. The graph illustrates how measured values ​​change with the number of cycles (CYC) under different conditions. The horizontal axis represents the number of cycles (CYC), ranging from 1 to 10,000,000. The vertical axis represents the measured value of Vt, in millivolts (mV). The graph contains three lines of different colors—blue, green, and red—representing different sets of measurement data, labeled "BOTTOM" (bottom layer) and "TOP" (top layer). The trend of the lines shows that as the number of cycles increases, the measured values ​​of all three lines generally decrease, with more significant decreases or fluctuations at certain cycle count nodes. This reflects the change in measured values ​​with increasing cycle count during endurance testing of the PCM, which is related to characteristics such as the threshold voltage drift of the PCM.

[0037] Please refer to Figure 4 , Figure 4This graph illustrates the relationship between the bit error rate (RBER) of a phase-change memory (PCM) and read voltage settings and cycle count limits. The graph shows how the RBER changes with the minimum write-to-read delay (minimal w2f delay) under different read voltage settings (Vread1 settings) and cycle count limits (CYClimit). Since the threshold voltage (Vt) of the PCM decreases after each cycle, different read voltages (Vread) are used depending on the R settings (e.g., R1-R5), with the Vread value decreasing in the order R1→R2→R3→R4→R5. The horizontal axis represents the Vread1 setting, arranged sequentially from R1 to R5, and the vertical axis represents the RBER value under the minimum write delay condition. The graph contains five curves, corresponding to CYC limit1-CYC limit4 and a gray curve t0, representing the trend of RBER with Vread1 settings under different cycle count limits. During the early lifespan (BOL) and late lifespan (EOL), the bit error rate (BER) decreases as Vread1 changes from R1 to R5. When the loop count reaches limit1, the system switches from R1 to R2; otherwise, at the minimum write delay, the BER will exceed the preset threshold (RBER or FBC limit, the horizontal dashed line in the figure). However, due to factors such as die-to-die variations, cell-to-cell variations, and wear-leveling accuracy, the Vread switching between different R values ​​in the figure is difficult to control precisely.

[0038] Please refer to Figure 5 , Figure 5 This is a graph showing the relationship between the reset threshold voltage and the cycle count limit for a phase-change memory. Figure 5 This diagram illustrates the relationship between the reset threshold voltage (Reset Vt) and the cycle count limit (CYC limit) in a phase-change memory. The figure shows the distribution of the reset threshold voltage under different cycle count limits using curves. There are five curves of different colors, each corresponding to a different cycle count limit. Figure 4The graph shows CYC limits 1-4 and a curve labeled t0. Curve t0 represents the distribution of the reset threshold voltage at the beginning of the lifespan. Looking at the relative positions of the curves, as the cycle count limit increases from CYC limit 1 to CYC limit 4, the position and shape of the curves change, reflecting the alteration of the reset threshold voltage distribution range and characteristics with increasing cycle count. This change is related to the durability characteristics of phase-change memory; that is, as the cycle operation progresses, the threshold voltage of the memory cell will drift and change. Figure 5 The curves visually demonstrate the changing trend of the reset threshold voltage under different cycle number limits.

[0039] In summary, Figures 1-5 The performance of phase-change memory in durability testing was demonstrated. Among other things, Figure 1 This indicates that the cyclic operation will cause the threshold voltage (Vt) to change and generate E3 loss, which in turn leads to reset state problems, requiring adjustment of the read voltage (Vread); Figure 2 The display shows that the reset threshold voltage has an approximately linear relationship with the logarithm of the number of cycles, revealing the characteristics of Vt as a function of the number of cycles; Figure 3 The phase-change memory reference data shows a decrease as the number of cycles increases; Figure 4 This demonstrates the changes in bit error rate under different read voltage settings and cycle count limits, and their relationship with the bit error rate limit. Figure 5 The distribution and trend of the reset threshold voltage under different cycle number limits are presented. In summary, Figures 1-5 This indicates that phase-change memory (PCM) exhibits issues such as threshold voltage variation, reference data changes, and bit error rate fluctuations during endurance testing. Furthermore, factors such as read voltage settings and cycle counts can significantly impact its performance, highlighting the necessity of precisely controlling and optimizing relevant parameters to ensure memory performance stability.

[0040] Please refer to Figure 6 , Figure 6 This is a flowchart of an adaptive control method for a phase-change memory according to a first embodiment of the present invention. An adaptive control method for a phase-change memory, wherein the phase-change memory includes at least one memory array, the memory array including a plurality of memory cells, the method comprising:

[0041] S610 writes all-zero data to the storage cell within the minimum write-to-read interval.

[0042] Optionally, the minimum write-to-read interval (e.g., 1µs, 10µs, 25µs, etc.) refers to the shortest allowed time interval from the end of a write operation to the start of a read operation. This parameter is used to simulate strict read-write timing conditions, enabling tests to expose potential bit error issues.

[0043] Optionally, the all-zero data mode is a mode in which a continuous sequence of logic 0 values ​​needs to be written to all the memory cells under test. This mode can effectively detect the stability of the reset state (high impedance state) because writing all zeros forces the phase change material into an amorphous state (reset state). If there is an abnormal reading at this time, it can reflect a bit error problem.

[0044] S620 performs a read operation on the storage cell that has been written in all-zero data mode to obtain the detection data.

[0045] Optionally, read operations must be performed immediately after writing to capture transient bit errors, such as those caused by write residual effects or material relaxation. The detection data includes the read status of all memory cells, providing raw data for subsequent bit error rate calculations.

[0046] S630: Based on the detection data, obtain the bit error rate index of at least one storage array.

[0047] Optionally, the bit error rate metrics include the bit error rate (RBER) and the fault bit count (FBC). The RBER is obtained by comparing the number of erroneous bits read in the reset state to the total number of bits, reflecting the reliability of the reset state. The fault bit count is obtained by counting the number of cells in at least one memory array that exceed a preset tolerance voltage range, used to locate localized failure areas; the preset tolerance voltage range represents the safe voltage fluctuation range (i.e., the safe operating range) allowed for a memory cell during read operations. The calculation must cover the entire phase-change memory to ensure the evaluation results are globally representative.

[0048] S640, based on the comparison result between the bit error rate index and the preset threshold, selects the target voltage level from the pre-configured voltage level set to adjust to the corresponding reading voltage value.

[0049] Optionally, the dynamic adjustment mechanism includes: if the bit error rate exceeds a preset threshold, gradually increasing the read voltage level of the current storage unit to the target voltage level according to a pre-configured set of voltage levels (e.g., R1→R2→R3...). After each increase in the read voltage level of the storage unit, the operation of obtaining detection data is repeated until the bit error rate is compared with the preset threshold. The adjustment terminates when the bit error rate is below the preset threshold and the read voltage level of the storage unit is within a preset safe operating range (to avoid overvoltage damage).

[0050] Optionally, the durability level association includes selecting the corresponding level based on the durability level (e.g., Limit1-Limit4) of the phase-change memory's cumulative erase / write cycles. For example, a higher level (e.g., R2 instead of R1) is preferred for high cycle counts. After each switch of the memory cell's read voltage to the new voltage level, the read voltage of the memory cell is maintained at the new voltage level for at least one detection cycle to ensure the memory cell's state is stable. The lower limit of the detection cycle is an integer multiple of the minimum write-to-read time interval; the specific multiple can be determined based on actual conditions.

[0051] Optionally, the verification and iteration steps include: after each switch of the reading voltage of the storage unit to a new voltage level, the operation of obtaining the bit error rate is re-executed after the voltage level is adjusted; if the bit error rate index still exceeds the preset threshold after adjustment, the reading voltage of the storage unit is switched to the next voltage level, and the operation of obtaining the bit error rate is performed until the requirements are met.

[0052] In some embodiments, the frequency of performing the bit error rate acquisition operation is determined based on any of the following factors:

[0053] The durability class range of a phase-change memory based on its cumulative erase / write cycles;

[0054] The continuous usage time of the current voltage level;

[0055] The growth rate of the bit error rate metric relative to historical test results.

[0056] Specifically, the detection frequency control is determined by dynamically adjusting the detection frequency based on the write / erase cycle level, the usage time of the current level, or the error rate growth rate. For example, higher durability levels (near the end of the lifespan) require more frequent detection.

[0057] In summary, the adaptive control method for phase-change memory of this invention first employs strict timing control with a minimum write-to-read delay to expose potential problems under the most stringent conditions; secondly, it uses writes in an all-zero data mode to specifically perform stability testing in the reset state (high-impedance state); then, it establishes a multi-dimensional evaluation system including bit error rate and fault bit count to comprehensively monitor the memory state from both macroscopic and microscopic levels; finally, based on real-time bit error feedback and durability level, it adopts a periodic inspection mechanism using multiple internal R values ​​(such as R1-R6) of the phase-change memory to dynamically determine the Vread switching timing. This periodic inspection mechanism can achieve precise control through the following methods:

[0058] First, dynamic switching timing is determined. The system periodically performs a full scan test on all preset R levels. By monitoring the bit error rate (BER) trend under each level, switching is triggered when the BER of the current voltage level exceeds a preset threshold. This design avoids the high BER risk caused by premature switching and prevents the error correction capability from exceeding limits due to late switching.

[0059] Second, balance durability differences. By running inspection algorithms independently within each die and introducing durability level ranges, the R switching threshold is dynamically adjusted based on the historical bit error rate growth curve of each die (such as Vt drift rate, bit error rate acceleration, etc.). For example, for dies aging rapidly, switching is triggered when the bit error rate reaches a preset threshold (e.g., 80%), while for dies aging slowly, the threshold is relaxed to a preset threshold (e.g., 90%). At the module level, by comparing the histograms of R value distributions for each module, compensatory intervention is implemented for modules with switching lag (e.g., more than 30% of dies remain at low levels), increasing their testing frequency (e.g., doubling it).

[0060] Through the timing control in step S610, the test mode in step S620, the evaluation index in step S630, and the voltage level adjustment in step S640, the performance degradation caused by threshold voltage drift, material aging, and cell discreteness is effectively compensated. Without exceeding the ECC error correction capability, dies with different durability performance can complete voltage switching at the optimal time, thereby maintaining stable read reliability throughout the entire life cycle and significantly improving the durability and data integrity of the memory.

[0061] Please refer to Figure 7 , Figure 7 This is a durability-read voltage correspondence table according to the second embodiment of the present invention. The table presents the read voltage selections and read voltage adjustments corresponding to different endurance ranges. The voltage range set includes the first to sixth voltage ranges (e.g., R1-R6) arranged in ascending order. Each voltage range corresponds to a pre-configured read voltage value (e.g., TBD, TBD-50mV, TBD-100mV, TBD-125mV, TBD-150mV, TBD-175mV) and an endurance level range (e.g., 0-20k, 2k-40k, 20k-100k, 50k-400k, 200k-1M, 400k-4M). It should be noted that the voltage range, read voltage value, and endurance level range can be adjusted according to actual conditions and are not limited to the examples above.

[0062] Optionally, durability is measured by the number of erase / write cycles, divided into several ranges: 0-20k cycles, the read voltage is set to R1, with the adjustment marked "TBD" (preset value); 2k-40k cycles, the read voltage is set to R2, with the adjustment "TBD-50mV" (preset value reduced by 50mV); 20k-100k cycles, the read voltage is set to R3, with the adjustment "TBD-100mV"; 50k-400k cycles, the read voltage is set to R4, with the adjustment "TBD-125mV"; 200k-1M cycles, the read voltage is set to R5, with the adjustment "TBD-150mV"; and 400k-4M cycles, the read voltage is set to R6, with the adjustment "TBD-175mV". This indicates that as the number of erase / write cycles increases, the durability changes, and the corresponding read voltage will have different selections and potential reduction adjustments.

[0063] Please refer to Figure 8 , Figure 8 This is a flowchart of an adaptive control method for a phase-change memory according to a second embodiment of the present invention. The read voltage adjustment process includes:

[0064] S810 sets the read voltage to Vread_R1.

[0065] S811 sets the minimum write-to-read interval and uses an all-zero data mode.

[0066] S812, check whether the bit error rate (RBER) and / or fault bit count (FBC) exceed the corresponding preset threshold (limit):

[0067] If the preset threshold is not exceeded, it means that the currently set read voltage Vread_R1 is appropriate, and the process ends.

[0068] If the preset threshold is exceeded, it means that Vread_R1 is not suitable, and proceed to S813.

[0069] S813 sets the read voltage to Vread_R2.

[0070] S814, re-set the minimum write-to-read interval and use all-zero data mode.

[0071] S815, recheck whether the bit error rate (RBER) or fault bit count (FBC) exceeds the corresponding preset threshold (limit):

[0072] If the preset threshold is not exceeded, it indicates that Vread_R2 is a suitable read voltage, and the process ends.

[0073] If the preset threshold is exceeded, it means that Vread_R2 is also unsuitable, and proceed to S816.

[0074] S816 sets the read voltage to Vread_R3.

[0075] S817 sets the minimum write-to-read interval and uses an all-zero data mode.

[0076] S818, check if the bit error rate (RBER) or fault bit count (FBC) exceeds the corresponding preset threshold (limit):

[0077] If the preset threshold is not exceeded, meaning Vread_R3 is a suitable read voltage, the process ends.

[0078] If the preset threshold is exceeded, the read voltage is set to the next preset read voltage (if there is a preset read voltage that has not yet been tested, such as Vread_R4 after Vread_R3; if all preset read voltage options have been traversed, the operation stops). Then, the minimum write-to-read interval is set again, and an all-zero data mode is used. Next, the bit error rate (RBER) or fault bit count (FBC) is rechecked to see if it exceeds the corresponding preset threshold. This process is repeated until a read voltage setting that satisfies the condition that the bit error rate (RBER) or fault bit count (FBC) does not exceed the corresponding preset threshold is found, or all preset read voltage options have been traversed.

[0079] Therefore, this invention addresses the read voltage mismatch problem caused by nonlinear threshold voltage drift in phase-change memory (PCM) by employing a dynamic, graded voltage adjustment mechanism combined with real-time error feedback to improve data reliability and device durability. The specific process includes: first, testing is performed using a preset initial read voltage (Vread_R1) along with a minimum write-to-read time interval and an all-zero data mode. Voltage matching is assessed by real-time monitoring of the bit error rate (RBER) or fault bit count (FBC). If the RBER exceeds a preset threshold, the process is progressively switched to higher-order read voltages (Vread_R2, Vread_R3, etc.), repeating the minimum write-to-read time interval and all-zero data mode process at each level until a stable read voltage that meets the bit error tolerance is found. This method, through voltage-bit error coordinated regulation, compensates for the nonlinear mismatch caused by threshold voltage drift and eliminates timing and data interference through the minimum write-to-read time interval and all-zero data mode test conditions. Ultimately, it achieves precise voltage matching adaptively to the aging state, significantly reducing the bit error rate and extending device lifespan.

[0080] The phase-change memory provided by the present invention will be described below. The phase-change memory described below and the adaptive control method of the phase-change memory described above can be referred to in correspondence.

[0081] Please refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of a phase-change memory provided in an embodiment of the present invention. A phase-change memory 900 includes at least one storage array 910, a data writing module 920, a data reading module 930, a bit error analysis module 940, and a voltage adjustment module 950.

[0082] Optionally, the storage array 910 includes several storage cells.

[0083] Optionally, the data writing module 920 is used for:

[0084] Write all-zero data to the storage cell within the minimum write-to-read interval.

[0085] Optionally, the data reading module 930 is used for:

[0086] A read operation is performed on the storage unit that has been written in the all-zero data mode to obtain the detection data.

[0087] Optionally, the bit error analysis module 940 is used for:

[0088] Based on the detection data, obtain the bit error rate index of at least one storage array.

[0089] Optionally, the voltage regulation module 950 is used for:

[0090] Based on the comparison result between the bit error rate index and the preset threshold, a target voltage level is selected from the pre-configured voltage level set to adjust the read voltage of the storage unit to the corresponding read voltage level.

[0091] Optionally, the minimum write-to-read interval refers to the shortest allowed time interval from the end of a write operation to the start of a read operation.

[0092] Optionally, the all-zero data mode is a mode in which a continuous sequence of logical zero values ​​is written to all the tested memory cells.

[0093] Optionally, the bit error rate metrics include the bit error rate and the fault bit count. The bit error analysis module 940 is also used for:

[0094] The bit error rate is determined by the ratio of the number of erroneous bits read in the reset state to the total number of bits.

[0095] and / or

[0096] The number of memory cells in at least one memory array that exceed a preset tolerance voltage range is counted to obtain the fault bit count.

[0097] Optionally, the voltage regulation module 950 is also used for:

[0098] When the bit error rate exceeds a preset threshold, the read voltage level of the current storage unit is increased to the target voltage level in the order of the voltage level set.

[0099] Each time the read voltage level of the storage unit is increased, the operation of obtaining detection data is repeated until the bit error rate index is compared with the preset threshold, until the bit error rate index is lower than the preset threshold.

[0100] When the bit error rate is lower than a preset threshold

[0101] The read voltage level of the storage unit is within a preset safe operating range.

[0102] Optionally, the voltage regulation module 950 is also used for:

[0103] Start adjusting from the initial voltage level in the voltage level set;

[0104] Based on the durability level range of the phase change memory's cumulative erase / write cycles, select the corresponding voltage level from the voltage level set to adjust the read voltage of the memory cell.

[0105] Furthermore, after each switch of the read voltage of the storage unit to a new voltage level, the read voltage of the storage unit is kept at the new voltage level for at least one detection cycle.

[0106] Optionally, the voltage regulation module 950 is also used for:

[0107] After each switch of the read voltage of the storage unit to a new voltage level, the operation of obtaining the bit error rate is repeated.

[0108] If the bit error rate indicator still exceeds the preset threshold, the read voltage of the storage unit is switched to the next voltage level, and the bit error rate is obtained.

[0109] Optionally, the frequency of the detection operation is determined based on any of the following factors:

[0110] The durability class range of the phase-change memory based on the cumulative number of erase / write cycles;

[0111] The continuous usage time of the current voltage level;

[0112] The growth rate of the bit error rate metric relative to historical test results.

[0113] Optionally, the voltage level set includes a first voltage level to a sixth voltage level arranged in ascending order, with each voltage level corresponding to a pre-configured reading voltage value and durability level range.

[0114] Optionally, the voltage regulation module 950 is also used for:

[0115] If the bit error rate (BER) of the current voltage level of the storage cell exceeds the preset threshold, the storage cell's read voltage is sequentially switched to the read voltage of the next higher voltage level. After each switch, the BER is verified to ensure that it is below the preset threshold and within the preset safe operating range, until the conditions are met or all voltage levels in the voltage level set have been traversed.

[0116] It should be noted that the phase-change memory provided in this embodiment of the invention can implement all the method steps implemented in the above method embodiment and achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.

[0117] Figure 10 This is a schematic diagram of the structure of the electronic device provided in the embodiment of the present invention, such as... Figure 10 As shown, the electronic device may include a processor 1010, a communications interface 1020, a memory 1030, and a communication bus 1040, wherein the processor 1010, the communications interface 1020, and the memory 1030 communicate with each other via the communication bus 1040. The processor 1010 can call logic instructions in the memory 1030 to execute the adaptive control method of the phase-change memory.

[0118] Furthermore, the logical instructions in the aforementioned memory 1030 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to execute the adaptive control method of the phase change memory provided by the above methods.

[0120] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the adaptive control methods of the phase-change memories provided above.

[0121] The present invention provides an electronic device, a computer program product, and a processor-readable storage medium, wherein the computer program stored thereon enables the processor to implement all the method steps implemented in the above method embodiments and achieve the same technical effect. Here, the parts that are the same as those in the method embodiments and the beneficial effects will not be described in detail.

[0122] The phase-change memory embodiments described above are merely illustrative examples; the units may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any inventive effort.

[0123] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adaptive control method for a phase-change memory, wherein the phase-change memory includes at least one memory array, the memory array including a plurality of memory cells, characterized in that, include: Write an all-zero data pattern to the storage unit within the minimum write-to-read interval; A read operation is performed on the storage unit in the write all-zero data mode to obtain the detection data; Based on the detection data, the bit error rate index of the at least one storage array is obtained, wherein the bit error rate index includes bit error rate and fault bit count; Based on the comparison result between the bit error rate index and the preset threshold, a target voltage level is selected from the pre-configured voltage level set to adjust the read voltage of the storage unit to the corresponding read voltage level.

2. The adaptive control method for phase-change memory according to claim 1, characterized in that, The step of obtaining the bit error rate metric for the at least one storage array includes: The bit error rate is determined by the ratio of the number of erroneous bits read in the reset state to the total number of bits. And / or, The number of memory cells in at least one memory array that exceed a preset tolerance voltage range is counted to obtain a fault bit count.

3. The adaptive control method for phase-change memory according to claim 1, characterized in that, The step of selecting a target voltage level from a pre-configured set of voltage levels to adjust the read voltage of the storage unit to the corresponding read voltage level includes: When the bit error rate exceeds a preset threshold, the read voltage level of the current storage unit is increased to the target voltage level in the order of the voltage level set. Each time the read voltage level of the storage unit is increased, the operation of obtaining detection data is repeated until the bit error rate index is compared with a preset threshold, until the bit error rate index is lower than the preset threshold: When the bit error rate is lower than a preset threshold, the read voltage level of the storage unit is within a preset safe operating range.

4. The adaptive control method for phase-change memory according to claim 1, characterized in that, The step of selecting a target voltage level from a pre-configured set of voltage levels to adjust the read voltage of the storage unit to the corresponding read voltage level includes: Start adjusting from the initial voltage level in the voltage level set; Based on the durability level range of the phase change memory's cumulative erase / write cycles, select the corresponding voltage level from the voltage level set to adjust the read voltage of the memory cell; Furthermore, after each switch of the read voltage of the storage unit to a new voltage level, the read voltage of the storage unit is kept at the new voltage level for at least one detection cycle.

5. The adaptive control method for phase-change memory according to claim 4, characterized in that, The method further includes: After each switch of the read voltage of the storage unit to a new voltage level, the operation of obtaining the bit error rate is repeated. If the bit error rate indicator still exceeds the preset threshold, the read voltage of the storage unit is switched to the next voltage level, and the bit error rate is obtained.

6. The adaptive control method for phase-change memory according to claim 5, characterized in that, The frequency of the operation to obtain the bit error rate is determined based on any of the following factors: The durability class range of the phase-change memory based on the cumulative number of erase / write cycles; The continuous usage time of the current voltage level; The growth rate of the bit error rate metric relative to historical test results.

7. The adaptive control method for phase-change memory according to claim 1, characterized in that, The voltage level set includes the first to sixth voltage levels arranged in ascending order, with each voltage level corresponding to a pre-configured reading voltage value and durability level range; The method further includes: If the bit error rate index corresponding to the current voltage level of the storage cell read voltage exceeds a preset threshold, the read voltage of the storage cell is switched sequentially to the read voltage corresponding to the next higher voltage level. After each switch of the read voltage of the storage unit to the next higher voltage level, verify whether the bit error rate indicator simultaneously meets the conditions of being below a preset threshold and within a preset safe operating range, until the conditions are met or all voltage levels in the voltage level set have been traversed.

8. A phase-change memory, characterized in that, include: At least one storage array, each storage array comprising a plurality of storage units; The data writing module is used to write all-zero data to the storage unit within the minimum write-to-read time interval; The data reading module is used to perform a reading operation on the all-zero data mode to obtain detection data; The bit error rate analysis module is used to obtain the bit error rate index of the at least one storage array based on the detection data, wherein the bit error rate index includes bit error rate and fault bit count; The voltage adjustment module is used to select a target voltage level from a pre-configured voltage level set based on the comparison result between the bit error rate index and a preset threshold, so as to adjust the read voltage of the storage unit to the corresponding read voltage level.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the adaptive control method for phase-change memory as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the adaptive control method for phase-change memory as described in any one of claims 1 to 7.

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