Semiconductor structure and forming method thereof
By forming a groove structure on the substrate and forming a capacitance structure of multi-layer electrodes and dielectric layers on its side walls and bottoms, the problem of capacitance density improvement in the prior art is solved, and efficient and low-cost capacitance density improvement is achieved.
Patent Information
- Application Number
- CN202411916509.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-03-25
AI Technical Summary
The prior art is difficult to effectively improve the capacitance density of capacitors, especially when maintaining high performance and miniaturized packaging.
By forming a groove structure on the substrate and forming a capacitive structure on the groove side wall and bottom surface, including a multilayer electrode layer and a dielectric layer, the effective area of the capacitive structure is increased by using the larger surface area of the groove side wall and bottom.
The effective area of the capacitance structure is significantly increased on the same substrate, the capacitance density is improved, and the process is simple and the cost is low, making it suitable for industrial applications.
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Figure CN119698007A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of microelectronics technology, the integration of integrated circuits continues to increase and the package size continues to shrink. This requires that the passive devices integrated in the package be minimized as much as possible while ensuring high performance.
[0003] Capacitors in passive devices are indispensable in most logic, radio frequency, and storage integrated circuits. Reducing the area occupied by capacitors is also an effort to improve the integration of integrated circuits and increase the number of dies. Nowadays, metal-insulator-metal capacitors (MIM) and metal-oxide-metal capacitors (MOM) are mostly used in circuit design. Among them, compared with metal-insulator-metal capacitors, metal-oxide-metal capacitors have good capacitance matching, process compatibility and lower cost, so they are widely used in analog circuits and digital integrated circuits.
[0004] Improving the capacitance density of capacitors is an ongoing issue that needs to be addressed. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the capacitance density of the capacitor.
[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a liner layer located on the substrate; a plurality of grooves located in the liner layer, at least the side wall surfaces of the grooves are recessed into the liner layer; a capacitor structure located on the side wall surfaces and bottom surfaces of the plurality of grooves, the capacitor structure comprising a plurality of electrode layers and a first dielectric layer located between two adjacent electrode layers.
[0007] Optionally, the method further includes: a bottom surface of the groove is recessed into the lining layer.
[0008] Optionally, the capacitor structure is also located on the liner layer between the grooves.
[0009] Optionally, a top surface of the capacitor structure in the groove is lower than or flush with a top surface of the capacitor structure on the liner layer between the grooves.
[0010] Optionally, the material of the liner layer includes dielectric material, semiconductor material, metal material or metal nitride material; when the material of the liner layer includes semiconductor material, metal material or metal nitride material, the semiconductor structure also includes: a second dielectric layer located between the capacitor structure and the liner layer.
[0011] Optionally, the plurality of electrode layers include: a first electrode layer located on the side wall surface and the bottom surface of the groove, a second electrode layer located on the top layer, and at least one third electrode layer located between the first electrode layer and the second electrode layer, and the second electrode layer located on the top layer fills the groove.
[0012] Optionally, the projection shape of the groove on the substrate includes a circle, an ellipse or a polygon, and the polygon includes a quadrilateral, a pentagon, a hexagon or an octagon.
[0013] Optionally, the cross-sectional shape of the groove in a direction perpendicular to the substrate surface includes a semicircle, a quasi-semicircle, a semicircle with a flat bottom, or a quasi-semicircle.
[0014] Optionally, it also includes: a plurality of conductive structures electrically connected to the plurality of electrode layers respectively, the conductive structures corresponding to two adjacent electrode layers being electrically connected to a first potential and a second potential respectively, the first potential and the second potential being opposite; a third dielectric layer located on the capacitor structure, the plurality of conductive structures being located in the third dielectric layer.
[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a liner layer and a plurality of grooves located in the liner layer on the substrate, wherein the side wall surfaces and the bottom surfaces of the grooves are recessed into the liner layer; forming a capacitor structure on the side wall surfaces and the bottom surfaces of the plurality of grooves, wherein the capacitor structure includes a plurality of electrode layers and a first dielectric layer located between two adjacent electrode layers.
[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0017] In the semiconductor structure of the technical solution of the present invention, the capacitor structure is located on the side wall surface and the bottom surface of the groove, and at least the side wall surface of the groove is recessed into the liner layer. Therefore, the side wall surface and the bottom surface of the groove can obtain a larger surface area, thereby increasing the effective area of the capacitor structure on a substrate of the same area, thereby improving the capacitor density.
[0018] Furthermore, the capacitor structure is also located on the liner layer between the grooves, which can further increase the effective area of the capacitor structure and improve the capacitor density.
[0019] The formation method of the technical solution of the present invention effectively utilizes the area of the side wall surface and the bottom surface of the groove, as well as the surface area of the liner layer between adjacent grooves, increases the effective area of the capacitor structure, and improves the capacitor density; in addition, the formation method has a simple process and low cost, which is conducive to industrial application.
[0020] Furthermore, when the material of the pad layer includes semiconductor material, metal material or metal nitride material, the semiconductor structure also includes: a second dielectric layer located between the capacitor structure and the pad layer, then the first electrode layer, the pad layer and the second dielectric layer can also constitute a capacitor structure, further increasing the effective area of the capacitor structure and improving the capacitor density. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figures 1 to 15 is a structural schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention;
[0022] Fig.16 It is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION
[0023] As described in the background art, improving the capacitance density of capacitors is a problem that needs to be solved continuously.
[0024] Specifically, capacitors are commonly used as passive devices and are widely used in integrated circuits. The capacitance value depends on the relative area of the plates, the thickness of the dielectric, and the dielectric constant of the dielectric. In order to increase the capacitance density, the commonly used methods are:
[0025] First, a material with a high dielectric constant is used as the dielectric layer. However, there are relatively few high dielectric constant materials available and their compatibility with the process is relatively poor.
[0026] Second, the capacitance density can be increased by reducing the thickness of the dielectric layer and shortening the plate spacing, but this will result in a decrease in the breakdown voltage of the capacitor.
[0027] Third, under the same projected area, the effective area of the electrode plate is increased, thereby increasing the capacitance density, such as using a three-dimensional structure, etching the electrode plate to form a groove structure, a micro-porous structure, etc. to increase the effective area of the capacitor electrode plate. However, there are still some problems, such as the limited increase in capacitance density of the three-dimensional capacitor structure; etching to form grooves will cause plasma accumulation on the electrode plate, resulting in a thinner dielectric layer that is easily broken down, reducing the breakdown voltage of the capacitor; the flatness of the dielectric layer of the micro-porous structure is low, the process cost is high, and the integration difficulty is greater.
[0028] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, by forming a capacitor structure on the side wall surface and the bottom surface of the groove, at least the side wall surface of the groove is recessed into the liner layer, so that the side wall surface and the bottom surface of the groove can obtain a larger surface area, thereby increasing the effective area of the capacitor structure on a substrate of the same area, thereby improving the capacitor density.
[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0030] Figures 1 to 15 It is a structural schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention.
[0031] Please refer to Figure 1 , providing a substrate 100 ; forming a liner layer 101 on the substrate 100 ; and forming a hard mask layer 102 on the liner layer 101 .
[0032] In this embodiment, the substrate 100 is made of silicon.
[0033] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0034] In this embodiment, the material of the liner layer 101 includes a dielectric material, and the material of the liner layer 101 includes silicon dioxide (SiO2) or a Low K material, and the Low K is a dielectric material with a dielectric constant less than 3.7. The process of forming the liner layer 101 includes a chemical vapor deposition process.
[0035] In other embodiments, the material of the liner layer includes semiconductor material, metal material or metal nitride material; the semiconductor material includes silicon (Si); the metal material includes nickel (Ni), aluminum (Al), titanium (Ti), tantalum (Ta), etc.; the metal nitride material includes titanium nitride (TiN) or tantalum nitride (TaN), etc. In this embodiment, the material of the liner layer 101 includes a dielectric material, and the material of the liner layer 101 includes silicon dioxide.
[0036] When the material of the liner layer includes a semiconductor material, a metal material or a metal nitride material, the process of forming the liner layer 101 includes a physical vapor deposition process.
[0037] In this embodiment, the thickness of the cushion layer 101 is in the range of 0.1 mm to 0.5 mm.
[0038] In this embodiment, the material of the hard mask layer 102 is different from the material of the liner layer 101 .
[0039] The material of the hard mask layer 102 includes amorphous carbon or silicon nitride (SiN).
[0040] Please refer to Figure 2 , performing a first etching on the hard mask layer 102 and the liner layer 101 to form a plurality of initial grooves 103 in the liner layer 101 .
[0041] In this embodiment, the first etching of the hard mask layer 102 and the pad layer 101 may include: forming a patterned mask layer (not shown) on the hard mask layer 102; etching the hard mask layer 102 and the pad layer 101 using the patterned mask layer as a mask to form a plurality of initial grooves 103 in the pad layer 101.
[0042] In this embodiment, the material of the patterned mask layer may include photoresist. The hard mask layer 102 is used to transfer the pattern of the patterned mask layer to avoid deformation of the pattern of the patterned mask layer when the photoresist is naturally consumed during the etching process, so that the pattern of the patterned mask layer can be stably transferred to the liner layer 101.
[0043] In this embodiment, the process of etching the hard mask layer 102 and the liner layer 101 may include an anisotropic dry etching process. The dry etching process has anisotropy and can form an initial groove 103 with good sidewall morphology and good dimensional accuracy.
[0044] Please refer to Figure 3 , a second etching is performed on the sidewall surface and the bottom surface of the initial groove 103 to form a plurality of grooves 104 located in the liner layer 101 , and the sidewall surface of the groove 104 is recessed into the liner layer 101 .
[0045] In this embodiment, the process of performing the second etching on the sidewall surface and the bottom surface of the initial groove 103 includes a wet etching process or an isotropic dry etching process.
[0046] In this embodiment, the second etching process may include a wet etching process. The isotropy of the wet etching process allows the sidewalls and bottom of the groove 104 to form an arc shape, forming a groove 104 whose sidewall surface and bottom surface are recessed into the liner layer 101. The wet etching process can release the plasma on the surface of the initial groove 103 during the dry etching process of the first etching, thereby reducing the damage of the plasma to the first dielectric layer formed subsequently, and improving the reliability of the capacitor.
[0047] In this embodiment, the aspect ratio of the groove 104 is in a range of 2:1 to 3.6:1. The depth of the groove 104 is smaller than the depth of the liner layer 101 .
[0048] In this embodiment, the projection shape of the groove 104 on the substrate 100 includes a circle, an ellipse or a polygon, and the polygon includes a quadrilateral, a pentagon, a hexagon or an octagon.
[0049] In this embodiment, the projection shape of the groove 104 on the substrate 100 includes a circle.
[0050] In this embodiment, the cross-sectional shape of the groove 104 in a direction perpendicular to the surface of the substrate 100 includes a semicircle, a quasi-semicircle, a semicircle with a flat bottom, or a quasi-semicircle.
[0051] In this embodiment, the cross-sectional shape of the groove 104 in a direction perpendicular to the surface of the substrate 100 includes a semicircular shape. The shape of the groove 104 includes a sphere or a semi-sphere.
[0052] In this embodiment, the side wall surface and the bottom surface of the groove 104 are arc-shaped and recessed into the liner layer 101, which is conducive to the deposition of a thinner electrode layer and a first dielectric layer, forming a capacitor structure with high flatness and density, thereby improving the reliability of the capacitor structure and the stability of the capacitance value.
[0053] In other embodiments, only the sidewall of the groove is recessed into the liner layer, and the bottom of the groove is a plane.
[0054] In this embodiment, the plurality of grooves 104 are distributed in an array on the substrate 100. The plurality of grooves 104 distributed in an array can effectively utilize the area of the substrate 100, so that the capacitor structure obtains the maximum capacitance density.
[0055] Please refer to Figure 4 After forming the groove 104 , the hard mask layer 102 is removed.
[0056] In this embodiment, the process of removing the hard mask layer 102 may include a wet etching process. The material of the hard mask layer 102 is different from that of the liner layer 101 , so the process of removing the hard mask layer 102 causes less damage to the liner layer 101 .
[0057] Next, a capacitor structure is formed on the sidewall surfaces and bottom surfaces of the grooves 104 . The capacitor structure may include a plurality of electrode layers and a first dielectric layer located between two adjacent electrode layers.
[0058] In this embodiment, the capacitor structure is also located on the liner layer 101 .
[0059] In this embodiment, the plurality of electrode layers may include: a first electrode layer located on the side wall surface and the bottom surface of the groove 104, a second electrode layer located on the top layer, and at least one third electrode layer located between the first electrode layer and the second electrode layer, wherein the second electrode layer located on the top layer fills the groove.
[0060] Please refer to the formation process of the capacitor structure Figures 5 to 10 .
[0061] Please refer to Figure 5 A first electrode layer 105 is formed on the sidewall surfaces and bottom surfaces of the grooves 104 and the liner layer 101 .
[0062] In this embodiment, the material of the first electrode layer 105 may include metal or metal nitride, the metal may include nickel (Ni), aluminum (Al), copper (Cu), titanium (Ti) or tantalum (Ta), etc., and the metal nitride may include titanium nitride (TiN) or tantalum nitride (TaN), etc.
[0063] In this embodiment, the process of forming the first electrode layer 105 may include a physical vapor deposition process.
[0064] In this embodiment, the thickness of the first electrode layer 105 is in the range of 0.1 mm to 0.5 mm.
[0065] In this embodiment, the material of the liner layer 101 may include a dielectric material, and the first electrode layer 105 is directly formed on the surface of the liner layer 101 .
[0066] In other embodiments, when the material of the pad layer includes semiconductor material, metal material or metal nitride material, a second dielectric layer may be formed on the surface of the pad layer before forming the first electrode layer, and the first electrode layer is formed on the surface of the second dielectric layer.
[0067] In this embodiment, the first electrode layer, the liner layer and the second dielectric layer can also form a capacitor structure, which further increases the effective area of the capacitor structure and improves the capacitor density.
[0068] In this embodiment, the material of the second dielectric layer may include a dielectric material, and the dielectric material may include a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.
[0069] In this embodiment, the material of the second dielectric layer may include silicon oxide. The material of the second dielectric layer may be the same as that of the first dielectric layer.
[0070] In other embodiments, the material of the second dielectric layer may be different from the material of the first dielectric layer.
[0071] Next, several first dielectric layers and at least one third electrode layer are formed on the surface of the first electrode layer 105. For the process, please refer to Figures 6 to 10 .
[0072] In this embodiment, only one third electrode layer is illustrated, and the plurality of first dielectric layers may include a first first dielectric layer located between the first electrode layer 105 and the third electrode layer, and a second first dielectric layer located between the third electrode layer and the second electrode layer.
[0073] In other embodiments, the third electrode layer has multiple layers.
[0074] In this embodiment, the thicknesses of the plurality of first dielectric layers are the same, and the materials of the plurality of first dielectric layers are the same.
[0075] In this embodiment, the material of the first dielectric layer is the same as that of the liner layer.
[0076] In this embodiment, the material of the first dielectric layer may include silicon dioxide (SiO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), etc.
[0077] In this embodiment, the material of the first dielectric layer may include silicon dioxide (SiO2).
[0078] In other embodiments, the material of the first dielectric layer is different from the material of the liner layer.
[0079] In other embodiments, the thicknesses of several layers of the first dielectric layers may not be completely the same; and the materials of several layers of the first dielectric layers may not be completely the same.
[0080] Please refer to Figure 6 , a first dielectric layer 106 may be formed on the surface of the first electrode layer 105 .
[0081] In this embodiment, the process of forming the first dielectric layer 106 may include a chemical vapor deposition process or an atomic layer deposition process.
[0082] In this embodiment, the process of forming the first first dielectric layer 106 may include an atomic layer deposition process, which can form a first first dielectric layer 106 with a dense structure and uniform thickness, so that the first first dielectric layer 106 is not easily broken down, thereby improving the reliability of the capacitor structure.
[0083] Please refer to Figure 7 A third electrode layer 107 is formed on the surface of the first dielectric layer 106 .
[0084] In this embodiment, the process of forming the third electrode layer 107 may include a physical vapor deposition process.
[0085] In this embodiment, the material of the third electrode layer 107 may be the same as that of the first electrode layer 105 .
[0086] In this embodiment, the material of the third electrode layer 107 may include metal or metal nitride, the metal may include nickel (Ni), aluminum (Al), copper (Cu), titanium (Ti) or tantalum (Ta), etc., and the metal nitride may include titanium nitride (TiN) or tantalum nitride (TaN), etc.
[0087] In other embodiments, the material of the third electrode layer may be different from the material of the first electrode layer.
[0088] In this embodiment, the thickness of the third electrode layer 107 is the same as the thickness of the first electrode layer 105 , so that the capacitance value can be well calculated.
[0089] In other embodiments, the thickness of the third electrode layer may be different from the thickness of the first electrode layer.
[0090] Please refer to Figure 8 , a second first dielectric layer 108 is formed on the surface of the third electrode layer 107 .
[0091] In this embodiment, the process of forming the second first dielectric layer 108 may include a chemical vapor deposition process or an atomic layer deposition process.
[0092] In this embodiment, the process of forming the second-layer first dielectric layer 108 may include an atomic layer deposition process, which can form a second-layer first dielectric layer 108 with a dense structure and uniform thickness, so that the second-layer first dielectric layer 108 is not easily broken down, thereby improving the reliability of the capacitor structure.
[0093] Please refer to Fig. 9 and Fig.10 , Fig.10 for Fig. 9 In the cross-sectional structural diagram along the section line AA1 , a second electrode layer 109 is formed on the surface of the second first dielectric layer 108 , and the second electrode layer 109 fills the groove 104 .
[0094] In this embodiment, the process of forming the second electrode layer 109 may include a physical vapor deposition process.
[0095] In this embodiment, the material of the second electrode layer 109 may be the same as the material of the third electrode layer 107 and the material of the first electrode layer 105 .
[0096] In this embodiment, the material of the second electrode layer 109 may include metal or metal nitride, the metal may include nickel (Ni), aluminum (Al), copper (Cu), titanium (Ti) or tantalum (Ta), etc., and the metal nitride may include titanium nitride (TiN) or tantalum nitride (TaN), etc.
[0097] In other embodiments, the material of the second electrode layer may be different from the material of the third electrode layer and the material of the first electrode layer.
[0098] In this embodiment, the thickness of the second electrode layer 109 is greater than the thickness of the third electrode layer 107 .
[0099] In the above embodiment, by making the thickness of the second electrode layer 109 greater than the thickness of the first electrode layer 105 , the second electrode layer 109 can fill the groove 104 , thereby reducing the possibility of forming defective devices and improving the yield of formed devices.
[0100] In summary, in a specific embodiment, the formed capacitor structure may include: a first electrode layer 105, a third electrode layer 107, a second electrode layer 109, and a first first dielectric layer 106 located between the first electrode layer 105 and the third electrode layer 107, and a second first dielectric layer 108 located between the third electrode layer 107 and the second electrode layer 109. The capacitor structure is located on the side wall surface and the bottom surface of the groove 104, and the side wall surface and the bottom surface of the groove 104 are recessed into the liner layer 101, so the side wall surface and the bottom surface of the groove 104 can obtain a larger surface area, so that the effective area of the capacitor structure can be increased on a substrate of the same area, and the capacitance density can be improved.
[0101] Furthermore, the capacitor structure is also located on the liner layer 101 between the grooves 104 , which can further increase the effective area of the capacitor structure and improve the capacitor density.
[0102] In this embodiment, the top surface of the capacitor structure in the groove 104 is lower than or flush with the top surface of the capacitor structure on the liner layer 101 .
[0103] In this embodiment, the top surface of the capacitor structure in the groove 104 is flush with the top surface of the capacitor structure on the liner layer 101 .
[0104] Please refer to Fig.11 , partially etching the second electrode layer 109 and the second first dielectric layer 108 , forming a first opening 110 in the second electrode layer 109 and the second first dielectric layer 108 on the liner layer 101 , wherein the first opening 110 exposes the surface of the third electrode layer 107 .
[0105] In this embodiment, the process of etching a portion of the second electrode layer 109 and the second first dielectric layer 108 may include a dry etching process.
[0106] Please refer to Fig.12 , partially etching the second electrode layer 109, the second first dielectric layer 108, the third electrode layer 107 and the first first dielectric layer 106, forming a second opening 111 in the second electrode layer 109, the second first dielectric layer 108, the third electrode layer 107 and the first first dielectric layer 106 on the pad layer 101, and the second opening 111 exposes the surface of the first electrode layer 105.
[0107] In this embodiment, the process of etching a portion of the second electrode layer 109 , the second first dielectric layer 108 , the third electrode layer 107 and the first first dielectric layer 106 may include a dry etching process.
[0108] Please refer to Fig.13 A third dielectric layer 112 is formed in the first opening 110 , in the second opening 111 and on the capacitor structure.
[0109] In this embodiment, the material of the third dielectric layer 112 may include a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.
[0110] In this embodiment, the process of forming the third dielectric layer 112 may include a chemical vapor deposition process.
[0111] Please refer to Fig.14 A first groove 113 is formed in the third dielectric layer 112, and the first groove 113 exposes a portion of the surface of the second electrode layer 109; a second groove 114 is formed in the third dielectric layer 112 and in the first opening 110, and the second groove 114 exposes a portion of the surface of the third electrode layer 107; a third groove 115 is formed in the third dielectric layer 112 and in the second opening 111, and the third groove 115 exposes a portion of the surface of the first electrode layer 105.
[0112] In this embodiment, the first trench 113 , the second trench 114 , and the third trench 115 are formed simultaneously.
[0113] In this embodiment, the process of forming the first trench 113 , the second trench 114 , and the third trench 115 may include a dry etching process.
[0114] Please refer to Fig.15 A first conductive structure 116 is formed in the first groove 113, and the first conductive structure 116 is electrically connected to the second electrode layer 109; a second conductive structure 117 is formed in the second groove 114, and the second conductive structure 117 is electrically connected to the third electrode layer 107; a third conductive structure 118 is formed in the third groove 115, and the third conductive structure 118 is electrically connected to the first electrode layer 105.
[0115] In this embodiment, the first conductive structure 116 , the second conductive structure 117 and the third conductive structure 118 are formed simultaneously, and the first conductive structure 116 , the second conductive structure 117 and the third conductive structure 118 are made of the same material.
[0116] In this embodiment, the materials of the first conductive structure 116, the second conductive structure 117 and the third conductive structure 118 include metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
[0117] In this embodiment, the method for forming the first conductive structure 116, the second conductive structure 117 and the third conductive structure 118 may include: forming a conductive material layer in the first trench 113, in the second trench 114, in the third trench 115 and on the third dielectric layer 112; planarizing the conductive material layer until the surface of the third dielectric layer 112 is exposed, forming the first conductive structure 116 in the first trench 113, forming the second conductive structure 117 in the second trench 114, and forming the third conductive structure 118 in the third trench 115.
[0118] In this embodiment, the process of forming the conductive material layer may include an electroplating process.
[0119] In this embodiment, several conductive structures are electrically connected to several layers of electrode layers, respectively, and the conductive structures corresponding to two adjacent electrode layers are electrically connected to the first potential and the second potential, respectively, and the conductive structures corresponding to two separated electrode layers are electrically connected to the same potential, and the first potential and the second potential are opposite.
[0120] In this embodiment, the plurality of conductive structures may include a first conductive structure 116, a second conductive structure 117 and a third conductive structure 118. The first conductive structure 116 and the second conductive structure 117 corresponding to two adjacent electrode layers are electrically connected to the first potential and the second potential, respectively, and the first conductive structure 116 and the third conductive structure 118 corresponding to two separated electrode layers are electrically connected to the first potential.
[0121] In this embodiment, the first potential and the second potential are opposite to each other, so that an electric field is loaded on two adjacent electrode layers to form a capacitor.
[0122] In the above embodiment, the semiconductor structure formed by the method effectively utilizes the side wall surface and the bottom surface of the groove 104, and the surface area of the liner layer 101 between adjacent grooves 104, thereby increasing the effective area of the capacitor structure and improving the capacitor density; in addition, the formation method has a simple process and low cost, which is conducive to industrial application.
[0123] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.15 , which may include:
[0124] Substrate 100;
[0125] A liner layer 101 located on the substrate 100;
[0126] A plurality of grooves 104 located in the liner layer 101, wherein at least the sidewall surfaces of the grooves 104 are recessed into the liner layer 101;
[0127] The capacitor structure is located on the sidewall surfaces and bottom surfaces of the grooves 104, and the capacitor structure includes a plurality of electrode layers and a first dielectric layer located between two adjacent electrode layers.
[0128] In this embodiment, the semiconductor structure may further include: a bottom surface of the groove 104 is recessed into the liner layer 101 .
[0129] In this embodiment, the capacitor structure may also be located on the liner layer 101 .
[0130] In this embodiment, the top surface of the capacitor structure in the groove 104 is lower than or flush with the top surface of the capacitor structure on the liner layer 101 .
[0131] In this embodiment, the material of the liner layer 101 may include any one of a dielectric material, a semiconductor material, a metal material or a metal nitride material.
[0132] In one embodiment, when the material of the liner layer 101 includes any one of a semiconductor material, a metal material or a metal nitride material, the semiconductor structure may further include: a second dielectric layer located between the capacitor structure and the liner layer 101 .
[0133] In this embodiment, the several layers of electrode layers may include: a first electrode layer 105 located on the side wall surface and the bottom surface of the groove 104, a second electrode layer 109 located on the top layer, and at least one third electrode layer 107 located between the first electrode layer 105 and the second electrode layer 109, and the second electrode layer 109 located on the top layer fills the groove 104.
[0134] In this embodiment, the projection shape of the groove 104 on the substrate 100 may include a circle, an ellipse or a polygon, and the polygon may include a quadrilateral, a pentagon, a hexagon or an octagon.
[0135] In this embodiment, the cross-sectional shape of the groove 104 in the direction perpendicular to the surface of the substrate 100 may include a semicircle, a quasi-semicircle, a semicircle with a flat bottom, or a quasi-semicircle.
[0136] In this embodiment, the plurality of grooves 104 are distributed in an array.
[0137] In this embodiment, the semiconductor structure may further include: a plurality of conductive structures electrically connected to the plurality of electrode layers respectively, the conductive structures corresponding to two adjacent electrode layers being electrically connected to a first potential and a second potential respectively, the first potential and the second potential being opposite; a third dielectric layer 112 located on the capacitor structure, and the plurality of conductive structures being located within the third dielectric layer 112.
[0138] Fig.16 It is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention.
[0139] Please refer to Fig.16 , Fig.16 and Fig.10 The difference is that the projection shape of the groove on the surface of the substrate 100 is a regular hexagon.
[0140] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; a liner layer located on the substrate; A plurality of grooves located in the liner layer, wherein the sidewall surfaces of the grooves are recessed into the liner layer; A capacitor structure is located on the sidewall surfaces and bottom surfaces of the grooves, and the capacitor structure includes a plurality of electrode layers and a first dielectric layer located between two adjacent electrode layers.
2. The semiconductor structure according to claim 1, wherein: Also includes: The bottom surface of the groove is recessed into the lining layer.
3. The semiconductor structure according to claim 1, wherein: The capacitor structure is also located on the liner layer between the grooves.
4. The semiconductor structure according to claim 3, characterized in that A top surface of the capacitor structure in the groove is lower than or flush with a top surface of the capacitor structure on the liner layer between the grooves.
5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a second dielectric layer located between the capacitor structure and the liner layer.
6. The semiconductor structure according to claim 1, wherein: The electrode layers include: a first electrode layer located on the sidewall surface and the bottom surface of the groove, a second electrode layer located on the top layer, and at least one third electrode layer located between the first electrode layer and the second electrode layer. The second electrode layer located on the top layer fills the groove.
7. The semiconductor structure according to claim 1, wherein: The projection shape of the groove on the substrate includes a circle, an ellipse or a polygon, and the polygon includes a quadrilateral, a pentagon, a hexagon or an octagon.
8. The semiconductor structure according to claim 1, wherein: The cross-sectional shape of the groove in a direction perpendicular to the substrate surface includes a semicircle, a quasi-semicircle, a semicircle with a flat bottom, or a quasi-semicircle.
9. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of conductive structures electrically connected to the plurality of electrode layers respectively, the conductive structures corresponding to two adjacent electrode layers being electrically connected to a first potential and a second potential respectively, the first potential and the second potential being opposite; a third dielectric layer located on the capacitor structure, the plurality of conductive structures being located in the third dielectric layer.
10. A method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: include: providing a substrate; forming a liner layer and a plurality of grooves in the liner layer on a substrate, wherein sidewall surfaces and bottom surfaces of the grooves are recessed into the liner layer; A capacitor structure is formed on the sidewall surfaces and bottom surfaces of the grooves. The capacitor structure includes a plurality of electrode layers and a first dielectric layer located between two adjacent electrode layers.