IGZO-FET device with suspended nanowire structure and preparation method thereof

Abstract

The present invention relates to the field of microelectronic manufacturing technology. The present invention discloses an IGZO-FET device with a suspended nanowire structure, wherein a gate dielectric layer, an IGZO channel layer, and a source and drain electrode layer are sequentially deposited on the surface of the suspended nanowire structure from the inside out, and the suspended electrode and the suspended nanowires connected thereto constitute the gate electrode of the CAA IGZO-FET device, and the suspended electrode is provided with an opening area for applying a gate voltage to the gate electrode formed by the suspended electrode connecting the suspended nanowires; or a buffer layer, an IGZO channel layer, a source and drain electrode layer, a gate dielectric layer, and a gate electrode layer are sequentially deposited on the surface of the suspended nanowire structure from the inside out to constitute a GAA IGZO-FET device. The high driving current and low subthreshold swing obtained by the present invention effectively improve the integration density of high-performance IGZO transistors, and are suitable for high-definition displays and high-density integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic manufacturing technology, and further to an IGZO-FET device with a suspended nanowire structure and a preparation method thereof, and in particular to a CAA or GAA IGZO-FET device structure and method thereof using suspended nanowires. Background Art

[0002] Thin-film transistors based on indium gallium zinc oxide (InGaZnO, IGZO) channels are widely used in high-definition display, flexible electronics, under-screen sensing, memory, and neuromorphic computing. The on-state drive current and subthreshold swing of IGZO thin-film transistors are important electrical performance parameters for their application in high-brightness flat-panel displays and logic electronics. As display technology tends to be high-definition, high-brightness, and flexible, and logic circuits require faster responses in the computing field, higher requirements are placed on the performance and size of the driving backplane IGZO transistors. However, flat-panel IGZO thin-film transistors (Thin Film Transistor, TFT) will exhibit more serious short channel effects when the channel length is reduced, resulting in increased leakage current and deteriorated switching characteristics. In addition, due to the two-dimensional layout, device scaling and integration density are restricted. IGZO TFTs have gradually become difficult to meet the application requirements of high-resolution displays or high-performance integrated circuits.

[0003] Nanowires (NWs) have many advantages over traditional transistor structures. The ultra-high specific surface area of ​​their one-dimensional structures shows unique potential in the process of semiconductor devices developing towards smaller size, high performance and low power consumption. The previous research results of this team are based on nanowires obtained by the "planar solid-liquid-solid" growth method, which have the advantages of planar or three-dimensional positioning, programmable morphology, controllable diameter and low cost, and can easily obtain a three-dimensional architecture based on nanowires.

[0004] Based on the above research results, the research team is currently working on exploring a channel-all-around (CAA) and gate-all-around (GAA) device with an ultra-short channel, better gate control capability, higher integration density, lower power consumption and better electrical stability to better serve the next generation of display technology and high-density three-dimensional integrated circuits. This is a technical challenge that the research team urgently needs to solve. Summary of the invention

[0005] The present application provides an IGZO-FET device with a suspended nanowire structure and a preparation method, which solves the technical problems in the prior art that IGZO thin-film transistors are prone to serious short channel effects when the channel length is reduced, resulting in increased leakage current and deteriorated switching characteristics, as well as restricted device scaling and integration density, and achieves the technical effects of high transistor drive current, fast device response and high integration density.

[0006] The present application provides a suspended nanowire structure, comprising a base layer arranged on a substrate, characterized in that it also comprises nanowires stacked in parallel and spaced apart perpendicular to the base layer, wherein both ends of the nanowires are respectively connected to suspended electrodes, and there is a gap between the middle part of the parallel and spaced-apart stacked nanowires and the base.

[0007] Preferably, the base layer is an alternating stacked structure of silicon oxide and silicon nitride, the parallel spaced stacked nanowires grow on the silicon nitride guide layer of the alternating stacked structure, and after the silicon oxide layer is etched, the gap is formed between the alternating stacked structure and the parallel spaced stacked nanowires, and the nanowires between the suspended electrodes at both ends constitute parallel stacked suspended nanowires.

[0008] The present invention also provides an IGZO-FET device with a suspended nanowire structure, which adopts the above-mentioned suspended nanowire structure, and is characterized in that the IGZO-FET device is a CAA IGZO-FET device, and a gate dielectric layer, an IGZO channel layer, and a source and drain electrode layer are sequentially deposited on the surface of the suspended nanowire structure from the inside to the outside, and the suspended electrode and the suspended nanowire connected thereto constitute the gate electrode of the CAA IGZO-FET device, and the suspended electrode is provided with an opening area for applying a gate voltage to the gate electrode formed by the suspended electrode connecting the suspended nanowire;

[0009] Or, the IGZO-FET device is a GAA IGZO-FET device, a buffer layer is deposited on the surface of the suspended nanowire structure, the suspended nanowire and the buffer layer constitute an inner core support, the buffer layer is sequentially deposited with an IGZO channel layer, a source and drain electrode layer, a gate dielectric layer and a gate electrode layer from the inside to the outside, and the gate dielectric layer on the surface of the source and drain electrode layer is removed to form an open area for applying source and drain voltages to the source and drain electrodes.

[0010] Preferably, there is an overlapping area between the source and drain electrode layers and the gate electrode layer of the GAA IGZO-FET device, and the IGZO conductive channel in the overlapping area is composed of the IGZO channel on the surface of the base layer, the IGZO channel on the side wall of the base layer and the IGZO channel on the substrate surface.

[0011] The present invention also discloses a method for preparing a suspended nanowire structure, which is characterized by comprising the following steps:

[0012] In the first step, a stacked structure of silicon oxide and silicon nitride is alternately deposited on a substrate using plasma enhanced chemical vapor deposition technology;

[0013] The second step is to expose the side structure of the silicon oxide and silicon nitride stack by using a reactive coupled plasma etching technique, and to etch the stack structure in a hot phosphoric acid solution to obtain a silicon nitride guide channel layer;

[0014] The third step is to use photolithography technology to locate the catalytic metal area at one end of the silicon nitride guide channel layer, and use thermal evaporation deposition technology to locate and deposit the metal film; using the planar solid-liquid-solid growth method, hydrogen plasma is used in the PECVD equipment to reduce the metal film into metal balls, which are then covered with precursors. In a vacuum and high temperature environment of 300°C to 350°C, the metal balls absorb the precursors along the etched silicon nitride guide channels to grow parallel nanowires;

[0015] The fourth step is to use high-precision photolithography technology to locate the nanowire suspended electrode area at both ends of the parallel nanowires, and pass the grown nanowire sample through a silicon oxide etchant to remove the native oxide layer on the surface of the nanowire; and use electron beam evaporation to deposit the nanowire suspended electrode to connect the two ends of the nanowire;

[0016] In the fifth step, the entire structure is finally immersed in a silicon oxide etching solution to etch the silicon oxide layer to form a parallel suspended nanowire structure separated from the silicon oxide and silicon nitride stack.

[0017] Preferably, the precursor is amorphous silicon or amorphous germanium, and the nanowires obtained by vacuum high temperature annealing are silicon nanowires or germanium nanowires.

[0018] Preferably, the suspended electrode is a platinum-gold metal stack material that is resistant to silicon oxide etching solution.

[0019] The present invention also discloses a method for preparing an IGZO-FET device with a suspended nanowire structure, which is applicable to the above-mentioned IGZO-FET device and is characterized in that the steps include:

[0020] First, a gate dielectric layer, an IGZO channel layer, and source and drain electrode layers are sequentially deposited on the suspended nanowire structure, and then the gate dielectric layer and the IGZO channel layer on the suspended electrode at both ends of the suspended nanowire are partially etched to form a CAA IGZO-FET device with an open area for applying a gate voltage;

[0021] Alternatively, a buffer layer is first deposited on the suspended nanowire structure, and then an IGZO channel layer, a source and drain electrode layer, a gate dielectric layer and a gate electrode layer are sequentially deposited on the surface of the buffer layer from the inside to the outside to obtain a GAA IGZO-FET device.

[0022] The present invention also discloses a method for preparing the CAA IGZO-FET device having a suspended nanowire structure, comprising:

[0023] In the first step, a gate dielectric layer and an IGZO channel layer are sequentially deposited on the surface of the suspended nanowire structure using the ALD technology. The gate dielectric layer and the IGZO layer do not need to be positioned and are deposited on the entire surface to wrap around the suspended nanowire structure.

[0024] In the second step, on the surface of the IGZO channel layer, the source and drain electrode layer regions are first positioned using high-precision photolithography technology, and the source and drain electrode layers are deposited using ALD technology, and then the source and drain electrodes outside the positioning region are stripped off to obtain a patterned source and drain electrode layer;

[0025] The third step is to use photolithography and etching technology to partially etch the gate dielectric layer and IGZO channel layer on the nanowire suspended electrode to form an opening area of ​​the CAA IGZO-FET device, so as to facilitate the application of gate voltage to the gate electrode formed by the nanowire suspended electrode connecting the suspended nanowire.

[0026] The present invention also discloses a method for preparing the above-mentioned GAA IGZO-FET device with a suspended nanowire structure, comprising:

[0027] In the first step, a buffer layer is first deposited on the entire surface of the suspended nanowire structure using ALD technology, wherein the suspended nanowire and the buffer layer constitute a core support, and then an IGZO channel layer is deposited on the surface of the buffer layer to wrap the IGZO channel layer;

[0028] The second step is to use high-precision photolithography technology to locate the source and drain electrode areas, and use ALD technology to deposit ITO thin films to form source and drain electrode layers;

[0029] The third step is to use ALD technology to wrap a high dielectric constant gate dielectric layer on the surface of the suspended nanowire structure;

[0030] The fourth step is to locate the gate electrode region using high-precision photolithography technology and deposit the conductive gate electrode using ALD technology;

[0031] The fifth step is to use photolithography and etching technology to remove the high dielectric gate dielectric layer on the surface of the source and drain electrode layers to form a GAA IGZO-FET device with an opening area to facilitate the application of source and drain voltages to the source and drain electrodes.

[0032] The various technical solutions provided in this application have at least the following technical effects or advantages:

[0033] 1. The present invention utilizes a suspended nanowire structure, and deposits a wrapped IGZO structure on its surface by atomic layer deposition (ALD) technology to prepare a CAA or GAA IGZO-FET device, thereby avoiding the short channel effect of a planar IGZO TFT caused by increased integration. The CAA or GAA IGZO-FET device has a higher gate control capability, a high driving current and a low subthreshold swing, which effectively improves the integration density of high-performance IGZO transistors and is more suitable for high-definition displays and high-density integrated circuits.

[0034] 2. The present invention can utilize high-precision photolithography technology to locate the region of the source / drain electrode layer to obtain CAA or GAA IGZO-FET devices with different IGZO channel lengths.

[0035] 3. The IGZO channel-enclosed or gate-enclosed structure of the present invention utilizes the one-dimensional structural characteristics of nanowires. Compared with the planar structure, the width of IGZO is increased by π times. The present invention can also further adjust the channel width-to-length ratio (W / L) of IGZO-FET by positioning the source / drain electrode layer area of ​​IGZO to obtain an IGZO FET device with optimal performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 is a flow chart of the preparation of a suspended nanowire structure in one embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of the structure of CAA and GAA IGZO-FET prepared by using suspended nanowire structure in one embodiment of the present invention;

[0039] Figure 3 is a schematic diagram of a CAA IGZO-FET device prepared using suspended nanowires in one embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of a GAA IGZO-FET device prepared by using suspended nanowires in one embodiment of the present invention;

[0041] In the figure: 101, alternating layers of silicon oxide and silicon nitride; 102, suspended nanowire; 103, nanowire suspended electrode; 110, CAA IGZO-FET device; 112, gate dielectric layer; 113, IGZO channel layer; 114, source and drain electrode layers; 120, GAA IGZO-FET device; 121, buffer layer; 122, gate electrode layer; 201, silicon oxide layer; 202, silicon nitride layer; 203, etched silicon nitride guide channel layer; 204, metal indium film; 205, indium ball; 207, nanowire after removing indium ball and native oxide layer; 209, etched silicon oxide layer; 301, gate layer opening area in CAA IGZO-FET device; 401, source and drain electrode layer opening area in GAA IGZO-FET device; 402, IGZO conductive channel in GAA IGZO-FET device. DETAILED DESCRIPTION

[0042] The present invention aims at the deficiencies of the prior art and utilizes the advantages of the morphology programming and three-dimensional positioning of suspended nanowires to prepare CAA and GAA IGZO-FET devices with the advantages of high on-state current, low subthreshold swing and high density. The present invention first realizes three-dimensional suspension on the basis of a planar nanowire structure, and then utilizes the nanowire suspended structure to further utilize the ALD deposition technology to deposit the IGZO channel layer, gate dielectric layer and electrode layer, thereby realizing high-performance CAA and GAA IGZO-FET devices.

[0043] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. Example

[0044] This embodiment provides a method for preparing a suspended nanowire structure. Figure 1 As shown, it includes the following steps:

[0045] In the first step, a silicon oxide layer 201 and a silicon nitride layer 202 are alternately deposited on a substrate (such as a silicon wafer) using a plasma enhanced chemical vapor deposition (PECVD) technique. In this embodiment, three layers are alternately deposited. In order to obtain nanowires with a diameter less than 20 nm, the thickness of the silicon nitride layer 202 is less than 20 nm, and the thickness of the silicon oxide is set to 20 nm or 30 nm respectively according to the requirements of preparing CAA or GAA IGZO-FET; the silicon oxide layer 201 and the silicon nitride layer 202 are patterned using a photolithography technique, such as Figure 2 The rectangular structure in

[0046] In the second step, the side structure of the stack of silicon oxide layer 201 and silicon nitride layer 202 is exposed by using an inductively coupled plasma (ICP) etching technique; the structure is placed in a hot phosphoric acid solution, and since the etching ratio of hot phosphoric acid to silicon nitride or silicon oxide is about 20:1, an etched silicon nitride guide channel layer 203 is obtained;

[0047] The third step is to use photolithography technology to locate the metal indium region at one end of the stack of the silicon oxide layer 201 and the etched silicon nitride guide channel layer 203, and use thermal evaporation deposition technology to locate and deposit the metal indium film 204; using the "planar solid-liquid-solid" growth method, use hydrogen plasma in the PECVD equipment to reduce the metal indium film 204 into indium balls 205, and then cover the amorphous silicon (a-Si) film, in a vacuum and high temperature environment of 300°C to 350°C, in a vacuum and high temperature environment, the indium balls 205 absorb a-Si along the etched silicon nitride guide channel layer 203, and grow crystalline silicon nanowires at the rear end;

[0048] The fourth step is to locate the nanowire suspended electrode region using high-precision photolithography technology (such as electron beam lithography (E-beam Lithography, EBL), and then pass the grown nanowire sample through a silicon oxide etchant (such as buffered oxide etchant BOE) for 2 seconds to remove the native oxide layer on the surface of the silicon nanowire, and then use electron beam evaporation (EBE) to deposit the nanowire suspended electrode 103 to connect the nanowire 207 after removing the indium ball and the native oxide layer, so as to form a good contact between the metal and the nanowire, wherein the nanowire suspended electrode 103 must have the characteristics of resisting etching by the silicon oxide etchant (such as platinum on the lower layer and gold metal stack on the upper layer);

[0049] In the fifth step, the entire structure is immersed in a silicon oxide etching solution (such as BOE) to obtain an etched silicon oxide layer 209, thereby obtaining a suspended nanowire structure separated from the silicon oxide and silicon nitride stack. Example

[0050] This embodiment provides a CAA IGZO-FET device having the above-mentioned suspended nanowire structure, the structure of which is as follows: Figure 1-Figure 3 As shown: the three-dimensional structure of the CAA IGZO-FET device 110 includes a gate dielectric layer 112, an IGZO layer and a positioned deposited source and drain electrode layer 114 deposited on the entire surface of the above-mentioned suspended nanowire structure; the suspended nanowire 102 connected by the nanowire suspended electrode 103 constitutes the gate of the CAA IGZO-FET device; the gate dielectric layer 112 is prepared by ALD of a high dielectric constant dielectric material, such as aluminum oxide or hafnium oxide.

[0051] Preferably, in order to obtain a higher integration density in the vertical direction, in this embodiment, when the thickness of the alternating stack of silicon oxide and silicon nitride 101 is 20 nm, the diameter of the suspended nanowire 102 can be compressed to less than 20 nm, and when the thickness of silicon nitride is 10 nm, the diameter of the suspended nanowire 102 in the vertical dimension can be compressed to about 7 nm. Therefore, the high dielectric constant gate dielectric layer 112 deposited by ALD technology can ensure complete wrapping of the nanowire, and a thinner (less than 10 nm) high dielectric constant gate dielectric layer can achieve good gate control of the IGZO channel layer.

[0052] The fully-enclosed IGZO channel has a higher driving current than the planar structure IGZO TFT due to its higher channel width-to-length ratio, in order to provide tolerance for further improving the integration density, to be able to withstand higher voltages, and to improve the reliability of the device; this embodiment uses ALD to deposit an IGZO channel layer 113 with a thickness of about 5 to 10 nm on the surface of the suspended nanowire 102 wrapped by the high dielectric constant gate dielectric layer 112.

[0053] Preferably, the present embodiment uses high-precision lithography technology such as electron beam lithography (E-beam Lithography, EBL) to locate the source and drain electrode layer regions, and then uses ALD technology to deposit a conductive film to form the source and drain electrodes of the CAA IGZO-FET device, such as an indium tin oxide (ITO) film that can form a good ohmic contact with the IGZO channel. According to the source and drain electrode intervals located by the high-precision lithography technology, the width-to-length ratio of the IGZO channel is adjusted, and IGZO channels with different width-to-length ratios match different IGZO thicknesses, so as to obtain a high-performance and highly integrated vertically stacked CAA IGZO-FET device.

[0054] This embodiment also discloses a method for preparing a CAA IGZO-FET device. First, a nanowire structure is grown along the silicon nitride layer in the alternating stack of silicon oxide and silicon nitride 101 by a planar solid-liquid-solid growth method. After the nanowire suspended electrode 103 is clamped to realize a suspended structure, the method further includes the following steps:

[0055] In the first step, the gate dielectric layer and the IGZO channel layer are sequentially deposited on the surface of the suspended nanowire structure using the ALD technology. The gate dielectric layer and the IGZO layer do not need to be positioned, and the entire surface is deposited and wrapped on the entire suspended nanowire structure.

[0056] In the second step, on the surface of the IGZO channel layer, Figure 3In the device structure shown, high-precision photolithography technology (such as EBL) is first used to locate the source and drain electrode layer area, which is consistent with the source and drain deposition layer area, and the area outside the area is covered with photoresist. After the source and drain electrode layers are deposited using ALD technology, the source and drain electrodes outside the positioning area are lifted off to obtain patterned source and drain electrode layers 114. According to the design of the photolithography pattern, CAA IGZO-FET devices with different IGZO channel lengths (L) are obtained.

[0057] In the third step, the gate dielectric layer and the IGZO channel layer on the nanowire suspended electrode are partially etched by photolithography and etching technology to form a gate layer opening area 301 in the CAA IGZO-FET device, so as to facilitate the application of gate voltage to the gate electrode formed by the nanowire suspended electrode connecting the suspended nanowire.

[0058] It is worth noting that the IGZO channel is deposited on the entire surface using ALD technology. Figure 3 In the device structure shown, except for the IGZO channel on the suspended nanowire structure, the remaining IGZO conductive channels between the source and drain electrodes do not overlap with the gate electrode, and the field effect formed is very weak, or can be ignored compared with the strong field effect on the suspended nanowire structure. Assuming the nanowire diameter is D, the width of the IGZO channel is the nanowire perimeter π*D, as provided in the present application Figure 2 The number of vertically stacked nanowires is 3. Under the condition of the same projected area, the aspect ratio of the CAA IGZO-FET device prepared by suspended nanowires is increased by 3π times compared with the planar IGZO TFT device, and the driving current per unit area is increased, which rapidly improves the driving current of the IGZO device and solves the application bottleneck of the IGZO channel in high-brightness display. Moreover, the IGZO device structure with the channel fully surrounded has a stronger gate control capability than the planar IGZO TFT device, which is suitable for fast logic calculations and further improves the integration density of integrated circuits. Example

[0059] This embodiment provides a GAA IGZO-FET device prepared using the above suspended nanowire structure, such as Figure 2 , Figure 4 As shown: The side structure diagram of the GAA IGZO-FET device 120 is shown in Figure 2 As shown below the three-dimensional schematic diagram, the ALD technology is used to deposit a silicon oxide buffer layer 121 on the entire surface of the suspended nanowire structure, and then the IGZO channel layer 113, the source and drain electrode layer 114, the gate dielectric layer 112 and the gate electrode layer 122 are deposited in sequence; the gate dielectric layer on the surface of the source and drain electrode layer 114 is removed to form the source and drain electrode layer opening area 401 in the GAA IGZO-FET device, which is convenient for applying the source / drain voltage to the source / drain electrodes.

[0060] Preferably, before depositing the IGZO channel layer 113 using the ALD technology, in order to prevent the suspended nanowire 102 from forming a conductive channel together with the IGZO channel layer 113, the buffer layer 121 is first deposited on the surface of the suspended nanowire 102 using ALD. The suspended nanowire and the buffer layer constitute an inner core support, and the buffer layer can be composed of a relatively thin (less than 10 nm) silicon oxide; the IGZO channel layer 113 with a thickness of about 5-10 nm is wrapped on the surface of the buffer layer 121; the source and drain electrode regions are positioned using high-precision lithography technology (such as EBL), and the ITO thin film is deposited using the ALD technology to form the source and drain electrode layer 114; then, a relatively thin (less than 10 nm) high dielectric constant gate dielectric layer 112 is wrapped on the surface of the structure using the ALD technology; the gate electrode region is positioned using high-precision lithography technology (such as EBL), and the conductive gate electrode is deposited using the ALD technology.

[0061] It is worth noting that the GAA IGZO-FET structure has a large number of film layers deposited on the surface of the suspended nanowire 102. Therefore, when preparing the nanowire growth guiding channel, the thickness of the silicon oxide film layer should be thickened (such as thickening the silicon oxide to 30 nm and maintaining the silicon nitride thickness at 20 nm) to obtain nanowires with slightly larger vertical stacking intervals, so as to provide greater compatibility for the subsequent ALD deposition of each film layer to prepare the GAA IGZO-FET device.

[0062] In the present embodiment, there is an overlapped region between the source and drain electrode layers and the gate electrode layer of the GAA IGZO-FET device. The IGZO conductive channel 402 in the GAA IGZO-FET device is composed of three parts, namely, the IGZO channel on the surface of the alternating stack of silicon oxide and silicon nitride 101, the IGZO channel on the sidewall of the alternating stack of silicon oxide and silicon nitride 101, and the IGZO channel on the surface of the silicon substrate. Assume that the width of the conductive channel formed in the overlapped region is W 0 , length is L, the height of the alternating stack of silicon oxide and silicon nitride is H, and the diameter of the nanowire is D, then the overall conductive channel is composed of a width-to-length ratio of (W 0 +H) / L vertical channel IGZO FET and three groups of GAA IGZO-FET with width-to-length ratio of (π*D) / L, the integration density is improved compared with the planar IGZO TFT (W 0 +H+3π*D) / W 0 times.

[0063] This application is based on the self-organized catalytic growth strategy induced by metal nanodroplets. It does not rely on the "top-down" etching method of high-precision photolithography technology, but can directly grow and prepare single-crystal nanowire structures with fine diameters in batches. Through the new "planar solid-liquid-solid" nanowire growth mode, the growth of nanowires is completely restricted and positioned on the three-dimensional surface. By etching and releasing part of the three-dimensional structure, a precise and suspended nanowire structure is formed, providing a convenient and reliable high-integration three-dimensional structure for the integration of IGZO. The structure or device of CAA or GAA IGZO-FET prepared by nanowires proposed in this application effectively solves the problems of low IGZO driving current, short channel effect, and difficult three-dimensional vertical integration, greatly improving the application potential of IGZO in high-performance display driving and ultra-large-scale logic integration.

[0064] The above is a detailed introduction to the structure and device of a CAA or GAAIGZO-FET prepared by using a suspended nanowire structure provided by several embodiments of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application; at the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present application.

[0065] The above description is only a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements without departing from the principle of the present invention. These improvements should also be regarded as within the scope of protection of the present invention.

Claims

1. A suspended nanowire structure, comprising a base layer disposed on a substrate, characterized in that: It also includes nanowires stacked in parallel and at intervals perpendicular to the base layer, wherein both ends of the nanowires are respectively connected to suspended electrodes, and there is a gap between the middle part of the nanowires stacked in parallel and at intervals and the base layer; The base layer is an alternating stacked structure of silicon oxide and silicon nitride, and the parallel and spaced nanowires are grown on a silicon nitride guide layer of the alternating stacked structure; After the silicon oxide is etched, the gap is formed between the alternating stacked structure and the parallel spaced nanowires, and the nanowires between the suspended electrodes at both ends constitute parallel stacked suspended nanowires.

2. An IGZO-FET device with a suspended nanowire structure, using the suspended nanowire structure according to claim 1, characterized in that: The IGZO-FET device is a CAA IGZO-FET device, a gate dielectric layer, an IGZO channel layer, and source and drain electrode layers are sequentially deposited on the surface of the suspended nanowire structure from the inside out, the suspended electrode and the suspended nanowires connected thereto constitute the gate electrode of the CAA IGZO-FET device, and the suspended electrode is provided with an opening region for applying a gate voltage to the gate electrode formed by the suspended electrode connecting the suspended nanowires; Or, the IGZO-FET device is a GAA IGZO-FET device, a buffer layer is deposited on the surface of the suspended nanowire structure, the suspended nanowire and the buffer layer constitute an inner core support, the buffer layer is sequentially deposited with an IGZO channel layer, a source and drain electrode layer, a gate dielectric layer and a gate electrode layer from the inside to the outside, and the gate dielectric layer on the surface of the source and drain electrode layer is removed to form an open area for applying source and drain voltages to the source and drain electrodes.

3. The IGZO-FET device with a suspended nanowire structure according to claim 2, characterized in that: There is an overlapping area between the source and drain electrode layers and the gate electrode layer of the GAAIGZO-FET device, and the IGZO conductive channel in the overlapping area is composed of the IGZO channel on the surface of the base layer, the IGZO channel on the side wall of the base layer and the IGZO channel on the substrate surface.

4. A method for preparing a suspended nanowire structure, characterized in that: The steps include: In the first step, a stacked structure of silicon oxide and silicon nitride is alternately deposited on a substrate using plasma enhanced chemical vapor deposition technology; The second step is to expose the side structure of the silicon oxide and silicon nitride stack by using a reactive coupled plasma etching technique, and to etch the stack structure in a hot phosphoric acid solution to obtain a silicon nitride guide channel layer; The third step is to use photolithography technology to locate the catalytic metal area at one end of the silicon nitride guide channel layer, and use thermal evaporation deposition technology to locate and deposit the metal film; using the planar solid-liquid-solid growth method, hydrogen plasma is used in the PECVD equipment to reduce the metal film into metal balls, which are then covered with precursors. In a vacuum and high temperature environment of 300°C to 350°C, the metal balls absorb the precursors along the etched silicon nitride guide channels to grow parallel nanowires; The fourth step is to use high-precision photolithography technology to locate the nanowire suspended electrode area at both ends of the parallel nanowires, pass the grown nanowire sample through a silicon oxide etchant to remove the native oxide layer on the surface of the nanowire, and use electron beam evaporation to deposit the nanowire suspended electrode to connect the two ends of the parallel nanowires; In the fifth step, the entire structure is finally immersed in a silicon oxide etching solution to etch the silicon oxide layer to form a parallel suspended nanowire structure separated from the silicon oxide and silicon nitride stack.

5. The method for preparing a suspended nanowire structure according to claim 4, characterized in that: The precursor is amorphous silicon or amorphous germanium, and the nanowires obtained by vacuum high-temperature annealing are silicon nanowires or germanium nanowires.

6. The method for preparing a suspended nanowire structure according to claim 4, characterized in that: The suspended electrode is a platinum-gold metal stack material that is resistant to silicon oxide etching solution.

7. A method for preparing an IGZO-FET device having a suspended nanowire structure, applicable to the IGZO-FET device according to any one of claims 2 to 3, characterized in that the steps include: First, a gate dielectric layer, an IGZO channel layer, and source and drain electrode layers are sequentially deposited on the suspended nanowire structure, and then the gate dielectric layer and the IGZO channel layer on the suspended electrode at both ends of the suspended nanowire are partially etched to form a CAA IGZO-FET device with an open area for applying a gate voltage; Alternatively, a buffer layer is first deposited on the suspended nanowire structure, and then an IGZO channel layer, a source and drain electrode layer, a gate dielectric layer and a gate electrode layer are sequentially deposited on the surface of the buffer layer from the inside to the outside to obtain a GAA IGZO-FET device.

8. The method for preparing the IGZO-FET device having a suspended nanowire structure according to claim 7, characterized in that: The preparation method of the CAA IGZO-FET device comprises: In the first step, a gate dielectric layer and an IGZO channel layer are sequentially deposited on the surface of the suspended nanowire structure using the ALD technology. The gate dielectric layer and the IGZO layer do not need to be positioned and are deposited on the entire surface to wrap around the suspended nanowire structure. In the second step, on the surface of the IGZO channel layer, the source and drain electrode layer regions are first positioned by using high-precision photolithography technology, and the source and drain electrode layers are deposited by using ALD technology, and then the source and drain electrodes outside the positioning region are stripped off to obtain patterned source and drain electrode layers; The third step is to use photolithography and etching technology to partially etch the gate dielectric layer and IGZO channel layer on the nanowire suspended electrode to form an opening area of ​​the CAA IGZO-FET device, so as to facilitate the application of gate voltage to the gate electrode formed by the nanowire suspended electrode connecting the suspended nanowire.

9. The method for preparing the IGZO-FET device having a suspended nanowire structure according to claim 7, characterized in that: The preparation method of the GAA IGZO-FET device comprises: In the first step, a buffer layer is first deposited on the entire surface of the suspended nanowire structure using ALD technology, wherein the suspended nanowire and the buffer layer constitute a core support, and then an IGZO channel layer is deposited on the surface of the buffer layer to wrap the IGZO channel layer; The second step is to use high-precision photolithography technology to locate the source and drain electrode areas, and use ALD technology to deposit ITO thin films to form source and drain electrode layers; The third step is to use ALD technology to wrap a high dielectric constant gate dielectric layer on the surface of the suspended nanowire structure; The fourth step is to locate the gate electrode region using high-precision photolithography technology and deposit the conductive gate electrode using ALD technology; The fifth step is to use photolithography and etching technology to remove the high dielectric gate dielectric layer on the surface of the source and drain electrode layers to form a GAA IGZO-FET device with an opening area to facilitate the application of source and drain voltages to the source and drain electrodes.

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