Epitaxial structure of III-V group semiconductor, and growth method and application thereof

Abstract

The invention discloses an epitaxial structure of a III-V semiconductor, a growth method and application thereof. The epitaxial structure comprises a substrate, a middle layer, an etching stop layer, a channel layer and a barrier layer which are sequentially arranged in a stacked mode in the designated direction. Wherein the channel layer and the barrier layer form a heterojunction, and the V-group polar surface faces the etching stop layer; the etching stop layer comprises a first sub-layer and a second sub-layer which are periodically stacked, and when etching is carried out, the etching rate of the first sub-layer is higher than that of the second sub-layer. The epitaxial structure provided by the invention adopts a multi-layer laminated structure as an etching stop layer, so that the equivalent total thickness of the second sub-layer is improved, the defects of cracks and the like of the independent thicker second sub-layer are avoided, an active layer structure with a certain thickness can be realized as required, the interface roughness and the interface state density can be effectively reduced, and the performance of the device is improved. The III-group polar heterojunction device which is high in carrier density, high in mobility, stable, uniform and high in quality can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor micro-nano manufacturing technology, and in particular to an epitaxial structure of a III-V semiconductor, a growth method thereof and applications thereof. Background Art

[0002] Polar III-V semiconductor materials have superior performance and broad application prospects. For example, nitrogen-polar gallium nitride (GaN) high electron mobility transistors (HEMTs) have lower ohmic contact resistance, stronger two-dimensional electron gas limit threshold, and stronger suppression of short channel effects. Their output power in the W band is more than twice that of traditional gallium-polar GaN HEMTs. They have become a research hotspot for millimeter-wave and terahertz band power devices and are expected to be used in important fields such as 6G mobile communications and high-precision radars.

[0003] However, nitrogen-polar GaN materials are difficult to prepare and their material properties are relatively active, which limits the application of nitrogen-polar GaN materials to a certain extent. It is very difficult to grow nitrogen-polar GaN materials by direct epitaxy due to the main challenges such as low carrier mobility caused by rough surface morphology and high RF loss caused by high oxygen impurity concentration. Only a few institutions in the world, such as the University of California and the University of Michigan, can achieve the growth of high-quality nitrogen-polar GaN heterojunction materials through complex technical means, and prepare RF microwave devices on this basis.

[0004] In addition to the direct epitaxial growth route, nitrogen-polarity GaN heterojunction materials can be prepared by reversing the gallium polarity reverse epitaxial material. Reversing the gallium polarity reverse epitaxy can not only avoid the problems of high roughness and high oxygen impurity concentration of directly grown nitrogen-polarity materials, but also flexibly select a second substrate with high thermal conductivity as needed to solve the problem of increased junction temperature during high-power output. However, reversing the gallium polarity reverse epitaxy not only requires stable transfer support technology and substrate stripping technology, but also requires etching away the substrate and buffer layer of the growing gallium polarity heterojunction. Etching will inevitably cause roughness and damage to the etching interface, as well as a large number of interface states, leading to problems such as low heterojunction carrier mobility, poor device breakdown characteristics, current collapse, and poor dynamic characteristics.

[0005] Inserting an etch stop layer between the bottom layer and the GaN heterojunction material is a feasible approach. However, the lattice constants of the two materials with large etching selectivity are quite different, so the difficult-to-etch material is often difficult to grow thick, which affects the etching uniformity and stability. Specifically, due to the reverse epitaxial growth process, the etch stop layer is grown first, and then the channel / back barrier / high resistance layer is grown. The etch stop layer material with a low etching rate has a serious lattice mismatch with the buffer layer, and the stress on the channel layer is relatively large. When the etch stop layer grows thicker, the material will crack, which seriously affects the crystal quality of the active area, resulting in low heterojunction carrier density and low mobility; when it grows too thin, it is difficult to achieve the purpose of etching stop, resulting in roughness and damage on the surface of the channel layer, and the generation of a large number of interface states, resulting in low heterojunction carrier mobility, poor device breakdown characteristics, and poor current collapse dynamic characteristics. Therefore, overcoming the problems of the existing etch stop technology in the preparation of polar III-V semiconductor devices by reverse epitaxial growth is of great significance for promoting the application of nitrogen polar (or III polar) III-V devices. Summary of the invention

[0006] In view of the deficiencies in the prior art, an object of the present invention is to provide an epitaxial structure of a III-V semiconductor, a growth method thereof and applications thereof.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0008] In a first aspect, the present invention provides an epitaxial structure of a III-V semiconductor, comprising a substrate, an intermediate layer, an etch stop layer, a channel layer and a barrier layer stacked in sequence along a specified direction; wherein the channel layer and the barrier layer form a heterojunction, and the epitaxial structure has a III-V polarity plane and a V-group polarity plane, the V-group polarity is in the direction from the heterojunction to the substrate, and the III-group polarity is in the direction from the substrate to the heterojunction; the etch stop layer comprises a first sublayer and a second sublayer periodically stacked along the specified direction, and when the etch stop layer is etched, the etching rate of the first sublayer is higher than that of the second sublayer.

[0009] In a second aspect, the present invention further provides a method for growing the above-mentioned epitaxial structure, which comprises:

[0010] growing an intermediate layer on a surface of the substrate;

[0011] Periodically growing a first sublayer and a second sublayer of the stack on the surface of the intermediate layer to form an etching stop layer;

[0012] A channel layer and a barrier layer are sequentially grown on the surface of the etch stop layer to form a heterojunction, wherein the heterojunction has a group III polarity surface and a group V polarity surface, and the group III polarity is the direction from the etch stop layer to the heterojunction.

[0013] In a third aspect, the present invention further provides a method for preparing a group V polarity III-V semiconductor structure, comprising:

[0014] Providing the above-mentioned epitaxial structure;

[0015] Covering the epitaxial surface of the epitaxial structure away from the substrate with a support layer;

[0016] The substrate, the intermediate layer and a selectable part of the etching stop layer in the epitaxial structure are etched and removed to obtain a III-V semiconductor structure with group V polarity.

[0017] In a fourth aspect, the present invention also provides a group V polarity III-V semiconductor structure prepared by the above preparation method.

[0018] In a fifth aspect, the present invention also provides a III-V semiconductor device, which includes the above-mentioned III-V semiconductor structure and a plurality of electrodes, wherein the electrodes pass through the etch stop layer remaining after etching to produce ohmic contact with the channel layer, and / or part of the electrodes are isolated from the channel layer by the etch stop layer and produce electrical interaction with the channel layer.

[0019] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention at least include:

[0020] The inverse epitaxial structure provided by the present invention adopts a stacked structure as an etching stop layer, and a first sublayer with a relatively fast etching rate is inserted between the second sublayers or between the second sublayer and the middle layer, which mainly slows down the etching rate. When multiple layers are stacked cyclically, the equivalent total thickness of the second sublayer can be increased, and defects such as cracks generated when a single second sublayer grows thicker can be avoided. An active layer structure of a certain thickness can be achieved as needed, and regardless of single-cycle stacking or multi-cycle stacking, the interface roughness and interface state density of the V-group polar heterojunction after etching can be effectively reduced; in addition, the first sublayer not only keeps the interface state density away from the channel, but also adjusts the channel band structure, so that the channel band is bent and the electric field becomes slower, which is more conducive to obtaining a stable, uniform and high-quality V-group polar heterojunction device with high mobility and high carrier density.

[0021] Furthermore, the total thickness of the channel region formed by the reverse epitaxial structure of the present invention after flipping can be adjusted between tens of nm and several μm from the support layer as required, which will be more conducive to heat dissipation and can further improve the maximum power density of the device.

[0022] The above description is only an overview of the technical solution of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement them according to the contents of the specification, the following is a description of the preferred embodiments of the present invention in conjunction with detailed drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the preparation process of a III-V semiconductor structure provided by some embodiments of the present invention;

[0024] Figure 2 It is a schematic diagram of the overall structure of the reverse epitaxial structure provided by some implementation cases of the present invention;

[0025] Figure 3 It is a schematic diagram of the overall structure of the reverse epitaxial structure provided by a typical implementation case of the present invention;

[0026] Figure 4 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0027] Figure 5 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0028] Figure 6 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0029] Figure 7 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0030] Figure 8 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0031] Fig. 9 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0032] Fig.10 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0033] Fig.11 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0034] Fig.12 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0035] Fig.13It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by a typical implementation case of the present invention;

[0036] Fig.14 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0037] Fig.15 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0038] Fig.16 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0039] Fig.17 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0040] Fig.18 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0041] Fig.19 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0042] Fig. 20 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0043] Fig.21 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0044] Fig. 22 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0045] Fig.23 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0046] Fig.24 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical embodiment of the present invention;

[0047] Fig.25 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0048] Fig.26 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0049] Fig. 27 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0050] Fig.28 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0051] Fig.29 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0052] Fig.30 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0053] Fig.31 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0054] Fig.32 This is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention.

[0055] Fig.33 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0056] Fig.34 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention;

[0057] Fig.35 It is a structural schematic diagram of the preparation and decomposition steps of a III-V semiconductor structure provided by another typical implementation case of the present invention. DETAILED DESCRIPTION

[0058] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0059] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0060] Moreover, relational terms such as “first” and “second” and the like are merely used to distinguish one component or method step from another having the same name, but do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0061] See also Figure 2 An embodiment of the present invention provides a reverse epitaxial structure of a III-V semiconductor, comprising a substrate, an intermediate layer, an etch stop layer, a channel layer, a barrier layer and a high resistance layer stacked in sequence along a specified direction; wherein the channel layer and the barrier layer form a heterojunction, and the epitaxial structure has a III-group polarity plane and a V-group polarity plane, the V-group polarity is in the direction from the heterojunction to the substrate, and the III-group polarity is in the direction from the substrate to the heterojunction; the etch stop layer comprises a first sublayer and a second sublayer periodically stacked along the specified direction, and when the etch stop layer is etched (especially when the mixed gas etching recorded in the embodiment), the etching rate of the first sublayer is higher than that of the second sublayer.

[0062] Among them, the intermediate layer refers to a semiconductor epitaxial layer that plays a buffer and connecting role between the substrate and the etch stop layer, such as the nucleation layer, transition layer and buffer layer exemplified below. Of course, there may be some changes in different implementations. There may be no transition layer or even a buffer layer, etc., or the name of the semiconductor layer may also change. This does not affect the scope of protection of the present invention. Equivalent replacements for semiconductor layers that can play an intermediate buffer and connecting role between the substrate and the etch stop layer are all within the scope of protection of the present invention.

[0063] Also, although the names of the multiple laminates are first / second sub-layers, these are functional film layer names, which does not mean that the two first sub-layers with the same name must be completely identical. For example, the multiple first sub-layers may be of the same material and thickness, or of different materials and thicknesses. The same is true for the multiple second sub-layers. For example, Figure 2 The thickness of the first GaN layer may be different from that of the second GaN layer, or the second GaN layer may be replaced by other materials with the same etching rate properties, or the thickness of the nth AlGaN layer and the n-1th AlGaN layer may be different or the materials may be replaced by materials with the same properties. These are all feasible implementations. Of course, for the convenience of preparation, an implementation in which all the first sublayers are the same and all the second sublayers are the same is generally selected. However, this does not mean that the implementations in which the above layers are different do not fall within the scope of protection of the present invention.

[0064] The key technical means of the present invention lies in the etching stop layer. Based on the above technical scheme, the present invention innovatively adopts the heterojunction structure design combined with the etching self-stop technology. The scheme selects a heterojunction composite layer with a high etching selectivity as the etching stop layer. In this scheme, the heterojunction material structure of the etching stop layer can avoid the crystal quality problem caused by stress during growth, and an equivalent thicker etching stop layer can be obtained, which can effectively reduce the interface roughness and interface state density of the III-group polar III-V heterojunction in steps; on the other hand, an active layer structure with a certain thickness can be realized as needed to realize a stable, uniform, high-quality V-group polar III-V heterojunction with high carrier density and high mobility, thereby realizing high-performance radio frequency devices, improving the device breakdown voltage, and effectively suppressing current collapse and other problems. The heterojunction etching stop layer can also be used as a cap layer for the active heterojunction, so that the surface of the epitaxial layer is away from the 2DEG channel layer, and the heterojunction surface / interface state effectively scatters the 2DEG and current collapses. Moreover, in the further process of preparing the device, the distance between the flipped channel and the support layer can be adjusted between tens of nm and several μm as needed, which will be more conducive to heat dissipation and further improve the power density, output power and efficiency of the device.

[0065] Thus, in some preferred embodiments, the intermediate layer includes a nucleation layer, a transition layer, and a buffer layer sequentially stacked along the specified direction;

[0066] In some embodiments, the inverse epitaxial structure also includes a high resistance layer disposed on the surface of the barrier layer, and the high resistance layer on the heterojunction is located between the support layer and the heterojunction, which may vary in different structures and may be present or absent.

[0067] As for the specific material of the etch stop layer, in some embodiments, the material of the first sublayer includes any one or a combination of two or more of GaN, InGaN, InN, etc.;

[0068] In some embodiments, the material of the second sub-layer includes any one of AlGaN, AlN, AlInN, AIInGaN, AlInN or a combination of two or more thereof, and is not limited thereto. Any material of the second sub-layer that can achieve the corresponding etching rate difference and can be combined with other layers to form a multi-layer structure can achieve the corresponding technical effect. It should be emphasized that not only the material selection of the second sub-layer, but also other aspects, such as the selection of the first sub-layer and the materials and thicknesses of other layers, the applicable scope of the present invention is not limited to the multiple specific exemplary scopes exemplified in the specific embodiments of the present invention, and the corresponding principle of achieving the technical effect of the present invention is sufficient.

[0069] Specifically, the above-mentioned etch stop layer can be a superlattice structure or a thicker stacked heterojunction based on its thickness. For example, the superlattice stop layer structure is not limited to the GaN / AlGaN superlattice structure, but also includes other superlattice structures, such as GaN / AlN, GaN / AlInN, GaN / AlInGaN, InGaN / AlGaN, InGaN / AlInN, InGaN / AlInGaN and other heterostructures.

[0070] In some embodiments, the group III polar face is a Ga polar face, and the group V polar face is an N polar face.

[0071] In some embodiments, the first sublayer has a thickness of 2-500 nm.

[0072] In some embodiments, the second sublayer has a thickness of 1-50 nm.

[0073] In some embodiments, the periodic stacking has a period number of 1-10.

[0074] In some embodiments, when the etch stop layer is etched, the etching rate of the first sub-layer is 2-10 times greater than that of the second sub-layer.

[0075] As for the structures and materials of other layers, the heterojunction formed by the barrier layer and the channel layer is not limited to the AlGaN / GaN heterojunction, but also includes GaN / AlN, GaN / AlInN, GaN / AlInGaN, InGaN / AlGaN, InGaN / AlInN, InGaN / AlInGaN and other heterojunction materials, and the thickness and composition of each layer are adjustable, and the barrier layer and channel layer with corresponding functions can be formed. Of course, the polarity surface needs to meet the above requirements, so as to achieve reverse epitaxy to overcome the crystal growth problem during forward epitaxy. The high-resistance layer is not limited to GaN materials, and it can also be absent, and it can also be other AlN, AlInGaN, AlInN and other materials to achieve high resistance. For example, when a high-resistance material is directly used to form a support layer, for example, the support layer can be any high-resistance material such as diamond, AlN, SiC, etc., and there is no need to set a high-resistance layer. The substrate is preferably a Si substrate, and its removal method is not limited to the method illustrated in the embodiment of the present invention. Any technology that can realize the peeling of the Si substrate is included in the protection scope of this patent. Of course, even if the substrate is replaced with a substrate of other materials, as long as it can be removed, that is: the substrate is not limited to Si substrate, but also includes all other materials that can epitaxially grow III-group nitrides, including GaN self-supporting substrates, AlN substrates, SiC substrates, sapphire substrates, diamond substrates, etc.

[0076] Corresponding to the above-mentioned inverse epitaxial structure, an embodiment of the present invention further provides a method for growing an inverse epitaxial structure, which comprises the following steps:

[0077] growing an intermediate layer on a surface of the substrate;

[0078] Periodically growing a first sublayer and a second sublayer of the stack on the surface of the intermediate layer to form an etching stop layer;

[0079] A channel layer and a barrier layer are sequentially grown on the surface of the etch stop layer to form a heterojunction, and the epitaxial structure has a group III polarity surface and a group V polarity surface, the group V polarity is the direction from the heterojunction to the substrate, and the group III polarity is the direction from the substrate to the heterojunction;.

[0080] In some embodiments, the further step includes: growing a high resistance layer on the surface of the barrier layer.

[0081] See also Figure 2 As a further application of the above technical solution, the present invention also provides a method for preparing a group V polarity III-V semiconductor structure, which comprises the following steps:

[0082] Providing a reverse epitaxial structure provided by any of the above embodiments;

[0083] A support layer is provided on the non-substrate surface (i.e., the surface facing away from the substrate or far away from the substrate) of the inverse epitaxial structure;

[0084] The substrate, the middle layer and a selectable part of the etching stop layer in the reverse epitaxial structure are etched and removed to obtain a III-V semiconductor structure with a V group polarity.

[0085] In some embodiments, after the etch stop layer is etched, at least all or part of a layer of the first sub-layer closest to the channel layer and a layer of the second sub-layer remain.

[0086] Correspondingly, an embodiment of the present invention further provides a group V polarity III-V semiconductor structure obtained by the above preparation method.

[0087] Specifically, the etching and removal method of the intermediate layer, especially the nucleation layer and the buffer layer, not only includes the ICP etching method, but also includes any method that can remove the nucleation layer and the buffer layer, including wet etching, etc. The etch stop layer can be etched or not etched as needed, and can also stop at any layer of the superlattice stop layer, the etch stop layer, and the heterojunction etch stop layer.

[0088] Specifically, an embodiment of the present invention also provides a III-V semiconductor device, which includes the above-mentioned III-V semiconductor structure and multiple electrodes, wherein the electrodes pass through the etch stop layer remaining after etching to produce ohmic contact with the channel layer, and / or part of the electrodes are isolated from the channel layer by the etch stop layer and produce electrical interaction with the channel layer.

[0089] In some embodiments, the electrodes include a source electrode, a drain electrode, and a gate electrode;

[0090] In some embodiments, the III-V semiconductor device includes any one of a diode and a triode. When a diode is selected, the corresponding structure name will be changed, and the corresponding electrode and electrode structure will also be changed accordingly.

[0091] The specific device structure manufacturing process can refer to the embodiments of the present invention, and can also refer to any existing technology or self-developed technology. The main inventive concept of the present invention lies in the structure, growth process and function of the above-mentioned etch stop layer, and rarely in how to specifically construct the electrode to realize the corresponding device; taking the triode as an example, the dielectric layer can continue to be covered on the surface of the remaining etch stop layer, and then the source and drain can be set through the dielectric layer and the etch stop layer and annealed to make them in ohmic contact with the channel layer, and the above-mentioned etch stop layer is etched by blind holes (without etching through), and then filled to construct the gate. The gate can be covered by the dielectric layer. This is a common practice in the field.

[0092] Of course, in various feasible implementations, the dielectric layer may not be used, and is not limited to SiN of MOCVD, but may also be other dielectric layers made by other methods (PECVD, LPCVD), such as Al2O3, SiO2, HfO2, La2O3, etc. The gate may not be made of dielectric coating, but may also be made of dielectric, and the method for making the dielectric and the dielectric material may be selected as needed. The drain and source ohmic metal may not only be Ti / Al / Ni / Au, but also include other metal systems that can form ohmic contact with GaN channel layer materials. And the ohmic contact process of the source and drain is not limited to high temperature annealing, but also includes other process technologies that can achieve ohmic contact, such as secondary epitaxial n-type heavily doped materials and ion implantation doping. The gate metal is not limited to Ni / Au, but may also be other metals such as Ni / Pt / Au, Ni / Pt, P-GaN, etc. that can form Schottky contact with the barrier layer. The active area isolation technology is not limited to etching, but can also be achieved by ion implantation technology.

[0093] Of course, general devices need to lead out the circuits of each electrode, and the lead-out pad can be made by gold wire bonding or electron beam evaporation, etc., and the metal is not limited to Au, but also includes other metals with conductive properties, such as Pt, Al, Cu, W, or double-layer or multi-layer composite metals such as Ti / Au, Ni / Au, Pt / Au, Cr / Cu. The specific device process is not limited to the process described in the embodiment, and this patent also includes other possible process steps, including thickening the passivation layer, field plate structure, thickening the interconnection electrode, etc. The process steps for realizing this structural device are not limited to the process steps described in the embodiment, but also include other process steps that can realize this structure.

[0094] The technical solution of the present invention is further described in detail below through several embodiments and in conjunction with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention, and do not limit the scope of the present invention.

[0095] Example 1

[0096] This embodiment illustrates a process of growing a reverse epitaxial structure and preparing a corresponding N-polarity GaN device based on the structure, which specifically includes the following steps:

[0097] 1. As Figure 3 As shown, a chemical vapor deposition (MOCVD) device is used to sequentially grow an AlN nucleation layer, an AlGaN transition layer, a GaN buffer layer, a GaN / AlGaN (~10nm / 5nm) superlattice stop layer on a silicon substrate, with a period of 5 layers, a GaN channel layer, an AlGaN barrier layer (forming a Ga polar heterojunction), and a GaN high resistance layer. The Al composition of the AlGaN barrier layer is 0.45.

[0098] 2. If Figure 4 As shown, the support layer is bonded on the buffer layer 2 using a bonding method.

[0099] 3. Figure 5 As shown, after flipping, the silicon substrate is removed through thinning, polishing and deep silicon etching processes;

[0100] 4. Etch the nucleation layer and transition layer by ICP dry etching process.

[0101] 5. Etch the buffer layer by ICP dry etching process. When approaching the superlattice layer, use Cl2 / BCl3 / SF6 or Cl2 / BCl3 / O2 etching gas to etch the buffer layer and part of the optional superlattice stop layer. The etching rate is controlled to be no more than 10nm / min. The superlattice stop layer can have one or more layers, or it can be the fifth AlGaN layer on the channel layer (the last layer of the second sublayer). Its structure is as follows Figure 6 shown.

[0102] 6. Such as Figure 7 As shown, after etching, a 2-100 nm SiN passivation layer is grown on the superlattice stop layer by dry and wet surface repair treatments.

[0103] 7. Such as Figure 8 As shown, using photoresist as a mask, RIE is used to etch away the SiN passivation layer in the source and drain regions, and ICP etching technology is used to etch away the superlattice stop layer in the source and drain regions.

[0104] 8. As Fig. 9 As shown, metal Ti / Al / Ni / Au is evaporated by electron beam evaporation technology, and annealed at 850°C for 30s to form the source and drain respectively.

[0105] 9. As Fig.10 As shown, the device isolation is made by using photoresist as a mask and ICP etching to remove the heterojunction outside the active area to form independent device structures on the supporting layer.

[0106] 10. As Fig.11 As shown, the gate contact region is prepared by photolithography, and RIE and slow ICP etching are respectively adopted until the AlGaN layer on the channel layer is etched.

[0107] 11. As Fig.12 As shown, photolithography is used to define the gate cap part, and electron beam evaporation equipment is used to evaporate metal Ni / Au as the gate.

[0108] 12. If Fig.13 As shown, the source and drain are led out to the Au pad, and the source metal is connected to the supporting layer.

[0109] At this point, the preparation of an N-polar heterojunction III-V semiconductor triode has been completed.

[0110] The mobility of the nitrogen-polar GaN heterojunction with only one GaN / AlGaN (~10nm / 5nm) stop layer left after etching is about ~2000cm 2 / Vs, the channel two-dimensional electron gas concentration is about 1.0×10 13 cm -2 , the interface state density on the heterojunction surface is less than 10 11 eV- 1 cm -2 .

[0111] Example 2

[0112] This embodiment illustrates a process of growing a reverse epitaxial structure and preparing a corresponding N-polarity GaN device based on the structure, which specifically includes the following steps:

[0113] 1. Use chemical vapor deposition (MOCVD) equipment to sequentially grow AlN nucleation layer, AlGaN transition layer, GaN buffer layer 1, GaN / AlN (~50nm / 5nm) 3-layer heterojunction stop layer, GaN channel layer, AlGaN barrier layer, GaN high resistance layer on silicon substrate, such as Fig.14 shown.

[0114] 2. Bond the support layer on the buffer layer 2 using a bonding method, such as Fig.15 shown.

[0115] 3. Remove the silicon substrate through thinning, polishing and deep silicon etching processes. Fig.16 Shown

[0116] 4. Etch the nucleation layer and transition layer by ICP dry etching process.

[0117] 5. Etch the buffer layer by ICP dry etching process, and use BCl3 / SF6 or BCl3 / O2 etching gas to etch when approaching the etch stop layer, and the etching rate shall not exceed 10nm / min. The heterojunction of the etch stop layer can have one or more layers, or it can be the third AlN layer on the channel layer, such as Fig.17 shown.

[0118] 6. After etching, dry and wet surface repair treatments are performed, and a 2-100nm SiN passivation layer is grown on the remaining etch stop layer using MOCVD, such as Fig.18 shown.

[0119] 7. Using photoresist as a mask, use RIE to etch away the SiN passivation layer in the source and drain regions, and use ICP etching technology to etch away the remaining etch stop layer in the source and drain regions, such as Fig.19 shown.

[0120] 8. Electron beam evaporation technology was used to evaporate metal Ti / Al / Ni / Au, and annealed at 850℃ for 30s. Fig. 20 shown.

[0121] 9. Device isolation fabrication: Use photoresist as a mask and use ICP to etch away the heterojunction outside the active area, such as Fig.21 shown.

[0122] 10. Photolithography of the gate contact area, using RIE and slow ICP etching, until the AlGaN layer on the channel layer is etched, such as Fig. 22 shown.

[0123] 11. Use photolithography to define the gate cap part, and use electron beam evaporation equipment to evaporate metal Ni / Au as the gate, such as Fig.23 shown.

[0124] 12. Make the source and drain lead Au pads, and connect the source metal to the support layer, such as Fig.24 shown.

[0125] At this point, the preparation of an N-polar heterojunction III-V semiconductor triode has been completed.

[0126] The mobility of the nitrogen-polar GaN heterojunction after etching a GaN / AlGaN (~10nm / 5nm) stop layer is about ~2000cm 2 / Vs, the channel two-dimensional electron gas concentration is about 1.0×10 13 cm -2 , the interface state density on the heterojunction surface is less than 10 11 eV -1 cm -2 .

[0127] Example 3

[0128] This embodiment illustrates a process of growing a reverse epitaxial structure and preparing a corresponding N-polarity GaN device based on the structure, which specifically includes the following steps:

[0129] 1. Use chemical vapor deposition (MOCVD) equipment to sequentially grow AlN nucleation layer, AlGaN transition layer, GaN buffer layer 1, GaN / AlGaN (~20nm / 20nm) 2 heterojunction stop layer, GaN channel layer, AlGaN barrier layer, GaN high resistance layer on silicon substrate, such as Fig.25 shown.

[0130] 2. Bond the support layer on the buffer layer 2 using a bonding method, such as Fig.26 shown.

[0131] 3. Remove the silicon substrate through thinning, polishing and deep silicon etching processes. Fig. 27 Shown

[0132] 4. Etch the nucleation layer and transition layer by ICP dry etching process.

[0133] 5. Etch the buffer layer by ICP dry etching process, and use BCl3 / SF6 or BCl3 / O2 etching gas to etch when approaching the etch stop layer. The heterojunction of the etch stop layer can have one or more layers, or it can be the second AlGaN layer on the channel layer, such as Fig.28 shown.

[0134] 6. After etching, dry and wet surface repair treatments are performed, and a 2-100nm SiN passivation layer is grown on the remaining etch stop layer using MOCVD, such as Fig.29 shown.

[0135] 7. Using photoresist as a mask, use RIE to etch away the SiN passivation layer in the source and drain regions, and use ICP etching technology to etch away the remaining etch stop layer in the source and drain regions, such as Fig.30 shown.

[0136] 8. Electron beam evaporation technology was used to evaporate metal Ti / Al / Ni / Au, and annealed at 850℃ for 30s. Fig.31 shown.

[0137] 9. Device isolation fabrication: Use photoresist as a mask and use ICP to etch away the heterojunction outside the active area, such as Fig.32 shown.

[0138] 10. Photolithography of the gate contact area, using RIE and slow ICP etching, until the AlGaN layer on the channel layer is etched, such as Fig.33 shown.

[0139] 11. Use photolithography to define the gate cap part, and use electron beam evaporation equipment to evaporate metal Ni / Au as the gate, such as Fig.34 shown.

[0140] At this point, the preparation of an N-polar heterojunction III-V semiconductor triode has been completed.

[0141] The mobility of the nitrogen-polar GaN heterojunction after etching a GaN / AlGaN (~10nm / 5nm) stop layer is about ~2000cm 2 / Vs, the channel two-dimensional electron gas concentration is about 1.0×10 13 cm -2 , the interface state density on the heterojunction surface is less than 10 11 eV -1 cm -2 .

[0142] Comparative Example 1

[0143] This comparative example is substantially the same as Example 1, except that:

[0144] In step 1, after the GaN buffer layer, only one layer of AlGaN with a thickness of 10 nm is grown as an etching stop layer.

[0145] The remaining steps and parameter conditions are consistent with those in Example 1.

[0146] In the comparative example, since the etching stop layer is very thin, a very dense surface state will be generated when etching reaches the stop layer, thereby affecting the channel layer through the thin stop layer.

[0147] The mobility of the etched nitrogen-polar GaN heterojunction is about 1500 cm 2 / Vs, the channel two-dimensional electron gas concentration is about 1.0×10 13 cm -2 , the interface state density on the heterojunction surface is greater than 10 13 eV -1 cm -2 .

[0148] Example 4

[0149] This embodiment is substantially the same as Embodiment 1, and the main difference is that:

[0150] The material of the first sublayer is replaced by InGaN, the material of the second sublayer is replaced by AlInN, and the number of cycles n is replaced by 1.

[0151] The obtained inverse epitaxial structure can still play a very excellent etching stop role, and the device finally obtained can effectively reduce the interface roughness and interface state density of the V-group polar heterojunction after etching, and can obtain a stable, uniform and high-quality V-group polar heterojunction device with high carrier density and high mobility. The performance is similar to that of Example 1, and is significantly improved compared to the traditional etch stop layer.

[0152] Example 5

[0153] This embodiment is substantially the same as Embodiment 1, and the main difference is that:

[0154] The material of the first sublayer is replaced with InGaN, the material of the second sublayer is replaced with AlInN, and the number of cycle periods n is replaced with 10.

[0155] The obtained reverse epitaxial structure can still play a very excellent etching stop role, and the various performances of the device finally obtained are similar to those of Example 1, and are significantly improved compared to the traditional etching stop layer.

[0156] Based on the above embodiments and comparative examples, it can be clearly seen that the present invention innovatively proposes to use a multi-layer heterojunction material layer design as an etch stop layer, which can not only realize an active layer structure with a certain thickness as required, but also effectively reduce the interface roughness and interface state density of the nitrogen-polar GaN heterojunction. Further, the introduction of an etch stop layer away from the channel is conducive to regulating the heterojunction energy band, realizing a stable, uniform, high-quality nitrogen-polar GaN heterojunction with high carrier density and high mobility, and thus realizing a high-performance RF device. Moreover, after flipping, the total thickness of the high-resistance layer from the support layer can be adjusted between tens of nm and several μm as required, which is not only more conducive to heat dissipation, further improving the power density of the device, but also avoiding the back-through hole process.

[0157] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. An epitaxial structure of a III-V semiconductor, comprising a substrate, an intermediate layer, an etch stop layer, a channel layer and a barrier layer stacked in sequence along a specified direction; The channel layer and the barrier layer form a heterojunction, the direction from the heterojunction to the substrate is the V group polarity of the material; the direction from the etch stop layer to the heterojunction is the III group polarity of the material; It is characterized in that The etch stop layer includes a first sublayer and a second sublayer periodically stacked along the designated direction. When the etch stop layer is etched, an etching rate of the first sublayer is higher than that of the second sublayer.

2. The epitaxial structure according to claim 1, characterized in that: The intermediate layer includes a nucleation layer, a transition layer and a buffer layer stacked in sequence along the specified direction; And / or, the epitaxial structure further includes a high resistance layer arranged on the surface of the barrier layer.

3. The epitaxial structure according to claim 1, characterized in that: The material of the first sublayer includes any one of GaN, InGaN, and InN, or a combination of two or more thereof; And / or, the material of the second sub-layer includes any one of AlGaN, AlN, AIInN, AlInGaN, AlInN, or a combination of two or more thereof; And / or, the group III polar surface is a Ga polar surface, and the group V polar surface is an N polar surface.

4. The epitaxial structure according to claim 1, characterized in that: The thickness of the first sublayer is 2-500 nm; and / or, the thickness of the second sublayer is 1-50 nm; And / or, the number of periods of the periodic stacking is 1-10.

5. The epitaxial structure according to claim 1, characterized in that: When the etch stop layer is etched, an etching rate of the first sub-layer is greater than twice an etching rate of the second sub-layer.

6. The method for growing an epitaxial structure according to any one of claims 1 to 5, characterized in that: include: growing an intermediate layer on a surface of the substrate; Periodically growing a first sublayer and a second sublayer of the stack on the surface of the intermediate layer to form an etching stop layer; A channel layer and a barrier layer are sequentially grown on the surface of the etch stop layer to form a heterojunction, wherein the heterojunction has a group III polarity surface and a group V polarity surface, wherein the group III polarity is the direction from the etch stop layer to the heterojunction.

7. The growth method according to claim 6, characterized in that: Also includes: A high resistance layer is grown on the surface of the barrier layer.

8. A method for preparing a group V polar III-V semiconductor structure, characterized in that: include: Providing an epitaxial structure according to any one of claims 1 to 5; Covering the surface of the epitaxial structure away from the substrate with a support layer; The substrate, the intermediate layer and a selectable part of the etching stop layer in the epitaxial structure are etched and removed to obtain a III-V semiconductor structure of III polarity.

9. The preparation method according to claim 8, characterized in that: After the etch stop layer is etched, at least a layer of the second sub-layer closest to the channel layer is retained.

10. A group V polar III-V semiconductor structure obtained by the preparation method according to any one of claims 8 to 9.

11. A III-V semiconductor device, characterized in that: It comprises the III-V semiconductor structure as described in claim 10 and a plurality of electrodes, wherein the electrodes pass through the etch stop layer remaining after etching to form ohmic contact with the channel layer, and / or part of the electrodes are isolated from the channel layer by the etch stop layer and form electrical interaction with the channel layer.

12. The III-V semiconductor device according to claim 11, characterized in that: The electrodes include a source electrode, a drain electrode and a gate electrode; And / or, the III-V semiconductor device includes any one of a diode and a triode.

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