Transistor structure with multiple vertical thin bodies

Abstract

The invention discloses a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region, and a gate region. The semiconductor body is provided with a convex structure, and the convex structure is provided with at least four conductive channels extending upwards. The source region is in contact with a first end of the convex structure. The drain region is in contact with a second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer crosses over the convex structure. Two or four conductive channels of the at least four conductive channels are not parallel to each other, and there is no shallow trench isolation region between the at least four conductive channels. Therefore, compared with the prior art, the transistor structure not only can effectively reduce the leakage current path of the transistor in the closed state, but also greatly increases the conduction current of the transistor in the on state.

Description

Technical Field

[0001] The present invention relates to a transistor structure, and in particular to a transistor structure having a plurality of vertical thin bodies, wherein the transistor structure having the plurality of vertical thin bodies can not only effectively reduce the leakage current path of the transistor in a closed state, but also greatly increase the conduction current of the transistor in a conducting state. Background Art

[0002] The single-chip integration of silicon integrated circuits has achieved more than 50 billion transistors on a single die in 2021, which is called the transition from the Very Large Scale Integration (VLSI) era (more than millions of transistors on a single die) to the Gigabit-Scale Integration (GSI) era (more than billions of transistors on a single die). This achievement of higher integration of transistors on a single die has greatly enabled more powerful microsystems, significantly improved the performance, power, area, and cost (PPAC) of microsystems, and created many powerful chips, such as central processing units (CPUs), graphic processing units (GPUs), field programmable gate arrays (FPGAs), systems on a chip (SOCs), static random-access memory (SRAMs), dynamic random access memory (DRAMs), etc., where these powerful chips can enhance system capabilities and continuously support Moore's Law to lay the foundation for creating exponential economic growth.

[0003] Since giant scale integrated circuits generate such high productivity to develop new applications, thus stimulating rapid growth in economic scale, there is a strong demand for integrating more transistors in one die. Therefore, it is expected that the semiconductor industry will do its best to move towards the TSI (Tera-Scale Integration) era, that is, integrating more than trillions of transistors on one die. Therefore, how to significantly improve transistors to meet this TSI challenge requires the invention and engineering improvements of some transistor structures that have fundamental changes in performance, power consumption, area and cost. For example, if 1 trillion transistors are indeed integrated on a die, and each transistor is set to have a standby current Ioff (or called shutdown current Ioff) of about 0.5 picoamperes (pA), then the standby current Ioff of 1 trillion transistors will be close to 0.5 amperes.

[0004] However, it is difficult for the most advanced transistors using technology less than 20 nanometers (nm) to achieve a standby current Ioff of 0.5 pA. Even if various transistor structures (such as Fin Field-Effect Transistor (FinFET) or three-gate transistor designs) are used, the standby current Ioff of some transistor structures is still as high as 5 to 10 pA. Therefore, how to continuously reduce the size of transistors and reduce their standby current Ioff (for example, below 1 pA) is a key challenge for the semiconductor industry.

[0005] Figure 1 is a schematic diagram illustrating a fin field effect transistor (FinFET) having an active region formed into a fin structure in the prior art. Figure 1As shown, the gate structure 5 of the fin field effect transistor is formed above the fin structure or a three-dimensional convex silicon surface, and the gate structure 5 includes some conductive materials (such as metal, polysilicon, or polyside, etc.) on an insulator or dielectric layer (such as oxide, oxide / nitride, or some high-k materials, etc.). Taking an N-type metal-oxide-semiconductor (MOS) transistor as an example, the source region 11 and the drain region 12 of the fin field effect transistor are formed by implanting high-concentration n-type (n+) dopants into a p-type substrate (or p-well) through ion implantation plus thermal annealing technology, thereby forming two separated heavily doped n+ / p junctions (n+ / p junctions) in the p-type substrate (or p-well). In addition, in order to reduce impact ionization and hot carrier injection in front of the heavily doped n+ / p junction, n- lightly doped-drains (LDD) 13 are usually formed in front of the source region 11 and the drain region 12 by ion implantation plus thermal annealing technology. Figure 1 As shown, such ion implantation plus thermal annealing technique often results in the lightly doped drain 13 penetrating into the portion of the active region below the gate structure 5. Therefore, the length of the effective channel 14 between the lightly doped drains 13 is inevitably shortened.

[0006] On the other hand, the progress of process technology is continuously and rapidly shrinking the geometric size of the N-type metal oxide semiconductor transistor in horizontal and vertical directions (for example, the minimum feature size called Lamda (λ) has been reduced from 28 nanometers (nm) to 5nm or 3nm). However, due to the shrinking geometric size of the fin field effect transistor (FinFET), the following problems are caused or made worse:

[0007] (1) As the length of the gate structure 5 decreases, it becomes increasingly difficult to reduce the standby current Ioff. Figure 2 The fin structure is formed in the fin structure, rather than only along the surface of the fin structure. Figure 3 Is to describe the evaluation and simulation Figure 2 The schematic diagram of the leakage current path is shown in Figure 3 (a) is the structure of a 3D fin field effect transistor simulated by Technology Computer-Aided Design (TCAD). Figure 3 (b) corresponds to Figure 3 (a) is a cross-sectional view of the structure of the 3D FinFET as shown in the red dashed rectangle 18, and Figure 3 (c) is the current distribution of the 3D fin field effect transistor when it is in the off state (that is, the standby current Ioff) (see "Impact of Current Flow Shape in Tapered (Versus Rectangular) FinFET on Threshold Voltage Variation Induced by Work-Function Variation", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014).

[0008] (2) Because the dimensions in both the horizontal and vertical directions must be reduced simultaneously, it is increasingly difficult to perfectly align the junction edge of the lightly doped drain 13 (or the edge of the source region 11 / drain region 12) with the edge of the gate structure 5 using only the conventional self-alignment method formed by the gate, spacer, and ion implantation. In addition, the thermal annealing technique used to eliminate the damage caused by the ion implantation must rely on high temperature processing techniques (e.g., rapid thermal annealing methods using various energy sources or other thermal processes). One problem derived from this is that although the gate-induced drain leakage (GIDL) current should be minimized to reduce the leakage current, the generation of the gate-induced drain leakage current is difficult to control. Another problem derived from this is that because the length of the effective channel 14 is difficult to control, the short channel effect (SCE) is difficult to minimize. In addition, the relative position between the edge of the source region 11 / drain region 12 and the edge of the gate structure 5 is also difficult to adjust to control the gate-induced drain leakage (GIDL) current.

[0009] (3) In addition, since the ion implantation for forming the lightly doped drain 13 (or the n+ / p junction in an N-type metal oxide semiconductor transistor or the p+ / n junction in a P-type metal oxide semiconductor transistor) is similar to bombardment so as to inject ions directly from the top of the silicon surface downward into the substrate, it is difficult to create a uniform material interface with low defects from the source region 11 and the drain region 12 to the effective channel 14 and the substrate-body region (because the distribution of the doping concentration in the vertical direction is not uniform, for example, in the vertical direction is from the top surface with a higher doping concentration to the junction with a lower doping concentration).

[0010] (4) In addition, when the size in the horizontal direction is reduced to 7nm, 5nm or 3nm, the height of the fin structure of the N-type metal oxide semiconductor transistor (for example, 40 to 100nm) is much larger than the width of the fin structure of the N-type metal oxide semiconductor transistor (for example, 3 to 10nm), thereby making the fin structure of the N-type metal oxide semiconductor transistor very fragile or even collapsed in the subsequent process (for example, forming the source region 11 / drain region 12, or the gate structure 5, etc.).

[0011] Therefore, the present invention discloses a new 3D transistor structure to solve the above-mentioned disadvantages of the FinFET. For example, the new 3D transistor structure can reduce the standby current Ioff by 10 to 100 times. Summary of the invention

[0012] One embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region, and a gate region. The semiconductor body has a convex structure, wherein the convex structure has at least four conductive channels extending upward. The source region contacts the first end of the convex structure. The drain region contacts the second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer spans over the top of the convex structure. Two conductive channels or four conductive channels among the at least four conductive channels are not parallel to each other, and there is no shallow trench isolation region between the at least four conductive channels.

[0013] In one embodiment of the present invention, a trench is formed in the convex structure, the trench is located between the first end and the second end, and the first portion of the gate conductive layer is filled in the trench.

[0014] In one embodiment of the present invention, the convex structure includes a group of thin bodies extending upward, and each thin body includes two conducting channels along the sidewalls of the thin body among the at least four conducting channels.

[0015] In one embodiment of the present invention, the trench is between two thin bodies in the group of thin bodies, a gate dielectric layer spans over the convex structure, and the first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench.

[0016] In an embodiment of the present invention, the groove is in a cone shape.

[0017] In one embodiment of the present invention, the convex structure comprises at least four upwardly extending conductor-oxide-semiconductor surfaces, and the at least four conductor-oxide-semiconductor surfaces are horizontally offset from each other.

[0018] An embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region and a gate region. The semiconductor body has a convex structure, wherein the convex structure has an original surface, the convex structure includes two thin bodies extending upward, and the two thin bodies are separated from each other. The source region contacts the first end of the convex structure. The drain region contacts the second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer spans the top of the convex structure. Each thin body is conical, and there is no shallow trench isolation region between the two thin bodies.

[0019] In one embodiment of the present invention, a trench is formed in the convex structure, the trench is located between the first end and the second end, and the first portion of the gate conductive layer is filled in the trench.

[0020] In one embodiment of the present invention, each thin body includes two conducting channels extending upward.

[0021] In one embodiment of the present invention, the trench separates the two thin bodies, a gate dielectric layer spans over the convex structure, and the first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench.

[0022] One embodiment of the present invention provides a transistor structure. The transistor structure includes a semiconductor body, a source region, a drain region, a gate region, a trench and an air electrode. The semiconductor body has a convex structure, wherein the convex structure has an original surface, and the convex structure includes two thin bodies extending upward. The source region is in contact with the first end of the convex structure. The drain region is in contact with the second end of the convex structure. The gate region has a gate conductive layer, wherein the gate conductive layer spans over the top of the convex structure. The trench is formed in the convex structure and is located between the first end and the second end, wherein the trench separates the two thin bodies. The air electrode is located in the trench and is covered by the gate conductive layer.

[0023] In an embodiment of the present invention, the convex structure includes a first outer sidewall and a second outer sidewall covered by the gate conductive layer, and the convex structure further includes a first inner sidewall and a second inner sidewall in the trench.

[0024] In one embodiment of the present invention, the transistor structure further comprises a first recess and a second recess. The first recess is used to accommodate the source region. The second recess is used to accommodate the drain region. The sidewalls of the first recess and the second recess are surrounded by a shallow trench isolation region.

[0025] In one embodiment of the present invention, the edge of the source region contacts the two thin bodies, and the edge of the drain region also contacts the two thin bodies.

[0026] In one embodiment of the present invention, the source region includes a lightly doped drain region, a heavily doped region and a metal region. The lightly doped drain region is in contact with the two thin bodies. The heavily doped region extends laterally from the lightly doped drain region. The metal region is located in the first recess and in contact with a side wall of the heavily doped region.

[0027] In one embodiment of the present invention, the width of each thin body is no greater than 3 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram illustrating a finfield-effect transistor (FinFET) having an active region formed as a fin structure in the prior art.

[0029] Figure 2 is a schematic diagram illustrating a higher leakage current path formed within a fin structure.

[0030] Figure 3 It is a diagram illustrating the structure of a 3D FinFET under Technology Computer-Aided Design (TCAD) simulation, a cross-sectional view of the structure of the 3D FinFET, and a schematic diagram of current distribution of the 3D FinFET in an off state.

[0031] Figure 4A It is a flow chart of a method for manufacturing a vertical thinbody field-effect transistor (VTBFET) disclosed in one embodiment of the present invention.

[0032] Figure 4B , Figure 4C , Figure 4D , Figure 4E Yes Description Figure 4A Schematic diagram of .

[0033] Figure 5 is a schematic diagram illustrating growing a pad oxide layer, depositing a pad nitride layer, and forming a trench.

[0034] Figure 6 is a schematic diagram illustrating depositing an oxide spacer layer on a p-type well and then depositing a nitride spacer layer on the oxide spacer layer.

[0035] Figure 7is a schematic diagram illustrating the formation of shallow trench isolation regions and the deposition of a nitride layer.

[0036] Figure 8 It is a schematic diagram illustrating that the gate region spans across the active region and the shallow trench isolation region.

[0037] Fig. 9 is a schematic diagram illustrating the removal of the lithography mask.

[0038] Fig.10 1 is a schematic diagram for explaining the formation of a carbon silicon oxide spacer-2 layer and the formation of a recess (or a groove) based on the carbon silicon oxide spacer-2 layer.

[0039] Fig.11 is a schematic diagram illustrating forming a dielectric layer to fill a recess to form a central electrode, and then forming a nitride cap layer over the central electrode.

[0040] Fig.12 is a schematic diagram illustrating etching back the exposed shallow trench isolation region to form the vertical convex structure in the defined gate region.

[0041] Fig.13 is a schematic diagram illustrating the use of etching to remove the nitride cap and carbon silicon oxide spacer-2 layer near the center pole correlation region.

[0042] Fig.14 It is a schematic diagram for explaining the removal of the liner oxide layer near the center pole related area and the oxide spacer layer covering the convex structure, and etching the shallow trench isolation area corresponding to the center pole related area.

[0043] Fig.15 is a schematic diagram illustrating that the center pole is removed to expose the groove-2.

[0044] Fig.16 is a schematic diagram illustrating forming a gate dielectric layer and depositing a gate conductive material in a gate region.

[0045] Fig.17 is a schematic diagram illustrating deposition of a cap layer and etching of shallow trench isolation regions.

[0046] Fig.18 It is a schematic diagram for explaining etching away the pad nitride layer and the pad oxide layer, etching back a portion of the shallow trench isolation region, and forming an oxide spacer-2 layer and a nitride spacer-2 layer on the edge of the gate region.

[0047] Fig.19 is a schematic diagram illustrating etching away some exposed silicon to form shallow trenches for source and drain regions of the vertical thin-body field effect transistor, growing an oxide-3 layer using a thermal oxidation process, and depositing nitride using chemical vapor deposition technology and etching back the nitride.

[0048] Fig. 20 is a schematic diagram illustrating depositing a tungsten layer and then depositing a titanium nitride layer over the tungsten layer.

[0049] Fig.21 is a schematic diagram illustrating etching away the oxide-3V layer to expose the silicon sidewall, then forming an n-type lightly doped drain, an n+ doped source and an n+ doped drain, and then depositing a titanium nitride layer and a tungsten layer.

[0050] Fig. 22 is a schematic diagram illustrating that a bonding pad is formed on an n+ doped source and an n+ doped drain.

[0051] Fig.23 is a schematic diagram illustrating a simulation result of a computer-aided design of a conventional fin field effect transistor and a vertical thin-body field effect transistor regarding on-state current.

[0052] Fig.24 is a schematic diagram illustrating a simulation result of a computer-aided design of the off current of a conventional fin field effect transistor and a vertical thin-body field effect transistor.

[0053] Fig.25 is a schematic diagram illustrating the structural difference between the conventional fin field effect transistor and the vertical thin-body field effect transistor.

[0054] Fig.26 and Figure 26-1 FIG. 2 is a schematic diagram illustrating forming a center electrode and a gate structure according to a second embodiment of the present invention.

[0055] Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 and Fig.34 FIG. 2 is a schematic diagram illustrating forming a vertical thin-body field effect transistor with a tapered central pole according to a third embodiment of the present invention.

[0056] The reference numerals are described as follows:

[0057] 5. Gate structure

[0058] 11 Source

[0059] 12 Drain region

[0060] 13 n-lightly doped drain

[0061] 14 Valid channels

[0062] 16 Dashed rectangular area

[0063] 18 Red dotted rectangle

[0064] 200 Semiconductor substrate

[0065] 202 p-type well

[0066] 204 Pad Oxide Layer

[0067] 206 pad nitride layer

[0068] 304 Oxidation Spacer

[0069] 306 Nitrided spacer

[0070] 402 Shallow Trench Isolation Area

[0071] 802, 15062, 1904 Nitride layer

[0072] 902 Micro-Shadow Mask

[0073] 904, 1202, 2904 Depression

[0074] 1102 Carbon Silicon Oxide Spacer - 2 Layers

[0075] 1302, 2601 center pole

[0076] 1402 Nitride Cap Layer

[0077] 1501 Groove-2

[0078] 1502 Gate dielectric layer

[0079] 1504 Gate Conductive Material

[0080] 15042 Top gate conductive part 1506 cap layer 15064 Hard mask oxide layer

[0081] 1802 Oxide Spacer - 2 layers 1804 Nitride Spacer - 2 layers

[0082] 1902 Shallow Groove

[0083] 1002 Oxide-3 layers

[0084] 10022 Oxide-3V layer

[0085] 10024 Oxide-3B layer

[0086] 1906, 2014 Tungsten layer

[0087] 1908, 2012 Titanium nitride layer

[0088] 2002 Silicon Sidewall

[0089] 2004、2006 n-type lightly doped drain

[0090] 2008 n+ doped source

[0091] 2010 N+ doped drain

[0092] 2102, 2104, 2106, 2108 Conductor-Oxide-Semiconductor Structures

[0093] 2202 Joint pad

[0094] 2502, 2504, 2506, 2508 N+ zone

[0095] 2602 Compliant Dielectric Pad

[0096] 2604 Non-compliant dielectric

[0097] 2606 Air Electrode

[0098] 2702 Semiconductor layer

[0099] 2902, 3002 Micro-Shadow Mask

[0100] 3102 thin body

[0101] 3302 Groove

[0102] 3402 Conical center pole

[0103] A, B length

[0104] G1~G3 vertical gate conductive part

[0105] Leff effective channel length

[0106] Lpole Pole length

[0107] OHS Original Horizontal Surface STI Shallow Trench Isolation

[0108] Sright, Sleft, VTB vertical thin body

[0109] Steps 10-50, 102-154 DETAILED DESCRIPTION

[0110] Please refer to Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 5 , Figure 6, Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 ,in Figure 4A is a flow chart of a method for manufacturing a vertical thin body field-effect transistor (VTBFET) disclosed in one embodiment of the present invention, and Figure 4A The manufacturing method of the vertical thin-body field effect transistor can make the vertical thin-body field effect transistor have lower standby current, lower gate-induced drain leakage (GIDL) current and lower short channel effect (SCE), and can form a solid fence wall to clamp the active region or narrow convex structure of the vertical thin-body field effect transistor. In addition, the detailed steps of the manufacturing method of the vertical thin-body field effect transistor (taking an N-type metal-oxide-semiconductor (MOS) transistor as an example) are as follows:

[0111] Step 10: Start;

[0112] Step 20: On the basis of the semiconductor substrate 200, an active region is defined and a convex structure having a plurality of current conducting channels or a plurality of vertical thin bodies is formed;

[0113] Step 30: forming a gate region of the vertical thin-body field effect transistor;

[0114] Step 40: forming a source region and a drain region of the vertical thin-body field effect transistor;

[0115] Step 50: End.

[0116] Please refer to Figure 4B , Figure 4C , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 Step 20 includes:

[0117] Step 102: Generate a pad oxide layer 204 and deposit a pad nitride layer 206;

[0118] Step 104: defining the active region by using a photolithographic mask technique, and removing a portion of the semiconductor material (eg, silicon) outside the active region to form the convex structure;

[0119] Step 106: depositing a nitride spacer 306 (or an oxide spacer 304 and a nitride spacer 306) to surround the active region, and etching back the nitride spacer 306 (or an oxide spacer 304 and a nitride spacer 306);

[0120] Step 108: Deposit an oxide layer and use chemical mechanical polishing (CMP).

[0121] Using CMP (Chemical Processing) technology to remove excess oxide layer to form shallow trench isolation (STI) region 402;

[0122] Step 110: depositing a thin nitride layer 802;

[0123] Step 112: using a lithography mask 902 to define a gate region spanning the active region and above the shallow trench isolation region 402, and etching away the nitride layer 802 and the pad nitride layer 206 corresponding to the gate region;

[0124] Step 114: Remove the lithography mask 902, wherein a central pole correlation region is defined in the active region.

[0125] (central pole related area);

[0126] Step 116: depositing a carbon silicon oxide (SiCOH) layer (or a combination of an oxide layer / nitride layer) to form a carbon silicon oxide spacer-2 layer 1102;

[0127] Step 118: Based on the carbon silicon oxide spacer-2 layer 1102 and the nitride layer 802, a depression (or groove) 1202 is formed in the convex structure by using anisotropic etching technique;

[0128] Step 120: forming a dielectric layer (e.g., thermal oxide) as a center pole 1302 to fill the recess 1202; Step 122: depositing a nitride-3 layer and etching back the nitride-3 layer to form a nitride cap layer 1402; Step 124: etching back the exposed shallow trench isolation region 402 to establish the convex structure in the gate region;

[0129] Step 126: removing the nitride layer 802, the nitride spacer layer 306, the nitride cap layer 1402 and the carbon silicon oxide spacer-2 layer 1102 near the center pole related area;

[0130] Step 128: Remove the oxide spacer layer 304, the center pole 1302 and the liner oxide layer 204 near the center pole related area.

[0131] Please refer to Figure 4D , Fig.16 , Fig.17 , Fig.18 Step 30 comprises:

[0132] Step 130: forming a gate dielectric layer 1502 in the gate region;

[0133] Step 132: depositing a gate conductive material 1504 in the gate region, and then etching back the gate conductive material 1504;

[0134] Step 134: forming a cap layer 1506 and polishing the cap layer 1506 by the chemical mechanical polishing technique; Step 136: etching back the shallow trench isolation region 402;

[0135] Step 138: Etch away the pad nitride layer 206 and the pad oxide layer 204 to expose the original horizontal surface

[0136] (original horizontal surface)OHS;

[0137] Step 140: Form an oxide spacer-2 layer 1802 and a nitride spacer-2 layer 1804 on the edges of the gate conductive material 1504 and the cap layer 1506.

[0138] Please refer to Figure 4E , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 Step 40 comprises:

[0139] Step 142: Etching away the exposed silicon;

[0140] Step 144: thermally grow oxide-3 layer 1002;

[0141] Step 146: forming a nitride layer 1904;

[0142] Step 148: forming a tungsten layer 1906;

[0143] Step 150: forming a titanium nitride (TiN) layer 1908;

[0144] Step 152: Etching away a portion of the oxide-3 layer 1002;

[0145] Step 154 ​​: forming n-type lightly doped drains (LDD) 2004 and 2006 , and then forming n+ doped source 2008 and n+ doped drain 2010 .

[0146] The detailed description of the above manufacturing method is as follows. Taking an N-type metal oxide semiconductor transistor as an example, it starts from a well-designed doped p-type well 202 mounted in a semiconductor substrate 200 (for example, in a p-type semiconductor substrate) (wherein in another embodiment of the present invention, it can start from the semiconductor substrate 200 instead of the p-type well 202), wherein in one embodiment of the present invention, the top surface of the p-type well 202 is about 500nm thick from the original horizontal surface OHS. In addition, for example, the semiconductor substrate 200 has a concentration close to 1x1016 dopant / cm3, but the actual doping concentration will be determined by the final mass production optimization.

[0147] In step 102, if Figure 5 As shown in FIG. 5( a ), a pad oxide layer 204 with a well-designed thickness is grown above the original horizontal surface OHS, and a pad nitride layer 206 with a well-designed thickness is deposited above the top surface of the pad oxide layer 204 .

[0148] In step 104, if Figure 5 As shown in (a), the active region of the vertical thin-body field effect transistor is defined by the anisotropic etching technology using the lithography mask technology, wherein the anisotropic etching technology removes part of the semiconductor material (e.g., silicon) outside the active region to form a trench (e.g., about 300 nanometers (nm) deep) to meet the needs of future shallow trench isolation regions 402, thereby also creating a convex structure of the active region. In addition, Figure 5 (b) is related to Figure 5 (a) The corresponding top view, where Figure 5 (a) is along Figure 5 (b) is a cross-sectional view taken along the X-direction cutting line.

[0149] In step 106, if Figure 6As shown in (a), an oxide spacer 304 is deposited at the edge of the active region, and then a nitride spacer 306 is deposited on the oxide spacer 304 (or the nitride spacer 306 is only deposited at the edge of the active region), and the anisotropic etching technology is used to etch back the oxide spacer 304 and the nitride spacer 306 so that the top surfaces of the oxide spacer 304 and the nitride spacer 306 are flush with the original horizontal surface OHS, wherein the oxide spacer 304 and the nitride spacer 306 are located outside the active region. Therefore, the key to step 106 is that the oxide spacer 304 and the nitride spacer 306 (or only the nitride spacer 306) form a solid fence wall (i.e., an isolation wall) to clamp the active region or the narrow convex structure, especially the sidewall of the convex structure. In addition, the strong fence wall can be a single layer (e.g., nitride spacer 306) or other composite layers (e.g., oxide spacer 304 and nitride spacer 306) to protect the narrow convex structure or the fin structure from collapsing during the formation of the source / drain or gate region of the vertical thin body field effect transistor.

[0150] In step 108, if Figure 7 As shown in (a), a thick oxide layer is deposited to completely fill the trench surrounding the active region, and the excess oxide layer is removed using the chemical mechanical polishing technique to form a shallow trench isolation region 402, wherein the top surface of the shallow trench isolation region 402 is flush with the top surface of the pad nitride layer 206. Similarly, the shallow trench isolation region 402 further surrounds or clamps the active region or the narrow convex structure, especially the sidewall of the convex structure, to protect the narrow convex structure from collapse during the formation of the source / drain or gate region of the vertical thin body field effect transistor.

[0151] In step 110, if Figure 7 As shown in (a), a nitride layer 802 is deposited on the pad nitride layer 206 and the shallow trench isolation region 402. In addition, Figure 7 (b) is related to Figure 7 (a) The corresponding top view, where Figure 7 (a) is along Figure 7 (b) is a cross-sectional view taken along the X-direction cutting line.

[0152] In step 112, if Figure 8 As shown in (a), a lithography mask 902 is used to define a gate region across the active region and above the shallow trench isolation region 402, thereby removing the nitride layer 802 and the liner nitride layer 206 corresponding to the gate region to form a recess 904. In addition, Figure 8 (b) is related to Figure 8 (a) The corresponding top view, where Figure 8 (a) is along Figure 8(b) is a cross-sectional view of the X-direction cutting line and Figure 8 (c) is along Figure 8 (b) is a cross-sectional view taken along the Y direction cutting line.

[0153] In step 114, if Fig. 9 As shown in (a), the lithography mask 902 is removed. In this way, a smooth edge of the gate region for the vertical thin-body field effect transistor is achieved, and the center pole related region is also defined in the active region, wherein the smooth edge is the edge of the nitride layer 802 and the liner nitride layer 206. In addition, Fig. 9 (b) is related to Fig. 9 (a) The corresponding top view, where Fig. 9 (a) is along Fig. 9 (b) is a cross-sectional view taken along the X-direction cutting line.

[0154] In step 116, if Fig.10 As shown in (a), the carbon silicon oxide layer (or the combination of the oxide layer / the nitride layer) is deposited in the central pole related area and etched back to form a carbon silicon oxide spacer-2 layer 1102 (wherein, for example, the width of the carbon silicon oxide spacer-2 layer 1102 may be 1-3 nm). Fig.10 As shown in (b), the carbon silicon oxide spacer-2 layer 1102 is located on the four surrounding edges within the central pole related area, and the carbon silicon oxide spacer-2 layer 1102 is used to protect the original silicon area below, wherein the original silicon area below the carbon silicon oxide spacer-2 layer 1102 serves as a surrounding ring of silicon (or surrounding Si ring) on ​​the central pole (SRS-CP) generated later.

[0155] In step 118, if Fig.10 As shown in (a), based on the carbon silicon oxide spacer-2 layer 1102 and the nitride layer 802, the anisotropic etching technology is used to etch the pad oxide layer 204 in the center pole related area and the semiconductor material of the semiconductor substrate 200 to form a depression (or groove) 1202 with a depth of about 50 to 80 nm (for example, 75 nm) in the exposed silicon area. That is, the carbon silicon oxide spacer-2 layer 1102 and the nitride layer 802 act as a mask so that the exposed pad oxide layer 204 in the center pole related area is removed and the exposed silicon is also removed about 75 nm deep to form a depression 1202 in the center pole related area. Therefore, the carbon silicon oxide spacer-2 layer 1102 acts like a rain cover to protect the silicon surrounding ring (SRS-CP) to be created. In addition, Fig.10 (b) is related to Fig.10(a) The corresponding top view, where Fig.10 (a) is along Fig.10 (b) is a cross-sectional view of the X-direction cutting line and Fig.10 (c) is along Fig.10 (b) is a cross-sectional view taken along the Y direction cutting line.

[0156] In step 120, if Fig.11 As shown in (a), the dielectric layer is formed (for example, by short-time growth of thermal oxide or chemical vapor deposition (CVD) deposition) as a central pole 1302 to fill the recess 1202, wherein the central pole 1302 is also called a central oxide pole or a column pole (CP).

[0157] In step 122, if Fig.11 As shown in (a), the nitride-3 layer is then deposited and etched back to form a nitride cap layer 1402 above the central pole 1302 to protect the central pole 1302. In addition, Fig.11 (b) is related to Fig.11 (a) The corresponding top view, where Fig.11 (a) is along Fig.11 (b) is a cross-sectional view of the X-direction cutting line and Fig.11 (c) is along Fig.11 (b) is a cross-sectional view taken along the Y direction cutting line.

[0158] In step 124, if Fig.12 As shown in (a), the exposed shallow trench isolation region 402 is etched back to a depth of about 50 to 80 nm to form a vertical convex structure in the defined gate region, wherein, for example, the shallow trench isolation region 402 in the defined gate region is etched down by about 75 nm (i.e., the height of the convex structure). In one embodiment of the present invention, the height of the convex structure is the same or substantially the same as the height of the center pole 1302 calculated from the original horizontal surface OHS of the p-type well 202 to the bottom of the center pole 1302. In addition, Fig.12 (b) is related to Fig.12 (a) The corresponding top view, where Fig.12 (a) is along Fig.12 (b) is a cross-sectional view taken along the Y direction cutting line.

[0159] In step 126, if Fig.13As shown in (a), etching is used to remove the nitride cap 1402 and the carbon silicon oxide spacer-2 layer 1102 near the central pole related area, the nitride layer 802, and the nitride spacer layer 306 covering the convex structure in the defined gate area. In this way, the previously defined central pole related area appears again. In addition, Fig.13 (b) is related to Fig.13 (a) The corresponding top view, where Fig.13 (a) is along Fig.13 (b) is a cross-sectional view of the X-direction cutting line and Fig.13 (c) is along Fig.13 (b) is a cross-sectional view taken along the Y direction cutting line.

[0160] In step 128, if Fig.14 As shown in (a), the liner oxide layer 204 near the center pole related area and the oxide spacer 304 covering the convex structure are removed by etching. The shallow trench isolation region 402 defined outside the gate region can also be etched a certain amount (for example, about 40 to 80 nm deep), so that the top surface of the shallow trench isolation region 402 defined outside the gate region is lower than the top surface of the liner nitride layer 206. Therefore, Fig.14 As shown in (c), the two outer sides of the single crystal silicon of the convex structure are exposed. More importantly, Fig.14 As shown in (b), there is the silicon surrounding ring (SRS-CP) on the central pole 1302. In addition, Fig.14 (b) is related to Fig.14 (a) The corresponding top view, where Fig.14 (a) is along Fig.14 (b) is a cross-sectional view of the X-direction cutting line and Fig.14 (c) is along Fig.14 (b) is a cross-sectional view taken along the Y direction cutting line.

[0161] Afterwards, if Fig.15 As shown in (a), the center pole 1302 is removed to expose the groove-2 1501. Fig.15 As shown in (c), in the convex structure, there are two vertical thin bodies Sright and Sleft for conducting current during the on-state of the vertical thin body field effect transistor, wherein the vertical thin body Sright has an outer side wall and an inner side wall adjacent to the trench-2 1501, and the vertical thin body Sleft is also the same. Fig.15 As shown in (c), in the groove-2 1501, the inner side wall of the vertical thin body Sright faces the inner side wall of the vertical thin body Sleft. In addition, Fig.15 (b) is related to Fig.15 (a) The corresponding top view, where Fig.15 (a) is along Fig.15(b) is a cross-sectional view of the X-direction cutting line and Fig.15 (c) is along Fig.15 (b) is a cross-sectional view taken along the Y direction cutting line.

[0162] In step 130, if Fig.16 As shown in (a), a gate dielectric layer (such as a high dielectric (high K) material or oxide) 1502 is then formed in the defined gate region.

[0163] In step 132, if Fig.16 As shown in (a), a gate conductive material (such as polysilicon, or a metal such as tungsten on a titanium nitride layer, or other metals with a suitable work function) 1504 is then deposited in the gate region, and the excess gate conductive material 1504 is removed using the chemical mechanical polishing technique, and then the gate conductive material 1504 is etched back / polished. Of course, in the presence of a gate last process, the previously formed gate conductive material 1504 can be removed and replaced with other suitable gate conductive materials. The portion of the gate conductive material 1504 in the trench-2 1501 can be referred to as a "conductive central pole", and the conductive central pole is surrounded by the gate dielectric layer 1502 in the trench-2 1501. In addition, Fig.16 (b) is related to Fig.16 (a) The corresponding top view, where Fig.16 (a) is along Fig.16 (b) is a cross-sectional view of the X-direction cutting line and Fig.16 (c) is along Fig.16 (b) is a cross-sectional view taken along the Y direction cutting line.

[0164] In step 134, if Fig.17 As shown in (a), a cap layer 1506 composed of a nitride layer 15062 and a hard mask oxide layer 15064 is then deposited in the gate region on the top surface of the gate conductive material 1504, wherein the cap layer 1506 is used to protect the gate conductive material 1504. Then, the cap layer 1506 is polished by the chemical mechanical polishing technique so that the top surface of the cap layer 1506 is flush with the top surface of the pad nitride layer 206.

[0165] In step 136, if Fig.17 As shown in (a), the shallow trench isolation region 402 is then etched (if there is a gate dielectric layer 1502 above the shallow trench isolation region 402, it is also etched together) to make the top surface of the shallow trench isolation region 402 flush with the top surface of the liner oxide layer 204. In addition, Fig.17 (b) is related to Fig.17(a) The corresponding top view, where Fig.17 (a) is along Fig.17 (a) is a cross-sectional view taken along the X-direction cutting line.

[0166] In step 138, if Fig.18 As shown in (a), the pad nitride layer 206 and the pad oxide layer 204 are etched away to expose the original horizontal surface OHS. In addition, a portion of the shallow trench isolation region 402 is etched back to make the top surface of the shallow trench isolation region 402 flush with the original horizontal surface OHS.

[0167] In step 140, if Fig.18 As shown in (a), an oxide-2 layer is then deposited on the edge of the gate material 1504 and the cap layer 506 to form an oxide spacer-2 layer 1802 and a nitride-2 layer is deposited to form a nitride spacer-2 layer 1804 on the edge of the gate material 1504 and the cap layer 506. In addition, Fig.18 (b) is related to Fig.18 (a) The corresponding top view, where Fig.18 (a) is along Fig.18 (b) is a cross-sectional view taken along the X-direction cutting line.

[0168] In step 142, if Fig.19 As shown in (a), some of the exposed silicon in the active region is then etched away to form shallow trenches 1902 (eg, about 50 nm to 60 nm deep) for the source and drain regions of the vertical thin-body field effect transistor.

[0169] In step 144, if Fig.19 As shown in (a), a thermal oxidation process called oxide-3 process is used to grow oxide-3 layer 1002 (including oxide-3V layer 10022 (assuming a sharp crystal direction (110)) penetrating the vertical sidewalls of the vertical thin body field effect transistor body and oxide-3B layer 10024 above the bottom of the shallow trench 1902. Since some sidewalls of the shallow trench 1902 have a vertical composite of oxide spacer-2 layer 1802 and nitride spacer-2 layer 1804, and those sidewalls of the shallow trench 1902 are further surrounded by shallow trench isolation region 402, the oxide-3 process should only grow very little oxide (that is, oxide-3 layer 1002) on these walls, so that the width of the source / drain region of the vertical thin body field effect transistor is practically unaffected by the thermal oxidation process. In addition, oxide-3V layer 10022 and oxide-3B layer 10024 appear at Fig.19The thicknesses in (a) and subsequent figures are only for illustration of the present invention, and the geometry of the oxide-3V layer 10022 and the oxide-3B layer 10024 is not proportional to the size of the shallow trench isolation region 402 shown in those figures. For example, the thickness of the oxide-3V layer 10022 and the oxide-3B layer 10024 is about 20-30 nm, but the vertical height of the shallow trench isolation region 402 can be about 200-250 nm. Based on the oxide-3 process, the thickness of the oxide-3V layer 10022 can be very accurately controlled under precisely controlled thermal oxidation temperature, time and growth rate. Since the thermal oxidation process on a well-defined silicon surface results in 40% of the thickness of the oxide-3V layer 10022 being removed, the thickness of the silicon surface (110) exposed in the vertical wall of the body of the vertical thin body field effect transistor and the remaining 60% of the thickness of the oxide-3V layer 10022 are considered as additions to the vertical wall of the body of the vertical thin body field effect transistor. In addition, in one embodiment of the present invention, the edge of the oxide-3V layer 10022 can be aligned or substantially aligned with the edge of the gate region.

[0170] In step 146, if Fig.19 As shown in (a), a nitride is deposited on the top surface of the oxide-3B layer 10024 using the chemical vapor deposition technology, and the nitride is etched back to form a nitride layer 1904. In addition, Fig.19 (b) is related to Fig.19 (a) The corresponding top view, where Fig.19 (a) is along Fig.19 (b) is a cross-sectional view taken along the X-direction cutting line.

[0171] In step 148, if Fig. 20 As shown in (a), tungsten is deposited and etched back to form a tungsten layer 1906 on the top surface of the nitride layer 1904.

[0172] In step 150, if Fig. 20 As shown in (a), titanium nitride is then deposited (e.g., atomic layer deposition (ALD)) and etched back to form a titanium nitride layer 1908 above the top surface of the tungsten layer 1906. In addition, Fig. 20 (b) is related to Fig. 20 (a) The corresponding top view, where Fig. 20 (a) is along Fig. 20 (b) is a cross-sectional view taken along the X-direction cutting line.

[0173] In step 152, if Fig.21As shown in (a), a portion of the oxide-3V layer 10022 is then etched away using the top surface of the titanium nitride layer 1908 as a reference to expose the silicon sidewalls 2002 (having a crystal direction (110)).

[0174] In another embodiment of the present invention, Fig. 20 The step of forming the tungsten layer 1906 and the titanium nitride layer 1908 in the embodiment of the present invention can be omitted, and Fig.21 The portion of the oxide-3V layer 10022 that is etched may use the top surface of the nitride layer 1904 as a reference.

[0175] In step 154, if Fig.21 As shown in (a), a selective growth technique (e.g., selective epitaxy growth (SEG) technique) is then used to form n-type lightly doped drains 2004 and 2006, and then an n+ doped source 2008 and an n+ doped drain 2010 are formed. It is worth mentioning that when forming all the n-type lightly doped drains 2004, 2006, n+ doped source 2008 and n+ doped drain 2010 of the vertical thin-body field effect transistor, ion distribution is not required, and high-temperature thermal annealing is not required to eliminate the damage caused by heavy bombardment when forming the n+ doped source 2008 and the n+ doped drain 2010.

[0176] like Fig.21 As shown in (a), finally, a titanium nitride layer 2012 and a tungsten layer 2014 are deposited (for example, by atomic layer deposition) and the titanium nitride layer 2012 and the tungsten layer 2014 are etched back. In one embodiment of the present invention, Fig.21 As shown in (a), the bottom of the conductive center electrode is lower than the bottom of the oxide-3B layer 10024, and the heights of the n+ doped source 2008 and the n+ doped drain 2010 are approximately 40 to 60 nm.

[0177] In one embodiment of the present invention, the height of the convex structure (about 75 nm) is about 10 to 30 nm (for example, 20 nm) higher than the height of the n+ doped source 2008 and the n+ doped drain 2010 (or the height of the titanium nitride layer 2012 and the tungsten layer 2014). Therefore, the gap between the bottom of the gate region and the n+ doped source 2008 and the n+ doped drain 2010 (or the bottom of the titanium nitride layer 2012 and the tungsten layer 2014) is about 10 to 30 nm (for example, 20 nm). That is, the bottom of the gate region (gate dielectric layer 1502 or gate conductive material 1504) is lower than the bottom of the n+ doped source 2008 and the n+ doped drain 2010 (or the bottom of the titanium nitride layer 2012 and the tungsten layer 2014).

[0178] like Fig.21(c) Fig.21 (c) is a schematic diagram illustrating that the vertical thin-body field effect transistor has three vertical gate conductive portions G1 to G3, wherein the vertical gate conductive portions G1 to G3 are connected by the top gate conductive portion 15042 of the gate conductive material 1504. As described above, the four vertical sidewalls of the convex structure are covered by the gate dielectric layer 1502 and the gate conductive material 1504. In the vertical gate conductive portion G1, the gate conductive material 1504, the oxide (i.e., the gate dielectric layer 1502) and the semiconductor material (i.e., the p-type well 202) form a conductor-oxide-semiconductor structure 2102 along one outer sidewall of the convex structure, wherein the conductor-oxide-semiconductor structure 2102 is similar to a metal-oxide-semiconductor (MOS) structure. Similarly, in the vertical gate conductive portion G3, the gate conductive material 1504, the oxide (i.e., the gate dielectric layer 1502) and the semiconductor material (i.e., the p-type well 202) along the other outer sidewall of the convex structure form a conductor-oxide-semiconductor structure 2104. Similarly, in the vertical gate conductive portion G2 (or the conductive center pole), the gate conductive material 1504, the oxide (i.e., the gate dielectric layer 1502) and the semiconductor material (i.e., the p-type well 202) along the inner sidewall of the convex structure form another two conductor-oxide-semiconductor structures 2106 and 2108. Therefore, there are four conductor-oxide-semiconductor structures (or metal-oxide-semiconductor (MOS) structures) 2102, 2104, 2106 and 2108. According to the present invention, the uniqueness of the above embodiment is that the four conductor-oxide-semiconductor structures 2102, 2104, 2106 and 2108 share a source region and a drain region in the vertical thin-body field effect transistor. However, the present invention can be applied to the convex structure having multiple (e.g., 6 or 8) conductor-oxide-semiconductor structures (or metal-oxide-semiconductor (MOS) structures).

[0179] In another embodiment of the present invention, the material of the vertical gate conductive portion G2 may be different from or the same as the material of the vertical gate conductive portions G1, G3 (or the top gate conductive portion 15042).

[0180] In addition, if Fig.21 As shown in (a), due to the presence of the silicon surrounding ring in the convex structure, the length B of the gate conductive layer above the original horizontal surface OHS is longer than the length A of the conductive center pole. In addition, the lateral length of the outer side wall of the convex structure is greater than the lateral length of the inner side wall of the convex structure. In addition, Fig.21(b) is related to Fig.21 (a) The corresponding top view, where Fig.21 (a) is along Fig.21 (b) is a cross-sectional view of the X-direction cutting line and Fig.21 (c) is along Fig.21 (b) is a cross-sectional view taken along the Y direction cutting line.

[0181] In addition, if Fig. 22 As shown, when the bonding pad 2202 is formed on the n+ doped source 2008 and the n+ doped drain 2010, at least two sides (a side wall and a top) of the n+ doped drain 2010 (or the n+ doped source 2008) are in contact with the titanium nitride layer 2012 / tungsten layer 2014 and the bonding pad 2202. Therefore, the contact resistance of the n+ doped source 2008 and the n+ doped drain 2010 is also reduced accordingly.

[0182] Fig.23 1 is a schematic diagram illustrating a simulation result of a technology computer-aided design (TCAD) of an on-current Ion of a conventional fin field-effect transistor (Fin Field-Effect Transistor, FinFET) and the vertical thin-body field-effect transistor, wherein the conventional fin field-effect transistor ( Fig.23 The middle figure) has a fin width of 8nm, a fin height of 70nm, a gate dielectric layer of 1nm thickness, and the vertical thin-body field effect transistor ( Fig.23 ) has a 1.5 nm vertical thin body Sright, a 1.5 nm vertical thin body Sleft and a 1 nm thick gate dielectric layer covering the vertical thin bodies Sleft and Sright, wherein the central pole (not shown in FIG. Fig.23 ) exists between the vertical thin body Sleft and the vertical thin body Sright. When the work function of the central electrode and / or gate conductive material 1504 is adjusted by using appropriate gate metal materials, the current density of the vertical thin body field effect transistor in the on state (shown by the blue curve) is 7 times the current density of the conventional fin field effect transistor in the on state (shown by the brown dotted line), and the on current Ion of the vertical thin body field effect transistor is approximately 2 times the on current Ion of the conventional fin field effect transistor. It is worth noting that because of the vertical thin body Sleft and the vertical thin body Sright, there are multiple current conduction channels in the vertical thin body field effect transistor.

[0183] on the other hand, Fig.24FIG. 1 is a schematic diagram illustrating the simulation results of the Technology Computer-Aided Design (TCAD) of the off current Ioff of the conventional fin field effect transistor and the vertical thin body field effect transistor. Fig.24 As shown in the right figure of FIG, the current density of the conventional fin field effect transistor in the off state (marked by the brown dotted line) is 14 times the current density of the vertical thin body field effect transistor in the off state (marked by the blue curve), and the off current Ioff of the conventional fin field effect transistor is about 34 times the off current Ioff of the vertical thin body field effect transistor. Thus, compared with the conventional fin field effect transistor, the vertical thin body field effect transistor effectively increases the Ion / Ioff ratio by about 68 times.

[0184] In addition, because the width of the vertical thin body Sleft / vertical thin body Sright is about 1.5-3 nm (that is, the width of the silicon surrounding ring is about 1.5-3 nm), in another embodiment of the present invention, when the n-type lightly doped drains 2004, 2006 and the highly doped semiconductor region (n+ doped source 2008 and n+ doped drain 2010) are selectively grown at a predetermined temperature, the edge of the n-type lightly doped drain 2006 can move laterally to contact the gate dielectric layer 1502, and the same is true for the edge of the n-type lightly doped drain 2004. Therefore, in this embodiment, the effective channel length of the vertical thin body field effect transistor can be shorter than Fig.21 (a) shows the effective channel length (Leff) of the vertical thin-body field effect transistor.

[0185] Fig.25 is a schematic diagram illustrating the structural difference between the conventional fin field effect transistor and the vertical thin body field effect transistor. Fig.25As shown in (a), in the conventional fin field effect transistor, in order to increase the on-current Ion, there are usually two (or more) independent fin structures, and the two (or more) independent fin structures are separated by a shallow trench isolation region, wherein the shallow trench isolation region is located between the two independent fin structures. The gate region (gate dielectric layer and gate conductive layer) will span the two independent fin structures and the shallow trench isolation region therebetween. Then each end of the fin structure provides a seed crystal region for selective epitaxial growth of a lightly doped drain region and a highly doped semiconductor region. In this way, the two N+ regions 2502 and 2504 of the two fin structures are grown separately by selective epitaxial growth (SEG) technology, and because the two N+ regions 2502 and 2504 grown in the conventional fin field effect transistor are not restricted by the shallow trench isolation region, the N+ regions 2502 and 2504 will gradually expand like two independent mushrooms, and finally cause the N+ regions 2502 and 2504 to be connected together. Therefore, Fig.25 The body of the conventional fin field effect transistor in (a) includes two (or more) independent fin structures, each of which has a width of 6nm, the width of the shallow trench isolation region between the two independent fin structures may be 25nm, and the width of the shallow trench isolation region between the conventional fin field effect transistor and another conventional fin field effect transistor is also 25nm. Therefore, Fig.25 The pitch distance between the conventional FinFET and another conventional FinFET in (a) is 62 nm.

[0186] However, if Fig.25 As shown in (b), in one embodiment of the present invention, as mentioned above, only one convex structure is formed based on the semiconductor substrate, and a groove is formed in the convex structure, so that there are two vertical thin bodies. However, there is no shallow trench isolation region between the two vertical thin bodies. Then the gate region (gate dielectric layer and gate conductive layer) will span the two vertical thin bodies and the groove between the two vertical thin bodies, wherein the portion of the gate conductive layer in the groove (that is, the central pole mentioned above) is surrounded by the gate dielectric layer, and in particular, the gate dielectric layer surrounds the central pole along the four side walls and bottom of the groove. The bottom of the groove is still the semiconductor material of the semiconductor substrate. Therefore, there is no shallow trench isolation region between the two vertical thin bodies.

[0187] like Fig.25 As shown in (b), even though there are two vertical thin bodies, due to the presence of the aforementioned silicon surrounding ring, one exposed end of the silicon surrounding ring only provides a seed crystal region for the selective epitaxial growth of the lightly doped drain region and the highly doped semiconductor region, rather than two separate seed crystal regions. Fig.25In the embodiment (b), the N+ region 2506 of the vertical thin-body field effect transistor is as follows: Fig.21 The described method is grown in a recess confined by a shallow trench isolation region by a selective epitaxial growth (SEG) technique. Fig.25 The body of the vertical thin body field effect transistor in (b) only includes a convex structure (or fin structure), and the convex structure has two vertical thin bodies extending upward, each of which has a width of about 1.5nm and a height of about 50-70nm. In each vertical thin body, there are two conductor-oxide-semiconductor structures or two conduction channels (located in the vertical thin body VTB (such as Fig.25 (b)). Fig.25 In the embodiment (b), as described above, due to the lateral displacement caused by the thermal process, the lightly doped drain region of the source region / drain region contacts the two vertical thin bodies. The width of the shallow trench isolation region between the vertical thin body field effect transistor and another vertical thin body field effect transistor can be 12nm. Therefore, Fig.25 The distance between the vertical thin body field effect transistor and the another vertical thin body field effect transistor in (b) is 22 nm.

[0188] in addition, Fig.25 (c) corresponds to another embodiment of the present invention, wherein Fig.25 (c) and Fig.25 The main difference of (b) is that the N+ region 2508 is not grown in a depression limited by the shallow trench isolation region. Therefore, the N+ region 2508 can gradually expand like a mushroom. It is worth noting again that even though there are two vertical thin bodies in the convex structure, because of the presence of the silicon surrounding ring mentioned above, one exposed end of the silicon surrounding ring only provides a seed crystal region for the selective epitaxial growth of the lightly doped drain region and the highly doped semiconductor region, rather than two separate seed crystal regions.

[0189] Also, please refer to Fig.26 , Fig.26 is a schematic diagram illustrating the formation of a central pole 2601 according to a second embodiment of the present invention, wherein Fig.26 It is a continuation Fig.10 .like Fig.26As shown in (a), a conformal dielectric liner 2602 is first deposited in the recess (or trench) 1202, wherein the pole length Lpole for forming the air pole should be 8 to 30 nanometers (nm). Then, a non-conformal dielectric 2604 is deposited in the recess 1202 to form an air pole 2606, wherein there is 2 to 4 nm of non-conformal dielectric 2604 on the top of the air pole 2606, and the center pole 2601 is composed of the conformal dielectric liner 2602, the non-conformal dielectric 2604 and the air pole 2606. In addition, as Fig.26 As shown in (a), the nitride-3 layer is then deposited and etched back to form a nitride cap layer 1402 over the central pole 2601 to protect the central pole 2601. Fig.26 (b) and Fig.26 As shown in (c), the shallow trench isolation region 402 in the gate region is then etched downward by about 75 nm to form the height of the convex structure. Fig.26 (b) is related to Fig.26 (a) The corresponding top view, where Fig.26 (a) is along Fig.26 (b) is a cross-sectional view of the X-direction cutting line and Fig.26 (c) is along Fig.26 (b) is a cross-sectional view taken along the Y direction cutting line.

[0190] Continue Fig.26 , remove the carbon silicon oxide spacer-2 layer 1102, the nitride cap layer 1402 and the pad oxide layer 204 in the gate region, and etch the non-compliant dielectric 2604 down to the original horizontal surface OHS. Then Figure 26-1 (a) and Figure 26-1 As shown in (b), a gate dielectric layer (e.g., a high dielectric (high K) material or oxide) 1502 is formed in the gate region, and then a gate conductive material (e.g., polysilicon, or a metal such as tungsten on a titanium nitride layer, or other metals with a suitable work function) 1504 is deposited in the gate region to cover the central pole 2601, and the chemical mechanical polishing (CMP) technology is used to remove excess gate conductive material 1504, and then the gate conductive material 1504 is etched back / polished. In addition, Figure 26-1 After that, you can execute the above Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22However, the air electrode 2606 is not removed to complete the vertical thin body field-effect transistor (VTBFET). Figure 26-1 (b) is related to Figure 26-1 (a) The corresponding top view, where Figure 26-1 (a) is along Figure 26-1 (b) is a cross-sectional view of the Y-direction cutting line. Then, as previously described Figures 19 to 22 The source region / drain region is formed.

[0191] Also, please refer to Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 and Fig.34 . Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 and Fig.34 FIG. 1 is a schematic diagram illustrating a vertical thin-body field effect transistor having a tapered central pole formed according to a third embodiment of the present invention, wherein the tapered central pole is a tapered trench filled with a gate conductive material. Fig. 27 Start, such as Fig. 27 As shown in (a), Fig. 27 (a) and Figure 5 The difference between (a) and (b) is that a semiconductor layer 2702 (such as a silicon germanium layer) is formed below the pad oxide layer 204. Fig. 27 (b) is related to Fig. 27 (a) The corresponding top view, where Fig. 27 (a) is along Fig. 27 (b) is a cross-sectional view of the X-direction cutting line. Fig. 27 Post-execution Figure 6 and Figure 7 To get Fig.28 ,in Fig.28 (b) is related to Fig.28 (a) The corresponding top view, where Fig.28 (a) is along Fig.28 (b) is a cross-sectional view taken along the X-direction cutting line.

[0192] Then continue Fig.28 ,like Fig.29As shown in (a), a photolithography mask 2902 is deposited on the nitride layer 802, and then the nitride layer 802, the pad nitride layer 206, the pad oxide layer 204, the semiconductor layer 2702 and the shallow trench isolation region 402 are removed by using the anisotropic etching technique and the pattern of the photolithography mask 2902 to form a recess 2904. In addition, Fig.29 (b) is related to Fig.29 (a) The corresponding top view, where Fig.29 (a) is along Fig.29 (b) is a cross-sectional view of the X-direction cutting line and Fig.29 (c) is along Fig.29 (b) is a cross-sectional view taken along the Y direction cutting line.

[0193] Then continue Fig.29 ,like Fig.30 As shown in (b), a lithography mask 3002 is deposited outside the gate region, and then the shallow trench isolation region 402, the oxide spacer 304 and the nitride spacer 306 in the gate region are etched downward using the anisotropic etching technology. In addition, Fig.30 (b) is related to Fig.30 (a) The corresponding top view, where Fig.30 (a) is along Fig.30 (b) is a cross-sectional view taken along the Y direction cutting line.

[0194] Then as Fig.31 As shown in (a), the lithography mask 3002 is removed, and then a thin body 3102 is formed by a selective growth technique (e.g., selective epitaxy growth (SEG) technique), and then the thin body 3102 is etched back to make the top surface of the thin body 3102 flush with the original horizontal surface OHS. In this way, a semiconductor body including a bottom portion (p-type well 202) and a recessed portion (thin body 3102) is formed. It is worth noting here that different in-situ doping concentrations of the thin body 3102 (epitaxial layer) can result in different selective etching capabilities between the thin body 3102 (epitaxial layer) and the semiconductor layer 2702. In addition, Fig.31 (b) is related to Fig.31 (a) The corresponding top view, where Fig.31 (a) is along Fig.31 (b) is a cross-sectional view of the X-direction cutting line and Fig.31 (c) is along Fig.31 (b) is a cross-sectional view of the Y-direction cutting line. Fig.31Then, an oxide spacer-2 layer 1802 and a nitride spacer-2 layer 1804 are formed along the side walls of the pad nitride layer 206 and the pad oxide layer 204, and then the above-mentioned Figures 19 to 22 To complete the source region / drain region of the vertical thin body field effect transistor (such as Fig.32 shown).

[0195] Then continue Fig.32 ,like Fig.33 As shown in (a), the nitride layer 802, the pad nitride layer 206, the pad oxide layer 204 and the semiconductor layer 2702 are first removed to form a trench 3302 in the gate region, and then a gate dielectric layer 1502 (such as a high dielectric (high K) material or oxide) is formed in the gate region to cover the sidewalls of the thin body 3102. Since the thin body 3102 (epitaxial layer) and the semiconductor layer 2702 have different selective etching capabilities, the thin body 3102 (epitaxial layer) can be left. In addition, Fig.33 (b) is related to Fig.33 (a) The corresponding top view, where Fig.33 (a) is along Fig.33 (b) is a cross-sectional view of the X-direction cutting line and Fig.33 (c) is along Fig.33 (b) is a cross-sectional view of the Y-direction cutting line shown in FIG. Then, a gate conductive material 1504 is deposited in the gate region and a Fig.17 To complete the gate structure of the vertical thin-body field effect transistor (such as Fig.34 (a)). In addition, after the gate structure of the vertical thin-body field effect transistor is completed, Fig.34 (c) shows a tapered central pole 3402. In addition, Fig.34 (b) is related to Fig.34 (a) The corresponding top view, where Fig.34 (a) is along Fig.34 (b) is a cross-sectional view of the X-direction cutting line and Fig.34 (c) is along Fig.34 (b) is a cross-sectional view taken along the Y direction cutting line.

[0196] In addition, it is obvious that there is no shallow trench isolation region 402 between the two thin bodies 3102 in the convex structure, and Fig.34As shown, the groove 3302 in the gate region separates the two thin bodies 3102, and the groove 3302 can be a conical groove that is narrow at the top and wide at the bottom. In addition, in one embodiment of the present invention, each thin body is conical and extends upward, and each thin body also includes two conductive channels extending upward, and there are two conductor-oxide-semiconductor surfaces along the two conductive channels. The two conductive channels of a thin body or the four conductive channels of two thin bodies are not parallel to each other. In one embodiment of the present invention, the conical thin body has a narrower upper half and a wider lower half, or the conical thin body has a wider upper half and a narrower lower half. Of course, the present invention is not only applicable to the above-mentioned embodiment of a semiconductor body and two thin bodies, but also to embodiments of more than two thin bodies.

[0197] In summary, there is a central pole in the convex structure in the vertical thin body field effect transistor, and the conductive central pole is surrounded by the gate dielectric layer 1502, so the conductive central pole in the convex structure can effectively suppress the leakage current path of the vertical thin body field effect transistor in the off state. However, the vertical thin body field effect transistor still has a plurality of vertical thin bodies (that is, vertical thin bodies Sright, Sleft) for conducting current during the on state. In addition, for example, the width of the vertical thin body Sright (or vertical thin body Sleft) can be about 1.5 to 2 nm. Because the conductive central pole is surrounded by the silicon surrounding ring, the conductive current of the vertical thin body field effect transistor in the on state will diverge and then converge in the conduction channel region extending from the drain region to the source region.

[0198] In addition, forming the solid fence wall (e.g. Figure 6 The oxide spacer 304 and the nitride spacer 306 shown in the figure are used to sandwich the active region or the narrow convex structure, especially the sidewall of the convex structure. The strong fence wall can be a single layer or other composite layers to protect the narrow convex structure from collapse during the formation of the source / drain region or the gate region of the vertical thin-body field effect transistor. In addition, the shallow trench isolation region 402 (such as Figure 7 As shown in the figure, the convex structure also surrounds or clamps the active region or the narrow convex structure (especially the sidewalls of the narrow convex structure) to protect the narrow convex structure from collapse during the formation of the source region / drain region or the gate region of the vertical thin-body field effect transistor. Therefore, even if the height of the convex structure of the vertical thin-body field effect transistor (e.g., 60 to 300 nm) is much larger than the width of the convex structure of the vertical thin-body field effect transistor (e.g., 3 to 7 nm), the convex structure protected by the solid fence wall is still unlikely to collapse in subsequent processes (e.g., forming the source region / drain region or the gate region, etc.).

[0199] Another advantage of the present invention is that, because the gate region (such as Fig.18 The thickness of the oxide spacer-2 layer 1802 and the nitride spacer-2 layer 1804 on the edge of the thermal oxidation process is controllable, and the oxide-3V layer 10022 and the oxide-3B layer 10024 (as shown in FIG. Fig.19 ) is also controllable, so the edge of the source region / the drain region can be aligned with the gate region (as shown in Fig.21 The edges of the source region / the drain region are aligned or substantially aligned, especially the source region / the drain region is formed by the selective epitaxial growth technology. Therefore, the relative position or distance between the edge of the source region / the drain region and the edge of the gate region is controllable and depends on the thickness of the spacer layer (oxide spacer-2 layer 1802 and nitride spacer-2 layer 1804) formed on the edge of the gate region and / or the thickness of the oxide layer (e.g. oxide-3V layer 10022). Therefore, the effective channel length Leff can be controlled, so that the problem of gate induced drain leakage (GIDL) current can be improved.

[0200] In summary, the vertical thin-body field effect transistor has the following advantages:

[0201] (1) Due to the presence of the conductive center electrode surrounded by the gate dielectric layer in the convex structure, the leakage current path of the vertical thin body field effect transistor in the OFF state can be reduced, and the conductive center electrode can effectively suppress the leakage current of the vertical thin body field effect transistor during the OFF state. In addition, there are multiple vertical thin bodies in the convex structure, and the multiple vertical thin bodies further increase the conduction current of the vertical thin body field effect transistor during the ON state.

[0202] (2) Taking the process with a minimum feature size (F) of 5nm as an example, the vertical thin body field effect transistor has multiple conductor-oxide-semiconductor structures and multiple conduction channels, and its structural dimensions are as follows: First, two vertical thin bodies with a width of about 1.5nm are made, the thickness of the gate dielectric layer is about 1nm, the thickness of the internal gate (the conductive center pole) is about 3nm, and the thickness of the convex structure is required to be about 8nm. Assuming that the width of the shallow trench isolation between the two convex structures is 8nm, the spacing (space plus width) between the two vertical thin bodies is about 16nm (=3.2F), which is much smaller than the spacing of traditional fin field effect transistors, wherein the fin width of the traditional fin field effect transistor is about 6nm, and the spacing between the two fins is about 24nm, so the spacing between the traditional fin field effect transistor and another traditional fin field effect transistor is about 30nm (=6F).

[0203] (3) Fig.23 , 24 It is a simulation result of the scientific computer-aided design of the vertical thin-body field effect transistor and the traditional fin field effect transistor (or tri-gate field effect transistor). The ratio of the on-current Ion of the vertical thin-body field effect transistor to the on-current Ion of the traditional fin field effect transistor is about 2, and the ratio of the off-current Ioff of the traditional fin field effect transistor to the off-current Ioff of the vertical thin-body field effect transistor is about 34, wherein the vertical thin-body field effect transistor greatly improves the above ratios. This improvement can be achieved by the device width pitch of the vertical thin-body field effect transistor being less than 4F and the device width pitch of the traditional fin field effect transistor being 6F. Therefore, the productivity of the vertical thin-body field effect transistor is indeed much better and is worthwhile for a new structure with a fairly affordable process complexity.

[0204] (4) The solid fence wall is used to clamp the active area or the narrow convex structure, especially the sidewall of the convex structure. In this way, even if the height of the convex structure (e.g., 60-300 nm) is much larger than the width of the convex structure (e.g., 3-7 nm), the convex structure protected by the solid fence wall is still unlikely to be damaged.

[0205] (5) The relative position or distance between the edge of the source region / the drain region and the edge of the gate region is controllable and depends on the thickness of the spacer layer formed on the edge of the gate region and / or the oxide layer (e.g., oxide-3V layer).

[0206] (6) The metal-semiconductor junction formed in the source region / the drain region can reduce the resistance of the source region / the drain region.

[0207] (7) Most of the source region / the drain region is isolated by an insulating material, wherein the insulating material includes a bottom structure consisting of an oxide-3B layer and / or a nitride-3 layer, so that the junction leakage current can be significantly reduced.

[0208] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A transistor structure, characterized in that Include: A semiconductor body having a convex structure, wherein the convex structure has at least four conductive channels extending upward; a source region, contacting the first end of the convex structure; a drain region contacting the second end of the convex structure; and a gate region having a gate conductive layer, wherein the gate conductive layer spans over the convex structure; Two conductive channels or four conductive channels among the at least four conductive channels are not parallel to each other, and there is no shallow trench isolation region between the at least four conductive channels.

2. The transistor structure according to claim 1, characterized in that A trench is formed in the convex structure, the trench is located between the first end and the second end, and the first portion of the gate conductive layer is filled in the trench.

3. The transistor structure according to claim 2, characterized in that The convex structure includes a group of thin bodies extending upward, and each thin body includes two conducting channels along the sidewalls of the thin body among the at least four conducting channels.

4. The transistor structure according to claim 3, characterized in that The trench is between two thin bodies in the group of thin bodies, a gate dielectric layer spans over the convex structure, and a first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench.

5. The transistor structure according to claim 2, characterized in that The groove is in a cone shape.

6. The transistor structure according to claim 2, characterized in that The convex structure includes at least four upwardly extending conductor-oxide-semiconductor surfaces, and the at least four conductor-oxide-semiconductor surfaces are horizontally offset from each other.

7. A transistor structure, characterized in that Include: A semiconductor body having a convex structure, wherein the convex structure has an original surface, The convex structure comprises two thin bodies extending upward, and the two thin bodies are separated from each other; a source region, contacting the first end of the convex structure; a drain region contacting the second end of the convex structure; and a gate region having a gate conductive layer, wherein the gate conductive layer spans over the convex structure; Each thin body is in a cone shape, and there is no shallow trench isolation region between the two thin bodies.

8. The transistor structure according to claim 7, characterized in that A trench is formed in the convex structure, the trench is located between the first end and the second end, and the first portion of the gate conductive layer is filled in the trench.

9. The transistor structure according to claim 8, characterized in that Each thin body includes two conducting channels extending upward.

10. The transistor structure according to claim 9, characterized in that The trench separates the two thin bodies, a gate dielectric layer spans over the convex structure, and the first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench.

11. A transistor structure, characterized in that Include: A semiconductor body having a convex structure, wherein the convex structure has an original surface, and the convex structure includes two thin bodies extending upward; a source region, contacting the first end of the convex structure; a drain region contacting the second end of the convex structure; a gate region having a gate conductive layer, wherein the gate conductive layer spans over the convex structure; a groove formed in the convex structure and located between the first end and the second end, wherein the groove separates the two thin bodies; and An air electrode is located in the groove and covered by the gate conductive layer.

12. The transistor structure according to claim 11, characterized in that The convex structure includes a first outer sidewall and a second outer sidewall covered by the gate conductive layer, and the convex structure further includes a first inner sidewall and a second inner sidewall in the trench.

13. The transistor structure according to claim 11, characterized in that Also includes: a first recess, for accommodating the source region; and a second recess, for accommodating the drain region; The sidewalls of the first recess and the second recess are surrounded by a shallow trench isolation region.

14. The transistor structure according to claim 13, characterized in that The edge of the source region contacts the two thin bodies, and the edge of the drain region also contacts the two thin bodies.

15. The transistor structure according to claim 14, characterized in that The source region comprises: a lightly doped drain region, contacting the two thin bodies; a heavily doped region extending laterally from the lightly doped drain region; and A metal region is located in the first recess and contacts a side wall of the heavily doped region.

16. The transistor structure according to claim 11, characterized in that The width of each thin body is no greater than 3 nanometers.

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