Super junction structure and manufacturing method thereof

Abstract

The invention discloses a super junction structure and a manufacturing method thereof, the super junction structure comprises a plurality of MOS cells which are connected in parallel, and each MOS cell comprises a drain electrode, an upper metal source electrode, a grid electrode, a semiconductor epitaxial layer and a substrate layer; a P well layer and an N well layer are formed on the semiconductor epitaxial layer through ion implantation; the P-well layer comprises a lightly doped P-well layer I and a heavily doped P-well layer I, a groove is etched between adjacent MOS cells and in the middle of the heavily doped P-well layer I, and the top of the groove is in contact with the upper metal source electrode; an oxide layer is deposited in the groove, and the groove is filled with the oxide layer. According to the method, the problem that the manufacturing process of the super-junction device is difficult is solved for the first time, the ion beam can penetrate into the groove through groove etching, the injection depth of the first heavily-doped P well layer is increased through the groove under the condition that the maximum injection depth of the injection machine is not changed, the requirement of the super-junction device for the injection machine is greatly reduced, and the manufacturing cost of the super-junction device is reduced. The manufacturing difficulty of the super junction device is obviously reduced, and the industrial application value is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction structure and a manufacturing method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles and other fields. With the gradual development of SiC MOSFET devices, the voltage requirements of the devices at the application end are gradually increasing. For SiC MOSFET, higher voltage resistance means thicker epitaxial layer, and the increase of epitaxial layer means a sharp increase in the on-resistance of the device. For devices with the same on-resistance, the epitaxial thickness and device area of ​​high-voltage devices will be much higher than those of low-voltage devices. The superjunction structure solves the above problems due to its special structure.

[0003] However, the manufacture of super junction structures usually requires very deep P+ implantation to improve voltage resistance and reduce on-resistance. The implantation depth of P+ ions is limited by the implantation capacity of the implantation machine. Currently, implantation machines in the industry can usually only achieve an implantation depth of 2 to 3 μm. If you want to manufacture a heavily doped P well layer with a thickness of more than 5 μm, it is actually impossible. Even with more advanced implantation machines, silicon carbide substrates cannot withstand such a high concentration of impurity ions, resulting in material damage. Limited by process manufacturing, super junction structures are greatly limited in actual device production and cannot be widely used. Summary of the invention

[0004] The purpose of the present invention is to provide a super junction structure and a manufacturing method thereof, so as to solve the problem in the prior art that P+ injection is limited by the injection capacity of the implanter, improve the feasibility of the process, and have great application value.

[0005] The technical solution adopted by the present invention is:

[0006] A super junction structure includes a plurality of MOS cells connected in parallel, wherein a single MOS cell includes a drain, an upper metal source, a gate, a semiconductor epitaxial layer, and a substrate layer, wherein a dielectric layer is provided on the surface of the gate; the semiconductor epitaxial layer is located on the surface of the substrate layer, also known as a diffusion layer, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer includes a lightly doped P-well layer 1 and a heavily doped P-well layer 1, wherein the heavily doped P-well layer 1 extends to the bottom of the semiconductor epitaxial layer and contacts the substrate layer;

[0007] The gate is arranged inside the upper metal source and is isolated from the upper metal source by a dielectric layer;

[0008] The substrate layer is arranged on the surface of the drain, the heavily doped P well layer 1 and the diffusion layer are arranged on the surface of the substrate layer, and the heavily doped P well layer 1 is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P well layer 1 located on both sides of the single MOS cell, the lightly doped P well layer 1 is arranged on the surfaces of the diffusion layer and the heavily doped P well layer 1, and are respectively connected to the diffusion layer and the heavily doped P well layer 1, the N well layer is located on the surface of the lightly doped P well layer 1, and is respectively connected to the lightly doped P well layer 1 and the heavily doped P well layer 1, and the gate is isolated and connected to the upper surface of the N well layer, the lightly doped P well layer 1 and the surface of the diffusion layer through a dielectric layer;

[0009] The upper metal source is connected to the upper surface of the N-well layer and the upper surface of the heavily doped P-well layer 1;

[0010] Furthermore, the N well layer includes a lightly doped N well layer 1 and a heavily doped N well layer 1, wherein the heavily doped N well layer 1 is located on the upper layer of the lightly doped N well layer 1; the lightly doped N well layer 1 is located on the surface of the lightly doped P well layer 1, and is respectively connected to the lightly doped P well layer 1 and the heavily doped P well layer 1; the heavily doped N well layer 1 is connected to the heavily doped P well layer 1, and the gate is connected to the upper surface of the heavily doped N well layer 1 through isolation from the dielectric layer; and the upper metal source is connected to the upper surface of the heavily doped N well layer 1.

[0011] Between adjacent MOS cells, in the middle of the heavily doped P-well layer 1, a groove is etched, the bottom of the groove may or may not extend to the substrate layer; an oxide layer is deposited inside the groove, the oxide layer fills the groove, and the top of the oxide layer contacts the upper metal source; and when the super junction structure is in a blocking state, the oxide layer bears pressure together with the device. The oxide layer will not cause the device's withstand voltage characteristics to decrease. In the device manufacturing process, the setting of the oxide layer can greatly reduce the requirements for the ion implanter in the super junction structure manufacturing process.

[0012] More preferably, the groove is perpendicular to the substrate layer.

[0013] The present invention also provides a method for manufacturing the super junction structure, the method comprising the following steps:

[0014] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0015] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0016] S3. Between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove. The depth and width of the groove can be set according to the specific device design.

[0017] S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications;

[0018] S5, depositing an oxide layer in the trench to fill the trench, so that the oxide layer fills the trench;

[0019] S6. Complete the remaining parts of the device according to the normal process.

[0020] In the step S6, the gate electrode, the dielectric layer, and the upper metal source electrode are generally manufactured according to normal processes.

[0021] In step S5, the oxide layer can be deposited using an oxide layer deposition device, such as a high-temperature oxidation furnace, and the specific steps can be: interface cleaning, after removing surface impurities, oxidation in a high-temperature oxidation furnace, oxidation to a thickness greater than 50nm, and then deposition and growth of the oxide layer until the oxide layers grown from the sides of the groove are in contact and become one, and there is no gap in the groove, and then high-temperature annealing is performed to fill the groove completely. The excess oxide layer grown on the device surface can be removed by wet or dry methods.

[0022] Furthermore, in step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, and:

[0023]

[0024] In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench;

[0025] When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0026] Furthermore, in step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating.

[0027]

[0028] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

[0029] The beneficial effects of the present invention are:

[0030] The present invention solves for the first time the problem of the difficulty of the super junction device manufacturing process. By increasing the groove etching, the ion beam of the implanter can penetrate deep into the groove, thereby increasing the injection depth of the heavily doped P-well layer 1 through the groove while keeping the maximum injection depth of the implanter unchanged, making it possible to manufacture the heavily doped P-well layer 1 with an injection depth greater than the maximum injection depth of the implanter. This greatly reduces the requirements of the super junction device for the implanter, significantly reduces the difficulty of manufacturing the super junction device, lowers the threshold for manufacturing the super junction device, and lays a solid foundation for the industrial application of super junction devices.

[0031] Furthermore, the present invention utilizes the trench to perform impurity injection and then fills the trench with oxide, which can reduce the difficulty of deep trench filling in the industrial manufacturing process without losing the withstand voltage characteristics of the device.

[0032] The present invention determines whether the substrate epitaxial layer trench etching process is qualified by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls and the amount of cracks on the inner surface of the trench. This method can efficiently and quickly inspect the trench etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the cross-sectional structure of the super junction structure of the present invention.

[0034] Figure 2 Schematic diagram of step S3 of preparing a super junction structure in Example 1.

[0035] Figure 3 Schematic diagram of step S4 of preparing a super junction structure in Example 1.

[0036] Figure 4 This is a process comparison diagram of super junction structures with different structures in Example 2.

[0037] Figure 5 for Figure 4 Theoretical structure diagram and actual structure diagram of structure 2 in .

[0038] Figure 6 Schematic diagram of the design dimensions and injection method of the groove in Example 2.

[0039] Figure 7 This is a schematic cross-sectional diagram of the super junction structure prepared in Example 2.

[0040] In the figure: 1, drain; 2, upper metal source; 3, dielectric layer; 4, gate; 6, oxide layer; 61, trench; 7, lightly doped P-well layer 1; 8, heavily doped P-well layer 1; 9, diffusion layer; 10, lightly doped N-well layer 1; 11, heavily doped N-well layer 1; 12, substrate layer. DETAILED DESCRIPTION

[0041] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments, but the protection scope of the present invention is not limited thereto. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0042] Example 1

[0043] This embodiment provides a super junction structure, the structural diagram is as follows Figure 1 As shown, it includes several MOS cells connected in parallel, and a single MOS cell includes a drain 1, an upper metal source 2, a gate 4, a semiconductor epitaxial layer, and a substrate layer 12. The surface of the gate 4 is provided with a dielectric layer 3; the semiconductor epitaxial layer is located on the surface of the substrate layer 12, also known as a diffusion layer 9, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer includes a lightly doped P-well layer 7 and a heavily doped P-well layer 8, wherein the heavily doped P-well layer 8 extends to the bottom of the semiconductor epitaxial layer and contacts with the substrate layer 12.

[0044] The gate 4 is arranged inside the upper metal source 2 and is isolated from the upper metal source 2 by a dielectric layer 3;

[0045] The substrate layer 12 is located on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are located on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is located on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 1 In the embodiment of the present invention, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7, and is connected to the lightly doped P well layer 7 and the heavily doped P well layer 8 respectively; the heavily doped N well layer 11 is connected to the heavily doped P well layer 8, and the gate 4 is isolated and connected to the upper surface of the heavily doped N well layer 11, the lightly doped P well layer 7 and the surface of the diffusion layer 9 through the dielectric layer 3;

[0046] The upper metal source 2 is connected to the upper surface of the heavily doped N-well layer 11 and the upper surface of the heavily doped P-well layer 8;

[0047] Between adjacent MOS cells, a groove 61 is etched in the middle of the heavily doped P-well layer 8, and the bottom of the groove 61 extends to the substrate layer 1; an oxide layer 6 is deposited inside the groove, the oxide layer 6 fills the groove 61, and the top of the oxide layer 6 is in contact with the upper metal source 2; and when the super junction structure is in a blocking state, the oxide layer 6 is under pressure together with the device.

[0048] Figure 1 The bottom of the groove 61 shown extends to the substrate layer 12, but the groove 61 may not extend to the substrate layer 12, because considering the implantation depth that the implanter can reach, the depth of the groove only needs to ensure that the impurities injected by the implanter can reach the bottom of the diffusion layer and the surface of the substrate layer. That is, the depth of the groove 61 can be greater than or equal to the target implantation depth minus the maximum implantation depth of the implanter.

[0049] The super junction structure is prepared by the following method:

[0050] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0051] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0052] S3, between adjacent MOS cells, the reserved heavily doped P well layer is etched to form a groove, such as Figure 2 As shown, Figure 2 In the diffusion layer 9, the etching depth reaches the trench 61 of the substrate layer, the trench is located between adjacent MOS cells and in the middle of the reserved heavily doped P well layer 8.

[0053] The depth and width of the trench can be set according to the specific device design.

[0054] In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating, and:

[0055]

[0056] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

[0057] Among them, for the semiconductor substrate layer, the ratio of the cross-sectional width at the bottom of the trench to the cross-sectional width at the top is m=1.5, and the maximum inclination angle of the trench sidewall after heating is u=4.2 (degrees), then:

[0058]

[0059] From the above calculation, it can be known that the vertical coefficient of the inner wall of the trench etched by the semiconductor substrate layer is h=1.8.

[0060] The average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench are inspected to determine whether the substrate epitaxial layer trench etching process is qualified.

[0061]

[0062] In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench;

[0063] When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0064] Among them, the average width of the trench etched for the substrate epitaxial layer is d=3.4 (micrometers), the target width of the etched trench is d0=2 (micrometers), and the existence rate of cracks in the inner surface of the trench is g=35% (the existence rate of cracks = the number of substrate epitaxial layers with more than 10 cracks in the trench ÷ the number of sampled substrate epitaxial layers), then:

[0065]

[0066] From the above calculations, it can be known that the process of trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0067] S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications;

[0068] like Figure 3 As shown, the wafer angle can be rotated to tilt the device to the left, and the ion beam of the implanter is implanted along the left side to obtain a portion of heavily doped P-well layer 1 of the left MOS cell. The device is then tilted to the right, and the implanter is implanted along the right side to obtain a portion of heavily doped P-well layer 1 of the right MOS cell. In this way, multi-angle and multiple implantations are completed in multiple grooves to obtain two heavily doped P-well layers 1 of adjacent cells.

[0069] S5, depositing an oxide layer in the trench to fill the trench, so that the oxide layer fills the trench;

[0070] The oxide layer deposition equipment can be used to deposit the oxide layer. The specific steps may be: interface cleaning, removal of surface impurities, oxidation in a high-temperature oxidation furnace, oxidation to a thickness greater than 50nm, and then deposition of a growing oxide layer until the oxide layers grown from the sides of the groove are in contact and become one, and there are no gaps in the groove, and then high-temperature annealing is performed to fill the groove completely.

[0071] S6. Complete the production of the gate, dielectric layer and upper metal source according to normal process.

[0072] Example 2

[0073] The present invention is further described with a specific embodiment.

[0074] The goal is to manufacture a SiC MOSFET transistor with a withstand voltage of 1200V. The maximum implant depth of the implanter is 3um. After considering other electrical parameters, the simulated super junction structure requires a P+ implant with a depth of 5um and a width of 3um. The specific implementation is as follows:

[0075] like Figure 4 As shown in structure 1, if the ordinary MOSFET transistor structure is used, to achieve a withstand voltage of 1200V, the thickness of the epitaxial layer needs to be more than 10μm. This preparation method is feasible, and the industry generally adopts this method of increasing the thickness of the epitaxial layer, but the increase of the epitaxial layer means a sharp increase in the on-resistance of the device.

[0076] Figure 4 Structure 2 shows a theoretical structure, that is, the thickness of the epitaxial layer is reduced to 5μm, but the depth of P+ injection needs to reach 5μm to achieve a higher withstand voltage. This is only feasible in theory, but cannot be produced in practice because the injection machine capacity is limited and the injection depth cannot reach 5μm, and the silicon carbide material cannot withstand it.

[0077] The theoretical structure of structure 2 and the schematic diagram of the structure that can be manufactured under the actual process are shown in Figure 5 As shown, since the theoretical depth cannot be reached, the actual depth of the P+ injection region can only reach 3 microns, which cannot reach the theoretical value of 1200V withstand voltage.

[0078] Therefore, the present invention creatively proposes a method of etching a groove in the middle of the reserved P+ implantation area, and the implantation depth is increased through the groove. Figure 4 When the epitaxial layer thickness of structure 3 is 5 μm, the implantation depth can be 5 μm. For the specific design and steps, please refer to Figure 6 and Figure 7 .

[0079] First, prepare according to steps S1 to S2 of Example 1, and then in step S3, Figure 6 As shown, the designed trench is located between two adjacent MOS cells, in the middle of the adjacent heavily doped P-well layer, and the designed trench depth is 2.5 μm and the width is 1.5 μm. Figure 6 and Figure 7 The trench 61 does not extend to the substrate layer.

[0080] Step S4, multiple times of multi-angle implantation to form a heavily doped P-well layer 1 that meets the specifications;

[0081] The wafer angle can be rotated to tilt the device to the left, and the ion beam of the implanter is implanted along the left side to obtain a part of the left MOS cell with a heavily doped P-well layer 1. The device is then tilted to the right, and the ion beam of the implanter is implanted along the right side to obtain a part of the right MOS cell with a heavily doped P-well layer 1. When the device is upright, the ion beam passes vertically downward through the groove and is injected into the bottom of the groove. The implantation parameters are reset to make the implantation depth reach 2.5μm, reaching the substrate layer. If the implantation is performed from the surface of the epitaxial layer, the implantation depth cannot reach the substrate layer due to limitations on the implantation capacity.

[0082] When the device is tilted, the ion beam can pass through the groove and be injected into the bottom of both sides of the groove from the bottom edge of the groove at an inclined angle. According to the maximum injection depth of the implanter of 3μm, at the tilt angle of the device, the implantation can reach the bottom of the epitaxial layer with a width of 1.5μm on both sides and reach the substrate layer.

[0083] According to the design, we can obtain Figure 6 The two adjacent cells are shown to have heavily doped P-well layers 1, and the depth of the heavily doped P-well layer 1 reaches 5 μm, which exceeds the maximum implantation depth of the implanter.

[0084] Therefore, the present invention can prepare a P+ injection layer with a depth of 5um and a width of 3um through multiple injections at multiple angles, and this depth exceeds the maximum injection depth of the implanter itself and cannot be achieved under the original structure. As a result, the biggest difficulty and obstacle in manufacturing the super junction structure has been solved, and the rest only needs to be manufactured according to the existing process.

[0085] The MOSFET transistor structure is fabricated according to steps S5 and S6 of Example 1, and the target withstand voltage value of 1200V can be achieved. The obtained super junction structure is as follows: Figure 7 As shown, Figure 7 The middle oxide layer 6 fills the trench 61, and the top is in contact with the upper metal source 2. The trench does not extend to the substrate layer.

Claims

1. A superjunction structure, comprising a plurality of MOS cells connected in parallel, characterized in that A single MOS cell comprises a drain, an upper metal source, a gate, a semiconductor epitaxial layer, and a substrate layer, wherein a dielectric layer is provided on the surface of the gate; the semiconductor epitaxial layer is located on the surface of the substrate layer, also known as a diffusion layer, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer comprises a lightly doped P-well layer 1 and a heavily doped P-well layer 1, wherein the heavily doped P-well layer 1 extends to the bottom of the semiconductor epitaxial layer and contacts the substrate layer; The gate is arranged inside the upper metal source and is isolated from the upper metal source by a dielectric layer; Between adjacent MOS cells, a groove is etched in the middle of the heavily doped P-well layer 1, and the bottom of the groove extends or does not extend to the substrate layer; an oxide layer is deposited inside the groove, the oxide layer fills the groove, and the top of the oxide layer contacts the upper metal source.

2. The super junction structure according to claim 1, characterized in that When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

3. The super junction structure according to claim 1, characterized in that The substrate layer is arranged on the surface of the drain, the heavily doped P well layer 1 and the diffusion layer are arranged on the surface of the substrate layer, and the heavily doped P well layer 1 is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P well layer 1 located on both sides of the single MOS cell, the lightly doped P well layer 1 is arranged on the surfaces of the diffusion layer and the heavily doped P well layer 1, and are respectively connected to the diffusion layer and the heavily doped P well layer 1, the N well layer is located on the surface of the lightly doped P well layer 1, and is respectively connected to the lightly doped P well layer 1 and the heavily doped P well layer 1, and the gate is isolated and connected to the upper surface of the N well layer, the lightly doped P well layer 1 and the surface of the diffusion layer through a dielectric layer; The upper metal source is connected to the upper surface of the N-well layer and the upper surface of the heavily doped P-well layer 1.

4. The super junction structure according to claim 1, characterized in that The N-well layer includes a lightly doped N-well layer 1 and a heavily doped N-well layer 1, wherein the lightly doped N-well layer 1 is located on the surface of the lightly doped P-well layer 1 and is connected to the lightly doped P-well layer 1 and the heavily doped P-well layer 1 respectively; the heavily doped N-well layer 1 is located on the upper layer of the lightly doped N-well layer 1, the heavily doped N-well layer 1 is connected to the heavily doped P-well layer 1, and the gate is connected to the upper surface of the heavily doped N-well layer 1 through isolation from the dielectric layer; and the upper metal source is connected to the upper surface of the heavily doped N-well layer 1.

5. The super junction structure according to claim 1, characterized in that The trench is perpendicular to the substrate layer.

6. The method for manufacturing a super junction structure according to any one of claims 1 to 5, characterized in that The method comprises the following steps: S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them; S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation; S3, between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove; S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications; S5, depositing an oxide layer in the trench to fill the trench, so that the oxide layer fills the trench; S6. Complete the remaining parts of the device according to the normal process.

7. The method according to claim 6, characterized in that In step S6, the gate electrode, dielectric layer and upper metal source electrode are fabricated according to normal processes.

8. The method according to claim 6, characterized in that In step S5, the oxide layer is deposited using an oxide layer deposition device, and the steps are as follows: after cleaning the interface and removing surface impurities, oxidation is performed in a high-temperature oxidation furnace. After oxidation to a thickness greater than 50 nm, a growing oxide layer is deposited until the oxide layers grown from the sides of the groove are in contact with each other and no gaps exist in the groove. High-temperature annealing is then performed to fill the groove completely.

9. The method according to claim 6, characterized in that In step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, as follows: In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench; When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

10. The method according to claim 9, characterized in that In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating. In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

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