A short-sized gallium oxide power device edge termination structure and its manufacturing method

Abstract

The present invention discloses an edge termination structure for a short-size gallium oxide power device and a preparation method thereof, relating to the technical field of semiconductor devices. The edge termination structure for the short-size gallium oxide power device includes a gallium oxide drift layer, an n-type doped gallium oxide substrate, and a cathode which are sequentially stacked. In the present invention, an etched mesa termination structure is combined with a field limiting ring termination structure to form a double trench buried p-type termination structure. When the device is under reverse bias, the depletion region will expand along the buried p-type layer at the bottom of the trench, effectively smoothing the electric field distribution at the edge of the device and improving the breakdown voltage of the device. At the same level of breakdown voltage, compared with the traditional field limiting ring structure, the size of the double trench buried p-type termination structure is smaller, which is beneficial to reducing the parasitic parameters of the device and improving the chip integration degree.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to an edge termination structure of a gallium oxide power device with a short size and a preparation method thereof. Background Art

[0002] In recent years, relying on the continuously developing and breakthrough power electronics technology, emerging industries such as new energy vehicles, high-speed trains, and 5G communications have flourished, bringing great convenience to people's lives. Among them, semiconductor power devices, as the core of modern power electronics technology, play an important role that cannot be ignored. Semiconductor power devices can be applied to energy conversion and switch control in circuits and are a key part of realizing an efficient power system.

[0003] With the increase in high-current and high-voltage application scenarios, ultra-wide bandgap semiconductors with a large bandgap width and a high theoretical breakdown field strength have attracted the attention of the industry. Gallium oxide (Ga2O3), as a kind of ultra-wide bandgap semiconductor material, has an ultra-wide bandgap of up to 4.8 eV and a large theoretical breakdown field strength of 8 MV / cm, and is an ideal material for preparing high-power semiconductor devices. However, due to the discontinuity of the space at the edge of the device, the electric field distribution in the depletion region is uneven under reverse bias, causing the electric field to concentrate at the corners of the device, resulting in device thermal concentration and premature breakdown.

[0004] In order to mitigate this electric field concentration effect, the prior art usually adds an edge termination structure at the edge of the device during device design. Among them, the field limiting ring structure can effectively alleviate the electric field concentration and improve the breakdown voltage of the device by expanding the depletion region through the pn junction under reverse bias. However, the field limiting ring structure usually requires dozens of pairs of rings to achieve good results, which will greatly increase the area occupied by a single device on the integrated chip and significantly reduce the integration degree of the chip. In addition, the added dozens of pairs of annular pn junctions will also introduce large parasitic parameters, which is not conducive to the application of the device in high-speed and low-power consumption scenarios. Summary of the Invention

[0005] In order to solve the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide an edge termination structure of a gallium oxide power device with a short size and a preparation method thereof. By mainly depositing a p-type oxide semiconductor thin layer at the bottom of the double grooves formed by etching to form a double groove buried p-type edge termination structure, the electric field concentration effect of the device is effectively improved, and the size of this structure is much smaller than that of the field limiting ring terminal structure under the same effect.

[0006] In order to achieve the above purpose, the present invention provides the following technical solutions:

[0007] On the one hand, the present invention provides an edge termination structure of a gallium oxide power device with a short size, including a gallium oxide drift layer, an n-type doped gallium oxide substrate, and a cathode that are sequentially stacked.

[0008] The described gallium oxide drift layer deposits a p-type oxide semiconductor on one side of the n-type doped gallium oxide substrate to form a first heterojunction pn junction region, and an anode is provided on the surface of the p-type oxide semiconductor;

[0009] The edge of the first heterojunction pn junction region is etched to form a double trench, and p-type oxide semiconductors are deposited on the bottom of the trench of the double trench and the top of the mesa formed between the double trenches to form a second heterojunction pn junction region;

[0010] The double trench is filled with a passivation layer, a field plate electrode is provided on the surface of the passivation layer, and the field plate electrode is connected to the anode.

[0011] Preferably, the p-type oxide semiconductor is in an amorphous or polycrystalline structure.

[0012] Preferably, the hole concentration of the p-type oxide semiconductor is 1×10 17 / cm 3 ~1×10 20 / cm 3 , and the hole concentration of the p-type oxide semiconductor thin layer is not lower than that of the gallium oxide drift layer.

[0013] Preferably, the thickness of the p-type oxide semiconductor is 10 nm to 1 μm.

[0014] Preferably, the trench depth of the double trench is 5 μm to 10 μm, the width is 2 μm to 5 μm, and the interval between the double trenches is 2 μm to 5 μm.

[0015] Preferably, the length of the passivation layer is greater than the length of the double trench.

[0016] Preferably, the field plate electrode is connected to the anode, and the length of its coverage on the passivation layer is greater than the length of the double trench region.

[0017] On the other hand, the present invention also provides a preparation method for the edge termination structure of the short-size gallium oxide power device described in any one of the above, including the following steps:

[0018] S1. Epitaxially grow a gallium oxide drift layer on an n-type doped gallium oxide substrate to obtain an n-type doped gallium oxide-based wafer;

[0019] S2. Deposit a cathode on the side of the n-type doped gallium oxide substrate away from the gallium oxide drift layer;

[0020] S3. Form a double trench structure by etching on the edge of the side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate;

[0021] S4. Deposit a p-type oxide conductor on the side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterojunction pn junction region, and deposit a p-type oxide conductor on the top of the mesa formed between the bottom and the double trenches of the double trench structure to form a second heterojunction pn junction region; deposit an anode on the first heterojunction pn junction region;

[0022] S5. Deposit a passivation layer in the double trench region to cover the p-type oxide semiconductor of the second heterojunction pn junction region and the gallium oxide drift layer at the edge of the n-type doped gallium oxide-based wafer;

[0023] S6. Deposit a field plate electrode on the surface of the passivation layer and connect the field plate electrode to the anode.

[0024] Preferably, in step S1, the cathode is deposited with a Ti / Au alloy or a Ti / Al / Ti / Au alloy by magnetron sputtering or electron beam evaporation, and in step S4, the anode is deposited with a Ni / Au alloy by magnetron sputtering or electron beam evaporation.

[0025] Preferably, the p-type oxide semiconductor in step S4 is prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition method, and the p-type oxide semiconductor material is a single-layer or multi-layer p-type oxide semiconductor material of NiO or Cu2O; the passivation layer in step S6 is prepared by atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, physical or chemical vapor deposition method, and the passivation layer material is a single-layer or multi-layer insulating dielectric material of Al2O3, SiO2 or SiNx.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] The short-size gallium oxide power device edge termination structure and its preparation method provided by the present invention have the advantage that by combining the etched mesa termination structure and the field limiting ring termination structure, a double trench buried p-type termination structure is formed. When the device is in reverse bias, the depletion region will expand along the buried p-type layer at the bottom of the trench, effectively smoothing the electric field distribution at the edge of the device and improving the breakdown voltage of the device. Under the same breakdown voltage level, compared with the traditional field limiting ring structure, the size of the double trench buried p-type termination structure is smaller, which is beneficial to reducing the parasitic parameters of the device and improving the chip integration. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings.

[0029] Figure 1It is a schematic diagram of an edge termination structure of a short-sized gallium oxide power device provided in Embodiment 1 of the present invention.

[0030] Figure 2 It is a simulation diagram of the electric field data of an edge termination structure of a short-sized gallium oxide power device provided in Embodiment 1 of the present invention under reverse bias.

[0031] Description of the reference numerals:

[0032] 101, cathode; 102, n-type doped gallium oxide substrate; 103, gallium oxide drift layer; 104, p-type oxide semiconductor; 105, anode; 106, passivation layer; 107, field plate electrode. Detailed implementation manners

[0033] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings. The following described implementation manners are only specific implementation manners exemplified by this application to illustrate the technical solutions of this application, rather than limiting it. The protection scope of this application is not limited thereto. In the description of the present invention, it should be noted that the orientation or positional relationship indicated by terms such as "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0034] Embodiment 1

[0035] As Figure 1 shown, this embodiment provides an edge termination structure of a short-sized gallium oxide power device, including a cathode 101, an n-type doped gallium oxide substrate 102, and a gallium oxide drift layer 103 stacked in sequence. On the side of the gallium oxide drift layer 103 away from the n-type doped gallium oxide substrate 102, a p-type oxide semiconductor 104 is provided to form a first heterojunction pn junction region. An anode 105 is provided on the surface of the first heterojunction pn junction region. A double trench structure is formed by etching at the edge of the first heterojunction pn junction region. A p-type oxide semiconductor 104 is provided at the bottom of the double trench structure and on the top of the mesa formed between the double trenches to form a second heterojunction pn junction region. The double trench region is filled with a passivation layer 106, and a field plate electrode 107 is provided on the top of the passivation layer 106.

[0036] The p-type oxide semiconductor 104 is in an amorphous or polycrystalline structure, and the hole concentration is 1×10 17 / cm 3 ~1×10 20 / cm 3, and its hole concentration is not lower than that of the gallium oxide drift layer, with a thickness of 10 nm to 1 μm. The depth of the trench is 5 μm to 10 μm, the width is 2 μm to 5 μm, and the double trench spacing is 2 μm to 5 μm. The gallium oxide drift layer 103 has a single crystal structure with a doping concentration of 5×10 14 cm -3 to 1×10 18 cm -3 , and a thickness of 2 μm to 5 mm. The length of the passivation layer 106 is greater than the length of the double trench region. The field plate electrode 107 is connected to the anode 105, and the length of its coverage on the passivation layer 106 is greater than the length of the double trench region.

[0037] This edge termination structure of a short-sized gallium oxide power device forms a double trench buried p-type termination structure by combining an etched mesa termination structure and a field limiting ring termination structure. When the device is under reverse bias, the depletion region expands along the buried p-type layer at the bottom of the trench, effectively smoothing the electric field distribution at the edge of the device and increasing the breakdown voltage of the device. At the same breakdown voltage level, compared with the traditional field limiting ring structure, the size of the double trench buried p-type termination structure is smaller, which is beneficial to reducing the parasitic parameters of the device and improving the chip integration density.

[0038] Figure 2 is a simulation diagram of the electric field data of an edge termination structure of a short-sized gallium oxide power device provided in Embodiment 1 under reverse bias. For the double trench buried p-type structure, the peak electric field under reverse bias appears at the gallium oxide drift layer at the bottom of the trench; for the field limiting ring structure, the peak electric field under reverse bias appears at the outermost annular pn junction. According to the extracted electric field distribution curve along the transverse direction, it can be seen that at the same reverse bias voltage, the peak electric fields of the two termination structures are similar, but the width of the double trench buried p-type termination structure is much smaller than that of the field limiting ring termination structure. In summary, the present invention adopts the double trench buried p-type termination structure, which can effectively reduce the device area, decrease the parasitic parameters, and improve the chip integration density.

[0039] Embodiment 2

[0040] This embodiment provides a preparation method for an edge termination structure of a short-sized gallium oxide power device, including the following steps:

[0041] S1. Epitaxially grow a gallium oxide drift layer 103 on an n-type doped gallium oxide substrate 102 to obtain an n-type doped gallium oxide-based wafer.

[0042] S2. Deposit metal on the side of the n-type doped gallium oxide substrate 102 away from the gallium oxide drift layer 103 to form a cathode 101, and the cathode 101 forms an ohmic contact with the substrate 102. The cathode 101 can deposit a Ti / Au alloy or a Ti / Al / Ti / Au alloy by magnetron sputtering or electron beam evaporation.

[0043] S3. Form a double-groove structure by etching on the side edge of the gallium oxide drift layer 103 away from the n-type doped gallium oxide substrate 102. Etching can be carried out by dry etching, wet etching and other methods.

[0044] S4. Deposit a p-type oxide conductor 104 on the side of the gallium oxide drift layer 103 away from the substrate 102 to form a first heterojunction pn junction region, and deposit a p-type oxide semiconductor 104 on the top of the mesa structure formed between the bottoms of the double grooves and between the double grooves to form a second heterojunction pn junction region. The p-type oxide semiconductor 104 can be prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition and other methods, and the material can be a single-layer or multi-layer p-type oxide semiconductor material such as NiO, Cu2O or others.

[0045] Define an electrode pattern by photolithography on the surface of the p-type oxide semiconductor 104 in the first heterojunction pn junction region, and deposit metal to form an anode 105. The anode 105 can deposit a Ni / Au alloy by magnetron sputtering or electron beam evaporation.

[0046] S5. Fill the double-groove region with a passivation layer 106 to cover the p-type oxide semiconductor 104 in the second heterojunction pn junction region and the gallium oxide drift layer 103 at the edge of the n-type doped gallium oxide-based wafer. The passivation layer 106 can be prepared by atomic layer deposition, plasma-enhanced chemical vapor deposition, magnetron sputtering, other physical or chemical vapor deposition and other methods, and the material can be a single-layer or multi-layer insulating dielectric material such as Al2O3, SiO2, SiNx or others.

[0047] Define a pattern on the passivation layer 106 by photolithography, and carry out patterning by dry etching, wet etching and other methods.

[0048] S6. Define a pattern by photolithography on the surface of the passivation layer 106, and deposit metal or polysilicon to form a field plate electrode 107. The field plate electrode 107 can be prepared by magnetron sputtering, electron beam evaporation, other physical or chemical vapor deposition and other methods. The field plate electrode 107 is connected to the anode 105.

[0049] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0050] The above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit it. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present application can still modify the technical solutions described in the foregoing embodiments, or can easily conceive of changes, or make equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. All of them should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A short-sized gallium oxide power device edge terminal structure, characterized in that: It includes a gallium oxide drift layer, an n-type doped gallium oxide substrate and a cathode which are stacked in sequence; An n-type doped gallium oxide based wafer is prepared by epitaxially growing a gallium oxide drift layer on the n-type doped gallium oxide substrate; a p-type oxide semiconductor is deposited on a side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterogeneous pn junction region, and an anode is provided on the surface of the p-type oxide semiconductor; The edge of the first heterogeneous pn junction region is etched to form a double trench, and a p-type oxide semiconductor is deposited on the bottom of the double trench and the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region; The double trench is filled with a passivation layer, which covers the p-type oxide semiconductor in the second heterogeneous pn junction region and the gallium oxide drift layer at the edge of the n-type doped gallium oxide-based wafer. A field plate electrode is provided on the surface of the passivation layer, and the field plate electrode is connected to the anode.

2. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The p-type oxide semiconductor is of an amorphous or polycrystalline structure.

3. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The hole concentration of the p-type oxide semiconductor is 1×10 17 / cm 3 ~1× 10 20 / cm 3 , and the hole concentration of the p-type oxide semiconductor is not lower than that of the gallium oxide drift layer.

4. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The thickness of the p-type oxide semiconductor is 10 nm to 1 μm.

5. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The double grooves have a groove depth of 5 μm to 10 μm, a width of 2 μm to 5 μm, and a spacing between the double grooves of 2 μm to 5 μm.

6. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The length of the passivation layer is greater than the length of the double trenches.

7. The short-sized gallium oxide power device edge terminal structure according to claim 1, characterized in that: The field plate electrode is connected to the anode, and the length of the field plate electrode covering the passivation layer is greater than the length of the double groove region.

8. The method for preparing a short-sized gallium oxide power device edge terminal structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, epitaxially growing a gallium oxide drift layer on an n-type doped gallium oxide substrate to obtain an n-type doped gallium oxide-based wafer; S2, depositing a cathode on a side of the n-type doped gallium oxide substrate away from the gallium oxide drift layer; S3, forming a double trench structure by etching at an edge of a side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate; S4, depositing a p-type oxide conductor on the side of the gallium oxide drift layer away from the n-type doped gallium oxide substrate to form a first heterogeneous pn junction region, depositing a p-type oxide conductor on the bottom of the double trench structure and the top of the mesa formed between the double trenches to form a second heterogeneous pn junction region; depositing an anode in the first heterogeneous pn junction region; S5, depositing a passivation layer in the double trench region to cover the p-type oxide semiconductor in the second heterogeneous pn junction region and the gallium oxide drift layer at the edge of the n-type doped gallium oxide-based wafer; S6. Deposit a field plate electrode on the surface of the passivation layer and connect the field plate electrode to the anode.

9. The method for preparing a short-sized gallium oxide power device edge terminal structure according to claim 8, characterized in that: The cathode in step S1 deposits Ti / Au alloy or Ti / Al / Ti / Au alloy by magnetron sputtering or electron beam evaporation, and the anode in step S4 deposits Ni / Au alloy by magnetron sputtering or electron beam evaporation.

10. The method for preparing a short-sized gallium oxide power device edge terminal structure according to claim 8, characterized in that: The p-type oxide semiconductor described in step S4 is prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition method, and the p-type oxide semiconductor material is a single layer or multilayer p-type oxide semiconductor material of NiO or Cu2O; the passivation layer described in step S6 is prepared by atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, physical or chemical vapor deposition method, and the passivation layer material is a single layer or multilayer insulating dielectric material of Al2O3, SiO2 or SiNx.

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