Semiconductor device and method of manufacturing the same
By designing a gate electrode with a separator region in the vertical gate trench of the semiconductor device, the problems of large resistance and high mechanical stress in the prior art are solved, lower resistance and mechanical stress are achieved, and mobility and performance are improved.
Patent Information
- Application Number
- CN202411316775.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-21
- Filing Date
- 2024-09-20
- Publication Date
- 2025-03-25
AI Technical Summary
In existing semiconductor devices, the gate electrode has a large resistance, resulting in an increase in mechanical stress and affecting mobility and resistance performance.
A gate electrode with a separator region is designed in a vertical gate trench, located inside the metal inlay region, reducing mechanical stress by lateral arrangement and reducing the coefficient of thermal expansion using a non-metallic separator material such as silicon material.
Effectively reduce the resistance of the gate electrode, reduce mechanical stress, improve mobility and overall performance of the semiconductor device.
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Figure CN119698054A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] The semiconductor device may have a gate electrode in a vertical gate trench, wherein a channel region is arranged laterally next to the gate trench. By applying a voltage to the gate electrode, channel formation in the channel region may be triggered. Depending on the specific device, a vertical current flow in the channel region may be caused, for example, between a source and a drain region. Summary of the invention
[0003] Examples of the present disclosure are directed to an advantageous semiconductor device having a gate electrode in a vertical gate trench.
[0004] In an embodiment, the gate electrode includes an outer gate region, a metal inlay region and a spacer region. From a central position within the gate electrode, the spacer region, the metal inlay region and the outer gate region are arranged laterally outward toward the channel region in succession. In other words, the outer gate region is laterally closer to the channel region than the metal inlay region, and the metal inlay region is laterally closer to the channel region than the spacer region, which may apply at least to a vertical section of the gate electrode, not necessarily to its entire vertical height.
[0005] The outer gate material close to or adjacent to the gate dielectric can, for example, be selected for work function optimization. This can, for example, enable a small work function difference and a low threshold voltage. Vice versa, the metal material of the metal inlay region can, for example, reduce the resistance of the gate electrode. However, the metal inlay may not completely fill the inner part of the gate electrode, instead, a separator region can be provided. Compared to a complete metal inlay, the separator region can, for example, reduce mechanical stresses, such as compressible stresses along the channel region, thereby increasing mobility and reducing the resistance of the semiconductor device.
[0006] Throughout the present disclosure, and in particular in the dependent claims, specific embodiments and features are provided. Thus, independent of the specific claim category, individual features will be disclosed, the present disclosure relates to equipment and device aspects, and also to method and use aspects. If, for example, a device is described that is manufactured or used in a specific way, this also discloses the corresponding manufacturing process or use, and vice versa. In general, the scheme of the present disclosure is to provide a gate electrode with a separator region, which is particularly located laterally inside a metal inlay region. For example, depending on the geometry, the separator region can also simplify manufacturing (for example, compared to a complete metal inlay).
[0007] The "contiguous arrangement" of the separator region, the metal inlay region and the outer gate region relates to a lateral direction, such as a first lateral direction. In a second lateral direction that is inclined relative to the first lateral direction or perpendicular to the first lateral direction, the gate electrode and the gate trench can have an elongated extension. In other words, the lateral successive arrangement can be visible in a vertical section perpendicular to the length extension of the gate electrode. For example, as seen in the section, the outer gate region can be adjacent to the gate dielectric, and / or the metal inlay region can be adjacent to the outer gate region (e.g., except for the intermediate silicide / barrier layer), and / or the separator region can be adjacent to the metal inlay region.
[0008] The "center position" to which the lateral arrangement refers is located in the gate electrode, for example in the center when viewed in a vertical section. As described in detail below, the gate electrode can in particular have a symmetrical design, the center position being, for example, a mirror symmetry axis or being located on a mirror symmetry axis. The lateral arrangement is present at least on a "vertical section" of the gate electrode, for example not necessarily on its entire height. The vertical section can, for example, have at least a vertical overlap with the channel region, in particular, it can extend in a vertical direction over the entire vertical height of the channel region. Below or above the vertical section, the gate electrode can have a different arrangement or geometry, for example only one or some of the regions can be present there.
[0009] "Vertical" or "in a vertical direction" refers to a vertical direction, which is, for example, perpendicular to a surface of a device, such as a surface of a substrate or an epitaxial layer formed on a substrate. "Above" means closer to a first side of a semiconductor body or device (e.g., a side to which a source terminal can be connected), and "below" means closer to a vertically opposite second side of a semiconductor body or device (e.g., a side to which a drain terminal can be connected). The upper part of an element or region is, for example, closer to the first side than the lower part of the same element or region. "Laterally" or "in a lateral direction" refers to a lateral direction perpendicular to the vertical direction, in which direction, for example, the area of a device or a die is taken. In particular, the first lateral direction can be a lateral direction of a gate electrode or a gate trench, wherein the second lateral direction is its length direction.
[0010] Together with the gate dielectric, the gate electrode may form a gate region of the device. For example, as seen in a vertical top view, the gate trench and the gate electrode can have elongated extensions, for example forming stripes or a grid pattern depending on the cell layout. In general, the semiconductor device may be any type of gate controlled device having a gate electrode in a trench, such as an IGBT or a lateral device having two load contacts (and a channel next to the gate trench) on the same side of the semiconductor body. In particular, the device is a vertical transistor device having its load contacts on opposite sides of the semiconductor body.
[0011] On a first side of the semiconductor body (the gate trench extends from the first side into the semiconductor body), a source region of a vertical transistor device may be arranged, wherein its drain region is arranged on a vertically opposite second side of the semiconductor body. In the middle, a body region located laterally next to the gate trench is placed, and a channel region is formed in the body region. In addition, the transistor device may include a drift region, which is located between the body region and the drain region in a vertical direction and is made of the same doping type as the drain region, but with a lower doping concentration. The source region, the drain region and the drift region may be made of a first doping type, and the body region may be made of a second doping type, wherein in an exemplary embodiment, the first type is n-type and the second type is p-type.
[0012] Considering the semiconductor device or die as a whole, reducing the resistance of the gate electrode with the metal inlay region can, for example, reduce the required gate contacts or gate contact runners (per area). This in turn can, for example, reduce the complexity in terms of testing and wiring, or reduce area consumption. In addition, for example, in the case of a layout where the gate resistance is coupled to the output resistance, a smaller output resistance (e.g., smaller than the gate resistance) can also cause problems with damping overshoot. In addition, a low gate resistance can, for example, support fast switching.
[0013] Vice versa, in addition to the different work functions, a fully metal gate or even a fully metal inlay may in some cases induce mechanical stresses. A separator region having different mechanical properties than the metal material can, for example, introduce less mechanical stress into the gate electrode, or even serve as a kind of buffer zone. Typically, the separator region may even be a cavity or a gap, for example not filled with solid material. Independently of whether a quasi-vacuum or a gas is present in such a cavity, it has different mechanical properties than the metal inlay region. In this way, a gate electrode comprising a metal inlay and a separator region adjacent to the metal inlay may allow a reduced resistance of the gate electrode while reducing the mechanical stresses in the gate electrode.
[0014] In an embodiment, the separator region is made of a separator material different from the metal material of the metal inlay region. In particular, the separator material can be a non-metallic material. Compared to metals, non-metallic materials can, for example, have a lower coefficient of thermal expansion, which can reduce mechanical stress during manufacture or use.
[0015] In an embodiment, the spacer material is a silicon material. The silicon material includes silicon, for example, as a component of a compound, or includes only silicon, such as amorphous silicon or polycrystalline silicon. In particular, the silicon material can be an electrically insulating material, such as silicon nitride or in particular silicon oxide. Typically, the gate electrode may include one or more additional regions in addition to the spacer region, such as a central gap region or one or more additional layers (e.g., silicon and / or silicon oxide). However, in particular, the central portion of the gate electrode is completely filled with the spacer region, which may be made in particular of silicon oxide.
[0016] In an embodiment, the external gate material is a conductive silicon material. This can, for example, allow a small work function difference, for example compared to a fully metal gate. A fully metal gate may require a strongly reduced body doping to achieve a comparable threshold voltage, which may, for example, result in a very low channel doping with increased leakage. In particular, for reduced gate dielectric thicknesses, a fully or direct metal gate may also be expected to create reliability issues. Independent of these details, the conductive silicon material can, for example, be amorphous silicon or in particular polysilicon, for example n-doped or p-doped polysilicon.
[0017] In an embodiment, the metal inlay region has a lateral thickness of a maximum of 200 nm. Even a fairly thin metal liner may still be sufficient to reduce resistance, while the thickness limitation may, for example, reduce mechanical stress. In addition, the upper limit of the lateral thickness of the metal inlay region may be 150 nm, 100 nm, 80 nm, or 60 nm, and the lower limit is, for example, 20 nm, 30 nm, or 40 nm. In an exemplary embodiment, it has a lateral thickness of approximately 50 nm.
[0018] As discussed above, the lateral stack having the separator region, the metal inlay region, and the outer gate region does not necessarily exist over the entire vertical height of the gate electrode. In an embodiment, the metal inlay region extends further upward than the outer gate region. In other words, the upper end of the metal inlay region can be located at a greater vertical height than the upper end of the outer gate region. The metal inlay region extending upward from the outer gate region can be used to increase or modify the resistance of the gate electrode. A larger vertical extension of the metal inlay region can reduce the resistance, while, for example, a smaller vertical extension of the metal inlay region can reduce the gate-source capacitance. With respect to the lower ends of the outer gate region and the metal inlay region, they can be located at different vertical heights or at the same vertical height.
[0019] In an embodiment, the insulating layer arranged on the first side of the semiconductor body is made of the same continuous spacer material as the spacer region. In other words, the spacer region and the insulating layer can be formed in the same process step, the deposited spacer material filling the central part of the gate electrode and forming the insulating layer on the first side of the semiconductor body. The spacer material can be, for example, borophosphosilicate glass (BPSG) or an oxide, such as silicon oxide, in particular a doped oxide.
[0020] In an embodiment, an additional insulating layer is arranged on the first side of the semiconductor body, that is to say below the insulating layer made of the separator material. The additional insulating layer can, for example, be an undoped oxide, such as silicon oxide, such as a plasma oxide. In summary, the insulating layer stack can, for example, comprise an HDPE oxide layer with a doped oxide layer above it, the latter forming the separator material. It can consist of two layers, such as an insulating layer and an additional insulating layer, or comprise another insulating layer in the middle, such as another undoped oxide layer, which may be followed by a reflowed doped oxide. Independently of these details, the additional insulating layer can, for example, be used as a hard mask in an etching step, see below for details. With respect to the device, the additional insulating layer can, for example, cover the outer gate region upwards in a vertical direction and be interrupted above the separator region.
[0021] In an embodiment, at least one of the barrier layer and the silicide layer is arranged laterally between the outer gate region and the metal inlay region. The barrier layer can, for example, include titanium (Ti) and / or tungsten (W) and / or tantalum (Ta), for example in combination with nitrogen (N) and / or carbon (C). Examples include, but are not limited to, TiN, TiW, tungsten nitride (W2N, WN, WN2), TaN, and the like. The silicide layer can, in particular, be arranged laterally between the outer gate region and the barrier layer. The silicide layer can, for example, be formed by heat treating a thin layer deposited for this purpose (that is, a silicide-forming layer) to diffuse metal atoms out of the thin layer (e.g., Ti layer).
[0022] In an embodiment, in a lateral portion of the gate electrode where the vertical gate contact contacts the gate electrode, a gate electrode is provided without a spacer region. In particular, it is also possible to provide a gate electrode without a metal inlay region there. In other words, the outer gate material (in particular, silicon gate material) can be left in place in this portion, which can, for example, simplify the vertical contact formation and / or allow the same vertical contact as in the case of a full silicon gate.
[0023] In an embodiment, the gate electrode has a symmetrical design, and the additional channel region is arranged on a laterally opposite side of the gate trench. Here, "laterally opposite" can refer to a first lateral direction (lateral direction). The vertical axis of mirror symmetry can particularly pass through the separator region in the center, see above. In other words, the gate electrode may include an additional (second) outer gate region and an additional (second) metal inlay region, which are arranged laterally outward from a central position in the gate electrode toward the additional channel region. Viewed in a vertical section, for example in the lower part of the gate electrode, the first and second outer gate regions and / or the first and second metal inlay regions may be connected to each other respectively. However, in particular, when viewed in a vertical section, the separator region may completely intersect the gate electrode in the vertical direction. In terms of manufacturing, the trench may initially be filled with a continuous outer gate material, which is then shaped into the first and second outer gate regions in an etching step.
[0024] The present disclosure also relates to a method of manufacturing a semiconductor device (particularly, a semiconductor device as discussed above). The method may include:
[0025] i.) etching vertical gate trenches;
[0026] ii.) depositing an external gate material in the vertical gate trench;
[0027] iii.) etching the outer gate material in the vertical gate trench to form an outer gate region;
[0028] iv.) depositing a metal material in the vertical gate trench to form a metal inlay region;
[0029] v.) forming a separator zone.
[0030] In the case of a separator region made of a solid separator material, step v.) can comprise depositing the separator material in the gate trench. Prior to step ii.), a gate dielectric may be formed in the gate trench, for example deposited or thermally grown. In step iii.), a hard mask arranged on the first side of the semiconductor body may be used to define the area for the etching step. In particular, the additional insulating layer discussed above may be used as a hard mask, so that the hard mask is not removed after the etching step.
[0031] In an embodiment, an etching step for etching back the metal material is applied between step iv.) and step v.). This can be, for example, an anisotropic etching, leaving a layer of metal material on the inner sidewalls of the outer gate region (the sidewalls facing away from the channel region). However, in general, the metal deposition in step iv.) can also be suitable for leaving a spacer region without the need for subsequent etching back.
[0032] In an embodiment, the gate electrode having the silicide layer may be formed by depositing the silicide-forming layer and annealing the silicide-forming layer to form the silicide. The silicide can in particular be formed before step iv.), in particular before the deposition of the barrier layer.
[0033] The contact plug of the device (particularly the source contact plug) may also include a silicide layer. The contact plug may be particularly a body / source contact plug, the silicide forming an electrical contact for the body region and the source region. The silicide layer of the contact plug may be formed particularly after the silicide layer of the gate electrode, so that the thermal budget is not constrained. Otherwise, the silicide of the contact plug may, for example, grow undefined in the body region / towards the channel. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The device and its production are explained in more detail below with the aid of exemplary embodiments, wherein individual features can also be relevant in different combinations.
[0035] Figure 1 shows a schematic cross section through a device having a gate electrode in a gate trench;
[0036] Figure 2 Show Figure 1 Detailed view of the gate electrode;
[0037] Figure 3a -e shows the different steps of manufacturing the gate electrode;
[0038] Figure 4 A flow chart summarizing some of the manufacturing steps is shown. DETAILED DESCRIPTION
[0039] Figure 1 A cross-sectional view through a semiconductor device 1 is shown. At a first side 30.1 of a semiconductor body 30, it comprises a source region 2 above a body region 3. Laterally beside the body region 3, a gate electrode 4 is arranged in a vertical gate trench 5. The gate electrode 4 is capacitively coupled to a channel region 6, which is formed in the body region 3. Below the channel region 6, a drift region 23 is formed. The drift region 23 has the same doping type as the drain region 24 arranged at the second side 30.2 of the semiconductor body 30, but has a lower doping concentration. In the example shown, the source region 2, the drift region 23 and the drain region 24 are n-doped, and the body region 3 is p-doped.
[0040] The gate electrode 4 comprises an outer gate region 8, which is made of an outer gate material 80. In addition, it comprises a metal inlay region 9 made of a metal material 90 and a spacer region 10. In the example shown, the outer gate material 80 is doped polysilicon and the metal material 90 is tungsten. For further details of the intermediate layer stack, refer to Figure 2The separator region 10 is made of a separator material 100, which in this example is BPSG.
[0041] With reference to the center position 20 in the gate electrode 4, the spacer region 10, the metal inlay region 9 and the outer gate region 8 are arranged laterally outwardly in succession towards the channel region 6. This applies in the vertical section 4.1 of the gate electrode 4, that is, in its lower part. In the upper part of the gate electrode 4, the metal inlay region 9 protrudes from the outer gate region 8, the upper end 9.1 of the metal inlay region 9 being located at a greater vertical height than the upper end 8.1 of the outer gate region 8.
[0042] At the first side 30.1 of the semiconductor body 30, an insulating layer 40 is arranged, wherein an additional insulating layer 45 is arranged between the insulating layer 40 and the semiconductor body 30. The additional insulating layer 45 can be used as a hard mask during the processing of the gate electrode 4 (see below), and can be made of undoped silicon oxide (e.g. plasma oxide). The insulating layer 40 is made of BPSG, that is, of the same continuous spacer material 100 as the spacer region 10.
[0043] On the insulating layer 40, a metallization 120 is arranged, which can be a metallization stack or a single source metal plate. The metallization 120 is connected to the source region 2 and to the body region 3 via a source contact plug 121 (referenced only on the right side, symmetrical design). The source contact plug 121 is connected to the source region 2 and the body region 3 via a silicide layer 122, which is not shown in more detail here.
[0044] exist Figure 1 , below the gate electrode 4, a field electrode region 110 is arranged in the gate trench 5. The field electrode region 110 includes a field electrode 111 and a field dielectric 112, which capacitively couples the field electrode 111 to the drift region 23 for field shaping. However, the field electrode region 110 may also not be present, or may be arranged outside the gate trench 5, such as in an additional elongated trench adjacent to the gate trench 5 or in one or more columnar or needle-shaped trenches adjacent to the gate trench 5. The present disclosure also contemplates such alternative arrangements of the field electrode region 110 and is not limited to the field electrode region 110 being arranged in the gate trench 5.
[0045] Figure 2 In a more detailed view, the gate electrode 4 is shown. In general, in the present disclosure, similar reference numerals are used for similar elements and reference is also made to the description of the other figures, respectively. The gate electrode 4 belongs to a gate region 140, which additionally comprises a first gate dielectric 141 and a second gate dielectric 142. The gate electrode 4 is coupled to the channel region 6 via the first gate dielectric 141 and to the additional channel region 106 via the second gate dielectric 142.
[0046] In addition to the separator region 10, the metal inlay region 9 and the external gate region 8, Figure 2 Also shown are a barrier layer 50 and a silicide layer 55. In the vertical section 4.1 of the gate electrode 4, the silicide layer 55 is laterally arranged between the outer gate region 8 and the barrier layer 50, and the barrier layer 50 is laterally arranged between the silicide layer 55 and the metal inlay region 9. The barrier layer 50 may be, for example, a titanium nitride layer.
[0047] The first lateral direction 131 is a lateral direction of the gate trench 5 , in a second lateral direction 132 it has an elongated extension. Both lateral directions 131 , 132 are perpendicular to the vertical direction 133 . Figure 2 Also shown is a symmetrical design of the gate electrode 4. On laterally opposite sidewalls of the gate trench 5, an additional channel region 106 is arranged, and the gate electrode 4 comprises an additional outer gate region 108, an additional silicide layer 155, an additional barrier layer 150 and an additional metal inlay region 109. The additional channel region 106 may be connected in parallel to the channel region 6, for example belonging to another device cell assigned to the same drain region 24.
[0048] Figure 3a -e illustrates some of the steps in making the gate electrode. Figure 3a , the gate trench 5 has been etched and the field electrode region 110 has been formed. In the upper part of the gate trench 5, the outer gate material 80 has been deposited and the first and second gate dielectrics 141, 142 have been formed. So far, this is a standard gate process for manufacturing polysilicon gates in trenches. The outer gate material 80 is covered by an additional insulating layer 45, which has been deposited on the first side 30.1 of the semiconductor body. On the additional insulating layer 45, a mask layer 170 (the mask layer 170 is a photoresist in the example shown) has been deposited and structured to provide an opening 171 in the center above the gate trench 5.
[0049] In a subsequent isotropic etching step, the opening 171 exposes the additional insulating layer 45. In a first step, a trench or recess 175 is etched in the additional insulating layer 45. In a second step, the additional insulating layer 45 with the recess 175 is used as a hard mask to etch a recess 176 in the outer gate material 80. Thus, the outer gate region 8 and the additional outer gate region 108 are formed, see Figure 3b , where the mask layer has been removed.
[0050] exist Figure 3cIn the embodiment of the present invention, the silicide layer 55, 155 has been formed by depositing a thin titanium layer (e.g., 2-5 nm) as a silicide-forming layer and annealing such a silicide-forming layer, for example, at a temperature of about 650° C.-750° C. Subsequently, in order to form the barrier layer 50, 150, a barrier layer material 180 (e.g., titanium nitride) has been deposited. The thickness may be about 5 nm-10 nm. On the barrier layer material 180, a metal material 90 has been deposited, for example, a tungsten layer having a thickness of about 100 nm.
[0051] Figure 3d The situation is shown after an anisotropic etching step which leaves the barrier layer 50, 150 and the metal material 90 on the inner sidewalls of the recess, that is to say the metal inlay region 9 and the additional metal inlay region 109. They can have a respective thickness of approximately 50 nm, for example. Figure 3e The gate electrode 4 is shown after the spacer region 10 has been formed by deposition of the spacer material 100. In the same process step, the insulating layer 40 has been formed, which is made of the same continuous spacer material 100, that is to say doped silicon oxide in this example. The insulating layer 40 has been planarized by a thermal step in the range of 850° C.-1000° C., for example.
[0052] Figure 4 Flowchart summarizing some manufacturing steps. After etching 201 the vertical gate trench, the outer gate material is deposited 202 in the gate trench. Then, the outer gate material is etched 203 to form the outer gate region before depositing 204 the metal material for the metal inlay region. After etching back 205 the metal material, the spacer region is formed 206.
Claims
1. A semiconductor device (1), comprising: A gate electrode (4) located in the vertical gate trench (5); A channel region (6) located laterally next to the gate trench (5); The gate electrode (4) comprises: An external gate region (8), made of an external gate material (80); A metal inlay region (9), made of a metal material (90); a separator area (10); wherein the outer gate material (80) and the separator region (10) are different from the metal material (90), And wherein the separator region (10), the metal inlay region (9) and the outer gate region (8) are arranged successively from a central position (20) within the gate electrode (4) laterally outward toward the channel region (6) at least in a vertical section (4.1) of the gate electrode (4).
2. The semiconductor device (1) as claimed in claim 1, wherein the spacer region (10) is made of a spacer material (100) different from the metal material (90).
3. The semiconductor device (1) as claimed in claim 2, wherein the spacer material (100) is a silicon material, in particular an electrically insulating silicon material.
4. A semiconductor device (1) as claimed in any one of the preceding claims, wherein the external gate material (80) is a conductive silicon material.
5. The semiconductor device (1) as claimed in any one of the preceding claims, wherein the metal inlay region (9) has a lateral thickness of at most 200 nm.
6. The semiconductor device (1) as claimed in any one of the preceding claims, wherein the metal inlay region (9) extends further upwards than the outer gate region (8).
7. A semiconductor device (1) as described in any one of the preceding claims, wherein the vertical gate trench (5) extends from a first side (30.1) of the semiconductor body (30) into the semiconductor body (30), and an insulating layer (40) is arranged on the first side (30.1) of the semiconductor body (30), wherein the insulating layer (40) is made of the same continuous separator material (100) as the separator region (10).
8. The semiconductor device (1) as claimed in claim 7, wherein an additional insulating layer (45) is arranged on the first side (30.1) of the semiconductor body (30) between the insulating layer (40) and the semiconductor body (30) in a vertical direction.
9. The semiconductor device (1) as claimed in any one of the preceding claims, wherein a barrier layer (50) and / or a silicide layer (55) is arranged laterally between the external gate region (8) and the metal inlay region (9).
10. A semiconductor device (1) as claimed in any one of the preceding claims, wherein the gate electrode (4) is formed without the spacer region (10), in particular, without the metal inlay region (9), in a lateral portion where the gate electrode (10) is contacted by a vertical gate contact.
11. The semiconductor device (1) as claimed in any one of the preceding claims, wherein the gate electrode (4) has a symmetrical design when viewed in a vertical section, additional channel regions (106) being arranged on laterally opposite sides of the gate trench (5).
12. A method for manufacturing a semiconductor device (1), in particular a method for manufacturing a semiconductor device (1) as claimed in any one of the preceding claims, the method comprising the steps of: i.) etching (201) a vertical gate trench (5); ii.) depositing (202) an outer gate material (80) in the vertical gate trench (5); iii.) etching (203) the outer gate material (80) in the vertical gate trench (5) to form an outer gate region (8); iv.) depositing (204) a metal material (90) in the vertical gate trench (5) to form a metal inlay region (9); v.) Particularly, forming (206) a spacer region (10) by depositing a spacer material (100) in said vertical gate trench (5).
13. The method of claim 12, comprising: An etching step for etching back (205) the metal material (90) in the vertical gate trench (5) after step iv.) and before step v.).
14. A method for manufacturing a semiconductor device (1) according to claim 12 or 13, wherein the semiconductor device (1) has a gate electrode (4), wherein the gate electrode (4) comprises a silicide layer (55) laterally located between the external gate region (8) and the metal inlay region (9), the method comprising: - depositing a silicide-forming layer; - annealing the silicide-forming layer to form the silicide layer (55); The annealing is carried out before step iv.).
15. A method for manufacturing a semiconductor device (1) as claimed in any one of claims 12 to 14, wherein the semiconductor device (1) has a gate electrode (4) including a silicide layer (55) and has a source contact plug (121) including a silicide layer (122), wherein the silicide layer (122) of the source contact plug (121) is formed after the silicide layer (55) of the gate electrode (4).