Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to the technical field of semiconductor structures, and discloses a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a first substrate slice and a second substrate slice; depositing polycrystalline silicon on the surface of one side of the second substrate slice to form a polycrystalline silicon layer; growing or depositing an oxide on the surface of one side, far away from the second substrate slice, of the polycrystalline silicon layer to form a first buried oxide layer; forming a graphic structure layer on the surface of one side, far away from the polycrystalline silicon layer, of the first buried oxide layer, wherein the graphic structure layer comprises a plurality of conductive structures and a plurality of insulator structures; based on a thermal oxidation process, growing an oxide on the surface of one side of the first substrate slice to form a second buried oxide layer; and carrying out bonding processing on the surface of one side, far away from the first buried oxide layer, of the graphic structure layer and the surface, subjected to ion implantation processing, of the second buried oxide layer so as to obtain the semiconductor structure. The threshold voltage of the semiconductor device can be adjusted, and the electrical performance of the semiconductor device can be flexibly optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Silicon on Insulator (SOI) adds a buried oxide layer (BOX) between the top silicon and the substrate. This structure electrically isolates the top silicon and the substrate, which can reduce the parasitic capacitance between transistors, reduce the delay in signal transmission, and increase the operating speed of the circuit. It also reduces the leakage current from the substrate to the top silicon device and reduces the power consumption of the circuit.

[0003] However, in the Partially Depleted Silicon on Insulator (PDSOI) process, since the silicon body layer is partially depleted and not connected to the substrate or the source, the silicon body layer becomes a floating potential region, making it impossible for the charge in the silicon body layer to be effectively released or fixed through an external path, thereby causing a floating body effect and affecting the electrical performance of semiconductor devices formed by SOI. Summary of the invention

[0004] In view of this, the present invention provides a method for preparing a semiconductor structure and a semiconductor structure to improve the problem of poor electrical performance of semiconductor devices formed by SOI.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor structure, the method comprising: providing a first substrate sheet constituting an active layer and a second substrate sheet constituting a semiconductor substrate layer; depositing polysilicon on a surface of one side of the second substrate sheet to form a polysilicon layer; growing or depositing oxide on a surface of the polysilicon layer on a side away from the second substrate sheet to form a first buried oxide layer; forming a graphic structure layer on a surface of the first buried oxide layer on a side away from the polysilicon layer, the graphic structure layer comprising a plurality of conductive structures and a plurality of insulator structures, the plurality of conductive structures and the plurality of insulator structures being alternately arranged in a preset direction, and one side of adjacent conductive structures and insulator structures being abutted; growing oxide on a surface of one side of the first substrate sheet based on a thermal oxidation process to form a second buried oxide layer; performing ion implantation treatment on a surface of the second buried oxide layer on a side away from the graphic structure layer; performing bonding treatment on a surface of the graphic structure layer on a side away from the first buried oxide layer and a surface of the second buried oxide layer after the ion implantation treatment to obtain a semiconductor structure.

[0006] The preparation method of the semiconductor structure provided in this embodiment forms a graphic structure layer between the buried oxide layers (i.e., the first buried oxide layer and the second buried oxide layer), which is equivalent to introducing a back gate in the SOI structure. The back gate can, on the one hand, reduce the parasitic capacitance of the semiconductor device and increase the maximum operating frequency and gain-bandwidth product of the semiconductor device. On the other hand, it can optimize the linear characteristics of the semiconductor device and reduce distortion. On the other hand, it can enhance the anti-interference ability of the semiconductor device to external signals. On the fourth hand, it can effectively absorb and conduct the heat generated by the device, improve thermal management, and improve the reliability of the semiconductor device. On the fifth hand, it can flexibly optimize the key RF performance indicators of the semiconductor device, such as gain, noise and linearity.

[0007] In an optional embodiment, a graphic structure layer is formed on a surface of the first buried oxide layer away from the polysilicon layer, including: depositing a conductive material on a surface of the first buried oxide layer away from the polysilicon layer; etching the conductive material to form a plurality of conductive structures; filling insulating material between the plurality of conductive structures based on a high aspect ratio process; removing part of the insulating material so that the height of the insulating material is a preset height to form a graphic structure layer.

[0008] In an optional implementation, removing a portion of the insulating material so that the height of the insulating material is a preset height includes: removing a portion of the insulating material based on a chemical mechanical polishing method so that the height of the insulating material is a preset height.

[0009] In this embodiment, directly using the CMP method to remove the insulating material can improve the surface quality to a certain extent, making the surface of the insulating material more flat and smooth, which is beneficial to the subsequent process, and can also reduce the complexity of the process flow and improve processing efficiency.

[0010] In an optional embodiment, removing a portion of the insulating material so that the height of the insulating material is a preset height includes: removing a portion of the insulating material based on a chemical mechanical polishing method so that the height of the insulating material exceeding the conductive structure is greater than and the height of the insulating material beyond the conductive structure is less than or equal to The silicon dioxide is etched to make the height of the insulating material reach a preset height.

[0011] In this embodiment, the insulating material is removed by combining CMP and etching treatment, which can make it easier to control the height of the insulating material and reduce the risk of over-polishing and damaging the conductive structure.

[0012] In an optional embodiment, the solution used for the etching treatment is hydrofluoric acid.

[0013] In an optional embodiment, after bonding the surface of the graphic structure layer away from the first buried oxide layer and the surface of the second buried oxide layer after ion implantation, the method further includes: thermally annealing the semiconductor structure in an argon environment or in a mixed gas environment of argon and hydrogen so that the surface roughness of the semiconductor structure is less than or equal to 0.5 nm.

[0014] In an optional embodiment, the temperature when depositing polysilicon on one side surface of the second substrate sheet is in the range of 900° C. to 1200° C.

[0015] In an optional embodiment, the temperature of the thermal oxidation process ranges from 900°C to 1200°C.

[0016] In an optional implementation, the process parameters of the bonding process include: a temperature value range of 400° C. to 600° C., and a time value range of 1 min to 60 min.

[0017] In a second aspect, the present invention provides a semiconductor structure, which is prepared by the method provided by the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of forming a polysilicon layer on a second substrate according to an embodiment of the present invention;

[0021] Figure 3 is a schematic structural diagram of forming a first buried oxide layer on a polysilicon layer according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of a structure in which a conductive material is formed on a first buried oxide layer according to an embodiment of the present invention;

[0023] Figure 5 is a schematic structural diagram of forming a plurality of conductive structures on a first buried oxide layer according to an embodiment of the present invention;

[0024] Figure 6is a schematic structural diagram of forming an insulating material on a plurality of conductive structures according to an embodiment of the present invention;

[0025] Figure 7 is a schematic structural diagram of forming a graphic structure layer on a first buried oxide layer according to an embodiment of the present invention;

[0026] Figure 8 is a schematic structural diagram of forming a second buried oxide layer on a first substrate layer according to an embodiment of the present invention;

[0027] Fig. 9 According to an embodiment of the present invention Figure 8 A schematic diagram of a structure for ion implantation based on the invention;

[0028] Fig.10 According to an embodiment of the present invention Figure 7 and Fig. 9 Schematic diagram of the structure after bonding treatment;

[0029] Fig.11 According to an embodiment of the present invention Fig.10 A schematic diagram of the structure after heating treatment on the basis of;

[0030] Fig.12 According to an embodiment of the present invention Figure 6 Schematic diagram of the structure after polishing on the basis of;

[0031] Fig.13 is a schematic diagram of another semiconductor structure according to an embodiment of the present invention;

[0032] Fig.14 is a schematic diagram of yet another semiconductor structure according to an embodiment of the present invention.

[0033] Figure numerals: 10, semiconductor substrate layer; 20, polysilicon layer; 30, first buried oxide layer; 40, graphic structure layer; 41, conductive structure; 42, insulator structure; 50, second buried oxide layer; 60, active layer; 70, second substrate sheet; 80, conductive material; 90, insulating material; 100, first substrate sheet; 110, injection layer. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0035] In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0036] In a PDSOI metal oxide semiconductor field effect transistor (MOSFET) formed by a conventional SOI wafer, a floating body region is easily formed between the drain region and the substrate, and the floating body region accumulates charges, forming a floating body voltage (also known as the floating body effect), which affects the electrical performance of the PDSOI MOSFET. Among them, MOSFET can be referred to as MOS tube.

[0037] Specifically, the floating voltage affects the threshold voltage of the MOS tube. For example, a positive floating voltage will reduce the threshold voltage, thereby increasing the leakage current, and a negative floating voltage will increase the threshold voltage. The floating voltage will also change dynamically with the change of the device working state, resulting in an unstable threshold voltage.

[0038] Moreover, the change of floating body voltage will also cause parasitic bipolar transistor effect, further affecting the threshold voltage of the device. In addition, floating body voltage will reduce the subthreshold swing of the device, affect the switching speed or switching ratio, and cause unstable operating current. The floating body voltage will also cause heat to be generated in the floating channel area, causing the device temperature to rise, further deteriorating the operating current characteristics of the device.

[0039] In view of this, the present invention provides a method for preparing a semiconductor structure and a semiconductor structure, wherein a graphic structure layer of alternating conductive structures and insulator structures is arranged in a buried oxide layer, which can adjust the threshold voltage of the semiconductor device and flexibly optimize key radio frequency (RF) performance indicators such as gain, noise and linearity of the semiconductor device.

[0040] It should be understood that the above-mentioned semiconductor device is a semiconductor device formed based on the semiconductor structure provided by the present invention.

[0041] The semiconductor structure prepared by the present invention can be used to form a PDSOI MOS tube or other semiconductor devices, and the formed semiconductor devices can be applied to the RF field. The semiconductor structure prepared by the present invention is briefly described below in conjunction with the accompanying drawings.

[0042] like Figure 1 As shown, the semiconductor structure prepared by the method for preparing a semiconductor structure provided by the present invention includes a semiconductor substrate layer 10, a polysilicon layer 20, a first buried oxide layer 30, a graphic structure layer 40, a second buried oxide layer 50 and an active layer 60.

[0043] The semiconductor substrate layer 10, the polysilicon layer 20, the first buried oxide layer 30, the pattern structure layer 40, the second buried oxide layer 50 and the active layer 60 are stacked from bottom to top.

[0044] Exemplarily, the material of the active layer 60 can be one or more of silicon (Si), silicon-germanium alloy (SiGe), III-V materials (such as gallium arsenide (GaAs) or indium phosphide (InP)), aluminum nitride (AlN), gallium nitride (GaN) or silicon carbide (SiC).

[0045] Specifically, silicon germanium alloys are used for strain engineering, optimizing electron mobility, and can be used to form complementary metal oxide semiconductor (CMOS) devices or radio frequency (RF) devices. III-V materials are used to achieve high-speed electronic or optoelectronic properties, and can be used to form optoelectronic devices (such as lasers, light emitting diodes (LEDs)) or high-frequency devices, which require buffer layers or special treatments when there is lattice mismatch.

[0046] Aluminum nitride or gallium nitride is used in high electron mobility transistors (HEMTs), which are particularly suitable for high-power and high-frequency applications. Aluminum nitride or gallium nitride can be used to form power amplifiers or 5G communication base stations, which need to overcome differences in thermal expansion coefficients and lattice mismatch. Silicon carbide is used in high-power and high-temperature resistant applications and can be used to form power devices (such as MOS tubes, insulated gate bipolar transistors (IGBT), etc.), and the cost of silicon carbide epitaxy is relatively high.

[0047] When epitaxially growing the active layer 60, the mismatch rate needs to be controlled to avoid dislocations. Due to the difference in thermal expansion coefficients, the stress during material heating and cooling also needs to be controlled when epitaxially growing the active layer 60. Moreover, the defect density and quality of the interface are crucial to device performance, so the interface quality also needs to be controlled.

[0048] The graphic structure layer 40 includes a plurality of conductive structures 41 and a plurality of insulating structures 42, wherein the plurality of conductive structures 41 and the plurality of insulating structures 42 are alternately arranged along a preset direction, and one side of adjacent conductive structures 41 and insulating structures 42 abuts against each other. The preset direction may be a horizontal direction, and the thickness of the conductive structure 41 and the thickness of the insulating structure 42 may be the same or different.

[0049] Specifically, a plurality of conductive structures 41 may be arranged horizontally and spaced apart on the upper surface of the first buried oxide layer 30, and a plurality of insulator structures 42 may be arranged in the interval between two adjacent conductive structures 41, and there is no interval between the insulator structure 42 and the conductive structure 41. Figure 1 As shown, the right end surface of the first conductive structure 41 is connected to the left end surface of the first insulator structure 42 , and the left end surface of the second conductive structure 41 is connected to the right end surface of the first insulator structure 42 .

[0050] The present invention does not limit the specific materials of the conductive structure 41 and the insulating structure 42, as long as the conductive structure 41 meets the conductive requirements and the insulating structure 42 meets the insulating requirements. For example, the material of the conductive structure 41 can be at least one of amorphous silicon, polycrystalline silicon and metal, and the material of the insulating structure 42 can be an insulating material such as silicon oxide or silicon dioxide.

[0051] The semiconductor structure provided in this embodiment has a graphic structure layer 40 arranged in the buried oxide layer, which is equivalent to introducing a back gate into the semiconductor structure. By adjusting the back gate voltage, the electrical performance of the semiconductor device can be more flexibly adjusted, so that the semiconductor structure can meet different application requirements.

[0052] After the back gate is introduced, firstly, the parasitic capacitance of the semiconductor device can be reduced, and the maximum operating frequency and gain bandwidth product (GBW) of the semiconductor device can be improved.

[0053] Specifically, the charge distribution of the silicon body layer in the semiconductor device can be actively controlled through the back gate, further reducing the capacitance effect between the positive gate and the body layer, and increasing the cutoff frequency of the device, thereby improving the maximum operating frequency and gain-bandwidth product of the semiconductor device.

[0054] The relationship between the cut-off frequency and the parasitic capacitance can be expressed as follows:

[0055]

[0056] In formula (1), f T represents the cut-off frequency, g m Indicates the transconductance of the MOS tube, the unit is A / V, C gs It represents the gate-source parasitic capacitance, that is, the parasitic capacitance between the gate and source of the MOS tube, C gd It represents the gate-drain parasitic capacitance, that is, the parasitic capacitance between the gate and drain of the MOS tube, C gs +C gd Represents the total gate parasitic capacitance.

[0057] It can be seen from the above formula (1) that the parasitic capacitance of the semiconductor device is inversely proportional to the cut-off frequency. The smaller the parasitic capacitance, the higher the cut-off frequency, that is, the semiconductor device can operate at a higher frequency. Therefore, after reducing the parasitic capacitance of the semiconductor device through the back gate, the cut-off frequency of the device can be increased, thereby increasing the maximum operating frequency of the semiconductor device.

[0058] The relationship between the gain-bandwidth product and the parasitic capacitance can be expressed as formula (2):

[0059]

[0060] In formula (2), GBW represents the gain-bandwidth product, which represents the product of the amplifier's gain and bandwidth. L Represents the load capacitance, which includes the parasitic capacitance of semiconductor devices and external capacitance.

[0061] It can be seen from the above formula (2) that the parasitic capacitance of the semiconductor device is inversely proportional to the gain-bandwidth product. When the parasitic capacitance increases, the gain-bandwidth product decreases, and when the parasitic capacitance decreases, the gain-bandwidth product increases. Therefore, after reducing the parasitic capacitance of the semiconductor device through the back gate, the gain-bandwidth product can be improved.

[0062] Specifically, lower parasitic capacitance reduces signal delay and charge accumulation time, enabling devices to respond quickly at higher frequencies while reducing high-frequency losses and improving the performance of RF switching devices.

[0063] Secondly, the linear characteristics of semiconductor devices can be optimized and distortion can be reduced. Specifically, through the coordinated operation of the front gate and the back gate, the potential of the body layer can be controlled, so that the charge distribution in the channel is more uniform, and the threshold voltage drift and on-current change caused by the body layer potential fluctuation can be reduced, thereby reducing the nonlinear effect, improving the linearity of the device and reducing distortion.

[0064] The nonlinearity of semiconductor devices means that the relationship between the input signal and the output signal of the semiconductor device is not linear, that is, the output signal is no longer a simple multiple relationship. If the semiconductor device has nonlinear effects, the output signal will contain multiple harmonic components of the input signal frequency, resulting in signal distortion and harmonic distortion.

[0065] Thirdly, the anti-interference ability of semiconductor devices to external signals can be enhanced. Specifically, after the back gate is introduced, the back gate can play the role of shielding and regulating the body layer potential, thereby suppressing the floating of the body layer and enhancing the anti-interference ability of the semiconductor device. That is, the back gate can stabilize the body layer potential by applying an appropriate bias, so that the device has better robustness when facing external interference signals, reduces the impact of noise on signal processing, and thus improves the signal integrity of the device.

[0066] Fourthly, it can effectively absorb and conduct the heat generated by the device, improve thermal management, and enhance the reliability of semiconductor devices. Specifically, the back gate can provide a new heat dissipation path for semiconductor devices, and the back gate is close to the body layer, which can absorb the heat caused by high-speed switching and high current, and transfer the heat through the thermal conductive material, thereby improving thermal management, reducing the operating temperature of the device, and improving the reliability and stability of the device.

[0067] Fifthly, key RF performance indicators such as gain, noise and linearity of semiconductor devices can be flexibly optimized. Specifically, different characteristics of semiconductor devices can be regulated by the coordinated work of the front gate and the back gate. For example, the on-current and threshold voltage of the semiconductor device can be controlled by the front gate, and the body layer potential can be further adjusted by the back gate, thereby affecting the charge distribution of the channel, so that designers can flexibly adjust the gain of semiconductor devices according to different application requirements.

[0068] Through the coordinated work of the front gate and the back gate, the gain and response characteristics of the semiconductor device can be dynamically optimized according to the frequency and amplitude of the input signal to obtain the best signal amplification performance. At the same time, unnecessary noise and distortion can be reduced through back gate regulation, further enhancing the high-frequency performance of the semiconductor device.

[0069] like Figures 2 to 11 As shown, an embodiment of the present invention provides a method for preparing a semiconductor structure, and the method includes but is not limited to steps S101 to S107.

[0070] Step S101 , providing a first substrate sheet constituting an active layer and a second substrate sheet constituting a semiconductor substrate layer.

[0071] Exemplarily, the first substrate sheet may be a silicon substrate sheet having a resistivity of 0 ohm-cm to 100 ohm-cm, and the second substrate sheet may be a high-resistance silicon substrate sheet having a resistivity greater than 1000 ohm-cm.

[0072] Specifically, in RF devices, low parasitic capacitance is crucial to achieve high-frequency operation. The semiconductor substrate layer formed by high-resistance silicon substrate has a higher resistivity, which can effectively reduce parasitic capacitance and leakage current, and provide better insulation performance, prevent charge leakage between different layers, and ensure the normal operation of semiconductor devices.

[0073] Step S102, depositing polysilicon on one side surface of the second substrate to form a polysilicon layer.

[0074] For example, the deposition method may be chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0075] Specifically, Figure 2 As shown, polysilicon can be deposited on the upper surface of the second substrate sheet 70 by CVD to form a polysilicon layer 20. The temperature of the deposition process can be 900°C to 1200°C, and the second substrate sheet 70 forms a semiconductor substrate layer 10.

[0076] Specifically, the polysilicon layer 20 can be used as a back gate electrode. By adjusting the back gate voltage, the threshold voltage of the semiconductor device and the carrier concentration in the channel can be controlled. The polysilicon layer 20 can also play a shielding role, reducing the parasitic capacitance between the buried oxide layer and the substrate layer, thereby improving the switching speed and power consumption of the semiconductor device.

[0077] In one example, the thickness of the polysilicon layer 20 may range from 0.5 μm to 5 μm. That is, the thickness of the polysilicon layer 20 may be any value between 0.5 μm and 5 μm. For example, the thickness of the polysilicon layer 20 may be 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.8 μm, 2 μm, 3 μm, 3.5 μm, 4 μm, or 5 μm.

[0078] A thicker polysilicon layer can provide a stronger back gate effect, thereby more effectively adjusting the threshold voltage, and a thinner polysilicon layer can reduce parasitic capacitance. Moreover, a thinner polysilicon layer 20 may cause non-uniformity and defects in the manufacturing process, while an overly thick polysilicon layer 20 may increase process difficulty and cost.

[0079] In this embodiment, the thickness of the polysilicon layer 20 is limited to between 0.5 μm and 5 μm, which can achieve a balance between reducing parasitic capacitance and ensuring the performance of the back gate electrode while ensuring the feasibility and stability of the manufacturing process.

[0080] Step S103 , growing or depositing oxide on a surface of the polysilicon layer away from the second substrate to form a first buried oxide layer.

[0081] Specifically, the material of the first buried oxide layer may be silicon dioxide (SiO2).

[0082] In some embodiments, in forming Figure 2 After the structure shown in FIG. 1 is formed, silicon dioxide can be deposited on the upper surface of the polysilicon layer 20 by CVD to form a Figure 3 A first buried oxide layer 30 is shown.

[0083] In other embodiments, Figure 2 The structure shown in FIG. 1 is placed in a high temperature oxidation furnace. At a high temperature (e.g., a temperature of 900° C. to 1200° C.), oxygen reacts chemically with the upper surface of the polysilicon layer 20 to grow a layer of silicon dioxide, forming a Figure 3 A first buried oxide layer 30 is shown.

[0084] The present invention does not specifically limit the thickness of the first buried oxide layer 30 , and the thickness can be set by designers according to application scenarios and design requirements.

[0085] For example, the thickness of the first buried oxide layer 30 may be to For example, the thickness of the first buried oxide layer 30 may be or wait.

[0086] Specifically, the thickness of the first buried oxide layer is limited to to The back gate and the semiconductor substrate layer 10 can be completely separated to provide a stronger insulation isolation effect, thereby reducing the electrical interference of the semiconductor substrate layer 10 on the back gate. Moreover, it can provide a certain mechanical support for the upper graphic structure layer 40, the second buried oxide layer 50 and the active layer 60, thereby reducing the structural deformation caused by external stress or process.

[0087] Step S104, forming a pattern structure layer on a surface of the first buried oxide layer away from the polysilicon layer.

[0088] Specifically, step S104 at least includes step S1041 to step S1044:

[0089] Step S1041 , depositing a conductive material on a surface of the first buried oxide layer away from the polysilicon layer.

[0090] Exemplarily, the conductive material may be at least one of amorphous silicon, polysilicon and metal.

[0091] Specifically, Figure 4 As shown, after the first buried oxide layer 30 is formed, a conductive material 80 may be deposited on the upper surface of the first buried oxide layer 30 by CVD.

[0092] For example, the thickness of the conductive material 80 may be greater than The thickness of the conductive material 80 is less than or equal to For example, the thickness of the conductive material 80 may be or wait.

[0093] Step S1042, etching the conductive material to form a plurality of conductive structures.

[0094] For example, in forming Figure 4 After the structure shown in FIG. 1 is formed, step S1042 may specifically include: forming a photoresist layer on the upper surface of the conductive material; exposing the photoresist layer; after the exposure, developing the photoresist layer; after the development of the photoresist layer, etching the conductive material using the remaining photoresist of the photoresist layer as a mask; removing the photoresist on the conductive material to obtain a conductive film as shown in FIG. Figure 5 A plurality of conductive structures 41 are shown.

[0095] Step S1043 , filling insulating material between the plurality of conductive structures based on a high aspect ratio process.

[0096] Exemplarily, the insulating material may be silicon dioxide.

[0097] Specifically, in forming Figure 5 After the structure shown in FIG. 1 is formed, a high aspect ratio process (HARP) can be used to fill insulating material 90 between the plurality of conductive structures to obtain a structure as shown in FIG. Figure 6 The structure shown.

[0098] Among them, the high aspect ratio process is a non-plasma CVD thermal oxidation process that can meet the strict gap filling requirements of applications such as shallow trench isolation (STI) structures.

[0099] Step S1044, removing part of the insulating material to make the height of the insulating material reach a preset height, thereby forming a graphic structure layer.

[0100] Specifically, the preset height can be determined by the designer. For example, the preset height can be the height of the conductive structure, that is, the height of the insulating material is the same as the height of the conductive structure. For another example, the preset height can also be greater than the height of the conductive structure. For example, the preset height can be the height of the conductive structure and N (e.g. or The sum of (etc.), N is greater than 0.

[0101] Specifically, in the formation Figure 6 After the structure shown in FIG. 1 is formed, part of the silicon dioxide can be removed by polishing and etching to make the height of the silicon dioxide and the conductive structure the same, forming a structure as shown in FIG. Figure 7 The graphic structure layer 40 is shown.

[0102] For example, the thickness of the graphic structure layer 40 may range from to That is to say, the thickness of the graphic structure layer 40 can be to For example, the thickness of the graphic structure layer 40 can be or wait.

[0103] Specifically, back gates of different thicknesses can generate electric fields of different strengths, thereby flexibly regulating the carrier concentration and conductivity in the channel. A thinner back gate can generate a stronger electric field, which is more sensitive to carrier control and helps achieve higher switching speeds and lower power consumption. A thicker back gate can provide a more uniform electric field, reduce carrier scattering, and thus improve carrier mobility.

[0104] Among them, Figure 7 As shown, the pattern structure layer 40 includes a plurality of conductive structures 41 and a plurality of insulating structures 42 , which are alternately arranged along a preset direction, and one side of adjacent conductive structures 41 and insulating structures 42 abut against each other.

[0105] The present invention does not limit the specific shape and size of the conductive structure 41 and the insulating structure 42, as long as the image structure layer 40 is disposed in the buried oxide layer. For example, for the convenience of processing, the conductive structure 41 and the insulating structure 42 can be rectangular.

[0106] Figure 7 Take the example that the width of the conductive structure 41 is equal to the width of the insulator structure 42, but the present invention is not limited thereto. Figure 7 As shown, the width of the conductive structure 41 refers to the length L1 of the conductive structure 41 in the horizontal direction, and the width of the insulator structure 42 refers to the length L2 of the insulator structure 42 in the horizontal direction.

[0107] The width of the conductive structure 41 and the width of the insulator structure 42 can be determined by the designer according to the process requirements. In one example, the width of the conductive structure 41 can range from 20nm to 1000μm, and the width of the insulator structure 42 can range from 20nm to 1000μm.

[0108] That is, the width of the conductive structure 41 may be any value between 20 nm and 1000 μm, for example, the width of the conductive structure 41 may be 20 nm, 28 nm, 30 nm, 36 nm, 50 nm, 80 nm, 100 nm, 10 μm, 100 μm, 500 μm or 1000 μm, etc. The width of the insulator structure 42 may be any value between 20 nm and 1000 μm, for example, the width of the insulator structure 42 may be 20 nm, 28 nm, 40 nm, 60 nm, 80 nm, 100 nm, 1 μm, 10 μm, 100 μm, 800 μm or 1000 μm, etc.

[0109] In some embodiments, the width of the conductive structure 41 is less than or equal to the width of the insulator structure 42 .

[0110] Specifically, conductive structures 41 of different widths can provide different degrees of back-gate effect, thereby flexibly adjusting the threshold voltage of the semiconductor device. A narrower conductive structure 41 may generate a stronger electric field and have a more significant effect on adjusting the threshold voltage, while a wider conductive structure 41 may reduce leakage current and provide a better electric field shielding effect.

[0111] Limiting the width of the conductive structure 41 to between 20 nm and 1000 μm can better optimize the electrical performance with a lower manufacturing process difficulty.

[0112] The width of the insulator structure 42 affects the capacitive coupling between the back gate and the channel. A narrower insulator structure 42 width may increase the capacitive coupling, making the back gate more sensitive to the channel, and helping to achieve higher gain and better subthreshold characteristics. A wider insulator structure can provide better insulation performance, reduce the generation of leakage current, and improve the performance and stability of semiconductor devices.

[0113] By limiting the width of the insulator structure 42 to between 20 nm and 1000 μm, the electrical performance of the semiconductor device can be better optimized at a lower manufacturing process difficulty, so that the SOI structure can meet the requirements of different applications.

[0114] Step S105 , based on a thermal oxidation process, growing oxide on one side surface of the first substrate to form a second buried oxide layer.

[0115] Exemplarily, the material of the second buried oxide layer may also be silicon dioxide.

[0116] Specifically, the cleaned first substrate is placed in a high temperature oxidation furnace, and the temperature of the high temperature oxidation furnace is controlled at 900° C. to 1200° C. At high temperature, oxygen reacts chemically with the first substrate, and silicon dioxide grows on one side surface (such as the upper surface) of the first substrate 100 to form a Figure 8 A second buried oxide layer 50 is shown.

[0117] Before performing subsequent processes, the first substrate sheet is cleaned to remove impurities and contaminants present in the first substrate sheet, thereby ensuring the quality and reliability of subsequent processes.

[0118] The present invention does not specifically limit the thickness of the second buried oxide layer 50 , and the thickness can be set by designers according to application scenarios and design requirements.

[0119] In one example, the thickness of the second buried oxide layer 50 may be to For example, the thickness of the second buried oxide layer 50 may be or wait.

[0120] Specifically, the thickness of the second buried oxide layer 50 is limited to to It can provide effective insulation isolation while enhancing the capacitive coupling between the back gate and the upper conductive structure, making the back gate more sensitive to the control of the upper channel.

[0121] Step S106, performing ion implantation on a surface of the second buried oxide layer away from the pattern structure layer.

[0122] Specifically, in forming Figure 8 After the structure shown in FIG. 1 is formed, an ion implanter is used to perform ion implantation on the upper surface of the second buried oxide layer 50 to form a 3D-type oxide film in the first substrate 100. Fig. 9 An implantation layer 110 is shown.

[0123] The implanted ions can be hydrogen or helium, and the implanted dose can be in the range of 1E15atom / cm 2 To 1E17atom / cm 2 For example, the implantation dose can be 1E15atom / cm 2 、1E16atom / cm 2 or 1E15atom / cm 2 In addition, the implantation depth may be determined based on the thickness of the active layer 60 . For example, the implantation depth may be the sum of the thickness of the second buried oxide layer 50 and the thickness of the active layer 60 .

[0124] Exemplarily, the thickness of the active layer 60 may range from to That is, the thickness of the active layer 60 may be to For example, the thickness of the active layer 60 may be

[0125] or wait.

[0126] Specifically, the thickness of the active layer 60 also affects the threshold voltage of the semiconductor device. By adjusting the thickness of the active layer 60, the electric field distribution and carrier concentration in the channel can be changed, thereby adjusting the magnitude of the threshold voltage.

[0127] Step S107 , bonding the surface of the pattern structure layer away from the first buried oxide layer and the surface of the second buried oxide layer after ion implantation to obtain a semiconductor structure.

[0128] Specifically, when obtaining Fig. 9 After the structure shown in FIG. 1 is formed, the upper surface of the second buried oxide layer 50 and the upper surface of the pattern structure layer 40 are bonded to each other. Figure 7 The structure shown and Fig. 9 The structures shown are combined together to obtain Fig.10 The initial SOI structure is then placed in a heating furnace to separate the first substrate sheet 100 at the implantation layer 110 to obtain the initial SOI structure shown in FIG. Fig.11 The SOI structure shown.

[0129] The temperature during the bonding process may be 400° C. to 600° C., and the bonding process time may be 1 min to 60 min.

[0130] The method for preparing the semiconductor structure provided in this embodiment forms a graphic structure layer between the buried oxide layers (i.e., the first buried oxide layer 30 and the second buried oxide layer 50), which is equivalent to introducing a back gate in the SOI structure. The back gate can, on the one hand, reduce the parasitic capacitance of the semiconductor device and increase the maximum operating frequency and gain-bandwidth product of the semiconductor device. On the other hand, it can optimize the linear characteristics of the semiconductor device and reduce distortion. On the other hand, it can enhance the anti-interference ability of the semiconductor device to external signals. On the fourth hand, it can effectively absorb and conduct the heat generated by the device, improve thermal management, and improve the reliability of the semiconductor device. On the fifth hand, it can flexibly optimize the key RF performance indicators of the semiconductor device, such as gain, noise, and linearity.

[0131] In some optional implementations, the above step S1044 may specifically be: removing part of the insulating material based on a chemical mechanical polishing (CMP) method, so that the height of the insulating material reaches a preset height.

[0132] Specifically, in the formation Figure 6 After the structure shown in the figure is formed, the silicon dioxide can be directly polished by CMP until the height of the insulating material reaches a preset height.

[0133] In this embodiment, directly using the CMP method to remove the insulating material can improve the surface quality to a certain extent, making the surface of the insulating material more flat and smooth, which is beneficial to the subsequent process, and can also reduce the complexity of the process flow and improve processing efficiency.

[0134] In some other optional implementations, the above step S1044 includes step a1 and step a2:

[0135] Step a1, removing part of the insulating material by chemical mechanical polishing, so that the height of the insulating material beyond the conductive structure is greater than and the height of the insulating material beyond the conductive structure is less than or equal to

[0136] Step a2, corroding the insulating material so that the height of the insulating material reaches a preset height.

[0137] Exemplarily, the solution used for the etching treatment is hydrofluoric acid.

[0138] Specifically, in the formation Figure 6 After the structure shown in the figure, the insulating material is first polished by CMP until the height of the insulating material 90 exceeding the conductive structure 41 is a first height. The first height is greater than And the first height is less than or equal to The height of the insulating material 90 beyond the conductive structure 41 can be as follows: Fig.12 As shown in h1.

[0139] After the insulating material exceeds the height h1 of the conductive structure to a first height, hydrofluoric acid is used for etching, and the etching rate is controlled to make the height of the insulating material 90 the same as the height of the conductive structure 41. Hydrofluoric acid etching has the characteristic of isotropy, which can compensate for the uneven material removal that may be caused by CMP to a certain extent.

[0140] In this embodiment, the insulating material is removed by combining CMP and etching treatment, which can make it easier to control the height of the insulating material and reduce the risk of over-polishing and damaging the conductive structure 41.

[0141] Exemplarily, after the bonding process, the method for preparing the semiconductor structure further includes: performing a thermal annealing process on the semiconductor structure in an argon environment or in a mixed gas environment of argon and hydrogen, so that the surface roughness of the semiconductor structure is less than or equal to 0.5 nm. Specifically, in the mixed gas environment of argon and hydrogen, the percentage of hydrogen is less than 5%.

[0142] The temperature of the thermal annealing treatment may be 1000° C. to 1300° C., and the time of the thermal annealing treatment may be 10 s to 60 s.

[0143] The present invention further provides a semiconductor structure, which is prepared by the method for preparing a semiconductor structure provided by any of the above embodiments. Figure 1 shown.

[0144] In some embodiments, the widths of the plurality of conductive structures 41 and the widths of the plurality of insulator structures 42 included in the graphic structure layer vary according to a preset rule, wherein the preset rule can be determined by a designer according to process requirements.

[0145] For example, Fig.13 As shown, the widths of the plurality of conductive structures 41 and the plurality of insulating structures 42 increase (or decrease) from left to right, that is, the difference in width between two adjacent conductive structures 41 is equal, and the difference in width between two adjacent insulating structures 42 is equal.

[0146] For example, Fig.14 As shown, the widths of the plurality of conductive structures 41 vary gradually from left to right, that is, the width differences of two adjacent conductive structures 41 are not equal.

[0147] Specifically, the width of each conductive structure 41 changes, affecting the gate capacitance and on-resistance of the corresponding semiconductor device. If the width of each conductive structure 41 is different, the on-speed of the semiconductor device corresponding to each conductive structure 41 is correspondingly different.

[0148] In this embodiment, if the width of the conductive structure 41 gradually increases, the gate capacitance of the corresponding switch unit increases successively, and the conduction speed gradually decreases, so that the corresponding switch units can be turned on or off one by one, avoiding the synchronous on / off of all units, thereby reducing the peak value of the transient current, helping to smooth the control signal switching, and reducing the power supply fluctuation or electromagnetic interference (EMI) caused by the transient current.

[0149] At the same time, by gradually changing the width of the conductive structure 41, the capacitive coupling between adjacent switch units can be reduced to a certain extent. Specifically, if the width of the conductive structure 41 is gradually reduced, the parasitic capacitance of adjacent units can be reduced, the crosstalk between signals can be suppressed, and the isolation effect can be improved especially under high frequency conditions.

[0150] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0151] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless otherwise clearly and specifically defined. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0152] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0153] The above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, and the scope of protection of the present invention is determined by the attached scope of protection.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a first substrate sheet constituting an active layer and a second substrate sheet constituting a semiconductor substrate layer; Depositing polysilicon on one side surface of the second substrate to form a polysilicon layer; Growing or depositing oxide on a surface of the polysilicon layer on one side away from the second substrate to form a first buried oxide layer; A graphic structure layer is formed on a surface of the first buried oxide layer away from the polysilicon layer, wherein the graphic structure layer includes a plurality of conductive structures and a plurality of insulating structures, wherein the plurality of conductive structures and the plurality of insulating structures are alternately arranged in a preset direction, and one side of adjacent conductive structures and insulating structures abuts against each other; Based on a thermal oxidation process, an oxide is grown on a surface of one side of the first substrate to form a second buried oxide layer; Performing ion implantation on a surface of the second buried oxide layer away from the graphic structure layer; A bonding process is performed on a surface of the pattern structure layer away from the first buried oxide layer and a surface of the second buried oxide layer after ion implantation to obtain a semiconductor structure.

2. The method according to claim 1, characterized in that A pattern structure layer is formed on a surface of the first buried oxide layer away from the polysilicon layer, comprising: Depositing a conductive material on a surface of the first buried oxide layer away from the polysilicon layer; Etching the conductive material to form a plurality of conductive structures; Filling insulating material between the plurality of conductive structures based on a high aspect ratio process; Part of the insulating material is removed so that the height of the insulating material reaches a preset height, thereby forming the graphic structure layer.

3. The method according to claim 2, characterized in that The step of removing part of the insulating material so that the height of the insulating material reaches a preset height includes: A portion of the insulating material is removed by chemical mechanical polishing so that the height of the insulating material reaches a preset height.

4. The method according to claim 2, characterized in that: The step of removing part of the insulating material so that the height of the insulating material reaches a preset height includes: A portion of the insulating material is removed by chemical mechanical polishing so that the height of the insulating material beyond the conductive structure is greater than The height of the insulating material beyond the conductive structure is less than or equal to The insulating material is subjected to etching treatment so that the height of the insulating material reaches a preset height.

5. The method according to claim 4, characterized in that The solution used for the corrosion treatment is hydrofluoric acid.

6. The method according to any one of claims 1 to 5, characterized in that After bonding the surface of the graphic structure layer away from the first buried oxide layer and the surface of the second buried oxide layer after the ion implantation, the method further comprises: The semiconductor structure is subjected to thermal annealing in an argon environment or in a mixed gas environment of argon and hydrogen, so that the surface roughness of the semiconductor structure is less than or equal to 0.5 nm.

7. The method according to any one of claims 1 to 5, characterized in that The temperature when depositing polysilicon on one side surface of the second substrate sheet is in the range of 900° C. to 1200° C.

8. The method according to any one of claims 1 to 5, characterized in that The temperature of the thermal oxidation process ranges from 900°C to 1200°C.

9. The method according to any one of claims 1 to 5, characterized in that The process parameters of the bonding process include: a temperature range of 400° C. to 600° C., and a time range of 1 min to 60 min.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method according to any one of claims 1 to 9.

Images