Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a display area and a non-display area located on at least one side of the display area. The non-display area is provided with a plurality of cascaded first driving units, the display area is provided with a plurality of second driving units arranged in an array, and each first driving unit is used for driving at least one row of second driving units; wherein each first driving unit comprises a first grid electrode, and the first grid electrode is provided with a first hollow part. Specifically, the first grid electrode of the first driving unit comprises the hollow part, and the electrical property of the first driving unit can be adjusted by utilizing the first hollow part, so that the electrical property of the first driving unit is consistent with that of the second driving unit, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices have been widely used in terminal display devices of various sizes due to their characteristics of light weight, small size and thin thickness. GIP (Gate in Panel) technology integrates scanning chips on OLED panels, which can save scanning chips, reduce material costs, reduce the number of processes and shorten process time, thereby reducing panel costs and achieving a narrower frame.

[0003] For pixel circuits, especially medium-sized full-oxide pixel circuits, because the GIP circuit requires a large output current, the width of the GIP TFT (Thin Film Transistor) in the non-display area is often designed to be dozens of times that of the TFT in the display area. In addition, since the electrical properties of the oxide TFT increase with the width, resulting in a negative bias in its threshold voltage Vth, the electrical properties of the TFT in the display area are more positive than those of the GIP TFT in the non-display area, resulting in inconsistent electrical properties of the TFT in the display area and the non-display area, thereby affecting the display effect. Summary of the invention

[0004] The present application provides an array substrate and a manufacturing method thereof, and a display panel, which can solve the problem of electrical inconsistency between a display area TFT and a non-display GIP TFT.

[0005] In order to solve the above technical problems, the first technical solution provided in the present application is: providing an array substrate, the array substrate comprising a display area and a non-display area located on at least one side of the display area; the non-display area has a plurality of cascaded first driving units, and the display area has a plurality of array-arranged second driving units, each of the first driving units is used to drive at least one row of the second driving units; wherein each of the first driving units comprises a first gate, and the first gate comprises a first hollow portion.

[0006] In one embodiment, the first hollow portion is a plurality of through holes penetrating the first gate along a thickness direction of the first gate.

[0007] In one embodiment, the first hollow portion further includes a plurality of notches penetrating the first gate along a thickness direction of the first gate.

[0008] In one embodiment, the first gate includes a plurality of sub-first gates arranged at intervals, and the first hollow portion is the gap between the plurality of sub-first gates; wherein the plurality of sub-first gates are arranged in parallel.

[0009] In one embodiment, the area of ​​the first hollow portion is 10%-50% of the area of ​​the first gate.

[0010] In one embodiment, the array substrate also includes a substrate and a gate insulation layer; the first driving unit also includes a first active layer, and the first active layer is arranged on one side of the substrate; the gate insulation layer covers the side of the first active layer away from the substrate, and the first gate is arranged on the side of the gate insulation layer away from the first active layer; wherein the gate insulation layer has a second hollow portion arranged corresponding to the first hollow portion, and at least part of the first active layer is exposed through the first hollow portion and the second hollow portion; the first hollow portion and the second hollow portion are used to pass processing gas into the first active layer.

[0011] In order to solve the above technical problems, the second technical solution provided by the present application is: to provide a method for preparing an array substrate, comprising: providing a substrate; forming an active layer on a first side of the substrate; forming a gate insulating layer covering the active layer on the first side of the substrate; forming a gate on a side of the gate insulating layer away from the substrate; the gate located in the non-display area is defined as a first gate; and patterning the first gate to form a first hollow portion;

[0012] The active layer is processed by using a processing gas through the first hollow portion.

[0013] In one embodiment, the step of patterning the first gate includes: patterning the first gate and the gate insulation layer below the first gate using a mask to form the first hollow portion on the first gate, and forming a second hollow portion on the gate insulation layer, so that at least part of the active layer is exposed through the first hollow portion and the second hollow portion; the step of processing the active layer using a processing gas through the first hollow portion includes: passing the processing gas into the active layer below the first gate through the first hollow portion and the second hollow portion.

[0014] In one embodiment, the process gas is plasma.

[0015] To solve the above technical problems, the third technical solution provided in this application is: providing a display panel, comprising an array substrate and a color film substrate, the array substrate being any of the array substrates described above; the color film substrate being arranged on a side of the array substrate away from the substrate.

[0016] Different from the prior art, the image array substrate and its preparation method, and the display panel provided by the present application, without changing the width of the first gate of the non-display area, by setting the first gate of the non-display area to have a hollow portion, the electrical properties of the first driving unit can be adjusted by utilizing the first hollow portion to make the electrical properties of the first driving unit in the non-display area consistent with the electrical properties of the second driving unit in the display area, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0018] Figure 1 A schematic diagram of a partial structure of an embodiment of an array substrate provided in the present application;

[0019] Figure 2 A schematic structural diagram of an embodiment of a first gate provided in the present application;

[0020] Figure 3 A schematic structural diagram of another embodiment of the first gate provided in the present application;

[0021] Figure 4 A schematic structural diagram of another embodiment of the first gate provided in the present application;

[0022] Figure 5 A schematic diagram of a partial structure of another embodiment of the array substrate provided in the present application;

[0023] Figure 6 A schematic diagram of a process of an embodiment of a method for preparing an array substrate provided in the present application;

[0024] Figure 7 A schematic diagram of a process of another embodiment of a method for preparing an array substrate provided in the present application;

[0025] Figure 8 A partial schematic diagram of an intermediate product after step S1 in the method for preparing an array substrate provided in the present application;

[0026] Fig. 9 A partial schematic diagram of an intermediate product after step S2 in the method for preparing an array substrate provided in the present application;

[0027] Fig.10 A partial schematic diagram of an intermediate product after step S3 in the method for preparing an array substrate provided in the present application;

[0028] Fig.11 A partial schematic diagram of an intermediate product after step S4 in the method for preparing an array substrate provided in the present application;

[0029] Fig.12 A schematic diagram of an intermediate product of an embodiment of the method for preparing an array substrate provided in the present application after step S5;

[0030] Fig.13 A partial schematic diagram of an intermediate product after steps S5 and S6 in the method for preparing an array substrate provided in the present application;

[0031] Fig.14 A partial schematic diagram of an intermediate product after step S7 in the method for preparing an array substrate provided in the present application;

[0032] Fig.15 This is a partial schematic diagram of an intermediate product after step S8 in the method for preparing an array substrate provided in the present application;

[0033] Fig.16 A partial schematic diagram of an array substrate formed after step S9 in the method for preparing an array substrate provided in the present application;

[0034] Fig.17 A schematic structural diagram of an embodiment of a display panel provided in the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] See also Figure 1 , Figure 1 A schematic diagram of the partial structure of an embodiment of an array substrate provided in the present application.

[0037] Specifically, the array substrate 100 includes a display area AA and a non-display area NA located on at least one side of the display area AA; the non-display area NA has a plurality of cascaded first driving units 10, and the display area AA has a plurality of array-arranged second driving units 20, and each first driving unit 10 is used to drive at least one row of second driving units 20.

[0038] Specifically, several cascaded first driving units 10 may be scanning transistors, light-emitting control transistors, etc., used to form a GIP circuit, and several array-arranged second driving units 20 may be driving transistors, reset transistors, etc., used to drive each sub-pixel to work.

[0039] Among them, since the output current required in the GIP circuit is relatively large, it is necessary to set the width of the first driving unit 10 to be several times or even dozens of times the width of the second driving unit 20. When both the first driving unit 10 and the second driving unit 20 are oxide TFTs, since the electrical properties of the oxide TFTs increase with the width, resulting in the characteristic that the threshold voltage Vth thereof is negatively biased, there is a situation where the electrical properties of the TFTs in the display area AA (the second driving unit 20) are more positive than the electrical properties of the GIP TFTs in the non-display area NA (the first driving unit 10), resulting in the electrical properties of the TFTs in the display area AA being inconsistent with those of the non-display TFTs, and the negative Vth of the GIP TFTs will cause the TFTs to be difficult to turn off, thereby resulting in the problem of poor display effect of the display panel.

[0040] In the related art, in order to avoid the situation where the GIP TFT is constantly turned off due to the negative Vth of the GIP TFT, the process is required to prepare a TFT with a positive Vth. Since the GIP TFT in the non-display area NA and the TFT in the display area AA are prepared under the same process, this will cause the electrical properties of the TFT in the display area AA to be more positive. After the electrical properties of the oxide TFT are positively biased, the corresponding positive bias temperature stress (PBTS) will deteriorate, which will seriously reduce the life of the screen.

[0041] It should be noted that the size of the GIP TFT is several times or even dozens of times the size of the TFT in the display area AA. Accordingly, the sizes of the components in the GIP TFT (eg, gate, source / drain, active layer, etc.) are also increased in proportion.

[0042] To solve the above problems, please refer to Figure 1-Figure 4 In the array substrate 100 provided in the present application, each first driving unit 10 includes a first gate 11, and the first gate 11 has a first hollow portion S.

[0043] The first hollow portion S refers to a pattern such as a notch, a hole, or a gap formed on the first gate 11 after the first gate 11 is processed by etching, patterning, drilling, or the like.

[0044] Specifically, in the embodiment of the present application, without changing the width of the first gate 11 of the non-display area NA and ensuring that the first gate 11 can carry the rated large current, the first gate 11 of the non-display area NA is provided with a first hollow portion S. The electrical properties of the first driving unit 10 can be adjusted by utilizing the first hollow portion S so that the electrical properties of the first driving unit 10 in the non-display area NA are consistent with the electrical properties of the second driving unit 20 in the display area AA, thereby improving the display effect of the display panel.

[0045] It should be noted that in the embodiment of the present application, only the first gate 11 of the GIP TFT is provided with the first hollow portion S, while the TFT of the display area AA is consistent with the TFT in the prior art, and the electrical properties of the GIP TFT are regulated by the first hollow portion S to make it consistent with the electrical properties of the TFT of the display area AA.

[0046] Among them, the method of using the first hollow portion S to adjust the electrical properties of the first driving unit 10 includes but is not limited to: adjusting the shape and size of the first hollow portion S; adjusting the arrangement and shape and size of each sub-hollow portion in the first hollow portion S; adjusting the ratio of the size of the first hollow portion S to the size of the first gate 11, etc.

[0047] See also Figure 2 In some optional embodiments, the first hollow portion S is a plurality of through holes S1 penetrating the first gate 11 along a thickness direction H of the first gate 11 .

[0048] Specifically, by setting a perforated gate of the GIP TFT, the wider first gate 11 is formed into a porous shape through a process such as etching, and by controlling the aperture size of each through hole S1, the proportion of the area of ​​multiple through holes S1 to the area of ​​the first gate 11, etc., the purpose of individually regulating the Vth and working current of the GIP TFT is achieved.

[0049] The plurality of through holes S1 may be arranged in an orderly or disorderly manner. In the embodiment of the present application, the plurality of through holes S1 are arranged at intervals and evenly along the width direction W of the first gate 11 to facilitate regulating the electrical properties of the GIP TFT.

[0050] The sizes of the plurality of through holes S1 may be completely the same, not completely the same, or completely different, and may be specifically set according to actual conditions, as long as the electrical properties of the GIP TFT can be precisely controlled.

[0051] See also Figure 3 , in some optional embodiments, with Figure 2 The difference from the structure of the first gate 11 in the embodiment is that the first hollow portion S further includes a plurality of notches S2 penetrating the first gate 11 along the thickness direction H of the first gate 11 .

[0052] Specifically, the notch S2 is located at the edge of the first gate 11, and the electrical properties of the GIP TFT are individually regulated to achieve a suitable Vth by controlling the aperture size of each through hole S1 and the notch S2, the proportion of the total area of ​​multiple through holes S1 and multiple notches S2 to the area of ​​the first gate 11, etc.

[0053] See also Figure 4In some optional embodiments, the first gate 11 includes a plurality of sub-first gates 110 arranged at intervals, and the first hollow portion S is a gap S3 between the plurality of sub-first gates 110 .

[0054] Specifically, by setting a discontinuous gate of the GIP TFT, the wider first gate 11 is formed into multiple segments through etching and other processes, and multiple sub-first gates 110 are arranged in parallel. By adjusting the distance between each segment of the sub-first gate 110, the Vth and operating current of the GIP TFT can be individually adjusted.

[0055] In the embodiment of the present application, the plurality of sub-first gates 110 may be connected in parallel through metal leads arranged in the same layer, or through vias in other film layers, which is not limited here.

[0056] Among them, in the above optional embodiments, the area of ​​the first hollow portion S is 10%-50% of the area of ​​the first gate 11. For example, the area of ​​the first hollow portion S is 10%, 20%, 30%, 40% or 50% of the area of ​​the first gate 11, and is specifically designed according to actual needs.

[0057] Specifically, if the area of ​​the first hollow portion S accounts for too large a proportion of the area of ​​the first gate 11, the first gate 11 may be unable to carry the preset rated current; if the area of ​​the first hollow portion S accounts for too small a proportion of the area of ​​the first gate 11, the electrical properties of the GIP TFT may not be able to achieve the expected effect. Therefore, in the embodiment of the present application, the electrical properties of the GIP TFT are regulated to achieve a suitable Vth by adjusting the area of ​​the first hollow portion S to 10%-50% of the area of ​​the first gate 11 to ensure that the first gate 11 can carry the rated current.

[0058] Please continue to see Figure 2-Figure 4 In one embodiment, the first gate 11 includes a forked portion and a connecting portion 111, wherein the connecting portion 111 extends along the length direction L of the first gate 11, and the forked portion includes a plurality of electrode portions 112 extending along the width direction W of the first gate 11, and the plurality of electrode portions 112 are arranged in parallel and the first ends are all connected to the connecting portion 111. The first hollow portion S is located on the plurality of electrode portions 112.

[0059] See also Figure 1 or Figure 5 , Figure 5 A partial structural diagram of another embodiment of the array substrate provided in the present application. In one embodiment, the array substrate 100 further includes a substrate 30 and a gate insulating layer 40 ; and the first driving unit 10 further includes a first active layer 12 .

[0060] Specifically, the first active layer 12 is disposed on one side of the substrate 30; the gate insulating layer 40 covers the side of the first active layer 12 away from the substrate 30, and the first gate 11 is disposed on the side of the gate insulating layer 40 away from the first active layer 12. Figure 5 The gate insulating layer 40 has a second hollow portion X arranged corresponding to the first hollow portion S, and at least part of the first active layer 12 is exposed through the first hollow portion S and the second hollow portion X; the first hollow portion S and the second hollow portion X are used to pass the processing gas into the first active layer 12.

[0061] The processing gas is a plasma gas, which includes plasma such as O, H or N2O. Specifically, after the first hollow portion S and the second hollow portion X are formed, the processing gas is passed into the first active layer 12 through the first hollow portion S and the second hollow portion X, and the electrical properties of the GIP TFT are regulated to achieve a suitable Vth and operating current according to process parameters such as the type of processing gas and processing time.

[0062] Among them, according to the type of processing gas, the Vth of the GIP TFT can be adjusted to be positive or negative. In this embodiment, the processing gas is used to adjust the Vth of the GIP TFT to be positive, so that the Vth of the GIP TFT is electrically consistent with the Vth of the TFT in the display area AA, and the operating current of the GIP TFT is adjusted to meet the rated requirements.

[0063] Specifically, the embodiment of the present application is provided with a first gate 11 having a first hollow portion S, and then the first hollow portion S and the second hollow portion X are further used to perform plasma gas treatment on the first active layer 12, and by controlling the size of the first hollow portion S (for example, the aperture size, the width of the gap S3, etc.), and controlling the plasma type and process, it is possible to individually regulate the GIP TFT to have a suitable Vth and a large current, and since the second gate 21 of the TFT in the display area AA does not have the first hollow portion S, the second gate 21 can be used as a shielding layer to protect the TFT in the display area AA from being affected by the plasma gas, thereby ensuring that the electrical properties of the TFT in the display area AA are not affected.

[0064] Please continue to see Figure 1 or Figure 5 In one embodiment, the substrate 30 includes a base layer 31 and a buffer layer 32 , and the first active layer 12 and the gate insulating layer 40 are located on a side of the buffer layer 32 away from the base layer 31 .

[0065] The material of the substrate 30 may be a flexible material or a rigid material, and the material of the buffer layer 32 includes but is not limited to SiOx and SiNx.

[0066] Please continue to see Figure 1 or Figure 5In one embodiment, the array substrate 100 further includes an interlayer dielectric layer 50, and the first driving unit 10 further includes a first source 13 and a first drain 14. Specifically, the interlayer dielectric layer 50 covers the side of the first gate 11 away from the substrate 30, the first source 13 and the first drain 14 are insulated and arranged on the side of the interlayer dielectric layer 50 away from the first gate 11, and the first source 13 and the first drain 14 are respectively connected to the two sides of the first active layer 12 through vias.

[0067] Furthermore, the array substrate 100 may further include a passivation layer 60 , a planarization layer 70 , and an encapsulation layer 80 , which are stacked on a side of the interlayer dielectric layer 50 away from the first gate 11 and cover the first source 13 and the first drain 14 .

[0068] Different from the prior art, the array substrate 100 provided in the above embodiments of the present application includes a first driving unit 10 (GIP TFT) in the non-display area NA, wherein the first driving unit 10 includes a first gate 11, and the first gate 11 includes a first hollow portion S, and the first hollow portion S can adjust the electrical properties of the first driving unit 10 without changing the width of the first gate 11, so that the electrical properties of the first driving unit 10 in the non-display area NA are consistent with the electrical properties of the second driving unit 20 in the display area AA, thereby improving the display effect of the display panel. Further, the first hollow portion S and the second hollow portion X can also be used to perform plasma gas treatment on the first active layer 12, and by controlling the size of the first hollow portion S (such as the aperture size, the width of the gap S3, etc.), and controlling the type of plasma and the process, the purpose of individually regulating the GIP TFT to have a suitable Vth and a large current is achieved.

[0069] See also Figures 6 to 16 , Figure 6 A schematic diagram of a process of an embodiment of a method for preparing an array substrate provided in the present application; Figure 7 A schematic diagram of a process of another embodiment of a method for preparing an array substrate provided in the present application; Figure 8 A partial schematic diagram of an intermediate product after step S1 in the method for preparing an array substrate provided in the present application; Fig. 9 A partial schematic diagram of an intermediate product after step S2 in the method for preparing an array substrate provided in the present application; Fig.10 A partial schematic diagram of an intermediate product after step S3 in the method for preparing an array substrate provided in the present application;

[0070] Fig.11 A partial schematic diagram of an intermediate product after step S4 in the method for preparing an array substrate provided in the present application; Fig.12 A schematic diagram of an intermediate product of an embodiment of the method for preparing an array substrate provided in the present application after step S5; Fig.13A partial schematic diagram of an intermediate product after steps S5 and S6 in the method for preparing an array substrate provided in the present application; Fig.14 A partial schematic diagram of an intermediate product after step S7 in the method for preparing an array substrate provided in the present application;

[0071] Fig.15 This is a partial schematic diagram of an intermediate product after step S8 in the method for preparing an array substrate provided in the present application; Fig.16 This is a partial schematic diagram of an array substrate formed after step S9 in the method for preparing an array substrate provided in the present application.

[0072] The present application also provides a method for preparing an array substrate 100, comprising:

[0073] Step S1: providing a substrate 30 .

[0074] The substrate 30 may be a rigid substrate 30 or a flexible substrate 30 .

[0075] See also Figure 8 In one embodiment, the substrate 30 includes a base layer 31 and a buffer layer 32 located on one side of the base layer 31. The material of the buffer layer 32 includes but is not limited to SiOx and SiNx.

[0076] The substrate 30 includes a display area AA and a non-display area NA.

[0077] Step S2 : forming an active layer on the first side of the substrate 30 .

[0078] See also Fig. 9 One side of the buffer layer 32 serves as the first side of the substrate 30, and an active layer is formed on the side of the buffer layer 32 away from the base layer 31. The active layer may be a metal oxide active layer.

[0079] The active layer located in the non-display area NA is defined as a first active layer 12 , and the active layer located in the display area AA is defined as a second active layer 22 .

[0080] Step S3 : forming a gate insulating layer 40 covering the active layer on the first side of the substrate 30 .

[0081] See also Fig.10 The gate insulating layer 40 is an inorganic layer including an inorganic material. For example, the gate insulating layer 40 may include an inorganic material such as silicon dioxide or silicon nitride.

[0082] Step S4 : forming a gate electrode on the side of the gate insulating layer 40 facing away from the substrate 30 .

[0083] See also Fig.11 The gate electrode located in the non-display area NA is defined as a first gate electrode 11 , and the gate electrode located in the display area AA is defined as a second gate electrode 21 .

[0084] The first gate 11 may be a gate of a GIP TFT, and its width is several times or even dozens of times greater than that of the second gate 21 .

[0085] Step S5: patterning the first gate 11 to form a first hollow portion S.

[0086] See also Fig.12 The first gate 11 may be patterned by punching, etching or masking to form a first hollow portion S on the first gate 11. The first hollow portion S may be a pattern such as a notch S2, a through hole S1, a gap S3, etc. formed on the first gate 11.

[0087] Among them, the first hollow portion S is used to adjust the electrical properties of the first driving unit 10 formed in the non-display area NA, and its adjustment methods include but are not limited to: adjusting the shape and size of the first hollow portion S; adjusting the arrangement and shape and size of each sub-hollow portion in the first hollow portion S; adjusting the ratio of the size of the first hollow portion S to the size of the first gate 11, etc.

[0088] Among them, the area of ​​the first hollow portion S is 10%-50% of the area of ​​the first gate 11. For example, the area of ​​the first hollow portion S is 10%, 20%, 30%, 40% or 50% of the area of ​​the first gate 11, and is specifically designed according to actual needs. Specifically, if the area of ​​the first hollow portion S accounts for too large a proportion of the area of ​​the first gate 11, it may be that the first gate 11 cannot carry the preset rated current, and if the area of ​​the first hollow portion S accounts for too small a proportion of the area of ​​the first gate 11, it may be that the electrical properties of the GIP TFT cannot achieve the expected effect. Therefore, in the embodiment of the present application, by adjusting the area of ​​the first hollow portion S to 10%-50% of the area of ​​the first gate 11, it is ensured that the first gate 11 can carry the rated current, and the electrical properties of the GIP TFT are regulated to achieve the purpose of a suitable Vth.

[0089] In one embodiment, see Fig.13 The step of patterning the first gate 11 includes: patterning the first gate 11 and the gate insulating layer 40 below the first gate 11 using a mask to form a first hollow portion S on the first gate 11, and forming a second hollow portion X on the gate insulating layer 40, so that at least part of the active layer is exposed through the first hollow portion S and the second hollow portion X.

[0090] Specifically, since the first hollow portion S and the second hollow portion X are formed in the same process, the first hollow portion S and the second hollow portion X correspond to each other, and the first active layer 12 is exposed through the first hollow portion S and the second hollow portion X.

[0091] It should be noted that in the embodiment of the present application, only the first gate 11 of the GIP TFT is patterned so that the first gate 11 has a first hollow portion S, while the second gate 21 of the display area AA is not patterned, that is, the second gate 21 has no hollow portion.

[0092] Step S6: using a processing gas to process the active layer through the first hollow portion S.

[0093] Please continue to see Fig.13 , the processing gas is a plasma gas, which includes plasma such as O, H or N2O.

[0094] Specifically, after forming the first hollow portion S and the second hollow portion X, the processing gas is passed into the first active layer 12 below the first gate 11 through the first hollow portion S and the second hollow portion X, and the electrical properties of the GIP TFT are regulated to achieve a suitable Vth and operating current according to process parameters such as the type of processing gas and the processing time. Since the second gate 21 of the display area AA does not have a hollow portion, the second gate 21 can be used as a shielding layer to protect the second active layer 22 of the display area AA from being affected by the plasma gas, thereby ensuring that the electrical properties of the TFT of the display area AA are not affected.

[0095] In one embodiment, after step S6, the method further includes:

[0096] Step S7 : forming an interlayer dielectric layer 50 covering the first gate 11 on the side of the gate insulating layer 40 facing away from the substrate 30 .

[0097] See also Fig.14 The interlayer dielectric layer 50 may be an inorganic layer, and the materials of the remaining gate insulating layers 40 are the same.

[0098] When the interlayer dielectric layer 50 is formed, the interlayer dielectric layer 50 may fill the first hollow portion S and the second hollow portion X.

[0099] Step S8 : forming an insulated source and drain on the side of the interlayer dielectric layer 50 away from the first gate 11 .

[0100] See also Fig.15 A metal layer may be formed on the side of the interlayer dielectric layer 50 away from the first gate 11, and then the metal layer may be patterned to form spaced source and drain electrodes.

[0101] The interlayer dielectric layer 50 and the gate insulating layer 40 have vias, and the source and the drain are connected to the active layer through the vias, respectively.

[0102] Among them, the source and drain of the non-display area NA are defined as the first source 13 and the first drain 14, the first source 13 and the first drain 14 are respectively connected to the two sides of the first active layer 12 through vias, and the first active layer 12, the first gate 11, the first source 13 and the first drain 14 form a first driving unit 10; the source and drain of the display area AA are defined as the second source 23 and the second drain 24, the second source 23 and the second drain 24 are respectively connected to the two sides of the second active layer 22 through vias, and the second active layer 22, the second gate 21, the second source 23 and the second drain 24 form a second driving unit 20.

[0103] Step S9: forming a passivation layer 60 , a planarization layer 70 and an encapsulation layer 80 that cover the source and the drain and are stacked on the side of the interlayer dielectric layer 50 away from the first gate 11 .

[0104] See Fig.16 Among them, in this step, an anode, a pixel definition layer, a support layer, etc. can also be formed in sequence between the planarization layer 70 and the encapsulation layer 80 in the display area AA, and the anode is connected to the source or drain in the display area AA through a via hole, and a sub-pixel connected to the anode is arranged in the pixel definition layer. The specific implementation method is basically consistent with the prior art and will not be repeated here.

[0105] Different from the prior art, the preparation method of the array substrate 100 provided in the present application, the substrate 30 includes a display area AA and a non-display area NA, and the first gate electrode 11 of the non-display area NA is provided with a first hollow portion S, and the gate insulation layer 40 of the non-display area NA is provided with a second hollow portion X corresponding to the first hollow portion S, so that the first active layer 12 is exposed through the first hollow portion S and the second hollow portion X, and then the first active layer 12 is processed by the processing gas, and the size of the first hollow portion S (such as the aperture size, the width of the gap S3, etc.) and the type and process of plasma are controlled, so as to achieve the purpose of individually regulating the first driving unit 10 (GIP TFT) to have a suitable Vth and a large current.

[0106] See also Fig.17 , Fig.17 A schematic structural diagram of an embodiment of a display panel provided in the present application.

[0107] The present application also provides a display panel 300, including an array substrate 100 and a color film substrate 200 which are stacked, wherein the array substrate 100 can be the array substrate 100 provided by any of the above embodiments, and the color film substrate 200 is arranged on a side of the array substrate 100 away from the substrate 30.

[0108] Among them, the display panel 300 can be applied to mobile phones, computers, tablets, smart wearable devices, etc.

[0109] In some specific embodiments, a display layer is further provided between the color film substrate 200 and the array substrate 100. Specifically, when the display panel 300 is an LCD display panel, the display layer is a liquid crystal layer. When the display panel is an OLED display panel, an AMOLED display panel, or the like, the display layer is a light-emitting layer including sub-pixels.

[0110] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate, comprising a display area and a non-display area located at at least one side of the display area; characterized in that: The non-display area has a plurality of cascaded first driving units, the display area has a plurality of second driving units arranged in an array, and each of the first driving units is used to drive at least one row of the second driving units; Wherein, each of the first driving units includes a first gate, and the first gate includes a first hollow portion.

2. The array substrate according to claim 1, characterized in that: The first hollow portion is a plurality of through holes penetrating the first gate along a thickness direction of the first gate.

3. The array substrate according to claim 2, characterized in that: The first hollow portion further includes a plurality of notches penetrating the first gate along a thickness direction of the first gate.

4. The array substrate according to claim 1, characterized in that: The first grid comprises a plurality of sub-first grids arranged at intervals, and the first hollow portion is a gap between the plurality of sub-first grids; Wherein, a plurality of the sub-first gates are arranged in parallel.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The area of ​​the first hollow portion is 10%-50% of the area of ​​the first gate.

6. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate also includes a substrate and a gate insulating layer; The first driving unit further includes a first active layer, which is disposed on one side of the substrate; the gate insulating layer covers a side of the first active layer away from the substrate, and the first gate is disposed on a side of the gate insulating layer away from the first active layer; The gate insulating layer has a second hollow portion arranged corresponding to the first hollow portion, and at least part of the first active layer is exposed through the first hollow portion and the second hollow portion; the first hollow portion and the second hollow portion are used to pass the processing gas into the first active layer.

7. A method for preparing an array substrate, characterized in that: include: providing a substrate; forming an active layer on a first side of the substrate; forming a gate insulating layer covering the active layer on a first side of the substrate; forming a gate on a side of the gate insulating layer facing away from the substrate; The gate located in the non-display area is defined as a first gate; Patterning the first gate to form a first hollow portion; The active layer is processed by using a processing gas through the first hollow portion.

8. The preparation method according to claim 7, characterized in that: The step of patterning the first gate includes: Using a mask, patterning the first gate and the gate insulating layer below the first gate to form the first hollow portion on the first gate and the second hollow portion on the gate insulating layer, so that at least part of the active layer is exposed through the first hollow portion and the second hollow portion; The step of using a processing gas to process the active layer through the first hollow portion includes: The processing gas is introduced into the active layer below the first gate through the first hollow portion and the second hollow portion.

9. The preparation method according to claim 7 or 8, characterized in that: The processing gas is plasma.

10. A display panel, characterized in that: include: An array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 6; The color filter substrate is arranged on a side of the array substrate away from the substrate.

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