Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor technology. Since at least two first gates and at least two first active regions in the semiconductor device are arranged in a cross manner, and the second active region is located between adjacent first active regions, and the second gate is located on the second active region, when forming at least four transistors in the semiconductor device, a fifth transistor is formed at the second active region and the second gate. While this arrangement does not change the structure of the semiconductor device, it increases the number of transistors and the integration degree of the semiconductor device, and further improves the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the birth of Moore's Law, the number of transistors in semiconductor devices doubles every year. As time goes by, the process node has reached 2nm or even 0.3nm, all aiming to increase the number of transistors and improve the operating speed of the chip.

[0003] After growing to a certain extent, it is impossible to increase the number of transistors without changing the structure, but changing the structure will make the process very complex.

[0004] Based on this, how to further increase the number of transistors in semiconductor devices through layout design has become a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] Based on this, in view of the problem of how to increase the number of transistors in semiconductor devices and improve the integration of semiconductor devices, it is necessary to provide a semiconductor device and a method for manufacturing the same.

[0006] To achieve the above object, on the one hand, the present invention provides a semiconductor device, which includes a substrate and a gate layer located on the substrate.

[0007] The substrate includes:

[0008] At least two first active regions, extending along a first direction and arranged along a second direction;

[0009] A second active region, located between adjacent first active regions in the second direction, the first direction and the second direction being parallel to the substrate, and the first direction intersecting the second direction;

[0010] The gate layer includes:

[0011] At least two first gates, extending along the second direction and arranged along the first direction, and at least two first gates intersecting at least two first active regions, and adjacent first gates being located on both sides of the second active region in the first direction;

[0012] A second gate, located on the second active region.

[0013] In one embodiment, the first active region includes a first channel region, and the second active region includes a second channel region; the first channel region and the second channel region have the same conductivity type.

[0014] In one embodiment, the first active region further includes a first doped region, the first doped region and the first channel region are arranged alternately along the first direction, the conductivity type of the first doped region is opposite to that of the second channel region, and the second channel region is connected to the first doped regions of two adjacent first active regions in the second direction.

[0015] In one embodiment, the second gate is connected to the first gate in the first direction.

[0016] In one embodiment, the first active region includes a first channel region, and the second active region includes a second channel region; the first channel region has a first conductivity type, the second channel region has a second conductivity type, and the conductivity types of the first channel region and the second channel region are different.

[0017] In one embodiment, the first active region further includes a second doped region, the second doped region and the first channel region are arranged alternately along the first direction, the second doped region includes a first sub-region, a second sub-region, and a third sub-region arranged in sequence along the first direction, the first sub-region and the third sub-region have the second conductivity type, the second sub-region has the first conductivity type, and the second channel region is connected to the second sub-regions of two adjacent first active regions at least in the second direction.

[0018] In one embodiment, the second gate and the first gate are spaced apart in the first direction.

[0019] In one embodiment, the second active region further includes a third doped region, the third doped region is located on both sides of the second channel region in the second direction, and the third doped region has the first conductivity type; the second gate is spaced apart from the first active region in the second direction.

[0020] In one embodiment, the first active region further includes a first doped region, the first doped region and the first channel region are arranged alternately along the first direction, the first doped region has the second conductivity type, and the third doped region is connected to the first doped region.

[0021] In one embodiment, the second gate is connected to the first gate in the first direction.

[0022] On the other hand, the present application also provides a method for manufacturing a semiconductor device, including:

[0023] Providing a substrate;

[0024] The substrate is doped to form active regions, which include a first active region and a second active region. The number of the first active regions is at least two. The first active regions extend along a first direction and are arranged along a second direction. The second active region is located between adjacent first active regions in the second direction. The first direction and the second direction are parallel to the substrate, and the first direction intersects with the second direction.

[0025] A gate layer is formed on the substrate. The gate layer includes a first gate and a second gate. The number of the first gates is at least two. The first gates extend along the second direction and are arranged along the first direction. At least two of the first gates are cross - arranged with at least two of the first active regions. Adjacent first gates are located on both sides of the second active region in the first direction. The second gate is located on the second active region.

[0026] Compared with the prior art, the above - mentioned technical solution has the following unexpected technical effects:

[0027] In this semiconductor device, it includes a substrate and a gate layer on the substrate. The substrate includes at least two first active regions, which extend along a first direction and are arranged along a second direction; a second active region, which is located between adjacent first active regions in the second direction. The first direction and the second direction are parallel to the substrate, and the first direction intersects with the second direction. The gate layer includes at least two first gates, which extend along the second direction and are arranged along the first direction. At least two of the first gates are cross - arranged with at least two of the first active regions. Adjacent first gates are located on both sides of the second active region in the first direction; a second gate, which is located on the second active region.

[0028] Since at least two first gates and at least two first active regions in this semiconductor device are cross - arranged, and the second active region is located between adjacent first active regions, and the second gate is located on the second active region, when forming at least four transistors in this semiconductor device, a fifth transistor is formed at the second active region and the second gate. While this arrangement does not change the structure of the semiconductor device, it increases the number of transistors and the integration degree of the semiconductor device, further improving the performance of the semiconductor device. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0030] Figure 1Schematic diagram of the structure of a semiconductor device provided by an embodiment of the present application;

[0031] Figure 2 Schematic diagram of the structure of another semiconductor device provided by an embodiment of the present application;

[0032] Figure 3 One of the schematic diagrams of the structure of yet another semiconductor device provided by an embodiment of the present application;

[0033] Figure 4 Schematic diagram of the structure of a first active region and a second active region provided by an embodiment of the present application;

[0034] Figure 5 Schematic diagram of the structure of a gate layer provided by an embodiment of the present application;

[0035] Figure 6 Two of the schematic diagrams of the structure of yet another semiconductor device provided by an embodiment of the present application;

[0036] Figure 7 Three of the schematic diagrams of the structure of yet another semiconductor device provided by an embodiment of the present application;

[0037] Figure 8 Four of the schematic diagrams of the structure of yet another semiconductor device provided by an embodiment of the present application;

[0038] Figure 9 Five of the schematic diagrams of the structure of yet another semiconductor device provided by an embodiment of the present application;

[0039] Figure 10 Six of the schematic diagrams of the structure of yet another semiconductor device provided by an embodiment of the present application;

[0040] Figure 11 Schematic flow diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0041] Figure 12 Schematic diagram of the structure after forming an active region during the manufacturing process of the semiconductor device provided by an embodiment of the present application;

[0042] Figure 13 Schematic diagram of the structure after forming an isolation structure during the manufacturing process of the semiconductor device provided by an embodiment of the present application;

[0043] Figure 14 Schematic diagram of the structure after forming a well region during the manufacturing process of the semiconductor device provided by an embodiment of the present application;

[0044] Figure 15 Schematic diagram of the structure after forming a gate layer during the manufacturing process of the semiconductor device provided by an embodiment of the present application;

[0045] Figure 16 Schematic diagram of the structure after forming the source or drain during the preparation process of the semiconductor device provided by the embodiment of the present application;

[0046] Figure 17 Schematic diagram of the structure after forming the metal silicide during the preparation process of the semiconductor device provided by the embodiment of the present application;

[0047] Figure 18 Schematic diagram of the structure after forming the contact structure during the preparation process of the semiconductor device provided by the embodiment of the present application.

[0048] Explanation of reference numerals: 01 - substrate; 02 - gate layer; 03 - first active region; 04 - second active region; 05 - first gate; 06 - second gate; 07 - first channel region; 08 - second channel region; 09 - first doping region; 10 - second doping region; 11 - first sub-region; 12 - second sub-region; 13 - third sub-region; 14 - third doping region; 15 - isolation structure; 16 - deep N-well; 17 - P-well, 18 - doping region; 19 - metal silicide; 20 - contact structure. Detailed implementation manners

[0049] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0051] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0052] Refer to Figure 1 , Figure 1 Schematic diagram of the structure of a semiconductor device provided by an embodiment of the present application; the semiconductor device includes a substrate 01 and a gate layer 02 located on the substrate 01.

[0053] The substrate 01 includes:

[0054] At least two first active regions 03 extend along a first direction M and are arranged along a second direction N.

[0055] A second active region 04 is located between adjacent first active regions 03 in the second direction N. The first direction M and the second direction N are parallel to the substrate 01, and the first direction M intersects the second direction N.

[0056] The gate layer 02 includes:

[0057] At least two first gates 05 extend along the second direction N and are arranged along the first direction M. At least two first gates 05 are cross - arranged with at least two first active regions 03, and adjacent first gates 05 are located on both sides of the second active region 04 in the first direction M.

[0058] A second gate 06 is located on the second active region 04.

[0059] Specifically, in this embodiment, both the first direction M and the second direction N are parallel to the plane where the substrate 01 is located, and the first direction M intersects the second direction N. In one embodiment, the first direction M and the second direction N are perpendicular to each other. Transistors are formed at the overlapping portions of the first active regions 03 and the first gates 05. At least two first active regions 03 and at least two first gates 05 are cross - arranged, and at least four cross - regions can be formed, that is, at least four transistors are formed.

[0060] The second active region 04 is located between adjacent first active regions 03 in the second direction N. It should be noted that the second active region 04 can be connected to the first active region 03 or not, without specific limitation. The second gate 06 is located on the second active region 04. The second gate 06 can completely cover the second active region 04 or partially cover the second active region 04, without specific limitation. For a clearer display, in Figure 1 is only an example.

[0061] With the arrangement of the first active regions 03 and the first gates 05 unchanged, a transistor can be formed at the overlapping portion of the second active region 04 and the second gate 06, so that in the existing layout of semiconductor devices, one more new transistor appears. Since the new transistor is located between the existing four transistors, no more layout settings are required, improving the integration of semiconductor devices. Further, with the semiconductor device structure unchanged, the number of transistors increases by 25%, improving the performance of semiconductor devices.

[0062] Optionally, referring to Figure 1 , in another embodiment of the present application, the first active region 03 includes a first channel region 07, and the second active region 04 includes a second channel region 08; the conduction types of the first channel region 07 and the second channel region 08 are the same.

[0063] Specifically, the overlapping region of the first active region 03 and the first gate 05 has a first channel region 07, and the extending direction of the first channel region 07 is the first direction M. The overlapping region of the second active region 04 and the second gate 06 has a second channel region 08, and the extending direction of the second channel region 08 is the second direction N, that is, the conduction directions of the first channel region 07 and the second channel region 08 are different.

[0064] It should be noted that the conduction types of the first channel region 07 and the second channel region 08 are the same, both being N-type conduction or both being P-type conduction. That is to say, the formed at least five transistors are the same transistors. The extending direction of the second channel region 08 is cross-set with that of the first channel region 07, which can increase the integration degree of the semiconductor device.

[0065] Optionally, refer to Figure 2 , Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application; in another embodiment of the present application, the first active region 03 further includes a first doping region 09. The first doping region 09 and the first channel region 07 are alternately arranged along the first direction M. The conduction type of the first doping region 09 is opposite to that of the second channel region 08. The second channel region 08 is connected to the first doping regions 09 of two adjacent first active regions 03 in the second direction N. It should be noted that the first doping region 09 serves as the source or drain of the transistor.

[0066] Specifically, taking two first active regions 03 and two first gates 05 as an example for illustration. The first doping region 09 and the first channel region 07 are alternately arranged along the first direction M. That is to say, in the embodiment of the present application, in the first direction M, the first doping region 09 between the transistors corresponding to the i-th row of the first channel region 07 and the transistors corresponding to the (i + 1)-th row of the first channel region 07 is shared, where i≥1 and i is a positive integer.

[0067] In this embodiment, the second channel region 08 is connected to the first doping regions 09 of two adjacent first active regions 03 in the second direction N. That is to say, as Figure 2As shown, the second channel region 08 uses the first doping region 09 as the doping region of the transistor formed here. In the second direction N, the first doping region 09 is shared between the transistors corresponding to the i-th column of the second channel region 08 and the transistors corresponding to the (i + 1)-th column of the second channel region 08. Among them, when at least five transistors share a partial doping region, the conductivity type of the first doping region 09 is opposite to that of the second channel region 08, and the conductivity type of the first doping region 09 is opposite to that of the first channel region 07. That is to say, the conductivity types of the first channel region 07 and the second channel region 08 are the same. At this time, at least five transistors of the same type can be formed, and the types of transistors include N-type transistors or P-type transistors. When the doping regions are shared, the integration degree of the semiconductor device can be further increased.

[0068] Optionally, refer to Figure 3 , Figure 3 is one of the schematic structural diagrams of another semiconductor device provided by the embodiment of the present application; refer to Figure 4 , Figure 4 is a schematic structural diagram of a first active region and a second active region provided by the embodiment of the present application; refer to Figure 5 , Figure 5 is a schematic structural diagram of a gate layer provided by the embodiment of the present application; in another embodiment of the present application, the second gate 06 is connected to the first gate 05 in the first direction M.

[0069] Specifically, taking two first active regions 03 and two first gates 05 as examples for illustration. When the second gate 06 is connected to the first gate 05 in the first direction M, as Figure 4 shown, the structures of the first active region 03 and the second active region 04 on the substrate 01 can be in an "I" shape, and as Figure 5 shown, the structure of the gate layer 02 can also be in an "I" shape. At this time, it is equivalent to the active region and the gate layer 02 being rotationally stacked to form a structure as Figure 3 shown. The second active region 04 is completely covered by the second gate 06, and the doping regions of the transistors formed at the first channel region 07 and the second channel region 08 are shared. When the doping regions are shared, the integration degree of the semiconductor device can be further increased.

[0070] It should be noted that in the above embodiment, when sharing the doping region, only by forming the second active region 04 and the second gate 06, a new transistor can be formed in the arrangement area of four transistors, increasing the number of transistors by 25% and improving the performance of the semiconductor device. In addition, such a setting further improves the integration degree of the semiconductor device.

[0071] Optionally, refer to Figure 1, in another embodiment of the present application, the first active region 03 includes a first channel region 07, and the second active region 04 includes a second channel region 08; the first channel region 07 has a first conductivity type, the second channel region 08 has a second conductivity type, and the conductivity types of the first channel region 07 and the second channel region 08 are different.

[0072] Specifically, the overlapping region of the first active region 03 and the first gate 05 has a first channel region 07, and the extending direction of the first channel region 07 is the first direction M. The overlapping region of the second active region 04 and the second gate 06 has a second channel region 08, and the extending direction of the second channel region 08 is the second direction N.

[0073] It should be noted that the first channel region 07 has a first conductivity type, the second channel region 08 has a second conductivity type, and the first conductivity type and the second conductivity type are different. The types of transistors formed at the overlapping portion of the first gate 05 and the first active region 03 and the types of transistors formed at the overlapping portion of the second gate 06 and the second active region 04 are different. When an N-type transistor is formed in the first channel region 07, a P-type transistor is formed in the second channel region 08; or when a P-type transistor is formed in the first channel region 07, an N-type transistor is formed in the second channel region 08. At this time, since the extending directions of the channel regions are not in the same direction when different types of transistors are arranged, the integration degree of the semiconductor device having two different types of transistors can be greatly improved.

[0074] Optionally, refer to Figure 6 , Figure 6 is a second schematic structural diagram of another semiconductor device provided by the embodiment of the present application; in another embodiment of the present application, the first active region 03 further includes a second doping region 10. The second doping region 10 and the first channel region 07 are alternately arranged along the first direction M. The second doping region 10 includes a first sub-region 11, a second sub-region 12, and a third sub-region 13 arranged in sequence along the first direction M. The first sub-region 11 and the third sub-region 13 have a second conductivity type, the second sub-region 12 has a first conductivity type, and the second channel region 08 is connected to the second sub-regions 12 of two adjacent first active regions 03 at least in the second direction N.

[0075] Specifically, when the first channel region 07 has a first conduction type and the second channel region 08 has a second conduction type, the first active region 03 further includes a second doping region 10, and the second doping region 10 and the first channel region 07 are alternately arranged along the first direction M. The second doping region 10 includes a first sub-region 11, a second sub-region 12, and a third sub-region 13 arranged in sequence along the first direction M. Among them, in the first direction M, the first sub-region 11 serves as the doping region of the transistor corresponding to the first channel region 07 in the i-th row, where i≥1 and i is a positive integer. The third sub-region 13 serves as the doping region of the (i + 1)-th row of transistors. Since the first channel region 07 has a first conduction type, both the first sub-region 11 and the third sub-region 13 have a second conduction type. The second sub-region 12 serves as the doping region of the transistor corresponding to the second channel region 08 in the i-th column. Since the second channel region 08 has a second conduction type, the second sub-region 12 has a first conduction type. It should be noted that the second channel region 08 is connected to the second sub-regions 12 of at least two adjacent first active regions 03 in the second direction N, and new transistors can be formed.

[0076] In this embodiment, since the conduction types of the first channel region 07 and the second channel region 08 are different, the conduction types of the doping regions on both sides of different channel regions also need to be different, and the types of the formed transistors are naturally different. When an N-type transistor is formed in the first channel region 07, a P-type transistor is formed in the second channel region 08, or when a P-type transistor is formed in the first channel region 07, an N-type transistor is formed in the second channel region 08. At this time, the first sub-region 11, the second sub-region 12, and the third sub-region 13 are provided in the second doping region 10, which can ensure that the first channel region 07 and the second channel region 08 are between their corresponding doping regions. Since the channel regions are not in the same direction when different types of transistors are arranged, the integration degree of the semiconductor device with two different types of transistors can be greatly improved.

[0077] Optionally, referring to Figure 6 , in another embodiment of the present application, the second gate 06 and the first gate 05 are spaced apart in the first direction M.

[0078] Specifically, when the first channel region 07 has a first conduction type and the second channel region 08 has a second conduction type, the second gate 06 and the first gate 05 can be spaced apart in the first direction M. Such a setting can reduce the area of the gate layer 02, reduce the use of the gate layer 02 material, and further reduce the manufacturing cost.

[0079] Optionally, referring to Figure 7 , Figure 7FIG. 3 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the present application; in another embodiment of the present application, the second active region 04 further includes a third doping region 14, the third doping region 14 is located on both sides of the second channel region 08 in the second direction N, and the third doping region 14 has a first conductivity type; the second gate 06 is spaced apart from the first active region 03 in the second direction N.

[0080] Specifically, in this embodiment, on one side of the second active region 04 in the second direction N, the third doping region 14 is located on both sides of the second channel region 08. Since the second channel region 08 has a second conductivity type, the third doping region 14 has a first conductivity type to form a transistor. It should be noted that the second gate 06 is spaced apart from the first active region 03 in the second direction N, that is, the second active region 04 is not connected to the first active region 03. At this time, since the first channel region 07 extends in the first direction M and the second channel region 08 extends in the second direction N, the types of transistors formed at the first channel region 07 of the first active region 03 and the second channel region 08 of the second active region 04 are different. In this embodiment, by arranging different types of transistors, that is, setting the extension directions of the channel regions in intersecting directions, the occupied area of the layout can be reduced and the integration degree of the semiconductor device can be increased.

[0081] Optionally, referring to Figure 8 , Figure 8 FIG. 4 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the present application; the first active region 03 further includes a first doping region 09, the first doping region 09 and the first channel region 07 are alternately arranged along the first direction M, the first doping region 09 has a second conductivity type, and the third doping region 14 is connected to the first doping region 09.

[0082] Specifically, in this embodiment, in the first direction M, the first doping region 09 is included on both sides of the first channel region 07 of the first active region 03, and the conductivity type of the first doping region 09 is opposite to that of the first channel region 07, that is, the first channel region 07 has a first conductivity type and the first doping region 09 has a second conductivity type. At this time, the third doping region 14 can be connected to the first doping region 09, but the doping types of the first doping region 09 and the third doping region 14 are different, that is, the type of transistor formed in the first active region 03 is different from the type of transistor formed in the second active region 04. The first doping region 09 and the first channel region 07 are alternately arranged along the first direction M, that is, two adjacent first channel regions 07 can share a first doping region 09 in the first direction M. At this time, due to the partial sharing of the first doping region 09, the area of the semiconductor device can be further reduced and the integration degree of the semiconductor device can be increased.

[0083] Optionally, referring to Figure 9 ,Figure 9 FIG. 5 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the present application; in another embodiment of the present application, the second gate 06 is connected to the first gate 05 in the first direction M.

[0084] Specifically, when the first channel region 07 has a first conductivity type and the second channel region 08 has a second conductivity type, the second gate 06 and the first gate 05 can be connected in the first direction M. At this time, the gate layer 02 is prepared in a "worker" shape, and such a setting can make the preparation of the gate layer 02 more convenient.

[0085] It should be noted that whether the second gate 06 and the first gate 05 are spaced apart in the first direction M or the second gate 06 and the first gate 05 are connected in the first direction M, different transistors can be formed at the second channel region 08 from those at the first channel region 07. While increasing the number of transistors, the integration degree of the semiconductor device is further improved.

[0086] In addition, based on the above structure where the first channel region 07 has a first conductivity type and the second channel region 08 has a second conductivity type, the present application also provides a stress introduction method, which will be described below.

[0087] With the development of integrated circuits, when the process node reaches below 45 nm, in order to improve the performance of NMOS devices and PMOS devices, some new processes are adopted to improve the carrier mobility, such as a series of methods including SMT (Stress Memory Technology), SPT, SiGe epitaxy, SIC epitaxy, ultraviolet irradiation, etc. For a semiconductor device structure that has both NMOS and PMOS, since the carriers for NMOS operation are electrons and the carriers for PMOS operation are holes, and the two devices prefer different stresses, different stress layers or different epitaxial processes need to be used for stress introduction when stress is introduced to NMOS or PMOS. The stresses required for NMOS and PMOS to improve performance are shown in Table 1 below:

[0088] Table 1

[0089]

[0090] When the semiconductor device in the present application is adopted, taking the formation of NMOS at the first channel region 07 and the formation of PMOS at the second channel region 08 as an example for description. Refer to Figure 10 , Figure 10This is the sixth schematic structural diagram of another semiconductor device provided by the embodiments of the present application; the extending direction of the first channel region 07 is L1, and the width direction of the first channel region 07 is W1. The extending direction of the second channel region 08 is L2, and the width direction of the second channel region 08 is W2. Among them, the stress required for the extending direction L of the second channel region 08 is a compressive stress y. Since the stress required for the width direction W1 of the first channel region 07 is a tensile stress x, providing the tensile stress x to the width direction W1 of the first channel region 07 can achieve the compressive stress y required for the extending direction L2 of the second channel region 08. And the stress required for the extending direction L1 of the first channel region 07 is the same as the stress required for the width direction W2 of the second channel region 08. Therefore, in this embodiment, the NMOS and PMOS can adopt the same stress layer for stress introduction. Similarly, forming a PMOS in the first channel region 07 and forming an NMOS in the second channel region 08 can also achieve stress introduction with the same stress layer. This stress introduction method realizes the stress introduction of two different types of transistors by only using one stress layer, reducing the process preparation cost.

[0091] Based on the above embodiments, the present application also provides a method for manufacturing a semiconductor device, referring to Figure 11 , Figure 11 This is a schematic flow chart of a method for manufacturing a semiconductor device provided by the embodiments of the present application; referring to Figures 12 - 18 , Figures 12 - 18 This is a partial structural schematic diagram of the structure obtained in the method for manufacturing a semiconductor device provided by the embodiments of the present application; the method includes the following steps:

[0092] Step S101: Provide a substrate 01.

[0093] Step S102: Dope the substrate 01 to form an active region AA.

[0094] Among them, the active region AA includes a first active region 03 and a second active region 04. The number of the first active regions 03 is at least two. The first active regions 03 extend along a first direction M and are arranged along a second direction N. The second active region 04 is located between adjacent first active regions 03 in the second direction N. The first direction M and the second direction N are parallel to the substrate 01, and the first direction M intersects the second direction N.

[0095] In this step, as Figure 12 shown, provide the substrate 01, form the active region AA on the substrate 01, and dope the regions where the first active region 03 and the second active region 04 need to be set to define the active region AA. The first active region 03 and the second active region 04 in this step can be of the types in the above embodiments, and no specific limitation is made here.

[0096] Then, perform isolation trench etching, as Figure 13As shown, isolation material is filled in the isolation trenches to form an isolation structure 15, and a polishing process is performed to planarize the surface. The polishing method can be Chemical Mechanical Planarization (CMP for short).

[0097] After that, as Figure 14 shown, well region implantation is performed in the formed active region AA. In this embodiment, a deep N well 16 can be formed first by ion implantation, and then a P well 17 is formed. It should be noted that the formation position of the well region is based on the type of transistors to be formed, and no specific limitation is made here. It is set according to the arrangement of specific transistors.

[0098] Step S103: A gate layer 02 is formed on the substrate 01.

[0099] Among them, the gate layer 02 includes a first gate 05 and a second gate 06. The number of the first gates 05 is at least two. The first gates 05 extend along the second direction N and are arranged along the first direction M. And at least two first gates 05 are cross - arranged with at least two first active regions 03, and adjacent first gates 05 are located on both sides of the second active region 04 in the first direction M. The second gate 06 is located on the second active region 04.

[0100] In this step, as Figure 15 shown, the gate layer 02 is formed on one side of the substrate 01. It should be noted that a gate oxide layer covering the substrate 01 is formed first before forming the gate layer 02, and then a gate material layer with a certain thickness is deposited on one side of the gate oxide layer, and then lithography is used for exposure, development, and etching to obtain the structure as Figure 15 . At this time, the gate layer 02 can be of the type in the above - mentioned embodiment, and no specific limitation is made here. Among them, the first gate 05 and the second gate 06 can be connected or not connected. Figure 15 In

[0101] only an example is given where the first gate 05 and the second gate 06 are not connected. After forming the gate layer 02, an oxide layer and a silicon nitride layer with a certain thickness are successively grown on one side of the gate layer 02 and the substrate 01, and photolithography is performed on the oxide layer and the silicon nitride layer to form a first sidewall around the gate layer 02. Then, Non - Local Damage Deposition (NLDD) of the drain and ion implantation of the doping region are carried out. And an annealing process is used to activate the implanted ions.

[0102] Then, continue to grow an oxide layer and a silicon nitride layer with a certain thickness in sequence on one side of the gate layer 02, the substrate 01, and the first sidewall, and perform photolithography on the oxide layer and the silicon nitride layer to form second sidewalls on both sides of the first sidewall. Then, perform N+ ion implantation or P+ ion implantation in the doping region 18 to form a source or a drain, forming a structure as shown in Figure 16 shown. It should be noted that according to the different devices formed, the conduction types of the formed source and drain will be correspondingly different. For example, when forming an NMOS device, the source and drain are formed by N+ ion implantation; when forming a PMOS device, the source and drain are formed by P+ ion implantation. Just form the source and drain according to specific needs, and then anneal at a certain temperature to activate the ions. It should be noted that the first sidewall and the second sidewall are not marked in the figure, and ions will not be implanted in the area covered by the first sidewall and the second sidewall.

[0103] Then, continue to use the SMT process to form a stress layer covering the gate layer 02, the substrate 01, the first sidewall, and the second sidewall. It should be noted that the NMOS device requires a stress layer with tensile stress, and the PMOS device requires a stress layer with compressive stress. This process needs to be determined according to the designed layout, and no specific limitation is made here. For example, when NMOS devices and PMOS devices are formed in a semiconductor device and the channel regions of the NMOS devices and the PMOS devices are cross - arranged, the same stress layer can be used for covering, and no specific limitation is made here. Then, use the annealing process to conduct the stress to the channel region to improve the performance of the transistor, and then remove the stress layer.

[0104] After that, form a self - alignment layer in the region where the contact structure 20 needs to be formed to reduce the resistance of the device, including depositing an oxide layer and a silicon nitride layer covering the gate layer 02, the substrate 01, the first sidewall, and the second sidewall in sequence, and then using an etching process to etch the oxide layer and the silicon nitride layer to expose the surface of the gate layer 02 and the source and drain on the substrate 01.

[0105] As shown in Figure 17 shown, then form a metal silicide 19 on the surface of the gate layer 02 and the source and drain on the substrate 01. It should be noted that Figure 17 in order to clearly show in the figure, the metal silicide 19 actually covers the gate layer 02, the source, and the drain.

[0106] The formation of metal silicide 19 includes first pre-cleaning the oxide layer on the surface of substrate 01 with SiCoNi by about 60 Å to ensure that the subsequently deposited metal can directly contact the clean silicon surface. Then, deposit NiPt alloy by about 120 Å for the subsequent formation of metal silicide. To protect the NiPt alloy from oxidation, deposit a 50 Å thick TIN layer thereon as a capping layer. Then, perform the first rapid thermal annealing at a temperature of 290 °C for a duration of 30 seconds. This step will promote the reaction between the NiPt alloy and silicon to form a high-resistance metal silicide Ni2PtSi. Then, perform the second rapid thermal annealing to form low-resistance NiPtSi2. After completing the two rapid thermal annealing steps, remove the nickel in the areas where NiPtSi2 is not formed to form as above Figure 17 structure.

[0107] After that, deposit 330 Å of amorphous silicon nitride. This material serves as a hard mask to protect the underlying materials during subsequent pattern transfer and etching processes.

[0108] Then deposit 2100 Å of oxide as an insulating layer, deposit 1900 Å of amorphous carbon (a-C) as an anti-reflective coating (ARC), continue to deposit 320 Å of silicon and 50 Å of silicon dioxide as a composite anti-reflective coating. Continue to deposit 200 Å of a bottom anti-reflective coating (BARC).

[0109] Then coat 1000 Å of photoresist (PR), and perform development and exposure for the contact structure. Use the photoresist as a mask to form contact holes for the contact structure 20 through dry or wet etching techniques. This process may include multiple etching steps, each optimized for a specific material layer to ensure precise dimensions and shapes. The position of the contact structure above the gate layer 02 can be set to one or multiple, which needs to be adjusted according to the actual application.

[0110] After the contact holes are formed, deposit a titanium thin film. The function of this thin film is to serve as an adhesion layer and a barrier layer, enhancing the adhesion of the subsequently deposited materials and preventing the diffusion of metals such as tungsten into silicon dioxide or other dielectric materials. Then deposit a titanium nitride thin film. This thin film also serves as an adhesion layer and a barrier layer, further enhancing the adhesion of the metal layer and the diffusion barrier ability. TiN also has good electrical conductivity, which helps to improve the performance of electrical connections.

[0111] Use physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods to deposit a layer of tungsten in the contact holes. After the tungsten layer is deposited, perform chemical mechanical polishing to planarize the surface to form as Figure 18The structure shown. Then continue with the subsequent processes.

[0112] When fabricating semiconductor devices using this preparation method, when the types of transistors formed are the same, the source or drain between different transistors can be shared. For example, an "I"-shaped active region and an "I"-shaped gate layer are provided, and the "I"-shaped active region and the "I"-shaped gate layer are rotationally crossed, so that a fifth transistor is formed among four transistors in the middle. At this time, the source and drain are shared, and while the layout area remains unchanged, the number of transistors is increased by 25%, improving the performance of the semiconductor.

[0113] In addition, when the types of transistors formed are different, the channel regions of NMOS devices and PMOS devices can be crossed according to the difference in the stress required by different types of transistors, reducing the area of the semiconductor device and enabling the introduction of stress for NMOS devices and PMOS devices by the same stress layer at one time, reducing the preparation cost.

[0114] In addition, this design can also be applied to the fin field-effect transistor process, and the improvement effect is more obvious.

[0115] In the description of this specification, the description with reference to terms such as "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0116] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0117] The above embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises a substrate and a gate layer located on the substrate. The substrate comprises: At least two first active regions extending along the first direction and arranged along the second direction; a second active region, located between adjacent first active regions in the second direction, the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction; The gate layer comprises: At least two first gates extend along the second direction and are arranged along the first direction, and at least two of the first gates are arranged to intersect at least two of the first active regions, and adjacent first gates are located on both sides of the second active regions in the first direction; a second gate, located on the second active region; The first active region includes a first channel region, and the second active region includes a second channel region; the first channel region and the second channel region have the same conductivity type; The first active region also includes a first doped region, which is alternately arranged with the first channel region along the first direction, the first doped region and the second channel region have opposite conductivity types, and the second channel region is connected to the first doped regions of two adjacent first active regions in the second direction.

2. The semiconductor device according to claim 1, wherein: The second gate is connected to the first gate in the first direction.

3. A semiconductor device, characterized in that: The semiconductor device comprises a substrate and a gate layer located on the substrate. The substrate comprises: At least two first active regions extending along the first direction and arranged along the second direction; a second active region, located between adjacent first active regions in the second direction, the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction; The gate layer comprises: At least two first gates extend along the second direction and are arranged along the first direction, and at least two of the first gates are arranged to intersect at least two of the first active regions, and adjacent first gates are located on both sides of the second active regions in the first direction; a second gate, located on the second active region; The first active region includes a first channel region, and the second active region includes a second channel region; the first channel region has a first conductivity type, the second channel region has a second conductivity type, and the conductivity types of the first channel region and the second channel region are different; The first active region also includes a second doped region, and the second doped region and the first channel region are arranged alternately along the first direction. The second doped region includes a first sub-region, a second sub-region and a third sub-region arranged in sequence along the first direction. The first sub-region and the third sub-region have the second conductivity type, and the second sub-region has the first conductivity type. The second channel region is connected to the second sub-regions of two adjacent first active regions at least in the second direction.

4. The semiconductor device according to claim 3, characterized in that The second gate is spaced apart from the first gate in the first direction.

5. The semiconductor device according to claim 3, characterized in that The second active region further includes a third doped region, the third doped region is located at both sides of the second channel region in the second direction, and the third doped region has the first conductivity type; the second gate is spaced apart from the first active region in the second direction.

6. The semiconductor device according to claim 5, characterized in that The first active region further includes a first doped region, the first doped region and the first channel region are alternately arranged along the first direction, the first doped region has a second conductivity type, and the third doped region is connected to the first doped region.

7. The semiconductor device according to claim 5, characterized in that The second gate is connected to the first gate in the first direction.

8. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; Doping the substrate to form an active region, wherein the active region includes a first active region and a second active region, the number of the first active regions is at least two, the first active regions extend along a first direction and are arranged along a second direction, the second active regions are located between adjacent first active regions in the second direction, the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect; A gate layer is formed on the substrate, wherein the gate layer includes a first gate and a second gate, wherein the number of the first gates is at least two, the first gates extend along the second direction and are arranged along the first direction, and at least two of the first gates are arranged to cross at least two of the first active regions, and adjacent first gates are located on both sides of the second active region in the first direction, and the second gate is located on the second active region; The first active region includes a first channel region, and the second active region includes a second channel region; the first channel region and the second channel region have the same conductivity type; The first active region also includes a first doped region, which is alternately arranged with the first channel region along the first direction, the first doped region and the second channel region have opposite conductivity types, and the second channel region is connected to the first doped regions of two adjacent first active regions in the second direction.

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