Single-photon avalanche photodiode and preparation method thereof

Abstract

The invention discloses a single photon avalanche photodiode and a preparation method thereof, and the method comprises the steps: firstly providing a first doping type substrate with a specific doping concentration, and the substrate comprises an epitaxial layer; performing doping of a second doping type on the epitaxial layer to form a first region; performing ion implantation of a first doping type on the epitaxial layer on the first region to form a second region, and forming a first avalanche junction by the first region and the second region; after the front-end process of the first wafer is completed, a back-end metallization process and a dielectric layer process are completed; overturning the first wafer, and arranging a second wafer on the back surface of the first wafer; forming a third region on the first region through ion implantation of the first doping type, wherein the third region and the first region form a second avalanche junction; or a fourth region is formed on the first region through doping of the second doping type, then a third region is formed on the fourth region through ion implantation of the first doping type, and the third region and the fourth region form a second avalanche junction.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor device processing, and in particular relates to a single-photon avalanche photodiode and a preparation method thereof. Background Art

[0002] In the field of semiconductor optoelectronic components, a single photon avalanche photodiode (SPAD) consists of a PN junction that operates at a reverse bias voltage far exceeding the operating voltage of a conventional diode. When the energy of the incident photon is high enough to overcome the potential barrier of the PN junction, it generates an electron-hole pair in the PN junction. If this pair of carriers obtains enough energy under the action of a strong electric field, they will further collide and generate more carrier pairs, triggering a chain reaction, namely the avalanche multiplication effect. This effect greatly enhances the photocurrent, making the SPAD have a very high light sensitivity and can even detect the arrival of a single photon.

[0003] SPAD is widely used in optical communication, laser radar, light detection and measurement systems due to its high sensitivity and low noise. The performance of single photon avalanche photodiode depends largely on its internal avalanche multiplication region, namely the PN junction region, which can produce carrier multiplication effect under the action of strong electric field, thereby improving the photoelectric conversion efficiency.

[0004] However, the PN junction in the traditional single-photon avalanche photodiode forms a sufficiently high electric field under a specific bias voltage by precisely controlling the doping concentration and thickness, so that the photogenerated carriers undergo collision ionization when crossing the depletion region, thereby triggering avalanche multiplication; because the traditional single-photon avalanche photodiode design usually only contains one PN junction region for avalanche breakdown. Although this design can achieve the basic avalanche multiplication effect, it has certain limitations in photon utilization efficiency. Since there is only one avalanche region, when the incident photon energy is low or the light intensity is weak, the probability of triggering avalanche breakdown will be significantly reduced, thereby affecting the overall efficiency of photoelectric conversion. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a single-photon avalanche photodiode and a preparation method thereof in view of the deficiencies in the above-mentioned prior art, so as to solve the current technical problem that when there is only one avalanche region and the incident photon energy is low or the light intensity is weak, the probability of triggering avalanche breakdown is significantly reduced, thereby affecting the overall efficiency of photoelectric conversion.

[0006] The present invention adopts the following technical solutions: A method for preparing a single-photon avalanche photodiode comprises the following steps: Providing a first doping type substrate with a specific doping concentration, the first doping type substrate comprising an epitaxial layer; doping the epitaxial layer with a second doping type to form a first region; Performing ion implantation of a first doping type into the epitaxial layer above the first region to form a second region; the first region and the second region form a first avalanche junction region; Complete the back-end metal process and dielectric layer process of the first wafer; flip the first wafer over, and place the second wafer on a side of the first wafer close to the dielectric layer; Forming a third region above the first region by ion implantation of the first doping type, wherein the third region and the first region form a second avalanche junction region; Or after forming the fourth region on the first region by doping with the second doping type, the third region is formed above the fourth region by ion implantation of the first doping type, and the third region and the fourth region form a second avalanche junction region.

[0007] Preferably, the doping concentration of the first doping type substrate is 1×10 14 cm -3 ~1×10 15 cm -3 .

[0008] Preferably, an ion implantation process is performed above the first region, using a dopant of the same first doping type as that of the substrate, and implanting the dopant into the epitaxial layer, thereby forming a second region with a specific doping concentration in the epitaxial layer.

[0009] Preferably, the doping concentration of the second region is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0010] Preferably, the first avalanche junction region and the second avalanche junction region share a cathode, and the cathode of the first avalanche junction region and the cathode of the second avalanche junction region are led out through the second wafer using a TSV process.

[0011] Preferably, it is characterized in that the anode of the first avalanche region is led out through the second wafer by using a TSV process; and the anode of the second avalanche junction region is led out on the third region.

[0012] Preferably, it is characterized in that the ion implantation energy and the dose of the second region are respectively the same as the ion implantation energy and the dose of the fourth region.

[0013] Another technical solution of the present invention is a single-photon avalanche photodiode prepared according to the method.

[0014] Preferably, from bottom to top, it includes: A first doping type substrate, a first doping type epitaxial layer arranged on the first doping type substrate, a second doping type first region arranged on the first doping type epitaxial layer, a first doping type second region arranged on the first region, the first region and the second region forming a first avalanche junction region; a first doping type third region arranged above the first region, the third region and the first region forming a second avalanche junction region; and a second wafer is arranged on a side of the first wafer close to the dielectric layer.

[0015] Preferably, from bottom to top, it includes: A first doping type substrate, a first doping type epitaxial layer arranged on the first doping type substrate, a first region of a second doping type arranged on the first doping type epitaxial layer, a second region of the first doping type arranged on the first region, the first region and the second region forming a first avalanche junction region; a fourth region of the second doping type arranged above the first region, a third region of the first doping type arranged above the fourth region, the third region and the fourth region forming a second avalanche junction region; and a second wafer is arranged on a side of the first wafer close to the dielectric layer.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: A method for preparing a single-photon avalanche photodiode, by N-doping the P-type epitaxial layer and then P-doping it, a unique PNP structure is formed, which not only retains the avalanche multiplication capability of the traditional PN junction, but also constructs a double avalanche junction area by introducing a second PN junction. More importantly, by back-illuminating and flipping the wafer and combining ion implantation technology, the two P-type dopings use the same implantation energy and dose, ensuring that the double avalanche junction can simultaneously and efficiently trigger avalanche multiplication, thereby significantly improving the photon utilization efficiency and avalanche triggering probability without increasing the photosensitive area.

[0017] Furthermore, a concentration of 1×10 14 cm -3 ~1×10 15 cm -3 The lightly doped substrate epitaxial concentration increases the lateral resistivity of the epitaxial layer.

[0018] Furthermore, an ion implantation process is performed above the first region, and a dopant having the same doping type as the first doping type of the substrate is used to implant the dopant into the epitaxial layer, thereby forming a 1×10 18 cm -3 ~1×10 19 cm -3 The second region of the doping concentration forms a first anode region for the avalanche region.

[0019] A single-photon avalanche photodiode optimizes the originally limited photon incident path through the application of back-illuminated flip wafer technology, so that more photons can directly and efficiently reach the photosensitive area, further enhancing the photosensitivity of the component. At the same time, the careful design of the PNP structure not only enhances the stability and controllability of the avalanche multiplication process, but also effectively amplifies the photoelectric signal through the synergistic effect of the double avalanche junction, so that under the same photosensitive area, the semiconductor avalanche photoelectric element of the present invention can show a photon utilization efficiency far exceeding that of traditional technologies.

[0020] Furthermore, the purpose or benefit of setting the second avalanche junction region formed by the second region and the first region is to form an avalanche junction biased towards the first avalanche junction at the surface position, which is conducive to the absorption and avalanche of photons in the blue-green wavelength range.

[0021] Furthermore, the purpose or benefit of setting up the second avalanche junction region formed by the second region and the third region is to form an avalanche junction biased towards a second avalanche junction located deep in the silicon body, which is beneficial to the absorption and avalanche of photons in the blue near-infrared range.

[0022] In summary, the device of the present invention includes a double avalanche junction capable of absorbing the multiplied blue-green light and the near-infrared band, which solves the problem in the prior art that there is only one avalanche region and it is not possible to efficiently absorb the multiplied blue-green light and the near-infrared band at the same time, thereby improving the overall efficiency of photoelectric conversion in the entire band of photon wavelengths.

[0023] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings to be used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a flow chart of the preparation method of the present invention; FIG2 is a schematic diagram of a device cross-section during the preparation of a single-photon avalanche photodiode according to the present invention, wherein (a) is a schematic diagram of an epitaxial layer, (b) is a cathode ion implantation process, (c) is a first avalanche junction anode ion implantation, (d) is a metal interconnection process, (e) is wafer flipping and stacking, (f) is wafer thinning, (g) is a second avalanche junction anode ion implantation, and (h) is a second anode back-end metal process; FIG3 is a cross-sectional schematic diagram of another single-photon avalanche photodiode provided by the present invention, wherein (a) is a schematic diagram of an epitaxial layer, (b) is a cathode ion implantation process, (c) is a first avalanche junction anode ion implantation, (d) is a metal interconnection process, (e) is a wafer flip stacking, (f) is a wafer thinning, (g) is a back cathode ion supplementary implantation process, (h) is a second avalanche junction anode ion implantation, and (i) a second anode back-end metal process; Figure 4 A schematic cross-sectional view of a double avalanche junction SPAD device provided in an embodiment of the present invention; Figure 5 A cross-sectional schematic diagram of another double avalanche junction SPAD device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "one side", "one end", "one side" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0030] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0031] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0033] In the field of semiconductor optoelectronics, single-photon avalanche photodiodes, as a high-performance photoelectric conversion device, are widely used in optical communications, spectral analysis, lidar, high-speed imaging and other fields. Its core working principle is to use the impact ionization effect of photogenerated carriers under the action of a strong electric field (i.e., the avalanche multiplication effect) to achieve efficient conversion of optical signals to electrical signals. However, the traditional SPAD design mainly relies on a single PN junction structure to achieve the avalanche effect, which has limitations in improving the efficiency of photon utilization and the probability of avalanche triggering.

[0034] The present invention provides a single-photon avalanche photodiode and a method for preparing the same, by performing N-type doping on a P-type epitaxial layer and then performing P-type doping to form a unique PNP structure. This design not only retains the avalanche multiplication capability of the traditional PN junction, but also constructs a double avalanche junction region by introducing a second PN junction. More importantly, by back-illuminating and flipping the wafer and combining it with fine ion implantation technology, the two P-type dopings use the same implantation energy and dose, ensuring that the double avalanche junction can simultaneously and efficiently trigger avalanche multiplication, thereby significantly improving the photon utilization efficiency and avalanche triggering probability without increasing the photosensitive area.

[0035] See also Figure 1 The present invention provides a method for preparing a single-photon avalanche photodiode, which can be performed by the following steps: S1, providing a first doping type substrate with a specific doping concentration, the substrate comprising an epitaxial layer; Please refer to FIG. 2 ( a ), in a semiconductor manufacturing process, firstly, a substrate 201 of a first doping type having a specific doping concentration is provided.

[0036] The substrate 201 serves as the basis of the entire device, and its doping type is determined according to requirements, for example, it can be P-type or N-type, depending on the functional requirements of subsequent devices.

[0037] On this basis, the substrate 201 further includes an epitaxial layer 202, which is formed on the surface of the substrate by epitaxial growth technology, and its crystal structure, composition and thickness are precisely controlled to meet specific performance requirements.

[0038] In particular, for the manufacturing method of this embodiment, the first doping type substrate provided needs to have a specific doping concentration, which is precisely calculated and experimentally verified, and is intended to provide the best electrical performance basis for the subsequent double avalanche junction structure. At the same time, the epitaxial layer not only helps to form a high-quality interface, but also can adjust the depletion region width of the device to a certain extent, thereby optimizing the conditions for the occurrence of the avalanche multiplication effect.

[0039] S2, doping the epitaxial layer with a second doping type to form a first region, where the doping concentration of the first region is 1×10 18 cm -3 ~1×10 19 cm -3 ; Referring to FIG. 2( b ), a specific type of doping treatment is performed on the epitaxial layer 202. This doping type is different from the first doping type of the substrate, which is referred to as the second doping type. Impurities of the second doping type are introduced into the epitaxial layer through a doping process (such as ion implantation, diffusion, etc.), thereby forming a first region 203 with a clear doping concentration and distribution characteristics above the substrate. By adjusting the doping concentration, depth and distribution, the electrical properties of the first region 203 can be controlled to optimize the conditions for the occurrence of the avalanche multiplication effect.

[0040] S3, implanting ions of the first doping type into the epitaxial layer above the first region to form a second region, wherein the doping concentration of the second region is 1×10 17 cm -3 ~1×10 18 cm -3 ; The first region and the second region form a first avalanche junction region; Referring to FIG. 2 (c), a precisely controlled ion implantation process is performed above the first region 203. In this process, a dopant of the same doping type as the first doping type of the substrate (for example, if the substrate is P-type, a P-type dopant is also used) is used, and the dopant is implanted into a certain depth of the epitaxial layer by setting ion beam parameters (such as energy, dose, and angle), thereby forming a second region 204 with a specific doping concentration in the epitaxial layer.

[0041] During the preparation of the semiconductor device, after the epitaxial layer is doped, a first region 203 having a different doping type from the substrate and the original epitaxial layer is formed. Since there is an obvious difference in doping type (for example, PN or NP) between the first region 203 and the second region 204, a PN junction is naturally formed between the two regions, namely, the first avalanche junction region.

[0042] The first avalanche junction region is a key component in semiconductor avalanche photoelectric elements. It can form a high electric field region under an appropriate external voltage, so that photogenerated carriers are impact-ionized in this region, thereby triggering an avalanche multiplication effect. By controlling the doping concentration, interface quality and geometric dimensions of the first and second regions, the electrical properties of the first avalanche junction region can be optimized, and its photon utilization efficiency and avalanche triggering probability can be improved.

[0043] S4. After completing all front-end processes of the first wafer, the next metallization process and dielectric layer process are completed; Please refer to FIG. 2 (d). In the semiconductor manufacturing process, when the first wafer (including the completed front-end processes such as doping, photolithography, etching, etc., to form the required circuit structure and avalanche junction area, such as all the processes in the above steps of the embodiment) is prepared, it immediately enters the back-end (back-end) process stage. This stage mainly includes metallization process and dielectric layer process, which aims to realize the electrical connection between the internal circuit of the wafer and the outside world (such as package pins, circuit boards, etc.), and provide necessary electrical isolation and protection.

[0044] The metallization process forms a series of metal wiring layers on the surface of the wafer through steps such as deposition, photolithography, and etching. These metal layers are not only used to connect transistors, diodes and other components inside the wafer, but are also responsible for transmitting signals to the outside of the wafer. In advanced manufacturing processes, multiple layers of metal wiring may be included, and each layer is connected to the next layer through vias or contacts to form a three-dimensional interconnection structure.

[0045] The dielectric layer is located between the metal wiring layers and between the metal layer and the wafer surface, and plays the role of electrical isolation. These dielectric layers are usually composed of insulating materials (such as silicon dioxide, silicon nitride, etc.) and are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The dielectric layer also contains through holes and contact holes, which are etched out so that the subsequent metallization process can form vertical electrical connections.

[0046] After completing the back-end metal process and dielectric layer process of the first wafer, the wafer will have a complete electrical connection network and necessary electrical isolation structure, providing a solid foundation for subsequent testing, packaging and final application.

[0047] S5, turning over the first wafer, and placing the second wafer on a side of the first wafer close to the dielectric layer; Please refer to FIG. 2 (e). At a specific stage of the semiconductor manufacturing process, the first wafer that has completed the subsequent metal process and the dielectric layer process needs to be flipped over. After the flipping of the first wafer, the dielectric layer side that originally faced the outside is now facing downward, ready to be docked with another wafer (i.e., the second wafer).

[0048] Next, the second wafer is placed on the side of the first wafer close to the dielectric layer, that is, on the flipped lower surface, through precise alignment and bonding processes. Temporary bonding glue, direct bonding technology (such as metal-metal bonding, oxide-oxide bonding, etc.) or other advanced wafer bonding technologies can be used to ensure a stable and reliable connection between the two wafers.

[0049] It should be noted that the second wafer can be a wafer with specific functions or structures, such as containing additional circuit layers, sensor arrays, storage units, etc.; by vertically stacking the two wafers and connecting them to each other, more complex functional integration and higher performance can be achieved.

[0050] Furthermore, in the semiconductor manufacturing process, when two wafers (usually wafers that have undergone specific processing or contain different circuit layers) are tightly combined by some means (such as metal bonding, direct bonding, etc.), wafer thinning operations are performed to reduce the thickness of the entire structure, improve performance, or meet packaging requirements. See Figure 2 (f). Chemical mechanical polishing (CMP), dry etching (such as plasma etching) or wet etching can be used to thin the bonded wafers. During the thinning process, the thickness of the wafer needs to be monitored in real time to ensure that it is thinned to the predetermined target thickness. At the same time, the thinning parameters, such as polishing rate, pressure, chemical solution concentration, etc., are adjusted according to the monitoring results to ensure the consistency and uniformity of the thinning.

[0051] S6, forming a third region above the first region by ion implantation of the first doping type, wherein the doping concentration of the third region is 1×1018 cm -3 ~1×10 19 cm -3 , the third region and the first region form a second avalanche junction region; or after forming a fourth region on the first region by doping with the second doping type, the third region is formed above the fourth region by ion implantation of the first doping type, and the third region and the fourth region form a second avalanche junction region.

[0052] In the semiconductor manufacturing process, in order to further enhance the performance of the avalanche photoelectric element, an additional doping or ion implantation step may be performed above the first region (above the first wafer after flipping) to form a second avalanche junction region. The present application embodiment provides two possible implementation methods: Referring to FIG. 2( g ), directly above the first region 203 (which may include the substrate and part or all of the epitaxial layer not affected by the previous doping), a third region 205 is formed by an ion implantation process of the first doping type. Since the third region 205 and the first region 203 have different doping types, a PN junction is formed between them, which is the second avalanche junction region.

[0053] In some embodiments, referring to FIG. 2 ( h ), firstly, the second doping type (N-type) is doped on the first region 203 to form the fourth region 206 ; Subsequently, the first doping type (P-type) is again doped on the fourth region 206 to form the third region 205 ; At this time, a second PN junction, ie, a second avalanche junction region, is formed between the third region 205 and the fourth region 206 due to the difference in doping types.

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0055] Example 1: High Sensitivity SiGe / Si SPAD S1: Use a P-type silicon substrate 201 with a doping concentration of 1×10 15 cm -3A 5 μm thick epitaxial layer 202 is grown on the substrate by chemical vapor deposition (CVD) technology, and the doping concentration of the epitaxial layer is the same as that of the substrate.

[0056] S2: Using ion implantation technology, an N-type dopant (such as phosphorus) is implanted into the epitaxial layer 202 to form a first region 203, and the doping concentration is set to 1×10 14 cm -3 .

[0057] S3: On the first region 203, ion implantation is performed using a P-type dopant (such as boron) to form a second region 204, with a doping concentration of 1×10 19 cm -3 .

[0058] S4 to S10: perform back-end metallization process, dielectric layer process, wafer flipping, thinning, forming contact holes and through holes, annealing, forming a passivation layer and a back metal layer according to the steps described above.

[0059] Performance evaluation: Breakdown voltage: The measured breakdown voltage is about 30V.

[0060] Quantum efficiency: At a wavelength of 1.06μm, the quantum efficiency reaches 4.2%.

[0061] Response speed: The device's response speed reaches nanosecond level.

[0062] Example 2: Low Noise SiGe / Si SPAD S1: Select a P-type silicon substrate 201 with a doping concentration of 1×10 15 cm -3 A 5 μm thick epitaxial layer 202 is grown on the substrate by CVD technology, and its doping concentration is the same as that of the substrate.

[0063] S2: Using ion implantation technology, an N-type dopant (such as phosphorus) is implanted into the epitaxial layer 202 to form a first region 203, and the doping concentration is set to 1×10 14 cm -3 .

[0064] S3: P-type dopants (such as boron) are used for ion implantation above the first region 203 to form a second region 204 with a doping concentration of 1×10 18 cm -3 .

[0065] S4 to S10: Same as Example 1.

[0066] Performance evaluation: Breakdown voltage: The measured breakdown voltage is about 30V.

[0067] Dark current: At room temperature, the dark current drops below 10nA, demonstrating the low noise characteristics of the device.

[0068] Response speed: The device's response speed reaches nanosecond level.

[0069] Example 3: High-gain SiGe / Si SPAD Step S1: Use a P-type silicon substrate 201 with a doping concentration of 1×10 14 cm -3 A 5 μm thick epitaxial layer 202 is grown on the substrate by CVD technology, and its doping concentration is the same as that of the substrate.

[0070] Step S2: Using ion implantation technology, an N-type dopant (such as phosphorus) is implanted into the epitaxial layer 202 to form a first region 203. The doping concentration is set to 1×10 15 cm -3 .

[0071] Step S3: P-type dopants (such as boron) are used for ion implantation above the first region 203 to form the second region 204, with a doping concentration of 1×10 18 cm -3 .

[0072] S4 to S10: Same as Example 1.

[0073] Performance evaluation: Breakdown voltage: The measured breakdown voltage is about 30V.

[0074] Gain: By optimizing the doping concentration and distribution of the first and second regions, the device exhibits up to 10 under specific operating conditions. 6 gain.

[0075] Response speed: The device's response speed reaches nanosecond level.

[0076] In summary, the present invention provides a single-photon avalanche photodiode and a method for preparing the same, and constructs a double avalanche junction photoelectric element of a PNP structure by back-illuminated wafer flipping and ion implantation process. In this manufacturing process, the two ion implantations into the P-type region use the same energy and dose parameters, ensuring that the double avalanche junction region can synchronously and efficiently achieve the avalanche multiplication effect when responding to photon excitation, thereby significantly improving the photon utilization efficiency and the probability of avalanche triggering.

[0077] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a single-photon avalanche photodiode, characterized in that: The following steps are involved: Providing a first doping type substrate with a specific doping concentration, the first doping type substrate comprising an epitaxial layer; doping the epitaxial layer with a second doping type to form a first region; Performing ion implantation of a first doping type into the epitaxial layer above the first region to form a second region; the first region and the second region form a first avalanche junction region; Complete the back-end metal process and dielectric layer process of the first wafer; flip the first wafer over, and place the second wafer on a side of the first wafer close to the dielectric layer; Forming a third region above the first region by ion implantation of the first doping type, wherein the third region and the first region form a second avalanche junction region; Or after forming the fourth region on the first region by doping with the second doping type, the third region is formed above the fourth region by ion implantation of the first doping type, and the third region and the fourth region form a second avalanche junction region.

2. The single-photon avalanche photodiode and the method for preparing the same according to claim 1, characterized in that: The doping concentration of the first doping type substrate is 1×10 14 cm -3 ~1×10 15 cm -3 .

3. The single-photon avalanche photodiode and the method for preparing the same according to claim 1, characterized in that: An ion implantation process is performed above the first region, and a dopant having the same first doping type as that of the substrate is implanted into the epitaxial layer, thereby forming a second region having a specific doping concentration in the epitaxial layer.

4. The single-photon avalanche photodiode and the method for preparing the same according to claim 3, characterized in that: The doping concentration of the second region is 1×10 18 cm -3 ~1×10 19 cm -3 .

5. The single-photon avalanche photodiode and the method for preparing the same according to claim 1, characterized in that: The first avalanche junction region and the second avalanche junction region share a cathode, and the cathode of the first avalanche junction region and the cathode of the second avalanche junction region are led out through the second wafer using a TSV process.

6. The single-photon avalanche photodiode and the method for preparing the same according to claim 1, characterized in that: By using the TSV process, the anode of the first avalanche region is led out through the second wafer; and the anode of the second avalanche junction region is led out on the third region.

7. The single-photon avalanche photodiode and the method for preparing the same according to claim 1, characterized in that: The ion implantation energy and the ion implantation dose in the second region are respectively the same as those in the fourth region.

8. A single photon avalanche photodiode, characterized in that: Prepared according to the method of claim 1.

9. The single-photon avalanche photodiode according to claim 8, characterized in that: From bottom to top, they include: A first doping type substrate, a first doping type epitaxial layer arranged on the first doping type substrate, a second doping type first region arranged on the first doping type epitaxial layer, a first doping type second region arranged on the first region, the first region and the second region forming a first avalanche junction region; a first doping type third region arranged above the first region, the third region and the first region forming a second avalanche junction region; and a second wafer is arranged on a side of the first wafer close to the dielectric layer.

10. The single-photon avalanche photodiode according to claim 8, characterized in that: From bottom to top, they include: A first doping type substrate, a first doping type epitaxial layer arranged on the first doping type substrate, a first region of a second doping type arranged on the first doping type epitaxial layer, a second region of the first doping type arranged on the first region, the first region and the second region forming a first avalanche junction region; a fourth region of the second doping type arranged above the first region, a third region of the first doping type arranged above the fourth region, the third region and the fourth region forming a second avalanche junction region; and a second wafer is arranged on a side of the first wafer close to the dielectric layer.

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