Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, forming an interconnection layer structure and an isolation structure in the substrate, exposing the top of the isolation structure from the substrate, and forming a first dielectric layer on the substrate; forming a first groove in the substrate and the first dielectric layer, wherein the first groove exposes part of the top of the interconnection layer structure; and in the same step, a welding pad is formed in the first groove, and a metal grid is formed on the first dielectric layer at the top of the isolation structure. According to the embodiment of the invention, in the same step, the welding pad is formed in the first groove, and the metal grid is formed on the first dielectric layer at the top of the isolation structure, so that the steps of forming the semiconductor structure are reduced, and correspondingly, the process efficiency of forming the semiconductor structure is improved; therefore, the production cycle time of the semiconductor structure is shortened. In addition, the process cost of the semiconductor structure is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Photoelectric sensors are devices that convert light signals into electrical signals. Their working principle is based on the photoelectric effect, which refers to the phenomenon that when light shines on certain substances, the electrons of the substances absorb the energy of photons and produce corresponding electrical effects.

[0003] According to the incident direction of light, it is divided into front-illuminated (FSI) and back-illuminated (BSI). In the back-illuminated image sensor, light is incident from the back of the sensor. Compared with the front-illuminated image sensor, light can enter the photoelectric sensing area (such as photodiode) more directly, reducing light loss. In the same unit time, a single pixel can obtain more light energy, which significantly improves the image quality.

[0004] However, the current manufacturing process of photoelectric sensors still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the manufacturing process of the photoelectric sensor.

[0006] To solve the above problems, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein an interconnection layer structure and an isolation structure are formed in the substrate, wherein the substrate exposes the top of the isolation structure, and wherein a first dielectric layer is formed on the substrate; forming a first groove in the substrate and the first dielectric layer, wherein the first groove exposes a portion of the top of the interconnection layer structure; in the same step, forming a solder pad in the first groove, and forming a metal grid on the first dielectric layer on the top of the isolation structure.

[0007] Accordingly, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate having a groove, an interconnection layer structure and an isolation structure formed in the substrate, the substrate exposing the top of the isolation structure; a first dielectric layer located on the substrate; a solder pad located at the bottom of the groove and electrically connected to the top of the interconnection layer structure; a metal grid located on the top of the isolation structure; wherein the solder pad and the metal grid are formed in the same step.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the same step, a solder pad is formed in the first groove, and a metal grid is formed on the first dielectric layer on the top of the isolation structure, which is beneficial to reducing the steps of forming the semiconductor structure, and correspondingly beneficial to improving the process efficiency of forming the semiconductor structure, thereby facilitating shortening the production cycle time (Cycle Time) of the semiconductor structure; moreover, it is also beneficial to reduce the process cost of the semiconductor structure.

[0010] The semiconductor structure provided by the embodiment of the present invention includes a pad and a metal grid formed in the same step, which is beneficial to reducing the steps of forming the semiconductor structure, and correspondingly beneficial to improving the process efficiency of forming the semiconductor structure, thereby beneficial to shortening the production cycle time of the semiconductor structure; moreover, it is also beneficial to reduce the process cost of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 6 to 11 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0013] Figure 12 to Figure 13 is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Fig.14 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Fig.15 It is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed. Figures 1 to 5 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1 , providing a substrate 10, wherein an interconnection layer structure 11 and an isolation structure 12 are formed in the substrate 10, wherein the substrate 10 exposes the top of the isolation structure 12, and a first dielectric layer 13 is formed on the substrate 10.

[0018] Continue to refer Figure 1 , a first groove 21 is formed in the first dielectric layer 13 , and the first groove 21 exposes the top of the substrate 10 .

[0019] refer to Figure 2 A grounding structure 26 is formed in the first groove 21 , and the grounding structure 26 also extends to cover a portion of the top of the first dielectric layer 13 , and a metal grid 27 is formed on the first dielectric layer 13 at the top of the isolation structure 12 .

[0020] refer to Figure 3 , forming a second dielectric layer 14 covering the ground structure 26 and the metal grid 27 .

[0021] Continue to refer Figure 3 A first sub-groove 22 is formed in the second dielectric layer 14, the first dielectric layer 13, and a partial thickness of the substrate 10 above the interconnection layer structure 11, and the first sub-groove 22 corresponds to the interconnection layer 11 structure.

[0022] refer to Figure 4 A third dielectric layer 15 is formed on the bottom and sidewalls of the first sub-groove 22 and on the second dielectric layer 14 outside the first sub-groove 22. The third dielectric layer 15 on the sidewalls of the first sub-groove 22 serves as a sidewall.

[0023] Continue to refer Figure 4 , remove the third dielectric layer 15 in a partial area of ​​the bottom of the first sub-groove 22 and the substrate 10 in a partial area to form a second sub-groove 23 that is connected to the first sub-groove 22, and the second sub-groove 23 exposes a portion of the top of the interconnection layer structure 11, and the second sub-groove 23 and the first sub-groove 22 constitute a second groove 25.

[0024] refer to Figure 5 A welding pad 28 is formed in the second sub-recess 25 and at the bottom of the first sub-recess 22 .

[0025] Research has found that forming the metal grid 27 and the pad 28 in different steps results in more steps for forming the semiconductor structure, which in turn easily leads to poor process efficiency for forming the semiconductor structure, thereby making the production cycle time of the semiconductor structure longer and also easily leading to higher process costs for the semiconductor structure.

[0026] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein an interconnection layer structure and an isolation structure are formed in the substrate, wherein the substrate exposes the top of the isolation structure, and wherein a first dielectric layer is formed on the substrate; forming a first groove in the substrate and the first dielectric layer, wherein the first groove exposes a portion of the top of the interconnection layer structure; in the same step, forming a solder pad in the first groove, and forming a metal grid on the first dielectric layer on the top of the isolation structure.

[0027] In the scheme disclosed in the embodiment of the present invention, in the same step, a welding pad is formed in the first groove, and a metal grid is formed on the first dielectric layer on the top of the isolation structure, which is beneficial to reducing the steps of forming the semiconductor structure, and correspondingly beneficial to improving the process efficiency of forming the semiconductor structure, thereby facilitating shortening the production cycle time of the semiconductor structure; moreover, it is also beneficial to reduce the process cost of the semiconductor structure.

[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figures 6 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0030] refer to Figure 6 , providing a substrate 100 , in which an interconnection layer structure 110 and an isolation structure 120 are formed, the substrate 100 exposes the top of the isolation structure 120 , and a first dielectric layer 130 is formed on the substrate 100 .

[0031] The substrate 100 is used to provide a process platform for subsequent process steps.

[0032] In this embodiment, in the step of providing the substrate 100, the substrate includes a logic substrate 101 and a pixel substrate 102 bonded to the logic substrate 101, an isolation structure 120 is formed in the pixel substrate 102, the pixel substrate 102 exposes the top of the isolation structure 120, and an interconnection layer structure 110 is formed in the logic substrate 101.

[0033] The logic substrate 101 is used to analyze and process the electrical signal provided by the pixel substrate 102. Specifically, a logic device (not shown) is formed in the logic substrate 101, and the logic device is used to analyze and process the electrical signal provided by the pixel substrate 102.

[0034] The interconnection layer structure 110 is used to lead out the electrical properties of the logic device or to realize the electrical connection between the logic devices.

[0035] The pixel substrate 102 is used to provide an operating platform for forming a photosensor.

[0036] Specifically, the pixel substrate 102 includes a substrate (not shown). Specifically, the material of the substrate may include one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or other types of substrates.

[0037] It should be noted that the pixel substrate 102 is a backside illumination (BSI) pixel wafer, and the surface of the pixel substrate 102 facing away from the logic substrate 101 is a light-receiving surface.

[0038] It should also be noted that the pixel substrate 102 includes a lead area (not marked) and a photosensitive area (not marked), and a pixel unit (not shown) is formed in the photosensitive area. The pixel unit is used to receive optical signals so as to convert the optical signals into electrical signals. The lead area is used to realize electrical connection between the pixel unit or other device structures in the photosensitive area and the external circuit.

[0039] The isolation structure 120 is located between adjacent pixel units to reduce optical crosstalk and electrical crosstalk between adjacent pixel units.

[0040] In this embodiment, the isolation structure 120 is a deep trench isolation (DTI) structure.

[0041] Specifically, according to the type and performance requirements of the photoelectric sensor, the material of the isolation structure 120 includes one or both of a dielectric material and a metal material. The metal material includes one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride and copper, and the dielectric material includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide and barium oxide.

[0042] The first dielectric layer 130 is used to isolate the substrate 100 from subsequently formed film layers (eg, metal grid, second dielectric layer, third dielectric layer, etc.), and to provide a flat surface for the formation of subsequent film layers.

[0043] In this embodiment, in the step of providing the substrate 100 , the first dielectric layer 130 includes a first sub-dielectric layer 131 and a second sub-dielectric layer 132 located on the first sub-dielectric layer 131 , and the material of the first sub-dielectric layer 131 includes a high-k dielectric material.

[0044] The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the first sub-dielectric layer 131 includes any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, strontium oxide, lanthanum oxide and barium oxide.

[0045] The material of the first sub-dielectric layer 131 includes a high-k dielectric material, which is beneficial to absorbing the charges on the surface of the pixel substrate 102, thereby helping to reduce the "white pixel" defect; moreover, the material of the first sub-dielectric layer 131 includes a high-k dielectric material, which is also convenient for filtering photoelectrons, allowing light in a specific band to pass through the first sub-dielectric layer 131.

[0046] The second sub-dielectric layer 132 is used to provide a flat surface for the film layer to be formed subsequently. Moreover, the second sub-dielectric layer 132 is also used to protect the top of the first sub-dielectric layer 131, reducing the probability that the top of the first sub-dielectric layer 131 is damaged or contaminated in the subsequent process. The second sub-dielectric layer 132 is an oxide layer. Specifically, the material of the second sub-dielectric layer 132 includes silicon oxide. In other embodiments, the material of the second sub-dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0047] refer to Figure 7 , and combined with reference Figure 6 In this embodiment, before forming the first groove, the method further includes: forming a second groove 140 in the first dielectric layer 130, wherein the second groove 140 exposes the substrate 100 (eg Figure 6 A ground structure 141 (Back Side Ground, BSGND) is formed in the second groove 140 (as shown); Figure 7 shown).

[0048] The grounding structure 141 is used to be electrically connected to the substrate 100 to reduce dark current. Specifically, the grounding structure 141 is used to be electrically connected to the pixel substrate 102 .

[0049] It should be noted that, in the process of forming the second groove 140, a portion of the thickness of the pixel substrate 102 is also removed to reduce the difficulty of exposing the substrate 100 by the second groove 140, so as to ensure that the second groove 140 exposes the substrate 100, thereby ensuring that the grounding structure 141 is electrically connected to the substrate 100. The portion of the thickness of the pixel substrate 102 is also removed, which means that the first portion of the thickness of the pixel substrate 102 is also removed.

[0050] In this embodiment, when the grounding structure 141 is formed before the first groove is formed, the forming method further includes: before the first sub-groove is formed, forming a third dielectric layer 150 on the first dielectric layer 130 and the grounding structure 140 .

[0051] The third dielectric layer 150 is used to protect the top of the grounding structure 140 .

[0052] Specifically, the third dielectric layer 150 is an oxide layer. Specifically, the material of the third dielectric layer 150 includes silicon oxide. In other embodiments, the material of the third dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0053] The thickness of the third dielectric layer 150 should not be too small or too large. If the thickness of the third dielectric layer 150 is too small, the thickness uniformity of the third dielectric layer 150 is poor; if the thickness of the third dielectric layer 150 is too large, unnecessary material waste is easily caused. Therefore, as an example, in the step of forming the third dielectric layer 150, the thickness of the third dielectric layer 150 ranges from 1000 angstroms to 1600 angstroms.

[0054] refer to Figure 8 , and combined with reference Figure 7 A first groove 160 (eg, Figure 8 As shown), the first recess 160 exposes a portion of the top of the interconnection layer structure 110 .

[0055] The first groove 160 is used to provide a space for subsequently forming a welding pad.

[0056] In this embodiment, the steps of forming the first groove 160 include: Figure 7 As shown, a first sub-groove 161 is formed in the first dielectric layer 130 above the interconnection layer structure 110 and in a partial thickness of the substrate 100, and the first sub-groove 161 corresponds to the interconnection layer structure 110; Figure 8 As shown, the substrate 100 at a first partial region of the bottom of the first sub-groove 161 is removed to form a second sub-groove 162 intersecting the first sub-groove 161 , and the second sub-groove 162 exposes a portion of the top of the interconnection layer structure 110 .

[0057] First, a first sub-groove 161 is formed in the first dielectric layer 130 above the interconnection layer structure 110 and a partial thickness of the substrate 100, and then a first partial area of ​​the substrate 100 at the bottom of the first sub-groove 161 is removed to form a second sub-groove 162 that is intersecting with the first sub-groove 161. This is beneficial in reducing the aspect ratio of the first sub-groove 161 during the process of forming the first sub-groove 161, thereby reducing the difficulty of forming the first groove 160, and also in reducing the probability of damage to the top of the interconnection layer structure 110 during the process of forming the first groove 160.

[0058] Specifically, a first sub-groove 161 is formed in the first dielectric layer 130 , the pixel substrate 102 and the partial-thickness logic substrate 101 above the interconnection layer structure 110 .

[0059] The partial thickness logic substrate 101 refers to: a second partial thickness logic substrate 101 .

[0060] As an example, before forming the first groove, in the case where the grounding structure 141 is formed, the forming method further includes: before forming the first sub-groove 161, forming a third dielectric layer 150 on the first dielectric layer 130 and the grounding structure 140. Accordingly, in the step of forming the first sub-groove 161, the third dielectric layer 150 in the second partial area is also removed.

[0061] In this embodiment, Figure 8 As shown, after forming the first sub-groove 161 and before forming the second sub-groove 162, it also includes: forming a second dielectric layer 170 on the bottom and side walls of the first sub-groove 161 and on the first dielectric layer 130 outside the first sub-groove 161, and the second dielectric layer 170 located on the side walls of the first sub-groove 161 serves as a side wall.

[0062] The sidewall is used to protect the sidewall of the first sub-recess 161 and reduce the probability of damage to the sidewall of the first sub-recess 161 during the subsequent formation of the pad. Specifically, the sidewall is used to reduce the probability of migration reaction between the material used to form the pad and the material of the sidewall of the first sub-recess 161.

[0063] Specifically, the second dielectric layer 170 is an oxide layer. More specifically, the material of the second dielectric layer 170 includes silicon oxide. In other embodiments, the material of the second dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0064] Accordingly, in this embodiment, in the step of forming the second sub-groove 162 , the second dielectric layer 170 in a first partial region of the bottom of the first sub-groove 161 is also removed.

[0065] Correspondingly, in this embodiment, in the step of forming the second dielectric layer 170 , the second dielectric layer 170 is located on the grounding structure 141 .

[0066] refer to Figures 9 to 11 In the same step, a pad 180 (eg, Fig.11 As shown), and forming a metal grid 181 (as shown) on the first dielectric layer 130 at the top of the isolation structure 120 Fig.11 As shown), it is beneficial to reduce the steps of forming the semiconductor structure, which is correspondingly beneficial to improving the process efficiency of forming the semiconductor structure, thereby facilitating shortening the production cycle time of the semiconductor structure; moreover, it is also beneficial to reduce the process cost of the semiconductor structure.

[0067] The pad 180 is used to be electrically connected to the interconnection layer structure 110 to electrically lead out the logic device.

[0068] The metal grid 181 is a grid-like structure. The position and shape of the metal grid 181 correspond to the isolation structure 120 . The area enclosed by the metal grid 181 corresponds to each pixel unit, thereby preventing optical crosstalk between adjacent pixel units.

[0069] In this embodiment, in the same step, the steps of forming the pad 180 and the metal grid 181 include: Fig. 9 As shown, a conformal metal material layer 182 is formed on the bottom and sidewalls of the first groove 160 and on the first dielectric layer 130 outside the first groove 160; Fig.10 As shown, a patterned mask layer 190 is formed on the metal material layer 182, and the mask layer 190 covers the bottom of the first groove 160 and the metal material layer 182 on the top of the isolation structure 120, and exposes the metal material layer 182 in the remaining area; using the mask layer 190 as a mask, the metal material layer 182 in the remaining area is removed, and the remaining metal material layer 182 at the bottom of the first groove 160 is used as the welding pad 180, and the remaining metal material layer 182 at the top of the isolation structure 120 is used as the metal grid 181; as shown Fig.11 As shown, after the bonding pad 180 and the metal grid 181 are formed, the process further includes: removing the mask layer 190 .

[0070] After forming a conformal metal material layer 182 on the bottom and sidewalls of the first groove 160 and on the first dielectric layer 130 outside the first groove 160, a patterned mask layer 190 is first formed on the metal material layer 182, and then the mask layer 190 is used as a mask to remove the metal material layer 182 from the remaining areas except the bottom of the first groove 160 and the top of the isolation structure 120, which helps to reduce the difficulty of forming the solder pad 180 and the metal grid 181.

[0071] Specifically, the mask layer 190 includes a photoresist, and the step of forming a patterned mask layer 190 on the metal material layer 182 includes: forming a mask material layer (not shown) on the metal material layer 182; providing a mask for patterning the mask material layer, the mask having a mask pattern, the projection of the mask pattern on the substrate 100 covering the bottom of the first groove 160 and the top of the isolation structure 120; using the mask to perform a photolithography operation on the mask material layer, removing the mask material layer in the remaining area except the bottom of the first groove 160 and the top of the isolation structure 120, so as to transfer the mask pattern to the mask material layer, and the remaining mask material layer is used as the mask layer 190, which is conducive to reducing the difficulty of forming the mask layer 190. Moreover, the mask layer 190 includes a photoresist, which is also conducive to reducing the difficulty of removing the mask layer 190. Accordingly, forming the pad 181 and the metal grid 182 in the same step is also conducive to saving the number of masks.

[0072] More specifically, the mask material layer may be a single-layer structure or a stacked-layer structure.

[0073] It should be noted that the process of removing the metal material layer 182 in the remaining area includes a dry etching process. The dry etching process has anisotropic etching characteristics, so the etching accuracy is high and the controllability of the cross section is better, which is conducive to improving the morphology accuracy and size accuracy of the pad 180 and the metal grid 181.

[0074] It is understandable that in the same step, the pad 180 and the metal grid 181 are formed by etching the metal material layer 182. Accordingly, the pad 180 and the metal grid 181 have the same height.

[0075] In this embodiment, in the step of forming the welding pad 180 , the welding pad 180 is formed in the second sub-groove 162 and at the bottom of the first sub-groove 161 , which is beneficial to reducing the material required to form the welding pad 180 .

[0076] Specifically, since the second dielectric layer 170 is formed on the bottom and sidewalls of the first sub-recess 161 and on the first dielectric layer 130 outside the first sub-recess 161, in the step of forming the bonding pad 180 and the metal grid 181, the bonding pad 180 is formed in the second sub-recess 162 and on the second dielectric layer 170 at the bottom of the first sub-recess 161, and the metal grid 181 is formed on the second dielectric layer 170 at the top of the isolation structure 120.

[0077] More specifically, before forming the second dielectric layer 170, the third dielectric layer 150 is formed on the first dielectric layer 130; accordingly, in the step of forming the metal grid 181, the metal grid 181 is formed on the first dielectric layer 130, the third dielectric layer 150, and the second dielectric layer 170 on the top of the isolation structure 120.

[0078] In this embodiment, the material of the welding pad 180 and the metal grid 181 is a metal material. The metal material generally has good electrical conductivity and is generally opaque.

[0079] As an example, the material of the pad 180 and the metal grid 181 includes aluminum.

[0080] Aluminum is a material that is easily etched, so it is convenient to form the pad 180 and the metal grid 181 in a patterning manner.

[0081] Figure 12 to Figure 13 1 is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between the second embodiment and the above embodiment are not repeated here. The difference between the second embodiment and the above embodiment is that, Fig.12 As shown, in the step of forming the second sub-groove 262, a second groove 240 is formed in the first dielectric layer 230 and the second dielectric layer 270 outside the first sub-groove 261, and the second groove 240 exposes the substrate 200; Fig.13 As shown, in the step of forming the pad 280 and the metal grid 281 , a grounding structure 241 is also formed in the second groove 240 , and the grounding structure 241 also extends to cover a portion of the top of the second dielectric layer 270 .

[0082] Forming the bonding pad 280 , the metal grid 281 , and the grounding structure 241 in the same step is beneficial to further reduce the steps of forming the semiconductor structure.

[0083] Specifically, the steps of forming the solder pad 280, the metal grid 281, and the grounding structure 241 in the same step include: forming a conformal covering metal material layer (not shown) on the bottom and side walls of the first groove 260 and on the first dielectric layer 230 outside the first groove 260; forming a patterned mask layer (not shown) on the metal material layer; using the mask layer as a mask, removing the metal material layer exposed by the mask layer to form the solder pad 280, the metal grid 281, and the grounding structure 241.

[0084] More specifically, the mask layer includes photoresist. It can be understood that in the process of forming the mask layer, a mask with a mask pattern is also provided, that is, a mask is used to etch the metal material layer to form the pad 280, the metal grid 281, and the grounding structure 241, which is conducive to further reducing the number of masks.

[0085] It should be noted that since the pad 280, the metal grid 281, and the grounding structure 241 are formed in the same step, after the first dielectric layer 230 is formed, the first groove 260 can be directly formed in the substrate 100 and the first dielectric layer 230, thereby further saving process steps. Accordingly, in the step of forming the second dielectric layer 270, the second dielectric layer 270 outside the first groove 260 is located on the first dielectric layer 230.

[0086] Correspondingly, the present invention also provides a semiconductor structure. Fig.14 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0087] refer to Fig.14 In this embodiment, the semiconductor structure includes: a substrate 500 having a groove 560, an interconnection layer structure 510 and an isolation structure 520 are formed in the substrate 500, and the substrate 500 exposes the top of the isolation structure 520; a first dielectric layer 530, located on the substrate 500; a pad 580, located at the bottom of the groove 560 and electrically connected to the top of the interconnection layer structure 510; a metal grid 581, located on the top of the isolation structure 520; wherein the pad 580 and the metal grid 581 are formed in the same step.

[0088] The substrate 500 is used to provide a process platform for forming a semiconductor structure.

[0089] The groove 560 is used as a first groove 560 .

[0090] In this embodiment, the substrate 100 includes a logic substrate 501 and a pixel substrate 502 located on the logic substrate 501, an isolation structure 520 is formed in the pixel substrate 502, the pixel substrate 502 exposes the top of the isolation structure 520, an interconnection layer structure 510 is formed in the logic substrate 501, and the groove 560 is located in the pixel substrate 502 and the partial thickness of the logic substrate 501.

[0091] The logic substrate 501 is used to analyze and process the electrical signal provided by the pixel substrate 502. Specifically, a logic device (not shown) is formed in the logic substrate 501, and the logic device is used to analyze and process the electrical signal provided by the pixel substrate 502.

[0092] The interconnection layer structure 510 is used to lead out the electrical properties of the logic device or to realize the electrical connection between the logic devices.

[0093] The pixel substrate 502 is used to provide an operating platform for forming a photosensor.

[0094] Specifically, the pixel substrate 502 includes a substrate (not shown). Specifically, the material of the substrate may include one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or other types of substrates.

[0095] It should be noted that the pixel substrate 502 is a back-illuminated pixel wafer, and the surface of the pixel substrate 502 facing away from the logic substrate 501 is a light-receiving surface.

[0096] It should also be noted that the pixel substrate 502 includes a lead area (not marked) and a photosensitive area (not marked), and a pixel unit (not shown) is formed in the photosensitive area. The pixel unit is used to receive optical signals so as to convert the optical signals into electrical signals. The lead area is used to realize electrical connection between the pixel unit or other device structures in the photosensitive area and the external circuit.

[0097] The isolation structure 520 is located between adjacent pixel units to reduce optical crosstalk and electrical crosstalk between adjacent pixel units.

[0098] In this embodiment, the isolation structure 520 is a deep trench isolation structure.

[0099] Specifically, according to the type and performance requirements of the photoelectric sensor, the material of the isolation structure 520 includes one or both of a dielectric material and a metal material. The metal material includes one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride and copper, and the dielectric material includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide and barium oxide.

[0100] The first dielectric layer 530 is used to isolate the substrate 500 from other film layers (eg, metal grid 581, second dielectric layer, third dielectric layer, etc.), and to provide a flat surface for the formation of other film layers.

[0101] In this embodiment, the first dielectric layer 530 includes a first sub-dielectric layer 531 and a second sub-dielectric layer 532 located on the first sub-dielectric layer 531 . The material of the first dielectric layer 531 includes a high-k dielectric material.

[0102] The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the first sub-dielectric layer 531 includes any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, strontium oxide, lanthanum oxide and barium oxide.

[0103] The material of the first sub-dielectric layer 531 includes a high-k dielectric material, which is beneficial to absorbing the charges on the surface of the pixel substrate 502, thereby helping to reduce the "white pixel" defect; moreover, the material of the first sub-dielectric layer 531 includes a high-k dielectric material, which is also convenient for filtering photoelectrons, allowing light in a specific band to pass through the first sub-dielectric layer 531.

[0104] The second sub-dielectric layer 532 is used to provide a flat surface for the formation of other film layers. In addition, the second sub-dielectric layer 532 is also used to protect the top of the first sub-dielectric layer 531, reducing the probability that the top of the first sub-dielectric layer 531 is damaged or contaminated during the process. The second sub-dielectric layer 532 is an oxide layer. Specifically, the material of the second sub-dielectric layer 532 includes silicon oxide. In other embodiments, the material of the second sub-dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0105] The first groove 560 is used to provide a space for forming a welding pad 580 .

[0106] In this embodiment, the groove 560 includes a first sub-groove 561 and a second sub-groove (not marked) located at the bottom of the first sub-groove 561 , and the second sub-groove and the first sub-groove 561 are interconnected.

[0107] Typically, a first sub-groove 561 is first formed in the first dielectric layer 530 above the interconnection layer structure 510 and in a partial thickness of the substrate 500, the first sub-groove 561 corresponding to the interconnection layer structure 510, and then a first partial area of ​​the substrate 500 at the bottom of the first sub-groove 561 is removed to form a second sub-groove intersecting the first sub-groove 561, the second sub-groove exposing a portion of the top of the interconnection layer structure 510, which is beneficial in reducing the aspect ratio of the first sub-groove 561 during the process of forming the first sub-groove 561, thereby reducing the difficulty of forming the first groove 560, and also reducing the probability of damage to the top of the interconnection layer structure 510 during the process of forming the first groove 560.

[0108] Specifically, a first sub-groove 561 is formed in the first dielectric layer 530 above the interconnection layer structure 510 , the pixel substrate 502 , and a portion of the thickness of the substrate 500 .

[0109] In this embodiment, the semiconductor structure further includes: a second dielectric layer 570 located on the sidewall of the first sub-recess 561 and on the first dielectric layer 530 outside the first sub-recess 561, wherein the second dielectric layer 570 located on the sidewall of the first sub-recess 561 serves as a sidewall.

[0110] The sidewall is used to protect the sidewall of the first sub-recess 561 and reduce the probability of the sidewall of the first sub-recess 561 being damaged during the formation of the pad 580. Specifically, the sidewall is used to reduce the probability of migration reaction between the material used to form the pad 580 and the material of the sidewall of the first sub-recess 561.

[0111] Specifically, the second dielectric layer 570 is an oxide layer. More specifically, the material of the second dielectric layer 570 includes silicon oxide. In other embodiments, the material of the second dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0112] In this embodiment, the semiconductor structure further includes: a grounding structure 541 located in the first dielectric layer 530 outside the groove 560 and electrically connected to the substrate 500 ; and the second dielectric layer 570 covers the grounding structure 541 .

[0113] The grounding structure 541 is used to be electrically connected to the substrate 500 to reduce dark current. Specifically, the grounding structure 541 is used to be electrically connected to the pixel substrate 502 .

[0114] It should be noted that the grounding structure 541 is also located in a portion of the thickness of the pixel substrate 502 to ensure that the grounding structure 541 is electrically connected to the substrate 500 .

[0115] In this embodiment, when the grounding structure 541 is only located in the first dielectric layer 530 outside the groove 560 and is electrically connected to the substrate 500, the semiconductor structure further includes: a third dielectric layer 550, located on the first dielectric layer 530 and the grounding structure 541; and the second dielectric layer 570 covers the third dielectric layer 550.

[0116] The third dielectric layer 550 is used to protect the top of the grounding structure 541 .

[0117] Specifically, the third dielectric layer 550 is an oxide layer. Specifically, the material of the third dielectric layer 150 includes silicon oxide. In other embodiments, the material of the third dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0118] The thickness of the third dielectric layer 550 should not be too small or too large. If the thickness of the third dielectric layer 550 is too small, the thickness uniformity of the third dielectric layer 550 is poor; if the thickness of the third dielectric layer 550 is too large, unnecessary material waste is easily caused. Therefore, as an example, the thickness of the third dielectric layer 550 ranges from 1000 angstroms to 1600 angstroms.

[0119] The pad 580 is used to be electrically connected to the interconnection layer structure 510 to electrically lead out the logic device.

[0120] The metal grid 581 is a grid-like structure. The position and shape of the metal grid 581 correspond to the isolation structure 520. The area enclosed by the metal grid 581 corresponds to each pixel unit, thereby preventing optical crosstalk between adjacent pixel units.

[0121] In this embodiment, the material of the welding pad 580 and the metal grid 581 is a metal material. The metal material generally has good electrical conductivity and is generally opaque.

[0122] As an example, the material of the pad 580 and the metal grid 581 includes aluminum.

[0123] Aluminum is a material that is easily etched, so it is convenient to form the pad 580 and the metal grid 581 in a patterning manner.

[0124] In this embodiment, the welding pad 580 is located in the second sub-groove and at the bottom of the first sub-groove 561 , which is beneficial to reducing the material required to form the welding pad 580 .

[0125] Since the semiconductor structure further includes a second dielectric layer 570 , accordingly, in this embodiment, the pad 580 is located in the second sub-groove and on the second dielectric layer 570 at the bottom of the first sub-groove 561 ; the metal grid 581 is located on the second dielectric layer 570 at the top of the isolation structure 520 .

[0126] Since the semiconductor structure further includes a third dielectric layer 550 , in this embodiment, the metal grid 581 is located on the first dielectric layer 530 , the third dielectric layer 550 , and the second dielectric layer 570 at the top of the isolation structure 520 .

[0127] Usually in the same step, the steps of forming the pad 580 and the metal grid 581 include: forming a conformal metal material layer (not shown) on the bottom and sidewalls of the first groove 560 and the first dielectric layer 530 outside the first groove 560; forming a patterned mask layer (not shown) on the metal material layer, the mask layer covers the bottom of the first groove 560 and the metal material layer on the top of the isolation structure 520, and exposes the metal material layer in the remaining area; using the mask layer as a mask, removing the metal material layer in the remaining area, the remaining metal material layer at the bottom of the first groove 560 is used as the pad 580, and the remaining metal material layer at the top of the isolation structure 520 is used as the metal grid 581. That is, the pad 580 and the metal grid 581 are formed by etching the same metal material layer, and accordingly, the pad 580 and the metal grid 581 have the same height.

[0128] Fig.15 6 is a schematic diagram of the structure of another embodiment of the semiconductor structure of the present invention. The similarities between the second embodiment and the aforementioned embodiment are not repeated here. The difference between the second embodiment and the aforementioned embodiment is that the semiconductor structure further includes: a grounding structure 641, located in the first dielectric layer 630 and the second dielectric layer 670 outside the groove 660, the grounding structure 641 also extends to cover a portion of the top of the second dielectric layer 670, and the grounding structure 641 is electrically connected to the substrate 600.

[0129] The grounding structure 641 is located in the first dielectric layer 630 and the second dielectric layer 670 outside the groove 660, so as to form the pad 680, the metal grid 681, and the grounding structure 641 in the same step, which is beneficial to further reduce the steps of forming the semiconductor structure.

[0130] It should be noted that since the pad 680, the metal grid 681, and the grounding structure 641 are formed in the same step, after forming the first dielectric layer 630, the groove 660 can be directly formed in the substrate 600 and the first dielectric layer 630, thereby further saving process steps. Accordingly, the second dielectric layer 670 outside the groove 660 is located on the first dielectric layer 630.

[0131] It should also be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein an interconnection layer structure and an isolation structure are formed in the substrate, the substrate exposes the top of the isolation structure, and a first dielectric layer is formed on the substrate; forming a first groove in the substrate and the first dielectric layer, wherein the first groove exposes a portion of the top of the interconnection layer structure; In the same step, a bonding pad is formed in the first groove, and a metal grid is formed on the first dielectric layer on top of the isolation structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the first groove comprises: forming a first sub-groove in a first dielectric layer above the interconnection layer structure and a substrate of a partial thickness, wherein the first sub-groove corresponds to the interconnection layer structure; removing a first partial area of ​​the substrate at the bottom of the first sub-groove to form a second sub-groove intersecting the first sub-groove, wherein the second sub-groove exposes a portion of the top of the interconnection layer structure; In the step of forming the pad, a pad is formed in the second sub-groove and at the bottom of the first sub-groove.

3. The method for forming a semiconductor structure according to claim 2, wherein: After forming the first sub-groove and before forming the second sub-groove, the method further includes: forming a second dielectric layer on the bottom and sidewalls of the first sub-groove and on the first dielectric layer outside the first sub-groove, wherein the second dielectric layer on the sidewalls of the first sub-groove serves as a sidewall; In the step of forming the second sub-groove, the second dielectric layer in a first partial area of ​​the bottom of the first sub-groove is also removed; In the step of forming the pad and the metal grid, the pad is formed in the second sub-groove and on the second dielectric layer at the bottom of the first sub-groove, and the metal grid is formed on the second dielectric layer at the top of the isolation structure.

4. The method for forming a semiconductor structure according to claim 3, wherein: Before forming the first groove, the method further includes: forming a second groove in the first dielectric layer, wherein the second groove exposes the substrate; and forming a grounding structure in the second groove; In the step of forming a second dielectric layer, the second dielectric layer is located on the ground structure; or, In the step of forming the second sub-groove, a second groove is formed in the first dielectric layer and the second dielectric layer outside the first sub-groove, wherein the second groove exposes the substrate; In the step of forming the bonding pad and the metal grid, a grounding structure is also formed in the second groove, and the grounding structure also extends to cover a portion of the top of the second dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: In the case where the grounding structure is formed before the first groove is formed, the forming method further comprises: before the first sub-groove is formed, forming a third dielectric layer on the first dielectric layer and the grounding structure; In the step of forming the first sub-groove, the third dielectric layer in the second partial area is also removed; In the step of forming the metal grid, a metal grid is formed on the first dielectric layer, the third dielectric layer, and the second dielectric layer on the top of the isolation structure.

6. The method for forming a semiconductor structure according to claim 1, wherein: In the same step, the steps of forming the pad and the metal grid include: forming a conformal metal material layer on the bottom and sidewalls of the first groove and on the first dielectric layer outside the first groove; forming a patterned mask layer on the metal material layer, wherein the mask layer covers the bottom of the first groove and the metal material layer on the top of the isolation structure and exposes the metal material layer in the remaining area; Using the mask layer as a mask, remove the metal material layer in the remaining area, use the remaining metal material layer at the bottom of the first groove as a welding pad, and use the remaining metal material layer at the top of the isolation structure as a metal grid; After forming the bonding pad and the metal grid, the method further includes: removing the mask layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The mask layer includes photoresist, and the step of forming a patterned mask layer on the metal material layer includes: forming a mask material layer on the metal material layer; Providing a photomask for patterning the mask material layer, the photomask having a photomask pattern, the projection of the photomask pattern on the substrate covering the bottom of the first groove and the top of the isolation structure; The mask material layer is photolithographically processed using the photomask to remove the mask material layer from areas other than the bottom of the first groove and the top of the isolation structure, so as to transfer the mask pattern to the mask material layer, and the remaining mask material layer serves as a mask layer.

8. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the metal material layer in the remaining area includes a dry etching process.

9. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer located on the first sub-dielectric layer, and the material of the first sub-dielectric layer includes a high-k dielectric material.

10. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the substrate includes a logic substrate and a pixel substrate bonded to the logic substrate, an isolation structure is formed in the pixel substrate, the pixel substrate exposes the top of the isolation structure, and an interconnection layer structure is formed in the logic substrate.

11. A semiconductor structure, characterized in that: include: A substrate having a groove, wherein an interconnection layer structure and an isolation structure are formed in the substrate, and the substrate exposes a top of the isolation structure; A first dielectric layer, located on the substrate; a solder pad, located at the bottom of the groove and electrically connected to the top of the interconnection layer structure; a metal grid located on top of the isolation structure; Wherein, the pad and the metal grid are formed in the same step.

12. The semiconductor structure according to claim 11, wherein: The groove comprises a first sub-groove and a second sub-groove located at the bottom of the first sub-groove, and the second sub-groove and the first sub-groove are interconnected; The pad is located in the second sub-groove and at the bottom of the first sub-groove.

13. The semiconductor structure according to claim 12, wherein: The semiconductor structure further includes: a second dielectric layer located on the sidewall of the first sub-groove and on the first dielectric layer outside the first sub-groove, wherein the second dielectric layer located on the sidewall of the first sub-groove serves as a sidewall; The pad is located in the second sub-groove and on the second dielectric layer at the bottom of the first sub-groove; The metal grid is located on the second dielectric layer on top of the isolation structure.

14. The semiconductor structure according to claim 13, wherein: The semiconductor structure further comprises: a grounding structure, located in the first dielectric layer outside the groove and electrically connected to the substrate, and the second dielectric layer covers the grounding structure; or, The semiconductor structure further includes a grounding structure located in the first dielectric layer and the second dielectric layer outside the groove, the grounding structure also extends to cover a portion of the top of the second dielectric layer, and the grounding structure is electrically connected to the substrate.

15. The semiconductor structure according to claim 11, wherein: The material of the pad and the metal grid includes aluminum.

16. The semiconductor structure according to claim 14, wherein: In the case where the grounding structure is only located in the first dielectric layer outside the groove and is electrically connected to the substrate, the semiconductor structure further includes: a third dielectric layer located on the first dielectric layer and the grounding structure; and the second dielectric layer covers the third dielectric layer.

17. The semiconductor structure according to claim 16, wherein: The thickness of the third dielectric layer 150 ranges from 1000 angstroms to 1600 angstroms.

18. The semiconductor structure according to claim 11, wherein: The first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer located on the first sub-dielectric layer, and the material of the first sub-dielectric layer includes a high-k dielectric material.

19. The semiconductor structure according to claim 11, wherein: The substrate includes a logic substrate and a pixel substrate located on the logic substrate, an isolation structure is formed in the pixel substrate, the pixel substrate exposes the top of the isolation structure, an interconnection layer structure is formed in the logic substrate, and the groove is located in the pixel substrate and the logic substrate with a partial thickness.

20. The semiconductor structure according to claim 11, wherein: The pad and the metal grid have the same height.

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