Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: providing a substrate, the substrate having an interconnection layer structure and an isolation structure formed therein, the substrate exposing a top of the isolation structure, and a first dielectric layer formed on the substrate; forming a first recess in the substrate and the first dielectric layer, the first recess exposing a part of a top of the interconnection layer structure; forming a solder pad in the first recess and a metal grid on the first dielectric layer on the top of the isolation structure in the same step. The embodiment of the present application forms the solder pad in the first recess and the metal grid on the first dielectric layer on the top of the isolation structure in the same step, which is advantageous to reduce the steps of forming the semiconductor structure, and accordingly, is advantageous to improve the process efficiency of forming the semiconductor structure, so as to shorten the production cycle time of the semiconductor structure, and further, is advantageous to reduce the process cost of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] A photoelectric sensor is a device that converts light signals into electrical signals. Its working principle is based on the photoelectric effect, which refers to the phenomenon where electrons in a substance absorb the energy of photons and produce corresponding electrical effects when light shines on them.

[0003] Based on the direction of light incidence, image sensors are divided into front-illuminated (FSI) and back-illuminated (BSI) sensors. In back-illuminated image sensors, light enters from the back of the sensor. Compared to front-illuminated image sensors, light can enter the photoelectric sensing area (such as photodiodes) more directly, reducing light loss. In the same unit of time, a single pixel can acquire more light energy, which significantly improves image quality.

[0004] However, the manufacturing process for photoelectric sensors still needs improvement. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the manufacturing process of photoelectric sensors.

[0006] To address the aforementioned problems, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate in which an interconnect layer structure and an isolation structure are formed, the top of the isolation structure being exposed on the substrate, and a first dielectric layer being formed on the substrate; forming a first groove in the substrate and the first dielectric layer, the first groove exposing a portion of the top of the interconnect layer structure; and in the same step, forming a bonding pad in the first groove and forming a metal grid on the first dielectric layer on top of the isolation structure.

[0007] Accordingly, embodiments of the present invention provide a semiconductor structure, comprising: a substrate having a groove, wherein an interconnect layer structure and an isolation structure are formed in the substrate, the top of the isolation structure being exposed; a first dielectric layer located on the substrate; a bonding pad located at the bottom of the groove and electrically connected to the top of the interconnect layer structure; and a metal grid located at the top of the isolation structure; wherein the bonding pad and the metal grid are formed in the same step.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, in the same step, a bonding pad is formed in the first groove and a metal grid is formed on the first dielectric layer on top of the isolation structure. This helps to reduce the number of steps in forming the semiconductor structure, thereby improving the process efficiency of forming the semiconductor structure and thus shortening the production cycle time of the semiconductor structure. Moreover, it also helps to reduce the process cost of the semiconductor structure.

[0010] The semiconductor structure provided in this embodiment of the invention includes a bonding pad and a metal grid formed in the same step, which helps to reduce the number of steps in forming the semiconductor structure, thereby improving the process efficiency of forming the semiconductor structure and thus shortening the production cycle time of the semiconductor structure; moreover, it also helps to reduce the process cost of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 6 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0013] Figures 12 to 13 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figure 14 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0015] Figure 15 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. Detailed Implementation

[0016] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one method for forming a semiconductor structure as an example. Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1 A substrate 10 is provided, wherein an interconnect layer structure 11 and an isolation structure 12 are formed in the substrate 10, the top of the isolation structure 12 is exposed in the substrate 10, and a first dielectric layer 13 is formed on the substrate 10.

[0018] Continue to refer to Figure 1 A first groove 21 is formed in the first dielectric layer 13, the first groove 21 exposing the top of the substrate 10.

[0019] refer to Figure 2 A grounding structure 26 is formed in the first groove 21, the grounding structure 26 also extends to cover a portion of the top of the first dielectric layer 13, and a metal grid 27 is formed on the first dielectric layer 13 on top of the isolation structure 12.

[0020] refer to Figure 3 This forms a second dielectric layer 14 covering the grounding structure 26 and the metal grid 27.

[0021] Continue to refer to Figure 3 A first sub-groove 22 is formed in the second dielectric layer 14, the first dielectric layer 13, and the substrate 10 of a certain thickness above the interconnect layer structure 11, and the first sub-groove 22 corresponds to the interconnect layer 11 structure.

[0022] refer to Figure 4 A third dielectric layer 15 is formed on the bottom and sidewall of the first sub-groove 22, and on the second dielectric layer 14 outside the first sub-groove 22. The third dielectric layer 15 on the sidewall of the first sub-groove 22 serves as a sidewall.

[0023] Continue to refer to Figure 4 The third dielectric layer 15 and the substrate 10 in a certain area at the bottom of the first sub-groove 22 are removed to form a second sub-groove 23 that communicates with the first sub-groove 22. The second sub-groove 23 exposes a certain top of the interconnect layer structure 11. The second sub-groove 23 and the first sub-groove 22 constitute the second groove 25.

[0024] refer to Figure 5 A solder pad 28 is formed in the second sub-groove 25 and at the bottom of the first sub-groove 22.

[0025] Research has shown that forming the metal grid 27 and the bonding pad 28 in different steps results in more steps in forming the semiconductor structure, which in turn can lead to poor process efficiency, longer production cycle time, and higher process cost.

[0026] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate in which an interconnect layer structure and an isolation structure are formed, the top of the isolation structure being exposed on the substrate, and a first dielectric layer being formed on the substrate; forming a first groove in the substrate and the first dielectric layer, the first groove exposing a portion of the top of the interconnect layer structure; and in the same step, forming a bonding pad in the first groove and forming a metal grid on the first dielectric layer on top of the isolation structure.

[0027] In the solution disclosed in the embodiments of the present invention, in the same step, a pad is formed in the first groove and a metal grid is formed on the first dielectric layer on top of the isolation structure. This helps to reduce the number of steps in forming the semiconductor structure, thereby improving the process efficiency of forming the semiconductor structure and thus shortening the production cycle time of the semiconductor structure. Moreover, it also helps to reduce the process cost of the semiconductor structure.

[0028] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figures 6 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0030] refer to Figure 6 A substrate 100 is provided, wherein an interconnect layer structure 110 and an isolation structure 120 are formed in the substrate 100, the top of the isolation structure 120 is exposed in the substrate 100, and a first dielectric layer 130 is formed on the substrate 100.

[0031] The substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0032] In this embodiment, in the step of providing the substrate 100, the substrate includes a logic substrate 101 and a pixel substrate 102 bonded to the logic substrate 101. An isolation structure 120 is formed in the pixel substrate 102, and the top of the isolation structure 120 is exposed in the pixel substrate 102. An interconnect layer structure 110 is formed in the logic substrate 101.

[0033] The logic substrate 101 is used to analyze and process the electrical signals provided by the pixel substrate 102. Specifically, a logic device (not shown) is formed within the logic substrate 101, and the logic device is used to analyze and process the electrical signals provided by the pixel substrate 102.

[0034] The interconnect layer structure 110 is used to bring out the electrical properties of logic devices or to realize electrical connections between logic devices.

[0035] The pixel substrate 102 is used to provide an operating platform for the formation of the photoelectric sensor.

[0036] Specifically, the pixel substrate 102 includes a substrate (not shown). Specifically, the substrate material may include one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0037] It should be noted that the pixel substrate 102 is a backside illumination (BSI) pixel wafer, and the side of the pixel substrate 102 facing away from the logic substrate 101 is the light-receiving surface.

[0038] It should also be noted that the pixel substrate 102 includes a lead area (not shown) and a photosensitive area (not shown). A pixel unit (not shown) is formed in the photosensitive area. The pixel unit is used to receive optical signals so as to convert the optical signals into electrical signals. The lead area is used to realize the electrical connection between the pixel unit or other device structure in the photosensitive area and the external circuit.

[0039] The isolation structure 120 is located between adjacent pixel units and is used to reduce optical crosstalk and electrical crosstalk between adjacent pixel units.

[0040] In this embodiment, the isolation structure 120 is a deep trench isolation (DTI) structure.

[0041] Specifically, depending on the type and performance requirements of the photoelectric sensor, the material of the isolation structure 120 includes one or two of dielectric materials and metallic materials. The metallic materials include one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride, and copper, while the dielectric materials include any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0042] The first dielectric layer 130 is used to isolate the substrate 100 from the subsequently formed film layers (e.g., metal grid, second dielectric layer, third dielectric layer, etc.) and to provide a flat surface for the formation of subsequent film layers.

[0043] In this embodiment, during the step of providing the substrate 100, the first dielectric layer 130 includes a first sub-dielectric layer 131 and a second sub-dielectric layer 132 located on the first sub-dielectric layer 131, wherein the material of the first sub-dielectric layer 131 includes a high-k dielectric material.

[0044] Here, high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the first sub-dielectric layer 131 includes any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0045] The material of the first sub-dielectric layer 131 includes a high-k dielectric material, which is beneficial for absorbing the charge on the surface of the pixel substrate 102, thereby helping to reduce the "white pixel" defect; moreover, the material of the first sub-dielectric layer 131 including a high-k dielectric material is also convenient for filtering photoelectrons, allowing light of a specific wavelength band to pass through the first sub-dielectric layer 131.

[0046] The second sub-dielectric layer 132 provides a flat surface for the subsequently formed film layer. Furthermore, the second sub-dielectric layer 132 also protects the top of the first sub-dielectric layer 131, reducing the probability of damage or contamination to the top of the first sub-dielectric layer 131 during subsequent processes. The second sub-dielectric layer 132 is an oxide layer. Specifically, the material of the second sub-dielectric layer 132 includes silicon oxide. In other embodiments, the material of the second sub-dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0047] refer to Figure 7 and in conjunction with references Figure 6 In this embodiment, before forming the first groove, the method further includes: forming a second groove 140 in the first dielectric layer 130, the second groove 140 exposing the substrate 100 (e.g., ...). Figure 6 As shown); a grounding structure 141 (Back Side Ground, BSGND) is formed in the second groove 140 (as shown). Figure 7 (As shown).

[0048] The grounding structure 141 is used to electrically connect to the substrate 100 to reduce dark current. Specifically, the grounding structure 141 is used to electrically connect to the pixel substrate 102.

[0049] It should be noted that during the formation of the second groove 140, a portion of the pixel substrate 102 is also removed to reduce the difficulty of exposing the substrate 100 by the second groove 140, thereby ensuring that the second groove 140 exposes the substrate 100 and ensuring that the grounding structure 141 is electrically connected to the substrate 100. Here, removing a portion of the pixel substrate 102 means removing a portion of the pixel substrate 102 that is also partially thick.

[0050] In this embodiment, if the grounding structure 141 is formed before the first groove is formed, the forming method further includes: forming a third dielectric layer 150 on the first dielectric layer 130 and the grounding structure 140 before forming the first sub-groove.

[0051] The third dielectric layer 150 is used to protect the top of the grounding structure 140.

[0052] Specifically, the third dielectric layer 150 is an oxide layer. Specifically, the material of the third dielectric layer 150 includes silicon oxide. In other embodiments, the material of the third dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0053] The thickness of the third dielectric layer 150 should not be too small or too large. If the thickness of the third dielectric layer 150 is too small, the thickness uniformity of the third dielectric layer 150 may be poor; if the thickness of the third dielectric layer 150 is too large, it may cause unnecessary material waste. Therefore, as an example, in the step of forming the third dielectric layer 150, the thickness of the third dielectric layer 150 is in the range of 1000 angstroms to 1600 angstroms.

[0054] refer to Figure 8 and in conjunction with references Figure 7 A first groove 160 is formed in the substrate 100 and the first dielectric layer 130 (e.g., Figure 8 As shown), the first recessed groove 160 exposes a portion of the top of the interconnect layer structure 110.

[0055] The first groove 160 is used to provide space for the subsequent formation of solder pads.

[0056] In this embodiment, the step of forming the first groove 160 includes: as follows Figure 7 As shown, a first sub-groove 161 is formed in the first dielectric layer 130 above the interconnect layer structure 110 and in a substrate 100 of a certain thickness, the first sub-groove 161 corresponding to the interconnect layer structure 110; as Figure 8 As shown, the base 100 of the first portion of the bottom region of the first sub-groove 161 is removed to form a second sub-groove 162 that communicates with the first sub-groove 161. The second sub-groove 162 exposes a portion of the top of the interconnect layer structure 110.

[0057] First, a first sub-groove 161 is formed in the first dielectric layer 130 above the interconnect layer structure 110 and in the substrate 100 of a certain thickness. Then, the substrate 100 in the first part of the bottom area of ​​the first sub-groove 161 is removed to form a second sub-groove 162 that communicates with the first sub-groove 161. This helps to reduce the aspect ratio of the first sub-groove 161 during the formation of the first sub-groove 161, thereby reducing the difficulty of forming the first groove 160. Moreover, it also helps to reduce the probability of damage to the top of the interconnect layer structure 110 during the formation of the first groove 160.

[0058] Specifically, a first sub-groove 161 is formed in the first dielectric layer 130, the pixel substrate 102, and the partial thickness logic substrate 101 above the interconnect layer structure 110.

[0059] Among them, the logic substrate 101 with partial thickness refers to the logic substrate 101 with a second partial thickness.

[0060] As an example, if the grounding structure 141 is formed before the first groove is formed, the forming method further includes forming a third dielectric layer 150 on the first dielectric layer 130 and the grounding structure 140 before forming the first sub-groove 161. Accordingly, in the step of forming the first sub-groove 161, the third dielectric layer 150 in the second portion region is also removed.

[0061] In this embodiment, as Figure 8 As shown, after the first sub-groove 161 is formed and before the second sub-groove 162 is formed, the method further includes: forming a second dielectric layer 170 on the bottom and sidewall of the first sub-groove 161 and on the first dielectric layer 130 on the outside of the first sub-groove 161, with the second dielectric layer 170 on the sidewall of the first sub-groove 161 serving as a sidewall.

[0062] The sidewall is used to protect the sidewall of the first sub-groove 161, reducing the probability of damage to the sidewall of the first sub-groove 161 during the subsequent formation of the solder pad. Specifically, the sidewall is used to reduce the probability of migration reaction between the material used to form the solder pad and the material of the sidewall of the first sub-groove 161.

[0063] Specifically, the second dielectric layer 170 is an oxide layer. More specifically, the material of the second dielectric layer 170 includes silicon oxide. In other embodiments, the material of the second dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0064] Accordingly, in this embodiment, during the step of forming the second sub-groove 162, the second dielectric layer 170 in the first portion region at the bottom of the first sub-groove 161 is also removed.

[0065] Accordingly, in this embodiment, during the step of forming the second dielectric layer 170, the second dielectric layer 170 is located on the grounding structure 141.

[0066] refer to Figures 9 to 11 In the same step, a solder pad 180 is formed in the first groove 160 (e.g., Figure 11 As shown), and a metal grid 181 is formed on the first dielectric layer 130 on top of the isolation structure 120 (as shown). Figure 11 As shown, this reduces the number of steps in forming a semiconductor structure, which in turn improves the process efficiency of forming the semiconductor structure, thereby shortening the production cycle time of the semiconductor structure; moreover, it also helps to reduce the process cost of the semiconductor structure.

[0067] The pads 180 are used for electrical connection with the interconnect layer structure 110 to bring out the electrical properties of the logic devices.

[0068] The metal grid 181 has a mesh structure. The position and shape of the metal grid 181 correspond to those of the isolation structure 120. The area enclosed by the metal grid 181 corresponds to each pixel unit, thereby preventing optical crosstalk between adjacent pixel units.

[0069] In this embodiment, the steps of forming the solder pad 180 and the metal grid 181 in the same step include: as follows Figure 9 As shown, a conformal metal material layer 182 is formed on the bottom and sidewalls of the first groove 160, and on the first dielectric layer 130 outside the first groove 160; as Figure 10 As shown, a patterned mask layer 190 is formed on the metal material layer 182. The mask layer 190 covers the bottom of the first groove 160 and the top of the isolation structure 120 of the metal material layer 182, and exposes the remaining areas of the metal material layer 182. Using the mask layer 190 as a mask, the remaining areas of the metal material layer 182 are removed. The remaining metal material layer 182 at the bottom of the first groove 160 serves as a solder pad 180, and the remaining metal material layer 182 at the top of the isolation structure 120 serves as a metal grid 181. Figure 11 As shown, after forming the solder pad 180 and the metal grid 181, the process further includes removing the mask layer 190.

[0070] After forming a conformal covering metal material layer 182 on the bottom and sidewalls of the first groove 160 and on the first dielectric layer 130 outside the first groove 160, a patterned mask layer 190 is first formed on the metal material layer 182. Then, using the mask layer 190 as a mask, the metal material layer 182 in the remaining areas except the bottom of the first groove 160 and the top of the isolation structure 120 is removed. This helps to reduce the difficulty of forming the solder pads 180 and the metal grid 181.

[0071] Specifically, the mask layer 190 includes photoresist. The step of forming the patterned mask layer 190 on the metal material layer 182 includes: forming a mask material layer (not shown) on the metal material layer 182; providing a photomask for patterning the mask material layer, the photomask having a photomask pattern, the projection of the photomask pattern onto the substrate 100 covering the bottom of the first groove 160 and the top of the isolation structure 120; performing a photolithography operation on the mask material layer using the photomask to remove the mask material layer in the remaining areas except for the bottom of the first groove 160 and the top of the isolation structure 120, so as to transfer the photomask pattern into the mask material layer, the remaining mask material layer serving as the mask layer 190, which helps to reduce the difficulty of forming the mask layer 190. Moreover, the mask layer 190 includes photoresist, which also helps to reduce the difficulty of removing the mask layer 190. Correspondingly, forming the bonding pad 181 and the metal grid 182 in the same step also helps to save the number of photomasks.

[0072] More specifically, the mask material layer can be a single-layer structure or a stacked structure.

[0073] It should be noted that the process for removing the remaining metal material layer 182 includes a dry etching process. Dry etching has anisotropic etching characteristics, thus offering high etching precision and better control over the cross-section, which is beneficial for improving the morphological and dimensional accuracy of the solder pads 180 and the metal grid 181.

[0074] Understandably, in the same step, the solder pads 180 and the metal grid 181 are formed by etching the metal material layer 182. Accordingly, the solder pads 180 and the metal grid 181 have the same height.

[0075] In this embodiment, during the step of forming the solder pad 180, the solder pad 180 is formed in the second sub-groove 162 and at the bottom of the first sub-groove 161, which helps to reduce the material required to form the solder pad 180.

[0076] Specifically, a second dielectric layer 170 is formed on the bottom and sidewalls of the first sub-groove 161, and on the first dielectric layer 130 outside the first sub-groove 161. Correspondingly, in the step of forming the solder pads 180 and the metal grid 181, the solder pads 180 are formed in the second sub-groove 162 and on the second dielectric layer 170 at the bottom of the first sub-groove 161, and the metal grid 181 is formed on the second dielectric layer 170 on top of the isolation structure 120.

[0077] More specifically, since a third dielectric layer 150 is formed on the first dielectric layer 130 before the second dielectric layer 170 is formed, correspondingly, in the step of forming the metal grid 181, the metal grid 181 is formed on the first dielectric layer 130, the third dielectric layer 150, and the second dielectric layer 170 on top of the isolation structure 120.

[0078] In this embodiment, the materials of the solder pad 180 and the metal grid 181 are metallic materials. These metallic materials typically have good electrical conductivity and are generally opaque.

[0079] As an example, the materials of the solder pad 180 and the metal grid 181 include aluminum.

[0080] Aluminum is an easily etchable material, which facilitates the patterning of the pads 180 and the metal grid 181.

[0081] Figures 12 to 13 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between the second embodiment and the foregoing embodiment will not be repeated here. The difference between the second embodiment and the foregoing embodiment is that, as... Figure 12 As shown, in the step of forming the second sub-groove 262, a second groove 240 is formed in the first dielectric layer 230 and the second dielectric layer 270 outside the first sub-groove 261, and the second groove 240 exposes the substrate 200; as Figure 13 As shown, in the step of forming the solder pad 280 and the metal grid 281, a grounding structure 241 is also formed in the second groove 240, the grounding structure 241 extending to cover a portion of the top of the second dielectric layer 270.

[0082] Forming the pad 280, metal grid 281, and grounding structure 241 in the same step helps to further reduce the number of steps in forming the semiconductor structure.

[0083] Specifically, the steps of forming the solder pad 280, the metal grid 281, and the grounding structure 241 in the same step include: forming a conformally covered metal material layer (not shown) on the bottom and sidewalls of the first groove 260 and on the first dielectric layer 230 outside the first groove 260; forming a patterned mask layer (not shown) on the metal material layer; and removing the metal material layer exposed by the mask layer using the mask layer as a mask to form the solder pad 280, the metal grid 281, and the grounding structure 241.

[0084] More specifically, the mask layer includes photoresist. It is understood that during the formation of the mask layer, a photomask with a photomask pattern is also provided, i.e., a photomask is used to form a mask layer for etching a metal material layer to form the bonding pad 280, the metal grid 281, and the grounding structure 241, thereby helping to further reduce the number of photomasks.

[0085] It should be noted that, since the solder pad 280, metal grid 281, and grounding structure 241 are formed in the same step, the first groove 260 can be directly formed in the substrate 100 and the first dielectric layer 230 after the first dielectric layer 230 is formed, which helps to further save process steps. Correspondingly, in the step of forming the second dielectric layer 270, the second dielectric layer 270 outside the first groove 260 is located on the first dielectric layer 230.

[0086] Accordingly, the present invention also provides a semiconductor structure. Figure 14 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0087] refer to Figure 14 In this embodiment, the semiconductor structure includes: a substrate 500 having a recess 560, wherein an interconnect layer structure 510 and an isolation structure 520 are formed in the substrate 500, and the top of the isolation structure 520 is exposed in the substrate 500; a first dielectric layer 530 located on the substrate 500; a bonding pad 580 located at the bottom of the recess 560 and electrically connected to the top of the interconnect layer structure 510; and a metal grid 581 located at the top of the isolation structure 520; wherein the bonding pad 580 and the metal grid 581 are formed in the same step.

[0088] The substrate 500 is used to provide a process platform for the formation of semiconductor structures.

[0089] The groove 560 is used as the first groove 560.

[0090] In this embodiment, the substrate 100 includes a logic substrate 501 and a pixel substrate 502 located on the logic substrate 501. An isolation structure 520 is formed in the pixel substrate 502, and the top of the isolation structure 520 is exposed in the pixel substrate 502. An interconnect layer structure 510 is formed in the logic substrate 501. The groove 560 is located in the pixel substrate 502 and a portion of the thickness of the logic substrate 501.

[0091] The logic substrate 501 is used to analyze and process the electrical signals provided by the pixel substrate 502. Specifically, a logic device (not shown) is formed within the logic substrate 501, and the logic device is used to analyze and process the electrical signals provided by the pixel substrate 502.

[0092] The interconnect layer structure 510 is used to bring out the electrical properties of logic devices or to realize electrical connections between logic devices.

[0093] The pixel substrate 502 is used to provide an operating platform for the formation of the photoelectric sensor.

[0094] Specifically, the pixel substrate 502 includes a substrate (not shown). Specifically, the substrate material may include one or more of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0095] It should be noted that the pixel substrate 502 is a back-illuminated pixel wafer, and the side of the pixel substrate 502 facing away from the logic substrate 501 is the light-receiving surface.

[0096] It should also be noted that the pixel substrate 502 includes a lead area (not shown) and a photosensitive area (not shown). A pixel unit (not shown) is formed in the photosensitive area. The pixel unit is used to receive optical signals so as to convert the optical signals into electrical signals. The lead area is used to realize the electrical connection between the pixel unit or other device structure in the photosensitive area and the external circuit.

[0097] The isolation structure 520 is located between adjacent pixel units and is used to reduce optical and electrical crosstalk between adjacent pixel units.

[0098] In this embodiment, the isolation structure 520 is a deep trench isolation structure.

[0099] Specifically, depending on the type and performance requirements of the photoelectric sensor, the material of the isolation structure 520 includes one or two of dielectric materials and metallic materials. The metallic materials include one or more of tungsten, aluminum, titanium, titanium nitride, tantalum nitride, and copper, while the dielectric materials include any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0100] The first dielectric layer 530 is used to isolate the substrate 500 from other film layers (e.g., metal grid 581, second dielectric layer, third dielectric layer, etc.) and to provide a flat surface for the formation of other film layers.

[0101] In this embodiment, the first dielectric layer 530 includes a first sub-dielectric layer 531 and a second sub-dielectric layer 532 located on the first sub-dielectric layer 531, and the material of the first dielectric layer 531 includes a high-k dielectric material.

[0102] Here, high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the first sub-dielectric layer 531 includes any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, strontium oxide, lanthanum oxide, and barium oxide.

[0103] The material of the first sub-dielectric layer 531 includes a high-k dielectric material, which is beneficial for absorbing the charge on the surface of the pixel substrate 502, thereby helping to reduce the "white pixel" defect; moreover, the high-k dielectric material of the first sub-dielectric layer 531 also facilitates the filtering of photoelectrons, allowing light of a specific wavelength band to pass through the first sub-dielectric layer 531.

[0104] The second sub-dielectric layer 532 provides a flat surface for the formation of other film layers. Furthermore, the second sub-dielectric layer 532 also protects the top of the first sub-dielectric layer 531, reducing the probability of damage or contamination to the top of the first sub-dielectric layer 531 during the process. The second sub-dielectric layer 532 is an oxide layer. Specifically, the material of the second sub-dielectric layer 532 includes silicon oxide. In other embodiments, the material of the second sub-dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0105] The first groove 560 is used to provide space for forming the solder pad 580.

[0106] In this embodiment, the groove 560 includes a first sub-groove 561 and a second sub-groove (not shown) located at the bottom of the first sub-groove 561, and the second sub-groove communicates with the first sub-groove 561.

[0107] Typically, a first sub-groove 561 is first formed in the first dielectric layer 530 above the interconnect layer structure 510 and in a substrate 500 of a certain thickness. The first sub-groove 561 corresponds to the interconnect layer structure 510. Then, a first portion of the substrate 500 at the bottom of the first sub-groove 561 is removed to form a second sub-groove that communicates with the first sub-groove 561. The second sub-groove exposes part of the top of the interconnect layer structure 510. This helps to reduce the aspect ratio of the first sub-groove 561 during its formation, thereby reducing the difficulty of forming the first sub-groove 560. Furthermore, it also helps to reduce the probability of damage to the top of the interconnect layer structure 510 during its formation.

[0108] Specifically, a first sub-groove 561 is formed in the first dielectric layer 530, the pixel substrate 502, and the substrate 500 of a certain thickness above the interconnect layer structure 510.

[0109] In this embodiment, the semiconductor structure further includes: a second dielectric layer 570 located on the sidewall of the first sub-groove 561 and on the first dielectric layer 530 outside the first sub-groove 561, wherein the second dielectric layer 570 located on the sidewall of the first sub-groove 561 serves as a sidewall.

[0110] The sidewall is used to protect the sidewall of the first sub-groove 561 and reduce the probability that the sidewall of the first sub-groove 561 will be damaged during the formation of the solder pad 580. Specifically, the sidewall is used to reduce the probability that the material used to form the solder pad 580 will migrate and react with the material of the sidewall of the first sub-groove 561.

[0111] Specifically, the second dielectric layer 570 is an oxide layer. More specifically, the material of the second dielectric layer 570 includes silicon oxide. In other embodiments, the material of the second dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0112] In this embodiment, the semiconductor structure further includes: a ground structure 541 located in the first dielectric layer 530 outside the groove 560 and electrically connected to the substrate 500, and the second dielectric layer 570 covering the ground structure 541.

[0113] The grounding structure 541 is used to electrically connect to the substrate 500 to reduce dark current. Specifically, the grounding structure 541 is used to electrically connect to the pixel substrate 502.

[0114] It should be noted that the grounding structure 541 is also located in the pixel substrate 502 of a certain thickness to ensure that the grounding structure 541 is electrically connected to the substrate 500.

[0115] In this embodiment, when the grounding structure 541 is located only in the first dielectric layer 530 outside the groove 560 and is electrically connected to the substrate 500, the semiconductor structure further includes: a third dielectric layer 550 located on the first dielectric layer 530 and the grounding structure 541; and a second dielectric layer 570 covering the third dielectric layer 550.

[0116] The third dielectric layer 550 is used to protect the top of the grounding structure 541.

[0117] Specifically, the third dielectric layer 550 is an oxide layer. Specifically, the material of the third dielectric layer 150 includes silicon oxide. In other embodiments, the material of the third dielectric layer may also include other suitable oxides, such as silicon oxynitride.

[0118] The thickness of the third dielectric layer 550 should not be too small or too large. If the thickness of the third dielectric layer 550 is too small, it is easy to have poor thickness uniformity; if the thickness of the third dielectric layer 550 is too large, it is easy to cause unnecessary material waste. Therefore, as an example, the thickness range of the third dielectric layer 550 is 1000 angstroms to 1600 angstroms.

[0119] The pad 580 is used for electrical connection with the interconnect layer structure 510 to bring out the electrical properties of the logic device.

[0120] The metal grid 581 has a mesh structure. The position and shape of the metal grid 581 correspond to those of the isolation structure 520. The area enclosed by the metal grid 581 corresponds to each pixel unit, thereby preventing optical crosstalk between adjacent pixel units.

[0121] In this embodiment, the materials of the solder pad 580 and the metal grid 581 are metallic materials. These metallic materials typically have good electrical conductivity and are generally opaque.

[0122] As an example, the materials of the solder pad 580 and the metal grid 581 include aluminum.

[0123] Aluminum is an easily etchable material, which facilitates the patterning of the pads 580 and the metal grid 581.

[0124] In this embodiment, the solder pad 580 is located in the second sub-groove and at the bottom of the first sub-groove 561, which helps to reduce the material required to form the solder pad 580.

[0125] Since the semiconductor structure also includes a second dielectric layer 570, accordingly, in this embodiment, the bonding pad 580 is located in the second sub-groove and on the second dielectric layer 570 at the bottom of the first sub-groove 561; the metal grid 581 is located on the second dielectric layer 570 at the top of the isolation structure 520.

[0126] Furthermore, the semiconductor structure also includes a third dielectric layer 550. Accordingly, in this embodiment, the metal grid 581 is located on the first dielectric layer 530, the third dielectric layer 550, and the second dielectric layer 570 on top of the isolation structure 520.

[0127] Typically, the steps of forming the solder pads 580 and the metal grid 581 in the same step include: forming a conformal covering metal material layer (not shown) on the bottom and sidewalls of the first groove 560 and on the first dielectric layer 530 outside the first groove 560; forming a patterned mask layer (not shown) on the metal material layer, the mask layer covering the metal material layer at the bottom of the first groove 560 and the top of the isolation structure 520, and exposing the remaining area of ​​the metal material layer; using the mask layer as a mask, removing the remaining area of ​​the metal material layer, the remaining metal material layer at the bottom of the first groove 560 serving as the solder pads 580, and the remaining metal material layer at the top of the isolation structure 520 serving as the metal grid 581. That is, the solder pads 580 and the metal grid 581 are formed by etching the same metal material layer, and correspondingly, the heights of the solder pads 580 and the metal grid 581 are equal.

[0128] Figure 15 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between the second embodiment and the foregoing embodiment will not be repeated here. The difference between the second embodiment and the foregoing embodiment is that the semiconductor structure further includes a grounding structure 641, located in the first dielectric layer 630 and the second dielectric layer 670 outside the groove 660. The grounding structure 641 also extends to cover a portion of the top of the second dielectric layer 670, and the grounding structure 641 is electrically connected to the substrate 600.

[0129] The grounding structure 641 is located in the first dielectric layer 630 and the second dielectric layer 670 outside the groove 660, which facilitates the formation of the pad 680, the metal grid 681 and the grounding structure 641 in the same step, and helps to further reduce the steps of forming the semiconductor structure.

[0130] It should be noted that since the solder pad 680, metal grid 681, and grounding structure 641 are formed in the same step, the groove 660 can be directly formed in the substrate 600 and the first dielectric layer 630 after the first dielectric layer 630 is formed, which helps to further save process steps. Correspondingly, the second dielectric layer 670 outside the groove 660 is located on the first dielectric layer 630.

[0131] It should also be noted that the semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0132] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, in which an interconnection layer structure and an isolation structure are formed, the substrate exposing a top of the isolation structure, a first dielectric layer being formed on the substrate; forming a first recess in the substrate and the first dielectric layer, the first recess exposing a part of a top of the interconnection layer structure; in the same step, forming a pad in the first recess, and forming a metal grid on the first dielectric layer on the top of the isolation structure; wherein the step of forming the first recess comprises: forming a first sub-recess in the first dielectric layer above the interconnection layer structure, and a part of the thickness of the substrate, the first sub-recess corresponding to the interconnection layer structure; removing the substrate in a first partial area of a bottom of the first sub-recess, forming a second sub-recess penetrating the first sub-recess, the second sub-recess exposing a part of a top of the interconnection layer structure; after forming the first sub-recess and before forming the second sub-recess, the method further comprises: forming a second dielectric layer on the bottom and sidewall of the first sub-recess, and on the first dielectric layer outside the first sub-recess, the second dielectric layer on the sidewall of the first sub-recess serving as a sidewall; in the step of forming the second sub-recess, a second recess is formed in the first dielectric layer and the second dielectric layer outside the first sub-recess, the second recess exposing the substrate; in the step of forming the pad and the metal grid, a grounding structure is also formed in the second recess, the grounding structure also extending to cover a part of a top of the second dielectric layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the first recess further comprises: in the step of forming the pad, the pad is formed in the second sub-recess, and on the bottom of the first sub-recess.

3. The method of claim 2, wherein in the step of forming the second sub-recess, the second dielectric layer in the first partial area of the bottom of the first sub-recess is also removed; in the step of forming the pad and the metal grid, the pad is formed on the second dielectric layer in the second sub-recess, and on the bottom of the first sub-recess, and the metal grid is formed on the second dielectric layer on the top of the isolation structure.

4. The method of forming a semiconductor structure of claim 1, wherein, In the same step, the step of forming the pad and the metal grid comprises: forming a conformal covering metal material layer on the bottom and sidewall of the first recess, and on the first dielectric layer outside the first recess; forming a patterned mask layer on the metal material layer, the mask layer covering the metal material layer on the bottom of the first recess and on the top of the isolation structure, and exposing the metal material layer in the remaining area; using the mask layer as a mask, removing the metal material layer in the remaining area, the remaining metal material layer on the bottom of the first recess serving as the pad, and the remaining metal material layer on the top of the isolation structure serving as the metal grid; after forming the pad and the metal grid, the method further comprises: removing the mask layer.

5. The method of forming a semiconductor structure of claim 4, wherein, The mask layer comprises photoresist, and the step of forming the patterned mask layer on the metal material layer comprises: forming a mask material layer on the metal material layer; A photo mask is provided for patterning the mask material layer, the photo mask has a photo mask pattern, a projection of the photo mask pattern on the substrate covers the bottom of the first recess and the top of the isolation structure; A photo etching operation is performed on the mask material layer by using the photo mask, the mask material layer is removed from the remaining areas except the bottom of the first recess and the top of the isolation structure, so as to transfer the photo mask pattern to the mask material layer, and the remaining mask material layer is used as a mask layer.

6. The method of forming a semiconductor structure of claim 4, wherein, The process of removing the metal material layer from the remaining areas includes a dry etching process.

7. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer located on the first sub-dielectric layer, and a material of the first sub-dielectric layer includes a high-k dielectric material.

8. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the substrate includes a logic substrate and a pixel substrate bonded on the logic substrate, the pixel substrate is formed with an isolation structure, the pixel substrate exposes a top of the isolation structure, and the logic substrate is formed with an interconnection layer structure.

9. A semiconductor structure, characterized by Comprise: A substrate with a recess, the substrate is formed with an interconnection layer structure and an isolation structure, and the substrate exposes a top of the isolation structure; A first dielectric layer located on the substrate; A pad located at the bottom of the recess and electrically connected to a top of the interconnection layer structure; A metal grid located on the top of the isolation structure; The recess includes a first sub-recess and a second sub-recess located at the bottom of the first sub-recess, and the second sub-recess and the first sub-recess are mutually penetrable; The semiconductor structure further comprises: a second dielectric layer located on the sidewall of the first sub-recess and the first dielectric layer outside the first sub-recess, wherein the second dielectric layer located on the sidewall of the first sub-recess is used as a sidewall; The semiconductor structure further comprises: a grounding structure located in the first dielectric layer and the second dielectric layer outside the recess, the grounding structure further extends to cover part of the top of the second dielectric layer, and the grounding structure is electrically connected to the substrate; The grounding structure is formed in the same step as the pad and the metal grid.

10. The semiconductor structure of claim 9, wherein The pad is located in the second sub-recess and at the bottom of the first sub-recess.

11. The semiconductor structure of claim 10, wherein The pad is located in the second sub-recess and on the second dielectric layer at the bottom of the first sub-recess; The metal grid is located on the second dielectric layer on the top of the isolation structure.

12. The semiconductor structure of claim 9, wherein, The materials of the pad and the metal grid include aluminum.

13. The semiconductor structure of claim 9, wherein, The first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer located on the first sub-dielectric layer, and a material of the first sub-dielectric layer includes a high-k dielectric material.

14. The semiconductor structure of claim 9, wherein, The substrate includes a logic substrate and a pixel substrate located on the logic substrate, the pixel substrate is formed with an isolation structure, the pixel substrate exposes a top of the isolation structure, the logic substrate is formed with an interconnection layer structure, and the recess is located in the pixel substrate and part of the thickness of the logic substrate.

15. The semiconductor structure of claim 9, wherein, The height of the solder pads and the metal grid are equal.

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