Electronic device

Abstract

There is provided an electronic device having a second area and a first area surrounded by the second area in a plan view, and including a display module defining a module aperture, a window, and an electronic module, a pixel in the second region; a data line connected to the pixel; and a dam pattern in the first region and surrounding the module hole in a plan view, the dam pattern includes a first pattern over the base layer, a lower layer over the first pattern, a second pattern over the lower layer and including the same material as the data line, and an upper layer over the second pattern and defining an opening exposing a portion of the second pattern; the window is arranged above the display module; the electronic module is under the display module, overlaps the first area, and overlaps the module hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0127371, filed on September 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] In this context, the present disclosure relates to electronic devices with improved quality. Background Art

[0004] The electronic device is activated according to the electrical signal. The electronic device may include a device composed of various electronic components such as a display panel configured to display an image and an input sensor configured to sense an external input. The electronic components may be electrically connected to each other through signal lines that are arranged differently. Summary of the invention

[0005] The present disclosure provides electronic devices with improved quality.

[0006] One or more embodiments of the present disclosure provide an electronic device having a second area and a first area surrounded by the second area in a plan view, and including a display module, a window, and an electronic module, wherein the display module defines a module hole and includes a base layer, pixels in the second area, data lines connected to the pixels, and a dam pattern in the first area and surrounding the module hole in the plan view, the dam pattern including a first pattern above the base layer, a lower layer above the first pattern, a second pattern above the lower layer and including the same material as the data line, and an upper layer above the second pattern and defining an opening, the opening exposing a portion of the second pattern; the window is above the display module; the electronic module is below the display module, overlapping with the first area, and overlapping with the module hole.

[0007] A thickness of the upper layer may be smaller than a thickness of the lower layer, wherein at least one of the opposite sides of the second pattern protrudes between the lower layer and the upper layer.

[0008] The display module may further include an encapsulation layer covering the pixels and including: a first inorganic encapsulation layer; a second inorganic encapsulation layer over the first inorganic encapsulation layer; and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0009] The first inorganic encapsulation layer may cover side surfaces of the lower layer, portions of the second pattern protruding between the lower layer and the upper layer, and side surfaces and an upper surface of the upper layer.

[0010] The organic encapsulating layer may have a boundary defined by any one of the dam patterns in the first region.

[0011] The lower layer may define a contact hole exposing at least a portion of the first pattern, wherein the second pattern is in the contact hole and contacts the first pattern.

[0012] The pixel may include: a transistor; and a light emitting element including a first electrode connected to the transistor, a second electrode above the first electrode, and a common layer between the first electrode and the second electrode.

[0013] The electronic device may further include a first floating pattern between the dam patterns adjacent to each other, including the same material as the common layer, and disconnected from the common layer.

[0014] The electronic device may further include a second floating pattern over the upper layer, disconnected from the first floating pattern and the common layer, and including the same material as the common layer.

[0015] Lower layers included in the dam pattern spaced apart from each other with the first floating pattern interposed therebetween may be connected to each other, and the first floating pattern may be disposed on the connected lower layers.

[0016] The electronic device may further include a barrier pattern between the dam patterns and separating the first floating patterns.

[0017] The blocking pattern may include: a first layer; a second layer over the first layer and including a material different from that of the first layer; and a third layer over the second layer and including the material of the first layer, wherein the first layer and the third layer protrude further than the second layer in a direction toward the dam pattern.

[0018] The blocking pattern may be provided in plurality, the blocking patterns being spaced apart from each other and surrounding the module hole.

[0019] The blocking pattern may be over a lower layer of the connection of the dam pattern spaced apart from each other with the first floating pattern therebetween.

[0020] Each of the second pattern and the data line may include a first layer including titanium, a second layer including aluminum over the first layer, and a third layer including titanium over the second layer.

[0021] At least one of opposite sides of the second pattern may protrude between the lower layer and the upper layer, wherein the first layer and the third layer protrude further than the second layer in a direction toward the dam pattern.

[0022] The second pattern may define a hole overlapping the opening, the hole having a groove corresponding to the removed portion of the second layer, and having a pattern opening passing through the third layer and overlapping the groove.

[0023] The hole may expose a lower surface of the third layer adjacent to the pattern opening.

[0024] The pixel may include a light emitting element connected to a transistor including an active pattern and a gate overlapping the active pattern, wherein one of the dam patterns further includes a dummy pattern, the dummy pattern is below and overlaps the first pattern and includes the same material as the gate or the active pattern.

[0025] The display module may include: a display panel including a base layer and pixels; an input sensor over the display panel for sensing an external input; an organic cover layer over the input sensor; and an anti-reflection layer between the organic cover layer and the window. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain aspects of the present disclosure. In the drawings:

[0027] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0028] Figure 2 is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0029] Figure 3 is a block diagram of an electronic device according to one or more embodiments of the present disclosure;

[0030] Figure 4 It is shown Figure 2 An enlarged view of region XX';

[0031] Figure 5 It is along Figure 2 A cross-sectional view taken along line II';

[0032] Fig. 6A It is along Figure 2 A cross-sectional view taken along line II-II';

[0033] Figure 6B yes Fig. 6A An enlarged view of one of the dam patterns shown in;

[0034] Figures 7 to 14 is a cross-sectional view showing a portion of a first region of a display module according to one or more embodiments of the present disclosure; and

[0035] FIG. 15A to FIG. 15H is a cross-sectional view illustrating a manufacturing method for forming a dam pattern according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] Aspects of some embodiments of the present disclosure and methods for implementing them can be more easily understood by reference to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for a complete understanding of aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, in all drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0037] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The "may", "may" or "may not" used in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various close combinations and drives are possible technically. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0038] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or for descriptive purposes. In addition, cross-hatching and / or shading are generally used in the drawings to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0039] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. In this way, deviations from the illustrated shapes, for example, due to manufacturing techniques and / or tolerances, are expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shapes, for example, caused by manufacturing.

[0040] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0041] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper", "upper side" and the like may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can cover both upper and lower orientations. The device can have another orientation (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this indicates that the first portion is arranged at the upper or lower side of the second portion, without being limited to its upper side based on the direction of gravity.

[0042] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section obtained by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and means that the second object can be above or below the first object, or on one side of the first object. In addition, the term "overlap" can include stacking, facing or facing, extending throughout..., covering or partially covering, or any other suitable term as will be understood and appreciated by a person of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from..." or "set beside..." or "deviation from..." and any other suitable equivalents as will be understood and appreciated by a person of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is inserted between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, but still facing each other.

[0043] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be formed directly on, or directly on, or directly connected to, or directly coupled to, another element, layer, region, or component, or indirectly formed on, or indirectly on, or indirectly connected to, or indirectly coupled to, another element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. Additionally, this may generally mean direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, etc. In describing embodiments, unless explicitly described as being directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or directly on another component without intermediate components.

[0044] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" another part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0045] For the purposes of this disclosure, when following an element of a list, expressions such as "at least one of," or "any one of," or "one or more of," modify the elements of the entire list rather than modifying individual elements of the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z," may be interpreted as only X, or only Y, or only Z, or any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, when preceding or following an element of a list, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases modify the elements of the entire list rather than modifying individual elements of the list.

[0046] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, but are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first part described below can be referred to as the second element, second component, second area, second layer or second part. Describing an element as a "first" element may not require or may not imply the presence of a second element or other elements. The terms "first", "second", etc. may also be used in this article to distinguish between different categories or different groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0047] In the example, the first direction DR1, the second direction DR2 and / or the third direction DR3 are not limited to the three axes of the rectangular coordinate system (such as the x-axis, the y-axis and the z-axis) and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2 and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0048] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the features, wholes, steps, operations, elements and / or parts described, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or combinations thereof.

[0049] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the value and means within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, "may" used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure".

[0050] In some embodiments, known structures and devices can be described in the accompanying drawings for one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of various embodiments. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and optionally, these blocks, units and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware, or dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules can be physically divided into two or more interactive discrete blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0052] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0053] Figure 2 is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0054] Figure 3 is a block diagram of an electronic device according to one or more embodiments of the present disclosure. Figure 4 It is shown Figure 2 Magnified view of region XX'.

[0055] refer to Figure 1 and Figure 2, the electronic device 1000 may display an image IM in a third direction DR3 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The display surface FS on which the image IM is displayed may correspond to a front surface of the electronic device 1000.

[0056] The display surface FS of the electronic device 1000 may be provided from the front surface FS of the window 300. Therefore, the display surface FS of the electronic device 1000 and the front surface FS of the window 300 may use the same reference numerals. The image IM displayed on the display surface FS may include a still image as well as a dynamic image. Figure 1 A clock and a plurality of icons are shown as examples of the image IM.

[0057] The front surface (or upper surface) and the rear surface (or lower surface) of each member are defined based on the direction along which the image IM is displayed. The front surface and the rear surface are opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be parallel to the third direction DR3. The spacing distance between the front surface and the rear surface of the electronic device 1000 (or its corresponding member) in the third direction DR3 can correspond to the thickness of the electronic device 1000 (or the member) in the third direction DR3.

[0058] The electronic device 1000 according to one or more embodiments of the present disclosure can sense the user's input TC applied from the outside. The user's input TC includes various types of external inputs, such as a part of the user's body, light, heat, or pressure. The user's input TC is shown as the user's hand applied to the front surface FS of the window 300.

[0059] However, this is shown as an example, and as described above, the user's input TC may be provided in various forms, and the electronic device 1000 may also sense the user's input TC applied to its side surface or rear surface, and the present disclosure is not limited thereto.

[0060] The electronic device 1000 according to one or more embodiments of the present disclosure may include a first area A1 overlapping the light transmission area TA. The first area A1 may be defined as an area overlapping the electronic module 400 located below the display module 100, which will be described later. The first area A1 may include a module hole MH (see Figure 2 ), the module hole MH is defined to pass through the display module 100 and overlap with the electronic module 400.

[0061] The electronic device 1000 may receive an external signal suitable for the electronic module 400 through the first area A1, or may provide a signal output from the electronic module 400 to the outside. According to the present disclosure, by disposing the first area A1 inside the light transmission area TA, the area of ​​the bezel area BZA may be reduced.

[0062] refer to Figure 2 , the electronic device 1000 may include a display module 100, a housing 200, a window 300, and an electronic module 400. The window 300 and the housing 200 are coupled to each other to form an appearance of the electronic device 1000.

[0063] The window 300 may include an insulating plate. For example, the window 300 may be made of glass, plastic, or a combination thereof. As described above, the front surface FS of the window 300 defines the front surface FS of the electronic device 1000. The window 300 may include a light transmission area TA and a frame area BZA adjacent to the light transmission area TA. The light transmission area TA may be an optically transparent area. For example, the light transmission area TA may have a visible light transmittance of about 90% or more. The frame area BZA may have a relatively low light transmittance as compared to the light transmission area TA. The frame area BZA defines the shape of the light transmission area TA.

[0064] The bezel area BZA may have a color (eg, a predetermined color). The bezel area BZA may be defined by a transparent substrate defining the light transmission area TA and a bezel layer provided separately, or by an ink layer formed by inserting into or coating the transparent substrate.

[0065] The display module 100 may include an electronic panel EP and a driving circuit IC. The electronic panel EP may display an image IM and may sense a user's input TC. The front surface IS of the electronic panel EP includes an active area AA and a peripheral area NAA. The active area AA may be activated according to an electrical signal.

[0066] The active area AA may be an area in which the image IM is displayed, and may also be an area in which the user's input TC is sensed. The active area AA may be an area in which a plurality of pixels PX are positioned.

[0067] According to the present disclosure, the active area AA may include a first area A1 and a second area A2 surrounding at least a portion of the first area A1 (e.g., surrounding at least a portion of the first area A1 in a plan view). The pixel PX may be located in the second area A2 of the active area AA. A module hole MH that penetrates the electronic panel EP from the front surface IS of the electronic panel EP to its rear surface may be defined in the first area A1. The electronic module 400 located below the electronic panel EP may overlap with the module hole MH defined in the first area A1.

[0068] The active area AA overlaps with at least a portion of the light transmission area TA. For example, the light transmission area TA overlaps with the entire surface of the active area AA or at least a portion of the active area AA. Therefore, the user may view the image IM through the light transmission area T, or the user's input TC may be provided through the light transmission area TA. However, this is shown as an example, and in the active area AA, the area in which the image IM is displayed and the area in which the user's input TC is sensed may be separated from each other, and the present disclosure is not limited thereto.

[0069] The peripheral area NAA may be covered by the border area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA (e.g., surround the active area AA in a plan view). The peripheral area NAA may be an area in which the image IM is not displayed. A driving circuit, a driving line, etc. for driving the active area AA may be located in the peripheral area NAA.

[0070] In one or more embodiments, a portion of the peripheral area NAA of the electronic panel EP may be bent. For example, the electronic panel EP may include a flat portion FN and a bent portion BN. The flat portion FN may be assembled in a state where the flat portion FN is substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. The active area AA may be disposed in the flat portion FN.

[0071] The bent portion BN may extend from the flat portion FN and may be bent along a virtual bending axis. The bent portion BN may be assembled by bending it to face the rear surface of the flat portion FN. If the bent portion BN is assembled, the bent portion BN overlaps the flat portion FN on a plane, and therefore, the bezel area BZA of the electronic device 1000 may be reduced. Meanwhile, this is shown as an example, and in the electronic panel EP, the bent portion BN may be omitted.

[0072] The driving circuit IC may be mounted on the bent portion BN. One or more embodiments in which the driving circuit IC is provided in the form of a chip are shown, but the present disclosure is not limited thereto, and the driving circuit IC may be provided on a separate circuit board and electrically connected to the electronic panel EP through a flexible film or the like.

[0073] The driving circuit IC is electrically connected to the components in the active area AA and sends electrical signals to the components in the active area AA. For example, the driving circuit IC may include a data driving circuit and may provide data signals to the pixels PX located in the active area AA. Alternatively, the driving circuit IC may include a touch driving circuit and may be electrically connected to an input sensor located in the active area AA. At the same time, this is described as an example, and the driving circuit IC may be designed to include various circuits in addition to the above-mentioned circuits, or to provide various electrical signals to the active area AA, and the present disclosure is not limited thereto.

[0074] The electronic device 1000 according to one or more embodiments of the present disclosure may further include a main circuit board electrically connected to the electronic panel EP and the driving circuit IC. The main circuit board may include various driving circuits for driving the electronic panel EP, a connector for a power supply, etc. The main circuit board may be a rigid printed circuit board (PCB), but is not limited thereto, and may also be a flexible circuit board, and the present disclosure is not limited thereto.

[0075] The electronic module 400 is located under the display module 100. The electronic module 400 may overlap with a module hole MH defined in the electronic panel EP, and may receive an external input transmitted through the module hole MH or may output a signal through the module hole MH.

[0076] Figure 2 A single module hole MH having a circular shape is shown as an example, but the present disclosure is not limited to this, and the number of (multiple) module holes MH in the electronic panel EP can be limited to correspond to the number of (multiple) electronic modules 400 located below the electronic panel EP, and the module hole MH can have any one of a polygonal shape and an elliptical shape, and is not limited to this.

[0077] According to the present disclosure, by providing the first area A1 having a relatively high transmittance inside the active area AA, the electronic module 400 may overlap with the active area AA. Therefore, the size of the bezel area BZA may be reduced.

[0078] The housing 200 may be coupled to the window 300 to provide an internal space (eg, a predetermined internal space), and may define an appearance of the electronic device 1000. Components of the electronic device 1000, such as the display module 100 and the electronic module 400, may be accommodated in the internal space.

[0079] The housing 200 may include a material having relatively high rigidity. For example, the housing 200 may include a plurality of frames and / or plates made of glass, plastic, or metal or a combination thereof. The housing 200 may stably protect the components of the electronic device 1000 housed in the internal space from external impacts.

[0080] refer to Figure 3 , the electronic device 1000 may include a display module 100, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 100, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0081] Figure 3 The display panel DP and the input sensor ISL of the display module 100 are shown. The display panel DP may be configured to generate an image IM. The image IM generated by the display panel DP is displayed on the display surface FS through the light transmission area TA and is viewed from the outside by the user. The input sensor ISL senses the user's input TC applied from the outside. As described above, the input sensor ISL may sense the user's input TC provided to the window 300.

[0082] The power module PM provides power suitable for the overall operation of the electronic device 1000. The power module PM may include a conventional battery module.

[0083] The first electronic module EM1 and the second electronic module EM2 include various functional modules for operating the electronic device 1000. In one or more embodiments, the first electronic module EM1 may be directly mounted on a motherboard electrically connected to the electronic panel EP, or may be mounted on a separate board and electrically connected to the motherboard through a connector or the like.

[0084] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of the modules may not be mounted on a motherboard but may be electrically connected to the motherboard through a flexible printed circuit board.

[0085] The control module CM controls the overall operation of the electronic device 1000. The control module CM may be a microprocessor. For example, the control module CM activates or deactivates the display module 100. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on a touch signal received from the electronic panel EP.

[0086] The wireless communication module TM can send / receive wireless signals to / from another terminal by using a Bluetooth or Wi-Fi line. The wireless communication module TM can send / receive voice signals by using a general communication line. The wireless communication module TM includes a transmitter TM1 and a receiver TM2, wherein the transmitter TM1 modulates the signal to be sent and sends the modulated signal, and the receiver TM2 demodulates the received signal.

[0087] The image input module IIM processes the image signal and converts the image signal into image data displayable on the electronic panel EP. The audio input module AIM receives an external audio signal through a microphone in a recording mode, a voice recognition mode, etc. and converts the external audio signal into electrical voice data.

[0088] The external interface IF is used as an interface for connecting to an external charger, a wired / wireless data port, a card (eg, a memory card or a SIM / UIM card) slot, etc.

[0089] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM and a camera module CMM. In one or more embodiments, the above components may be directly mounted on a motherboard, or may be mounted on a separate board and electrically connected to the electronic panel EP via a connector, or may be electrically connected to the first electronic module EM1.

[0090] The audio output module AOM converts audio data received from the wireless communication module TM or audio data stored in the memory MM and outputs the audio data to the outside.

[0091] The light emitting module LM generates and outputs light. The light emitting module LM may output infrared rays. The light emitting module LM may include an LED element. The light receiving module LRM may detect infrared rays. When infrared rays of a corresponding level (e.g., a predetermined level) or higher are detected, the light receiving module LRM may be activated. The light receiving module LRM may include a CMOS sensor. After the infrared light generated in the light emitting module LM is output, the infrared light is reflected by an external object (e.g., a finger or face of a user), and the reflected infrared light may be incident on the light receiving module LRM. The camera module CMM captures external images.

[0092] The electronic module 400 according to one or more embodiments of the present disclosure may include at least any one of the components of the second electronic module EM2. For example, the electronic module 400 may include at least one of a camera, a speaker, a light sensor, and a thermal sensor. The electronic module 400 may detect an external object received through the first area A1, or may provide a sound signal such as a voice to the outside through the first area A1. In addition, the electronic module 400 may include a plurality of components and is not particularly limited. In one or more embodiments, the electronic module 400 may be attached to the electronic panel EP by a separate adhesive.

[0093] Figure 4 The display panel DP (see FIG. Figure 3 ) a portion XX' of the active area AA adjacent to the module hole MH.

[0094] refer to Figure 4 , most of the pixels PX included in the display panel DP may be located in the second area A2, and some of the pixels PX may be located in the second area A2 along a boundary between the first area A1 and the second area A2 and may be spaced apart from the first area A1.

[0095] The module hole MH may be defined in the active area AA. Therefore, at least some of the pixels PX may be adjacent to the module hole MH, and at least some of the pixels PX may be spaced apart from each other with the module hole MH interposed therebetween. The electronic module 400 may overlap the module hole MH.

[0096] At least one dam pattern DMP may be located in the first area A1 of the display panel DP. Figure 2 ) can block the path through which moisture and / or oxygen flows from the module hole MH to the pixel PX by using the dam pattern DMP. In the dam pattern DMP according to the present disclosure, on a plane, the upper layer IL2 (see Figure 6B ) may expose the second pattern SD2 included in the dam pattern DMP (see Figure 6B ) section SE. An explanation on this point will be provided later.

[0097] The dam pattern DMP may be located in the first area A1 and may surround at least a portion of the module hole MH. According to one or more embodiments of the present disclosure, the dam pattern DMP may have a closed line shape surrounding the module hole MH on a plane.

[0098] According to one or more embodiments of the present disclosure, a filler may be located inside the module hole MH. The filler may include a polymer resin. Since the filler is located inside the module hole MH, a flat surface may be provided for a component located on the module hole MH.

[0099] A portion of each of the plurality of signal lines SGL1 and SGL2 connected to the pixel PX may be located in the first area A1. The signal lines SGL1 and SGL2 are connected to the pixels PX spaced apart from each other with the module hole MH interposed therebetween via the first area A1. For convenience of explanation, Figure 4 Two signal lines SGL1 and SGL2 are shown among a plurality of signal lines connected to the pixel PX.

[0100] The first signal line SGL1 extends along the first direction DR1. The first signal line SGL1 is connected to pixels arranged in the same row along the first direction DR1 among the pixels PX. The first signal line SGL1 is interpreted as corresponding to any one of the scan lines connected to the pixels PX.

[0101] On a plane, some of the pixels PX connected to the first signal line SGL1 are located on the left side of the module hole MH, and the other are located on the right side of the module hole MH. Therefore, although some pixels concentrated around the module hole MH may be omitted, the pixels PX in the same row connected to the first signal line SGL1 may be turned on / off by substantially the same scan signal.

[0102] The second signal line SGL2 extends along the second direction DR2. The second signal line SGL2 is connected to pixels arranged in the same column along the second direction DR2 among the pixels PX. The second signal line SGL2 is interpreted as corresponding to any one of the data lines connected to the pixels PX.

[0103] On a plane, some of the pixels connected to the second signal line SGL2 are located above the module hole MH, and others are located below the module hole MH. Therefore, although some pixels concentrated around the module hole MH may be omitted, pixels in the same column connected to the second signal line SGL2 may receive data signals through the same line.

[0104] At a point where the first signal line SGL1 and the second signal line SGL2 cross each other, at least any one of the first signal line SGL1 and the second signal line SGL2 may be disconnected within the first area A1. A connection pattern located in a layer different from that of the disconnected signal line and connecting the disconnected portion may be further included. However, the connection relationship between the pixels PX spaced apart from each other and having the module hole MH interposed therebetween is not limited thereto.

[0105] Figure 5 It is along Figure 2 A cross-sectional view taken along line I-I'. Figure 5 In, omitted Figure 1 The housing 200 described in. Figure 5 The electronic device 1000 is shown Figure 2 The cross section corresponding to the pixel PX described in FIG.

[0106] refer to Figure 5 According to one or more embodiments of the present disclosure, an electronic device 1000 may include a display module 100, Figure 2 The housing 200 and the window 300 described in the embodiment of the present invention are shown in FIG. 1 . The display module 100 may include a display panel DP, an input sensor ISL, an organic cover layer IJP, and an anti-reflection layer ARL. The display panel DP may include a base layer 110, a driving element layer 120, a light emitting element layer 130, and an encapsulation layer 140.

[0107] Figure 2 The pixel PX described in the embodiment may include a light emitting element LD and a pixel driving circuit. The pixel driving circuit may include a plurality of transistors and a capacitor Cst. Figure 5A silicon transistor S-TFT and an oxide transistor O-TFT are shown. However, the configuration of the pixel driving circuit is not necessarily limited thereto. The pixel driving circuit may include only one type of transistor among the silicon transistor S-TFT and the oxide transistor O-TFT.

[0108] The base layer 110 may be provided as a single layer. The base layer 110 may be flexible or rigid. For example, the base layer 110 may include a synthetic resin film, or may include any one of glass and metal.

[0109] The barrier layer 10br may be located on the base layer 110 (as used herein, "on" may mean "above" or "over"). The barrier layer 10br reduces or prevents foreign matter from entering from the outside. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include a silicon oxide layer and a silicon nitride layer. Each of these layers may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0110] The first shielding electrode BMLa may be located on the barrier layer 10br. The first shielding electrode BMLa may correspond to the silicon transistor S-TFT. The first shielding electrode BMLa may include metal.

[0111] The first shielding electrode BMLa may receive a bias voltage. The first shielding electrode BMLa may receive a first power voltage. The first shielding electrode BMLa may prevent the potential caused by polarization from affecting the silicon transistor S-TFT. The first shielding electrode BMLa may block external light from reaching the silicon transistor S-TFT. In one or more embodiments of the present disclosure, the first shielding electrode BMLa may be a floating electrode having a shape separated from other electrodes or lines.

[0112] The buffer layer 10bf may cover the first shielding electrode BMLa and may be located on the barrier layer 10br. The buffer layer 10bf may reduce or prevent metal atoms or impurities from the base layer 110 from diffusing into the first semiconductor pattern SC1 located above the buffer layer 10bf. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

[0113] The first semiconductor pattern SC1 may be located on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low temperature polycrystalline silicon.

[0114] The first semiconductor pattern SC1 may have different electrical characteristics depending on whether it is doped or not. The first semiconductor pattern SC1 may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped at a lower concentration than the first region. The first semiconductor pattern SC1 may be an N-type transistor.

[0115] The conductivity of the first region may be greater than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to a channel region (or an active region) of a transistor. In other words, a portion of the first semiconductor pattern SC1 may be a channel of a transistor, another portion may be a source or drain of the transistor, and another portion may be a connection electrode or a connection signal line.

[0116] A source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed by the first semiconductor pattern SC1. The source region SE1 and the drain region DE1 may extend in opposite directions from the channel region AC1 in cross section.

[0117] The inorganic insulating layer 10a may cover the first semiconductor pattern SC1 and may be located on the buffer layer 10bf. The inorganic insulating layer 10a may be an inorganic layer. The inorganic insulating layer 10a may be a single-layer silicon oxide layer. In addition to the inorganic insulating layer 10a, an inorganic layer of the driving element layer 120 to be described later may also have a single-layer or multi-layer structure and may include at least one of the above materials, but the present disclosure is not limited thereto.

[0118] For convenience of explanation, in this specification, the barrier layer 10 br , the buffer layer 10 bf , and the inorganic insulating layer 10 a may be defined as one “first insulating layer 10 ”.

[0119] The gate GT1 may be located on the inorganic insulating layer 10a. The gate GT1 overlaps the channel region AC1. The gate GT1 may be a part of the metal pattern. The gate GT1 may be a mask in the process of doping the first semiconductor pattern SC1.

[0120] The first electrode CE10 of the capacitor Cst may be located on the inorganic insulating layer 10 a. According to one or more embodiments of the present disclosure, the first electrode CE10 may have a shape integral with the gate electrode GT1.

[0121] The second insulating layer 20 may cover the gate electrode GT1 and may be located on the inorganic insulating layer 10 a. In one or more embodiments of the present disclosure, an upper electrode overlapping the gate electrode GT1 may be further located on the second insulating layer 20 .

[0122] The second electrode CE20 of the capacitor Cst may be located on the second insulating layer 20. The second electrode CE20 may overlap the first electrode CE10. According to one or more embodiments of the present disclosure, the upper electrode overlapping the gate electrode GT1 may have a shape integral with the second electrode CE20 in a plane.

[0123] The second shielding electrode BMLb may be located on the second insulating layer 20. The second shielding electrode BMLb may correspond to the oxide transistor O-TFT. In one or more embodiments of the present disclosure, the second shielding electrode BMLb may be omitted. According to one or more embodiments of the present disclosure, the first shielding electrode BMLa may extend under the oxide transistor O-TFT and may replace the second shielding electrode BMLb.

[0124] The third insulating layer 30 may be located on the second insulating layer 20. The second semiconductor pattern SC2 may be located on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include an oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ).

[0125] The oxide semiconductor may include a plurality of regions SE2, AC2, and DE2 divided according to whether the transparent conductive oxide is reduced. The region in which the transparent conductive oxide is reduced (hereinafter referred to as the reduced region) has a greater conductivity than the region in which the transparent conductive oxide is not reduced (hereinafter referred to as the unreduced region). The reduced region is basically used as the source / drain or signal line of the transistor. The unreduced region basically corresponds to the semiconductor region (or channel) of the transistor. In other words, a portion of the second semiconductor pattern SC2 may be a semiconductor region of the transistor, another portion of the second semiconductor pattern SC2 may be a source region SE2 / drain region DE2 of the transistor, and another portion of the second semiconductor pattern SC2 may be a signal transmission region.

[0126] The fourth insulating layer 40 may cover the second semiconductor pattern SC2 and may be located on the third insulating layer 30. In one or more embodiments of the present disclosure, the fourth insulating layer 40 may be an insulating pattern that overlaps the gate electrode GT2 of the oxide transistor O-TFT and exposes the source region SE2 and the drain region DE2 of the oxide transistor O-TFT.

[0127] The gate GT2 of the oxide transistor O-TFT may be located on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a portion of the metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps the channel region AC2.

[0128] The fifth insulating layer 50 may cover the gate electrode GT2 and may be located on the fourth insulating layer 40. Each of the inorganic insulating layer 10a, the second insulating layer 20 to the fifth insulating layer 50 may be an inorganic layer. In the present specification, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be defined as "intermediate insulating layers".

[0129] The first connection electrode CNP1 may be located on the fifth insulating layer 50. The first connection electrode CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT through a contact hole passing through the inorganic insulating layer 10a, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50.

[0130] A sixth insulating layer 60 (lower interlayer insulating layer) may be located on the fifth insulating layer 50. The second connection electrode CNP2 may be located on the sixth insulating layer 60. The second connection electrode CNP2 may be connected to the first connection electrode CNP1 through a contact hole passing through the sixth insulating layer 60. The data line DL may be located on the sixth insulating layer 60. The second connection electrode CNP2 and the data line DL may include the same material.

[0131] The seventh insulating layer 70 (upper interlayer insulating layer) may cover the second connection electrode CNP2 and the data line DL, and may be located on the sixth insulating layer 60. Because the second connection electrode CNP2 and the data line DL may be formed by the same process, they may have the same material and the same stacking structure. In this specification, components located on the same layer and including the same material may be described as being formed by the same process. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0132] The first shielding electrode BMLa, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium having relatively good heat resistance. According to one or more embodiments of the present disclosure, the first connection electrode CNP1 and the second connection electrode CNP2 may include aluminum having high conductivity. The first connection electrode CNP1 and the second connection electrode CNP2 may have a three-layer stacked structure of titanium / aluminum / titanium.

[0133] The light emitting element LD may include an anode AE ​​(or a first electrode), a common layer EL and a cathode CE (or a second electrode). The anode AE ​​of the light emitting element LD may be located on the seventh insulating layer 70. The anode AE ​​may be a (semi) transmissive electrode or a reflective electrode. The anode AE ​​may include a stacked structure of ITO / Ag / ITO stacked in sequence. The positions of the anode AE ​​and the cathode CE may be changed with each other.

[0134] The pixel definition film PDL may be located on the seventh insulating layer 70. The pixel definition film PDL may be an organic layer. The pixel definition film PDL may have a characteristic of absorbing light. For example, the pixel definition film PDL may have a black color. The pixel definition film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition film PDL may correspond to a light blocking pattern having a characteristic of blocking light.

[0135] The opening PDL-OP exposing the portion of the anode AE ​​may be defined in the pixel defining film PDL. The light emitting area LA may be defined to correspond to the opening PDL-OP. In one or more embodiments of the present disclosure, the common layer EL may include a light emitting layer, a hole control layer between the light emitting layer and the anode AE, and an electron control layer between the light emitting layer and the cathode CE. The hole control layer may include a hole transport layer and may also include a hole injection layer. The electron control layer may include an electron transport layer and may also include an electron injection layer.

[0136] Fig. 6A The common layer EL is shown to be located in the opening PDL-OP defined in the pixel definition film PDL and patterned in the opening PDL-OP, but this may correspond to the shape of the light emitting layer included in the common layer EL, and the hole control layer and the electron control layer included in the common layer EL may be formed in the entire first area A1 and the second area A2 through the opening mask. If the hole control layer and the electron control layer included in the common layer EL are formed in the entire area, a path through which moisture and oxygen enter the common layer EL via the module hole MH may be provided. Therefore, a structure in which the common layer EL is disconnected is suitable.

[0137] The encapsulation layer 140 may cover the light emitting element LD. The encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 stacked in sequence, but the layers constituting the encapsulation layer 140 are not necessarily limited thereto. The inorganic encapsulation layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and the like. Each of the inorganic encapsulation layers 141 and 143 may have a multilayer structure. The organic encapsulation layer 142 may include an acrylic-based organic layer, but is not limited thereto. The organic encapsulation layer 142 may have a dam pattern DMP (or Fig. 6A The boundary is defined by any one of the dam patterns DMP1, DMP2, DMP3 and DMP4). Fig. 6A , the organic encapsulating layer 142 may have a boundary defined by the fourth dam pattern DMP4 in the first area A1.

[0138] The input sensor ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer).

[0139] The input sensor ISL may include a first insulating layer 210 (or a first sensor insulating layer), a first conductive layer 220, a second insulating layer 230 (or a second sensor insulating layer), a second conductive layer 240, and a third insulating layer 250 (or a third sensor insulating layer). Figure 5 Conductive lines of a first conductive layer 220 and conductive lines of a second conductive layer 240 are shown.

[0140] The first insulating layer 210 may be directly on the display panel DP. The first insulating layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0141] Each of the first conductive layer 220 and the second conductive layer 240 may have a single-layer structure, or may have a multi-layer structure stacked along the third direction DR3. The first conductive layer 220 and the second conductive layer 240 may include conductive lines defining electrodes in a grid shape. The conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 may be connected through contact holes passing through the second insulating layer 230, or may not be connected therethrough. The connection relationship between the conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 may be determined according to the type of sensor forming the input sensor ISL.

[0142] The first conductive layer 220 and the second conductive layer 240 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0143] The first conductive layer 220 and the second conductive layer 240 having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The multi-layer conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0144] The second insulating layer 230 may be located between the first conductive layer 220 and the second conductive layer 240. The third insulating layer 250 may cover the second conductive layer 240. In one or more embodiments of the present disclosure, the third insulating layer 250 may be omitted. The second insulating layer 230 and the third insulating layer 250 may include an inorganic layer or an organic layer.

[0145] The organic cover layer IJP may be located on the input sensor ISL. The organic cover layer IJP may compensate for a step difference generated during a process of forming the display panel DP and the input sensor ISL. Thus, a substantially flat surface may be provided to a component located on the display panel DP. The organic cover layer IJP may include an organic material. The organic cover layer IJP may be formed on the first adhesive layer AD1 by an inkjet process.

[0146] The display module 100 according to one or more embodiments of the present disclosure may further include an anti-reflection layer ARL. The anti-reflection layer ARL may be located between the organic cover layer IJP and the window 300. The anti-reflection layer ARL may reduce reflection of light incident from the outside of the electronic device 1000. That is, the anti-reflection layer ARL may reduce the external light reflectivity of the electronic device 1000. The anti-reflection layer ARL according to one or more embodiments of the present disclosure may include a polarization layer, a phase shifter, a destructive interference structure, or a plurality of color filters.

[0147] The first adhesive layer AD1 may be located between the anti-reflection layer ARL and the organic cover layer IJP to couple the anti-reflection layer ARL and the organic cover layer IJP to each other. The first adhesive layer AD1 may include at least one of an optically transparent adhesive, an optically transparent adhesive resin, and a pressure sensitive adhesive (PSA).

[0148] The window 300 may be located on the anti-reflection layer ARL. The second adhesive layer AD2 may be located between the anti-reflection layer ARL and the window 300 to couple the anti-reflection layer ARL and the window 300 to each other. The second adhesive layer AD2 may include the same material as the first adhesive layer AD1.

[0149] Fig. 6A It is along Figure 2 A cross-sectional view taken along line II-II'. Figure 6B yes Fig. 6A An enlarged view of one of the dam patterns shown in FIG.

[0150] refer to Fig. 6A , the active area AA of the electronic device 1000 may include a first area A1 and a second area A2. At least a portion of the first area A1 may overlap with the electronic module 400, and the second area A2 may surround at least a portion of the first area A1. The second area A2 may be where the Figure 2 The area of ​​the pixel PX described in FIG.

[0151] The module hole MH may be formed by passing through the display panel DP, the input sensor ISL, the first adhesive layer AD1, the anti-reflection layer ARL, the second adhesive layer AD2, and the organic cover layer IJP. The window 300 covers the module hole MH so that exposure of the sides of the display panel DP, the input sensor ISL, and the organic cover layer IJP defining the module hole MH can be reduced or prevented. According to one or more embodiments of the present disclosure, a resin layer located inside the module hole MH may further be included.

[0152] The first area A1 of the display module 100 may include at least one of the dam patterns DMP1, DMP2, DMP3, and DMP4. Figure 6B , an enlarged view of the second dam pattern DMP2 is shown as an example, and the description of the second dam pattern DMP2 may be applied to the first dam pattern DMP1, the third dam pattern DMP3, and the fourth dam pattern DMP4.

[0153] refer to Figure 6B Each of the dam patterns DMP1, DMP2, DMP3, and DMP4 may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2. The fourth dam pattern DMP4 may include a plurality of first patterns SD1 spaced apart from each other between one lower layer IL1 and one upper layer IL2, and a plurality of second patterns SD2 spaced apart from each other between one lower layer IL1 and one upper layer IL2.

[0154] The first pattern SD1 may be located on the fifth insulating layer 50. The first pattern SD1 may be located on the fifth insulating layer 50. Figure 5The first connection electrode CNP1 described in the foregoing is located on the same layer. The first pattern SD1 may be formed by the same process as the first connection electrode CNP1. Therefore, the first pattern SD1 may include the same material as the first connection electrode CNP1.

[0155] The lower layer IL1 may cover the first pattern SD1 and may be located on the fifth insulating layer 50. The lower layer IL1 may include or define a contact hole IC exposing at least a portion of the first pattern SD1. Basically, the lower layer IL1 may be formed by applying a material forming the sixth insulating layer 60 to the entire surface of the active area AA and by performing patterning so as to overlap with the first pattern SD1. Therefore, the lower layer IL1 may include the same material as the sixth insulating layer 60. The lower layer IL1 and the sixth insulating layer 60 may include an organic material.

[0156] The second pattern SD2 may be located on the lower layer IL1. The second pattern SD2 may be located in the contact hole IC defined in the lower layer IL1 and may contact the first pattern SD1 exposed by the contact hole IC. The second pattern SD2 may include Figure 5 The second pattern SD2 may include the same material as the data line DL and the second connection electrode CNP2. The second pattern SD2 may have a three-layer stack structure of titanium / aluminum / titanium.

[0157] According to the present disclosure, opposite ends of the second pattern SD2 may protrude from the lower layer IL1 and the upper layer IL2 to the outside. Portions protruding from the lower layer IL1 and the upper layer IL2 may be defined as tip portions TIP2-1 and TIP2-2.

[0158] A side surface of the lower layer IL1 , the tip portions TIP2 - 1 and TIP2 - 2 of the second pattern SD2 , and a side surface and a top surface of the upper layer IL2 may be covered by the first inorganic encapsulation layer 141 .

[0159] When the tip portions TIP2 - 1 and TIP2 - 2 protrude from the lower layer IL1 , the tip portions TIP2 - 1 and TIP2 - 2 and the lower layer IL1 may have an undercut shape.

[0160] like Fig. 6A As shown in FIG, the first dam pattern DMP1 may include one tip portion TIP1 protruding in a direction adjacent to the module hole MH, and the third dam pattern DMP3 may include a tip portion TIP3 protruding in a direction toward the fourth dam pattern DMP4. The fourth dam pattern DMP4 may include a first tip portion TIP4-1 protruding from one second pattern SD2 and a second tip portion TIP4-2 protruding from another second pattern SD2.

[0161] Reference again Figure 6B , the upper layer IL2 may be located on the second pattern SD2. The upper layer IL2 may overlap the lower layer IL1. Basically, the upper layer IL2 may be formed by applying a material forming the seventh insulating layer 70 to the entire surface of the active area AA and by performing patterning so as to overlap the second pattern SD2. Therefore, the upper layer IL2 may include the same material as the seventh insulating layer 70. The upper layer IL2 and the seventh insulating layer 70 may include an organic material.

[0162] The upper layer IL2 according to the present disclosure may include / define an opening IL-OP exposing a portion SE of the second pattern SD2. Since the upper layers IL2 are spaced apart from each other and the opening IL-OP is interposed therebetween, an organic layer (e.g., a second floating pattern EL-T) located on the upper layer IL2 may be separated on the upper layer IL2. The second floating pattern EL-T may be defined as an organic material formed in the first area A1 in the process of forming the common layer EL and disconnected from the common layer EL located in the second area A2 by the second dam pattern DMP2. Therefore, a path through which moisture and oxygen enter the common layer EL via the second floating pattern EL-T located on the upper layer IL2 may be appropriately blocked.

[0163] The second dam pattern DMP2 according to one or more embodiments of the present disclosure may further include a dummy pattern GP. The dummy pattern GP may overlap with the first pattern SD1. Figure 5 The second electrode CE20 of the capacitor Cst described in the embodiment is located on the same layer and may include the same material as the second electrode CE20. Fig. 6A As shown in FIG. 1 , the dummy pattern GP may be included in the second, third, and fourth dam patterns DMP2 , DMP3 , and DMP4 , and may be omitted in the first dam pattern DMP1 .

[0164] According to one or more embodiments of the present disclosure, another dummy pattern may be further included, which is located between the first insulating layer 10 and the second insulating layer 20 and overlaps with the dummy pattern GP. According to one or more embodiments of the present disclosure, the other dummy pattern may include Figure 5 The gate electrode GT1 of the silicon transistor S-TFT shown in FIG. 1 or the first semiconductor pattern SC1 is made of the same material.

[0165] The window 300 according to one or more embodiments of the present disclosure may further include a bezel pattern BM on the rear surface of the window 300. The bezel pattern BM may be printed or colored on the rear surface of the window 300, or may be attached to the window 300 by a separate adhesive layer.

[0166] An opening located in the first area A1 and overlapping the module hole MH may be defined in the bezel pattern BM. The bezel pattern BM may block unnecessary external light from entering the electronic module 400, thereby improving the performance of the electronic module 400. In addition, the bezel pattern BM may reduce or prevent a user from visually recognizing a component located in the first area A1. The bezel pattern BM may include a material that blocks light, but the present disclosure is not limited thereto.

[0167] Figures 7 to 14 is a cross-sectional view showing a portion of a first region of a display module according to one or more embodiments of the present disclosure. Figures 7 to 14 The description of the dam patterns DMP-A and DMP-B shown in FIG. 1 can be applied to Fig. 6A The same / similar reference numerals are used for the dam patterns DMP1, DMP2, DMP3 and DMP4 shown in FIG. Figures 1 to 6B The same / similar parts as those described in the drawings are referred to herein and repeated descriptions are omitted.

[0168] refer to Figure 7 The display panel DP according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0169] The first pattern SD1 may be located on the fifth insulating layer 50. The lower layer IL1 may cover the first pattern SD1 and may be located on the fifth insulating layer 50. The lower layer IL1 may include / define a contact hole IC exposing at least a portion of the first pattern SD1. The lower layer IL1 may include an organic material.

[0170] The second pattern SD2 may be located on the lower layer IL1. The second pattern SD2 may be located in a contact hole IC defined in the lower layer IL1, and may contact the first pattern SD1 exposed through the contact hole IC.

[0171] The upper layer IL2 may cover the second pattern SD2 and may be located above the lower layer IL1. The upper layer IL2 according to the present disclosure may include / define an opening IL-OP exposing at least a portion SE of the second pattern SD2. Since the upper layer IL2 includes / defines the opening IL-OP, the length of the second floating pattern EL-T located on the upper layer IL2 may be increased, or the second floating pattern EL-T may be separated. The second floating pattern EL-T may be Figure 5 The common layer EL described in is disconnected.

[0172] A portion of the second pattern SD2 of the first dam pattern DMP-A may protrude from the lower layer IL1 and the upper layer IL2 in a direction toward the second dam pattern DMP-B. The protruding portion may be defined as a first tip portion TIP-A.

[0173] A portion of the second pattern SD2 of the second dam pattern DMP-B may protrude from the lower layer IL1 and the upper layer IL2 in a direction toward the first dam pattern DMP-A. The protruding portion may be defined as a second tip portion TIP-B.

[0174] According to the present disclosure, the first dam pattern DMP-A and the second dam pattern DMP-B may be spaced apart from each other to expose a portion of the fifth insulating layer 50. The first floating pattern EL-P may be located on the fifth insulating layer 50 exposed by the first dam pattern DMP-A and the second dam pattern DMP-B. The first floating pattern EL-P may be defined as being formed in the first area A1 in the process of forming the common layer EL and being connected to the common layer EL located in the second area A2 by the first dam pattern DMP-A and the second dam pattern DMP-B (see Fig. 6A ) is disconnected. Therefore, the first floating pattern EL-P may include the same material as the common layer EL.

[0175] If the common layer EL (see Fig. 6A ) is formed in the first area A1, a common layer EL is formed between the first dam pattern DMP-A and the second dam pattern DMP-B (see Fig. 6A ) may be appropriately separated by the tip portions TIP-A and TIP-B in a region between the first dam pattern DMP-A and the second dam pattern DMP-B.

[0176] In addition, the upper layer IL2 according to the present disclosure may include / define an opening IL-OP exposing a portion SE of the second pattern SD2. Since the upper layers IL2 are spaced apart from each other and the opening IL-OP is interposed therebetween, the second floating pattern EL-T located on the upper layer IL2 may be separated on the upper layer IL2. The second floating pattern EL-T may be defined as an organic material formed in the first area A1 in the process of forming the common layer EL and disconnected from the common layer EL located in the second area A2 by the opening IL-OP. Therefore, the second floating pattern EL-T and the common layer EL may include the same material.

[0177] According to one or more embodiments of the present disclosure, the dam patterns DMP-A and DMP-B, the floating patterns EL-P and EL-T, and portions of the fifth insulating layer 50 exposed by the dam patterns DMP-A and DMP-B may be covered by the first inorganic encapsulation layer 141 .

[0178] According to the present disclosure, the common layer EL (see Fig. 6A ) is mainly divided by the tip portions TIP-A and TIP-B in the region between the dam patterns DMP-A and DMP-B, and since the upper layer IL2 included in each of the dam patterns DMP-A and DMP-B includes the opening IL-OP, the common layer EL (see Fig. 6A ) can be separated again by the opening IL-OP. According to one or more embodiments of the present disclosure, although the common layer EL (see Fig. 6A ) are not separated by the opening IL-OP, but with the common layer EL located on the side defining the opening IL-OP (see Fig. 6A ) increases in length, through which moisture and oxygen enter the common layer EL in the second area A2 from the module hole MH (see Fig. 6A ) is lengthened, so the inflow of moisture and oxygen can be delayed. Therefore, moisture and oxygen flowing into the module hole MH can be appropriately blocked / delayed. Therefore, an electronic device 1000 having improved display quality and improved performance of the electronic module can be provided (see Figure 1 ).

[0179] refer to Figure 8 , the display panel DP-1 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0180] The first pattern SD1 may be located on the fifth insulating layer 50. The lower layer IL1 may cover the first pattern SD1 and may be located on the fifth insulating layer 50. The lower layer IL1 may include / define a contact hole IC exposing at least a portion of the first pattern SD1. The second pattern SD2 may be located on the lower layer IL1. The second pattern SD2 may be located in the contact hole IC defined in the lower layer IL1 and may contact the first pattern SD1 exposed through the contact hole IC.

[0181] The upper layer IL2 may cover the second pattern SD2 and may be located above the lower layer IL1. The upper layer IL2 according to the present disclosure may include / define an opening IL-OP exposing at least a portion SE of the second pattern SD2. Since the upper layer IL2 includes / defines the opening IL-OP, the length of the second floating pattern EL-T located on the upper layer IL2 may be increased, or the second floating pattern EL-T may be separated.

[0182] The lower layer IL1 included in the first dam pattern DMP-A and the lower layer IL1 included in the second dam pattern DMP-B may be connected to each other. Therefore, the first floating pattern EL-P may be located on the lower layer IL1 connected to each other. The first floating pattern EL-P may include a common layer EL (see Fig. 6A )same materials.

[0183] The upper layer IL2 may include / define an opening IL-OP exposing a portion SE of the second pattern SD2. Since the upper layers IL2 are spaced apart from each other and the opening IL-OP is interposed therebetween, the second floating pattern EL-T located on the upper layer IL2 may be separated on the upper layer IL2. The second floating pattern EL-T may include a portion SE of the common layer EL (see Fig. 6A )same materials.

[0184] According to one or more embodiments of the present disclosure, the dam patterns DMP-A and DMP-B, the floating patterns EL-P and EL-T, and the lower layer IL1 connected to each other may be covered by the first inorganic encapsulation layer 141 .

[0185] refer to Fig. 9 , the display panel DP-2 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0186] The first pattern SD1 may be located on the fifth insulating layer 50. The lower layer IL1 may cover the first pattern SD1 and may be located on the fifth insulating layer 50. The lower layer IL1 may include / define a contact hole IC exposing at least a portion of the first pattern SD1. The second pattern SD2 may be located on the lower layer IL1. The second pattern SD2 may be located in the contact hole IC defined in the lower layer IL1 and may contact the first pattern SD1 exposed through the contact hole IC.

[0187] The upper layer IL2 may cover the second pattern SD2 and may be located above the lower layer IL1. The upper layer IL2 according to the present disclosure may include / define an opening IL-OP exposing at least a portion SE of the second pattern SD2. Since the upper layer IL2 includes / defines the opening IL-OP, the length of the second floating pattern EL-T located on the upper layer IL2 may be increased, or the second floating pattern EL-T may be separated.

[0188] The description of the first dam pattern DMP-A and the second dam pattern DMP-B is the same as Figure 7 The same as those described in , and the differences will be mainly described.

[0189] The second pattern SD2 included in each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a plurality of conductive layers. According to one or more embodiments of the present disclosure, the second pattern SD2 may include a first layer TI1, a second layer AL, and a third layer TI2 stacked sequentially. The thickness of the first layer TI1 and the third layer TI2 may be less than the thickness of the second layer AL. The first layer TI1 and the third layer TI2 may include titanium (Ti), and the second layer AL may include aluminum (Al). Similar to the second pattern SD2, referring to Figure 5 The depicted data line DL may also include a first layer TI1, a second layer AL, and a third layer TI2 that are sequentially stacked.

[0190] According to one or more embodiments of the present disclosure, among the layers of the second pattern SD2, the first layer TI1 and the third layer TI2 located in the portion defined as the tip portions TIP-A and TIP-B may protrude relatively more than the second layer AL in a direction toward the adjacent dam pattern. Among the second pattern SD2, the shapes of the tip portions TIP-A and TIP-B may be formed due to the difference in etching rates among the first layer TI1, the second layer AL, and the third layer TI2.

[0191] Therefore, the common layer EL (see Fig. 6A ) can be more appropriately separated due to the shapes of the tip portions TIP-A and TIP-B. Therefore, it is possible to appropriately block moisture and oxygen from passing through the module hole MH (see Fig. 6A ) into the common layer EL in the second area A2 (see Fig. 6A )'s moving path.

[0192] refer to Fig.10 The display panel DP-3 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0193] The second pattern SD2 included in each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a plurality of conductive layers. According to one or more embodiments of the present disclosure, the second pattern SD2 may include a first layer TI1, a second layer AL, and a third layer TI2 stacked sequentially. The thickness of the first layer TI1 and the third layer TI2 may be less than the thickness of the second layer AL. The first layer TI1 and the third layer TI2 may include titanium (Ti), and the second layer AL may include aluminum (Al).

[0194] The description of the first dam pattern DMP-A and the second dam pattern DMP-B is the same as Fig. 9 The same as those described in , and the differences will be mainly described.

[0195] The second pattern SD2 included in each of the first dam pattern DMP-A and the second dam pattern DMP-B may further include a hole overlapping the opening IL-OP. The hole may include a groove AL-H and a pattern opening TI-OP, wherein a portion of the second layer AL is removed from the groove AL-H, and the pattern opening TI-OP passes through the third layer TI2 and the pattern opening TI-OP overlaps the groove AL-H. The groove AL-H may expose the lower surface of the third layer TI2 overlapping the groove AL-H.

[0196] The process of forming the pattern opening TI-OP by removing the third layer TI2 may use a fluorine-based process gas used in a process of ashing a photoresist layer used as a mask when patterning an insulating layer located on the second pattern SD2 and including an organic material. For example, the process gas may include carbon fluoride.

[0197] The second floating pattern EL-T located on the upper layer IL2 may be separated by a hole defined in the second pattern SD2. Fig. 6A ) in the common layer EL (see Fig. 6A ) and the second floating pattern EL-T are separated, moisture and oxygen may be blocked from passing through the module hole MH (see Fig. 6A ) into the common layer EL in the second area A2 (see Fig. 6A )'s moving path.

[0198] refer to Fig.11 The display panel DP-4 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0199] The first pattern SD1 may be located on the fifth insulating layer 50. The lower layer IL1 may cover the first pattern SD1 and may be located on the fifth insulating layer 50. The lower layer IL1 may include / define a contact hole IC exposing at least a portion of the first pattern SD1. The second pattern SD2 may be located on the lower layer IL1. The second pattern SD2 may be located in the contact hole IC defined in the lower layer IL1 and may contact the first pattern SD1 exposed through the contact hole IC.

[0200] The description of the first dam pattern DMP-A and the second dam pattern DMP-B is the same as Figure 7 The same as those described in , and the differences will be mainly described.

[0201] The display panel DP-4 according to one or more embodiments of the present disclosure may further include a blocking pattern IP-A. The blocking pattern IP-A may be located between the first dam pattern DMP-A and the second dam pattern DMP-B adjacent to each other. The blocking pattern IP-A may be located on the fifth insulating layer 50 exposed by the first dam pattern DMP-A and the second dam pattern DMP-B. The blocking pattern IP-A may be formed in the same process as the first pattern SD1 and may include the same material as the first pattern SD1. The blocking pattern IP-A may be covered by the first inorganic encapsulation layer 141.

[0202] Since the barrier pattern IP-A is formed between the first dam pattern DMP-A and the second dam pattern DMP-B, the first floating pattern EL-P, which may be formed after forming the barrier pattern IP-A, may be separated. Therefore, moisture and oxygen may be properly blocked from entering the module hole MH (see Fig. 6A ) into the common layer EL in the second area A2 (see Fig. 6A )'s moving path.

[0203] refer to Fig.12 , the display panel DP-5 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0204] The first pattern SD1 may be located on the fifth insulating layer 50. The lower layer IL1 may cover the first pattern SD1 and may be located on the fifth insulating layer 50. The lower layer IL1 may include / define a contact hole IC exposing at least a portion of the first pattern SD1. The second pattern SD2 may be located on the lower layer IL1. The second pattern SD2 may be located in the contact hole IC defined in the lower layer IL1 and may contact the first pattern SD1 exposed through the contact hole IC.

[0205] The upper layer IL2 may cover the second pattern SD2 and may be located above the lower layer IL1. The upper layer IL2 according to the present disclosure may include / define an opening IL-OP exposing at least a portion SE of the second pattern SD2. Since the upper layer IL2 includes / defines the opening IL-OP, the length of the second floating pattern EL-T located on the upper layer IL2 may be increased, or the second floating pattern EL-T may be separated.

[0206] The lower layer IL1 included in the first dam pattern DMP-A and the lower layer IL1 included in the second dam pattern DMP-B may be connected to each other. Therefore, the first floating pattern EL-P may be located on the lower layer IL1 connected to each other. The first floating pattern EL-P may include a common layer EL (see Fig. 6A )same materials.

[0207] The display panel DP-5 may further include a blocking pattern IP-B. The blocking pattern IP-B may be located between the first dam pattern DMP-A and the second dam pattern DMP-B adjacent to each other. The blocking pattern IP-B may be located on the lower layer IL1 connected to each other. The first floating pattern EL-P may be separated by the blocking pattern IP-B on the lower layer IL1 connected to each other.

[0208] refer to Fig.13 , the display panel DP-6 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0209] Description and Reference of the First Dam Pattern DMP-A and the Second Dam Pattern DMP-B Fig.12 The description given of the first dam pattern DMP-A and the second dam pattern DMP-B are the same, and the difference will be mainly described.

[0210] The blocking pattern IP-C may include a plurality of conductive layers. According to one or more embodiments of the present disclosure, the blocking pattern IP-C may include a first layer PL, a second layer PC, and a third layer PU stacked sequentially. The thickness of the first layer PL and the third layer PU may be less than the thickness of the second layer PC. The first layer PL and the third layer PU may include titanium (Ti), and the second layer PC may include aluminum (Al).

[0211] According to one or more embodiments of the present disclosure, the ends of the first layer PL and the third layer PU may protrude relatively more than the end of the second layer PC in a direction toward the adjacent dam pattern. The shape of the end of the blocking pattern IP-C may be formed due to the difference in etching rates among the first layer PL, the second layer PC, and the third layer PU.

[0212] refer to Fig.14The display panel DP-7 according to one or more embodiments of the present disclosure may include a first dam pattern DMP-A and a second dam pattern DMP-B located in the first area A1 and spaced apart from each other. Each of the first dam pattern DMP-A and the second dam pattern DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0213] Description and Reference of the First Dam Pattern DMP-A and the Second Dam Pattern DMP-B Fig.12 The description given of the first dam pattern DMP-A and the second dam pattern DMP-B are the same, and the difference will be mainly described.

[0214] The display panel DP-7 may further include a blocking pattern IP-D. The blocking pattern IP-D may include a plurality of patterns P1 and P2 spaced apart from each other. The patterns P1 and P2 may surround the module hole MH on a plane (see Fig. 6A ). The first floating pattern EL-P may be appropriately separated by the patterns P1 and P2 on the lower layer IL1 which are connected to each other.

[0215] FIG. 15A to FIG. 15H is a cross-sectional view illustrating a manufacturing method for forming a dam pattern according to one or more embodiments of the present disclosure. Figures 1 to 7 The same / similar parts as those described in the drawings are referred to herein and repeated descriptions are omitted.

[0216] refer to Fig.15A , a method of manufacturing an electronic device according to one or more embodiments of the present disclosure may include forming a first pattern SD1. The first pattern SD1 may be formed on the fifth insulating layer 50. The first pattern SD1 may be formed by Figure 5 The first pattern SD1 may be formed by stacking a plurality of conductive layers. For example, the first pattern SD1 may have a three-layer structure in which titanium (Ti), aluminum (Al), and titanium (Ti) are sequentially stacked.

[0217] refer to Fig. 15B , a method of manufacturing an electronic device according to one or more embodiments of the present disclosure may include: patterning a first pattern SD1 ; forming a lower layer IL1 on the first pattern SD1 ; and forming a second pattern SD2 on the lower layer IL1 .

[0218] Patterning the first pattern SD1 may include patterning the first pattern SD1 into a plurality of first patterns SD1 by removing a portion of one first pattern SD1.

[0219] The lower layer IL1 can be formed by applying a Figure 5The lower layer IL1 may be made of the same material as the sixth insulating layer 60 described in the above. The lower layer IL1 may include an organic material. According to one or more embodiments of the present disclosure, a contact hole IC may be formed through the lower layer IL1 and expose the first pattern SD1.

[0220] Forming the second pattern SD2 may be performed by applying a conductive material on the lower layer IL1 and patterning the conductive material. The second pattern SD2 may be formed by Figure 5 The second pattern SD2 may be formed by stacking a plurality of conductive layers. For example, the second pattern SD2 may have a three-layer structure in which titanium (Ti), aluminum (Al), and titanium (Ti) are sequentially stacked.

[0221] refer to Fig. 15C and Fig.15D The method of manufacturing an electronic device according to one or more embodiments of the present disclosure may include forming an upper layer IL2. The upper layer IL2 may be formed by applying a Figure 5 The upper layer IL2 may be made of the same material as the seventh insulating layer 70 described above. The upper layer IL2 may include an organic material.

[0222] The upper layer IL2 may have a thickness reduced by about 30% to about 70% compared with the thickness of the lower layer IL1. The upper layer IL2 may be formed using a half-tone mask.

[0223] Thereafter, patterning the upper layer IL2 may be included. One upper layer IL2 may be partially removed and patterned into upper layers IL2 spaced apart from each other. The lower layer IL1 may be exposed between the upper layers IL2 spaced apart from each other.

[0224] This may include forming an opening IL-OP in each of the upper layers IL2 . Portions SE of the second pattern SD2 may be exposed by the upper layer IL2 through the opening IL-OP.

[0225] refer to Fig.15E and Fig.15F According to one or more embodiments of the present disclosure, the method of manufacturing an electronic device may include forming a mask pattern IG and forming a photoresist pattern PR. The mask pattern IG may be entirely located on the lower layer IL1 and the upper layer IL2. According to one or more embodiments of the present disclosure, the mask pattern IG may include indium gallium zinc oxide (IGZO).

[0226] Thereafter, a photoresist pattern PR may be formed on the mask pattern IG overlapping the upper layer IL2. The photoresist pattern PR is not limited to any embodiment as long as it is used in a photoresist process.

[0227] Thereafter, the mask pattern IG may be patterned by using the photoresist pattern PR as a mask. In this case, the patterning of the mask pattern IG may be performed by a wet etching process. The mask pattern IG may be patterned and located only on the upper layer IL2, and the mask pattern IG originally located on the lower layer IL1 may be removed.

[0228] Thereafter, the photoresist pattern PR may be removed.

[0229] refer to Figure 15G , a method of manufacturing an electronic device according to one or more embodiments of the present disclosure may include patterning the lower layer IL1. A portion of the lower layer IL1 may be removed by using the mask pattern IG as a mask. The patterning of the lower layer IL1 may be performed by a dry etching process. In the dry etching process, only oxygen (O 2 ) as process gas.

[0230] refer to Fig.15H The method of manufacturing an electronic device according to one or more embodiments of the present disclosure may include removing the mask pattern IG. The mask pattern IG may be removed by a wet etching process.

[0231] First and second dam patterns DMP-A and DMP-B spaced apart from each other may be formed on the fifth insulating layer 50. Each of the first and second dam patterns DMP-A and DMP-B may include a first pattern SD1, a second pattern SD2, a lower layer IL1, and an upper layer IL2.

[0232] The first width defined between the sides SD-W of the second pattern SD2 may be smaller than the second width defined between the sides IL-W of the upper layer IL2. Therefore, the common layer EL (see FIG. 1 ) formed between the first dam pattern DMP-A and the second dam pattern DMP-B Fig. 6A ) may be separated by a second pattern SD2 between the first dam pattern DMP-A and the second dam pattern DMP-B.

[0233] In addition, since the upper layer IL2 includes / defines the opening IL-OP, the common layer EL (see Fig. 6A ) can be increased, or the common layer EL (see Fig. 6A ) can be separated by the opening IL-OP on the upper layer IL2.

[0234] According to one or more embodiments of the present disclosure, the common layer included in the light emitting element can be mainly separated by the tip portion in the area between the dam patterns. In addition, since the upper layer included in each of the dam patterns includes an opening, the common layer can be separated again by the opening. Therefore, moisture and oxygen can be appropriately prevented from entering the common layer included in the pixel through the module hole. Therefore, an electronic device with improved display quality and improved performance of the electronic module can be provided.

[0235] Although the above content has been described with reference to various embodiments of the present disclosure, it will be understood by those skilled in the art or those of ordinary skill in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and technical scope of the present disclosure as described in the appended claims. Therefore, the present disclosure should not be limited to the content described in the detailed description of the specification, but should be determined by the appended claims and the functional equivalents to be included therein.

Claims

1. An electronic device having a second area and a first area surrounded by the second area in a plan view, and comprising: a display module defining a module hole and comprising a base layer, pixels in the second region, data lines connected to the pixels, and a dam pattern in the first region and surrounding the module hole in a plan view, the dam pattern comprising a first pattern over the base layer, a lower layer over the first pattern, a second pattern over the lower layer and comprising the same material as the data line, and an upper layer over the second pattern and defining an opening, the opening exposing a portion of the second pattern; a window above the display module; as well as The electronic module is located below the display module, overlaps the first area, and overlaps the module hole.

2. The electronic device according to claim 1, wherein: The thickness of the upper layer is smaller than the thickness of the lower layer, and Wherein, at least one of the opposite sides of the second pattern protrudes between the lower layer and the upper layer.

3. The electronic device according to claim 2, wherein: The display module further includes an encapsulation layer, which covers the pixels and includes: a first inorganic encapsulation layer; a second inorganic encapsulation layer, above the first inorganic encapsulation layer; and The organic encapsulation layer is between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

4. The electronic device according to claim 3, wherein: The first inorganic encapsulating layer covers a side surface of the lower layer, a portion of the second pattern protruding between the lower layer and the upper layer, and a side surface and an upper surface of the upper layer.

5. The electronic device according to claim 3, wherein: The organic encapsulation layer has a boundary defined by any one of the dam patterns in the first region.

6. The electronic device according to claim 1, wherein: The lower layer defines a contact hole exposing at least a portion of the first pattern, and The second pattern is in the contact hole and contacts the first pattern.

7. The electronic device according to claim 1, wherein: The pixels include: transistors; and A light emitting element includes a first electrode connected to the transistor, a second electrode above the first electrode, and a common layer between the first electrode and the second electrode. 8 . The electronic device of claim 7 , further comprising a first floating pattern including a same material as the common layer between the dam patterns adjacent to each other and disconnected from the common layer. 9 . The electronic device of claim 8 , further comprising a second floating pattern over the upper layer, disconnected from the first floating pattern and the common layer, and comprising a same material as the common layer.

10. The electronic device according to claim 8, wherein: The lower layers included in the dam patterns spaced apart from each other with the first floating patterns interposed therebetween are connected to each other, and The first floating pattern is disposed on the connected lower layer. 11 . The electronic device of claim 8 , further comprising a barrier pattern between the dam patterns and separating the first floating patterns.

12. The electronic device according to claim 11, wherein: The blocking pattern comprises: First floor; a second layer over the first layer and comprising a material different from that of the first layer; and a third layer, above the second layer and comprising the material of the first layer, The first layer and the third layer protrude further than the second layer in a direction toward the dam pattern.

13. The electronic device according to claim 11, wherein: The blocking pattern is provided in plurality, the blocking patterns are spaced apart from each other and surround the module hole.

14. The electronic device according to claim 11, wherein: The blocking pattern is over the lower layer of the connection of the dam patterns spaced apart from each other with the first floating pattern therebetween.

15. The electronic device according to claim 1, wherein: Each of the second pattern and the data line includes: The first layer, contains titanium; a second layer, overlying the first layer, comprising aluminum; and A third layer, above the second layer, comprises titanium.

16. The electronic device according to claim 15, wherein: At least one of the opposite sides of the second pattern protrudes between the lower layer and the upper layer, and The first layer and the third layer protrude further than the second layer in a direction toward the dam pattern.

17. The electronic device according to claim 15, wherein: The second pattern defines a hole overlapping the opening, the hole having a groove corresponding to the removed portion of the second layer, and having a pattern opening passing through the third layer and overlapping the groove.

18. The electronic device according to claim 17, wherein: The hole exposes a lower surface of the third layer adjacent to the pattern opening.

19. The electronic device according to claim 1, wherein: The pixel includes a light emitting element connected to a transistor, the transistor including an active pattern and a gate overlapping the active pattern, and One of the dam patterns further includes a dummy pattern, the dummy pattern is below the first pattern and overlaps the first pattern, and includes the same material as the gate or the active pattern.

20. The electronic device according to claim 1, wherein: The display module comprises: A display panel comprising the base layer and the pixels; An input sensor, above the display panel, for sensing external input; an organic cover layer over the input sensor; and An anti-reflective layer is between the organic cover layer and the window.

Images