Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a substrate, the surface of the substrate comprises at least one group of stacked layers which are oppositely arranged, the opposite surfaces of the stacked layers are step-shaped, the stacked layers comprise a plurality of first dielectric layers and reference layers which are alternately stacked, the starting layer and the ending layer of the stacked layer are first dielectric layers, and each group of adjacent first dielectric layer and reference layer is a step; the isolation layer covers the side wall of the stacking layer and the exposed surface of the starting layer of the stacking layer and does not change the stepped shape of the opposite surface of the stacking layer; the free layer penetrates through part of the stacking layer to a starting layer of the stacking layer, and the side wall of the free layer is in a step shape; and the heavy metal layer penetrates through the free layer, the isolation layer and the starting layer of the stacking layer and is connected with the surface of the substrate. The invention provides a semiconductor structure and a forming method thereof, which can improve the integration density of an SOT-MRAM device and realize a multi-bit operation mode.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As a new type of memory, Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) has a fast write speed, which can reach sub-nanosecond write speed. The write current density is low, which can be 2 orders of magnitude lower than that of two-terminal devices based on spin transfer torque. In addition, SOT-MRAM has read-write separation, and the reading information is based on the tunnel magnetoresistance TMR of the magnetic tunnel junction (MTJ).

[0003] However, the current SOT-MRAM still has the problems of low device density, large occupied area and single operation mode. Therefore, it is necessary to provide a more effective and reliable technical solution to improve the integration density of SOT-MRAM devices and realize multi-bit operation mode. Summary of the invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can improve the integration density of a SOT-MRAM device and realize a multi-bit operation mode.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, forming a stacked layer on the surface of the substrate, the stacked layer comprising a plurality of first dielectric layers and a plurality of second dielectric layers stacked alternately in sequence, wherein the starting layer and the ending layer of the stacked layer are both first dielectric layers; forming an opening in the stacked layer to expose the starting layer of the stacked layer, the sidewall of the opening being in a stepped shape, wherein each group of adjacent first dielectric layers and second dielectric layers is a step; etching the second dielectric layer on the sidewall of the opening to form a recess, and forming a reference layer in the recess; forming an isolation layer on the sidewall and bottom of the opening, the isolation layer not changing the sidewall shape of the opening, and filling a free layer in the opening; forming a heavy metal layer in the free layer that penetrates the free layer, the isolation layer and the starting layer of the stacked layer and connects to the surface of the substrate.

[0006] In some embodiments of the present application, the material of the first dielectric layer is silicon oxide, and the material of the second dielectric layer is silicon nitride.

[0007] In some embodiments of the present application, the stacked number of layers of the plurality of first dielectric layers and the plurality of second dielectric layers is seven layers, and the stacking order of the plurality of first dielectric layers and the plurality of second dielectric layers starting from the substrate surface is a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer, a second silicon nitride layer, a third silicon oxide layer, a third silicon nitride layer and a fourth silicon oxide layer.

[0008] In some embodiments of the present application, a method for forming an opening in the stacked layer to expose the starting layer of the stacked layer includes: etching the fourth silicon oxide layer and the third silicon nitride layer to form a first opening; etching the third silicon oxide layer and the second silicon nitride layer at the bottom of the first opening to form a second opening, the width of the second opening being smaller than the width of the first opening; etching the second silicon oxide layer and the first silicon nitride layer at the bottom of the second opening to form a third opening, the width of the third opening being smaller than the width of the second opening, and the first opening, the second opening and the third opening constitute the opening.

[0009] In some embodiments of the present application, after forming the isolation layer and the free layer and before forming the heavy metal layer, it also includes: forming a mask layer on the surface of the fourth silicon oxide layer, the isolation layer and the free layer; etching the mask layer, the plurality of second dielectric layers and the first dielectric layer to expose the substrate surface to form a first groove; removing the second dielectric layer on the side wall of the first groove to expose the reference layer; and forming a metal layer connected to the reference layer in the first groove.

[0010] In some embodiments of the present application, the method for forming the semiconductor structure further includes: etching the metal layer and the heavy metal layer to form an isolation trench exposing the substrate; and forming a dielectric layer in the isolation trench to fill the isolation trench.

[0011] In some embodiments of the present application, a dual transistor structure is formed in the substrate, the heavy metal layer is electrically connected to the drain of one transistor of the dual transistor structure, and the metal layer is connected to the drain of the other transistor of the dual transistor structure.

[0012] Another aspect of the present application also provides a semiconductor structure, including: a substrate, the surface of the substrate includes at least one group of relatively arranged stacked layers, the opposite surfaces of the stacked layers are stepped, the stacked layers include a plurality of alternately stacked first dielectric layers and reference layers, wherein the starting layer and the ending layer of the stacked layers are both first dielectric layers, wherein each group of adjacent first dielectric layers and reference layers is a step; an isolation layer, covering the side walls of the stacked layers and the exposed surface of the starting layer of the stacked layers without changing the stepped shape of the opposite surfaces of the stacked layers; a free layer, penetrating part of the stacked layers to the starting layer of the stacked layers, the side walls of the free layer are stepped; a heavy metal layer, penetrating the free layer, the isolation layer and the starting layer of the stacked layers to connect to the surface of the substrate.

[0013] In some embodiments of the present application, the material of the first dielectric layer is silicon oxide.

[0014] In some embodiments of the present application, the stacking order of the plurality of first dielectric layers starting from the substrate surface is a first silicon oxide layer, a second silicon oxide layer, a third silicon oxide layer and a fourth silicon oxide layer.

[0015] In some embodiments of the present application, the semiconductor structure further includes: a metal layer, which penetrates through the stacked layers to the surface of the substrate, and a sidewall of a portion of the metal layer located in the reference layer protrudes beyond a sidewall of the first dielectric layer.

[0016] In some embodiments of the present application, the semiconductor structure further includes: a dielectric layer, penetrating the heavy metal layer and the metal layer.

[0017] In some embodiments of the present application, a dual transistor structure is formed in the substrate, the heavy metal layer is electrically connected to the drain of one transistor of the dual transistor structure, and the metal layer is connected to the drain of the other transistor of the dual transistor structure.

[0018] The present application provides a semiconductor structure and a method for forming the same. On the one hand, a standard MOSFET process and a magnetic tunnel junction (MTJ) technology are used for three-dimensional (3D) integration to form a 3D dual-transistor nMTJ (2TnMTJ) MRAM memory device, which can improve the integration density of SOT-MRAM devices. On the other hand, a free layer structure is made into a structure with multi-level step thickness, and different free layer thicknesses are used to control different MTJ structures to be written, thereby realizing a multi-level operation mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0020] Figures 1 to 12 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0022] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0023] Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is considered a promising candidate for the next-generation non-volatile memory because of its fast operation speed (<10 nanoseconds), high data retention (>10 years @ 815 degrees) and high endurance (>1E10).

[0024] However, in recent years, the new technology SOT-MRAM has been widely studied because it has higher write time, lower write energy, higher read time and lower read energy compared to STT-MRAM.

[0025] However, the current SOT-MRAM requires a larger area than STT-MRAM because it requires at least two transistors to operate. And the current SOT-MRAM has only one operation mode, and the operation is single. Based on this, the present application provides a semiconductor structure and a method for forming the same. On the one hand, a three-dimensional (3D) integration is performed using standard MOSFET process and magnetic tunnel junction (MTJ) technology to form a 3D dual-transistor nMTJ (2TnMTJ) MRAM memory device, which can improve the integration density of SOT-MRAM devices; on the other hand, the free layer structure is made into a structure with multi-level step thickness, and different free layer thicknesses are used to control different MTJ structures to be written, thereby realizing a multi-level operation mode.

[0026] Figures 1 to 12 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.

[0027] refer to Figure 1 As shown, a substrate 100 is provided. In some embodiments of the present application, a dual transistor structure 140 is formed in the substrate 100. The dual transistor structure refers to an active device structure composed of two transistors, that is, a 2T structure commonly referred to in semiconductor structures.

[0028] Continue to refer Figure 1 As shown, specifically, the base 100 includes: a semiconductor substrate 110, a well region 120 and an isolation structure 130 that penetrates the well region 120 and separates the well region 120 into a plurality of device regions. Specifically, the isolation structure 130 is distributed in the well region 120 along the x-direction and the z-direction to form a grid structure, each grid is a device unit, and a dual transistor structure 140 is formed in each device unit.

[0029] In some embodiments of the present application, the material of the semiconductor substrate 110 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0030] In some embodiments of the present application, the well region 120 is formed by performing an ion implantation process in the semiconductor substrate 110. The doping type of the well region 120 is, for example, P type.

[0031] In some embodiments of the present application, the isolation structure 130 penetrates the well region 120 and extends into the semiconductor substrate 110. The material of the isolation structure 130 is, for example, silicon oxide.

[0032] Continue to refer Figure 1 As shown, a plurality of gate structures extending along the z direction are also formed on the surface of the well region 120, and a source and a drain are respectively formed in the well region 120 on both sides of the gate structure. Specifically, a dual transistor structure 140 is formed in each device unit, and each dual transistor structure 140 includes two gate structures (gate structure 141 and gate structure 142 respectively), and the gate structure 141 and the gate structure 142 share a source 143, the gate structure 141 has a drain 144, and the gate structure 142 has a drain 145.

[0033] In some embodiments of the present application, the gate structure includes: a metal gate, a work function layer located on both sides and at the bottom of the metal gate, a capping layer located on both sides and at the bottom of the work function layer, a high dielectric constant layer located at the bottom of the capping layer, a gate oxide layer located at the bottom of the high dielectric constant layer, and sidewalls located on the side walls of the gate oxide layer, the high dielectric constant layer, and the capping layer.

[0034] Continue to refer Figure 1 As shown, a metal interconnection layer 150 is also formed above the well region 120, and the metal interconnection layer 150 includes: a first through hole 151 electrically connected to the source / drain; a first metal layer 152 electrically connected to the first through hole 151; a second through hole 153 electrically connected to a portion of the first metal layer 152 electrically connected to the drain 144 and the drain 145; and a second metal layer 154 electrically connected to the second through hole 153. The first metal layer 152 electrically connected to the source 143 is a source line (SL: source line).

[0035] It should be noted that the metal layer interconnection layer 150 is formed in the interlayer dielectric layer, and the interlayer dielectric layer is omitted in the drawings of this application to avoid the interlayer dielectric layer blocking other structures. It should also be noted that the substrate 100 is formed by a standard MOSFET process, so the detailed structure and formation steps of the substrate 100 are not repeated here.

[0036] refer to Figure 2 As shown, a stacked layer 200 is formed on the surface of the substrate 100, and the stacked layer 200 includes a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked in sequence, wherein the starting layer and the ending layer of the stacked layer 200 are both first dielectric layers.

[0037] In some embodiments of the present application, the material of the first dielectric layer is silicon oxide, and the material of the second dielectric layer is silicon nitride.

[0038] In some embodiments of the present application, the stacked number of layers of the plurality of first dielectric layers and the plurality of second dielectric layers is seven layers, and the stacking order of the plurality of first dielectric layers and the plurality of second dielectric layers starting from the surface of the substrate 100 is a first silicon oxide layer 201, a first silicon nitride layer 202, a second silicon oxide layer 203, a second silicon nitride layer 204, a third silicon oxide layer 205, a third silicon nitride layer 206 and a fourth silicon oxide layer 207.

[0039] In some embodiments of the present application, the method of forming the stacked layer 200 on the surface of the substrate 100 includes a chemical vapor deposition process or a physical vapor deposition process.

[0040] refer to Figure 3 As shown, an opening 210 is formed in the stacked layer 200 to expose the starting layer (ie, the first silicon oxide layer 201 ) of the stacked layer 200 , and the sidewall of the opening 210 is stepped, wherein each group of adjacent first dielectric layers and second dielectric layers is a step.

[0041] In some embodiments of the present application, a method for forming an opening 210 in the stacked layer 200 to expose a starting layer (i.e., the first silicon oxide layer 201) of the stacked layer 200 includes: etching the fourth silicon oxide layer 207 and the third silicon nitride layer 206 to form a first opening; etching the third silicon oxide layer 205 and the second silicon nitride layer 204 at the bottom of the first opening to form a second opening, wherein the width of the second opening is smaller than the width of the first opening; etching the second silicon oxide layer 203 and the first silicon nitride layer 202 at the bottom of the second opening to form a third opening, wherein the width of the third opening is smaller than the width of the second opening, and the first opening, the second opening, and the third opening constitute the opening 210.

[0042] refer to Figure 4 As shown, the second dielectric layer (ie, the first silicon nitride layer 202, the second silicon nitride layer 204 and the third silicon nitride layer 206) on the sidewall of the opening 210 is etched to form a recess, and a reference layer 220 is formed in the recess.

[0043] In some embodiments of the present application, the material of the reference layer 220 can be selected from one or more of Co, Ni, Fe, CoFe, CoNi, NiFe, CoFeNi, CoB, FeB, CoFeB, NiFeB, Pt, Pd, PtPd, FePt, Ir, Ru, Re, Rh, B, Zr, V, Nb, Ta, Mo, W, Cu, Ag, Au, Al and Hf. That is, it can be a single material or an alloy of several materials. Those skilled in the art can select a suitable material to form the reference layer 220 of the embodiment of the present application according to actual conditions.

[0044] refer to Figure 5 As shown, an isolation layer 230 is formed on the sidewall and bottom of the opening 210 , the isolation layer 230 does not change the shape of the sidewall of the opening 210 , and a free layer 240 is filled in the opening 210 , and the sidewall of the free layer 240 is also stepped.

[0045] In some embodiments of the present application, the material of the isolation layer 230 is selected from one or more of magnesium oxide, silicon oxide, silicon nitrogen compound, aluminum oxide, magnesium aluminum oxide, titanium oxide layer, tantalum oxide, calcium oxide and iron oxide. That is, it can be a single material or a mixture of several materials. Those skilled in the art can select a suitable material to form the isolation layer 230 of the embodiment of the present application according to actual conditions.

[0046] In some embodiments of the present application, the material of the free layer 240 is selected from one or more of Co, Fe, Ni, Pt, Pd, Ru, Ta, Cu, CoB, FeB, NiB, CoFe, NiFe, CoNi, CoFeNi, CoFeB, NiFeB, CoNiB, CoFeNiB, FePt, FePd, CoPt, CoPd, CoFePt, CoFePd, FePtPd, CoPtPd and CoFePtPd. That is, it can be a single material or an alloy of several materials. Those skilled in the art can select a suitable material to form the free layer 240 of the embodiment of the present application according to actual conditions.

[0047] In some embodiments of the present application, the method for forming the reference layer 220, the isolation layer 230 and the free layer 240 can be any method in the prior art, such as magnetron sputtering, physical vapor deposition or molecular beam epitaxial deposition, etc. Those skilled in the art can select appropriate methods to set each film layer according to actual conditions.

[0048] refer to Figure 6 As shown, a mask layer 251 is formed on the surface of the fourth silicon oxide layer 207 (ie, the end layer of the stacked layer 200 ), the isolation layer 230 , and the free layer 240 .

[0049] refer to Figure 7 As shown, the mask layer 251 and the stacked layer 200 are etched until the surface of the substrate 100 is exposed to form a first groove 252 .

[0050] refer to Figure 8 As shown, the second dielectric layer (ie, the first silicon nitride layer 202 , the second silicon nitride layer 204 and the third silicon nitride layer 206 ) on the sidewall of the first trench 252 is removed to expose the reference layer 220 .

[0051] refer to Fig. 9 As shown, a metal layer 260 connected to the reference layer 220 is formed in the first groove 252 , and then a portion of the metal layer 260 higher than the surface of the mask layer 251 is removed by grinding, and the metal layer 260 is made flush with the mask layer 251 .

[0052] refer to Fig.10 As shown, a heavy metal layer 270 is formed in the free layer 240, penetrating the free layer 240, the isolation layer 230 and the starting layer (i.e., the first silicon oxide layer 201) of the stacked layer 200 and connected to the surface of the substrate 100. The heavy metal layer 270 is electrically connected to the drain of one transistor of the dual transistor structure, and the metal layer 260 is connected to the drain of the other transistor of the dual transistor structure.

[0053] In some embodiments of the present application, the material of the heavy metal layer 270 may include at least one of Pt, Ta, W, Ru, Ir, Ti, and Bi.

[0054] refer to Fig.11 As shown, in some embodiments of the present application, the method for forming the semiconductor structure further includes: etching the metal layer 260 and the heavy metal layer 270 to form an isolation trench exposing the substrate 100; and forming a dielectric layer 280 filling the isolation trench in the isolation trench.

[0055] The projection position of the dielectric layer 280 on the surface of the well region 120 roughly corresponds to the position of the isolation structure 130. The dielectric layer 280 is distributed in the x-direction and the z-direction to form a grid structure like the isolation structure 130, each grid includes a memory cell 290, and each memory cell 290 includes a reference layer 220, an isolation layer 230, a free layer 240, a metal layer 260 and a heavy metal layer 270.

[0056] refer to Fig.12 A contact structure 291 electrically connected to the heavy metal layer 270 and a third metal layer 292 extending along the x direction and electrically connected to the contact structure 291 in the x direction are formed on the heavy metal layer 270 .

[0057] In the technical solution of the present application, the reference layer 220 is magnetized, and the magnetization direction is in the x direction (for example, Fig.12 The free layer 240 is also magnetized, and the magnetization direction is in the x direction (for example, the Fig.12 The magnetization direction (left direction or right direction) of the free layer 240 can be changed by the current in the heavy metal layer 270. By inputting the write current Iwrite into the heavy metal layer 270, the magnetization direction of the free layer 240 is flipped, so that the relative position relationship between the magnetization directions of the free layer 240 and the reference layer 220 is changed, so that the resistance of the memory cell is different, and data writing is realized.

[0058] Continue to refer Fig.12 As shown, with one (specifically, the attached Fig.12 The memory cell 290 and the dual transistor structure 150 corresponding to the one in the lower right corner of the figure are used as examples. Line A is for reading, and line B is for writing and erasing. The two transistors in the dual transistor structure 150 are used to control reading and writing respectively. During the read operation, the transistor passing through line A is turned on, and the current passes through the MTJ structure. During the write operation, the transistor on line B is turned on, and the current passes through the heavy metal layer 270. Among them, the third metal layer 292 is a bit line (BL), the metal gate passing through line B is a word line (WL), and the metal gate passing through line A is a read word line (RWL: read word line).

[0059] Table 1: Operational Configuration of Memory Cell 290

[0060] WL RWH SL BL Write VDD VSS VSS Vwrite wipe VDD VSS Verase VSS read VSS VDD VSS Vread

[0061] As shown in Table 1, during a write operation, the word line WL is connected to VDD, the read word line RWL is connected to VSS, the source line SL is connected to VSS, and the bit line BL is connected to Vwrite. During an erase operation, the word line WL is connected to VDD, the read word line RWL is connected to VSS, the source line SL is connected to Verase, and the bit line BL is connected to VSS. During a read operation, the word line WL is connected to VSS, the read word line RWL is connected to VDD, the source line SL is connected to VSS, and the bit line BL is connected to Vread.

[0062] The technical solution of the present application utilizes standard MOSFET process and magnetic tunnel junction (MTJ) technology for three-dimensional (3D) integration to form a 3D dual-transistor nMTJ (2TnMTJ) MRAM memory device, which can improve the integration density of SOT-MRAM devices.

[0063] Continue to refer Fig.12As shown, in each memory cell 290, the thickness (dimension in the x direction) of the free layer 240 changes stepwise in the y direction to attach Fig.12 For example, the thickness of the free layer 240 increases in three steps from bottom to top, and the free layer 240 has three thickness steps. Due to the different thicknesses, the current thresholds for the magnetization direction reversal of the free layer 240 of different thickness steps are different, so the free layer 240 of three or more thickness steps of the present application can achieve multi-level operation. The reference layer 220, the isolation layer 230 and the free layer 240 constitute an MTJ structure, and the reference layers 220 of different thicknesses and the MTJ structures they constitute are marked as MTJ0, MTJ1, and MTJ2 from bottom to top.

[0064] Table 2: Multi-level operation states of memory cell 290

[0065]

[0066]

[0067] As shown in Table 2, when the magnetization direction of the MTJ structure is reversed, its resistance value changes from high resistance state RH to low resistance state R L Therefore, according to the magnetization direction reversal of different MTJ structures, the memory cell can generate different Bit states. When different currents flow through the heavy metal layer 270, different MTJ structures can be flipped under different currents because of the different thicknesses of the free layer 240. The MTJ structure with a thinner free layer 240 will be easier to flip, thereby changing the resistance from R H Transition to R L Since the resistance values ​​of all MTJs are read simultaneously during reading, and since the MTJs are connected in parallel, different bits are obtained by connecting the resistance states of different MTJs in parallel. For example, the three MTJ structures of the present application can obtain a total of four bits.

[0068] The technical solution of the present application manufactures the free layer structure into a structure with multi-level step thickness, and uses different free layer thicknesses to control different MTJ structures to be written, thereby realizing a multi-level operation mode.

[0069] The present application provides a method for forming a semiconductor structure. On the one hand, a standard MOSFET process and a magnetic tunnel junction (MTJ) technology are used for three-dimensional (3D) integration to form a 3D dual-transistor nMTJ (2TnMTJ) MRAM memory device, which can improve the integration density of SOT-MRAM devices; on the other hand, a free layer structure is made into a structure with multi-level step thickness, and different free layer thicknesses are used to control different MTJ structures to be written, thereby realizing a multi-level operation mode.

[0070] The embodiment of the present application also provides a semiconductor structure, referring to Fig.12 As shown, it includes: a substrate 100, the surface of the substrate 100 includes at least one group of stacked layers 200 arranged oppositely, the opposite surfaces of the stacked layers 200 are stepped, and the stacked layers 200 include a plurality of alternately stacked first dielectric layers and reference layers 220, wherein the starting layer and the ending layer of the stacked layers 200 are both first dielectric layers, wherein each group of adjacent first dielectric layers and reference layers is a layer of steps; an isolation layer 230, covering the side walls of the stacked layers 200 and the exposed surface of the starting layer of the stacked layers 200 without changing the stepped shape of the opposite surfaces of the stacked layers 200; a free layer 240, penetrating part of the stacked layers 200 to the starting layer of the stacked layers 200, and the side walls of the free layer 240 are stepped; a heavy metal layer 270, penetrating the free layer 240, the isolation layer 230 and the starting layer of the stacked layers 200 to connect to the surface of the substrate 100.

[0071] In some embodiments of the present application, a dual transistor structure 140 is formed in the substrate 100. The dual transistor structure refers to an active device structure composed of two transistors, which is also known as a 2T structure in semiconductor structures.

[0072] Specifically, refer to Fig.12 As shown, the base 100 includes: a semiconductor substrate 110, a well region 120 and an isolation structure 130 that penetrates the well region 120 and separates the well region 120 into a plurality of device regions. Specifically, the isolation structure 130 is distributed in the well region 120 along the x-direction and the z-direction to form a grid structure, each grid is a device unit, and a dual transistor structure 140 is formed in each device unit.

[0073] In some embodiments of the present application, the material of the semiconductor substrate 110 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0074] In some embodiments of the present application, the well region 120 is formed by performing an ion implantation process in the semiconductor substrate 110. The doping type of the well region 120 is, for example, P type.

[0075] In some embodiments of the present application, the isolation structure 130 penetrates the well region 120 and extends into the semiconductor substrate 110. The material of the isolation structure 130 is, for example, silicon oxide.

[0076] Continue to refer Fig.12 As shown, a plurality of gate structures extending along the z direction are also formed on the surface of the well region 120, and a source and a drain are respectively formed in the well region 120 on both sides of the gate structure. Specifically, a dual transistor structure 140 is formed in each device unit, and each dual transistor structure 140 includes two gate structures (gate structure 141 and gate structure 142 respectively), and the gate structure 141 and the gate structure 142 share a source 143, the gate structure 141 has a drain 144, and the gate structure 142 has a drain 145.

[0077] In some embodiments of the present application, the gate structure includes: a metal gate, a work function layer located on both sides and at the bottom of the metal gate, a capping layer located on both sides and at the bottom of the work function layer, a high dielectric constant layer located at the bottom of the capping layer, a gate oxide layer located at the bottom of the high dielectric constant layer, and sidewalls located on the side walls of the gate oxide layer, the high dielectric constant layer, and the capping layer.

[0078] Continue to refer Fig.12 As shown, a metal interconnection layer 150 is also formed above the well region 120, and the metal interconnection layer 150 includes: a first through hole 151 electrically connected to the source / drain; a first metal layer 152 electrically connected to the first through hole 151; a second through hole 153 electrically connected to a portion of the first metal layer 152 electrically connected to the drain 144 and the drain 145; and a second metal layer 154 electrically connected to the second through hole 153. The first metal layer 152 electrically connected to the source 143 is a source line (SL: source line).

[0079] It should be noted that the metal layer interconnection layer 150 is formed in the interlayer dielectric layer, and the interlayer dielectric layer is omitted in the drawings of this application to avoid the interlayer dielectric layer blocking other structures. It should also be noted that the substrate 100 is formed by a standard MOSFET process, so the detailed structure and formation steps of the substrate 100 are not repeated here.

[0080] Continue to refer Fig.12 As shown, the surface of the substrate 100 includes at least one group of relatively arranged stacked layers 200, the opposite surfaces of the stacked layers 200 are stepped, and the stacked layers 200 include a plurality of alternately stacked first dielectric layers and reference layers 220, wherein the starting layer and the ending layer of the stacked layers 200 are both first dielectric layers, and each group of adjacent first dielectric layers and reference layers is a layer of steps.

[0081] In some embodiments of the present application, the material of the first dielectric layer is silicon oxide.

[0082] In some embodiments of the present application, the stacking order of the plurality of first dielectric layers starting from the surface of the substrate 100 is a first silicon oxide layer 201 , a second silicon oxide layer 203 , a third silicon oxide layer 205 and a fourth silicon oxide layer 207 .

[0083] In some embodiments of the present application, the material of the reference layer 220 can be selected from one or more of Co, Ni, Fe, CoFe, CoNi, NiFe, CoFeNi, CoB, FeB, CoFeB, NiFeB, Pt, Pd, PtPd, FePt, Ir, Ru, Re, Rh, B, Zr, V, Nb, Ta, Mo, W, Cu, Ag, Au, Al and Hf. That is, it can be a single material or an alloy of several materials. Those skilled in the art can select a suitable material to form the reference layer 220 of the embodiment of the present application according to actual conditions.

[0084] Continue to refer Fig.12 As shown, the isolation layer 230 covers the sidewalls of the stacked layer 200 and the exposed surface of the starting layer of the stacked layer 200 without changing the stepped shape of the opposite surface of the stacked layer 200 .

[0085] In some embodiments of the present application, the material of the isolation layer 230 is selected from one or more of magnesium oxide, silicon oxide, silicon nitrogen compound, aluminum oxide, magnesium aluminum oxide, titanium oxide layer, tantalum oxide, calcium oxide and iron oxide. That is, it can be a single material or a mixture of several materials. Those skilled in the art can select a suitable material to form the isolation layer 230 of the embodiment of the present application according to actual conditions.

[0086] Continue to refer Fig.12 As shown, the free layer 240 penetrates part of the stacked layer 200 to the starting layer of the stacked layer 200 , and the sidewall of the free layer 240 is stepped.

[0087] In some embodiments of the present application, the material of the free layer 240 is selected from one or more of Co, Fe, Ni, Pt, Pd, Ru, Ta, Cu, CoB, FeB, NiB, CoFe, NiFe, CoNi, CoFeNi, CoFeB, NiFeB, CoNiB, CoFeNiB, FePt, FePd, CoPt, CoPd, CoFePt, CoFePd, FePtPd, CoPtPd and CoFePtPd. That is, it can be a single material or an alloy of several materials. Those skilled in the art can select a suitable material to form the free layer 240 of the embodiment of the present application according to actual conditions.

[0088] Continue to refer Fig.12As shown, a mask layer 251 is formed on the surface of the fourth silicon oxide layer 207 (ie, the end layer of the stacked layer 200 ), the isolation layer 230 , and the free layer 240 . The mask layer 251 is used to protect the memory cell 290 located below the mask layer 251 .

[0089] Continue to refer Fig.12 As shown, in some embodiments of the present application, the semiconductor structure also includes: a metal layer 260, which penetrates the mask layer 251 and the stacked layer 200 to the surface of the substrate 100, and the sidewall of the portion of the metal layer 260 located in the reference layer 220 protrudes from the sidewall of the first dielectric layer.

[0090] Continue to refer Fig.12 As shown, the heavy metal layer 270 penetrates the mask layer 251, the free layer 240, the isolation layer 230 and the starting layer of the stacked layer 200 to connect to the surface of the substrate 100. The heavy metal layer 270 is electrically connected to the drain of one transistor of the dual transistor structure 140, and the metal layer 260 is connected to the drain of the other transistor of the dual transistor structure 140.

[0091] In some embodiments of the present application, the material of the heavy metal layer 270 may include at least one of Pt, Ta, W, Ru, Ir, Ti, and Bi.

[0092] Continue to refer Fig.12 As shown, in some embodiments of the present application, the semiconductor structure further includes: a dielectric layer 280, which penetrates the heavy metal layer 270 and the metal layer 260. The projection position of the dielectric layer 280 on the surface of the well region 120 roughly corresponds to the position of the isolation structure 130. The dielectric layer 280 is distributed in the x-direction and the z-direction to form a grid structure like the isolation structure 130, each grid includes a memory cell 290, and each memory cell 290 includes a reference layer 220, an isolation layer 230, a free layer 240, a metal layer 260 and a heavy metal layer 270.

[0093] Continue to refer Fig.12 A contact structure 291 electrically connected to the heavy metal layer 270 and a third metal layer 292 extending along the x direction and electrically connected to the contact structure 291 in the x direction are formed on the heavy metal layer 270 .

[0094] In the technical solution of the present application, the reference layer 220 is magnetized, and the magnetization direction is in the x direction (for example, Fig.12 The free layer 240 is also magnetized, and the magnetization direction is in the x direction (for example, the Fig.12The magnetization direction (left direction or right direction) of the free layer 240 can be changed by the current in the heavy metal layer 270. By inputting the write current Iwrite into the heavy metal layer 270, the magnetization direction of the free layer 240 is flipped, so that the relative position relationship between the magnetization directions of the free layer 240 and the reference layer 220 is changed, so that the resistance of the memory cell is different, and data writing is realized.

[0095] Continue to refer Fig.12 As shown, with one (specifically, the attached Fig.12 The memory cell 290 and the dual transistor structure 150 corresponding to the one in the lower right corner of the figure are used as examples. Line A is for reading, and line B is for writing and erasing. The two transistors in the dual transistor structure 150 are used to control reading and writing respectively. During the read operation, the transistor passing through line A is turned on, and the current passes through the MTJ structure. During the write operation, the transistor on line B is turned on, and the current passes through the heavy metal layer 270. Among them, the third metal layer 292 is a bit line (BL), the metal gate passing through line B is a word line (WL), and the metal gate passing through line A is a read word line (RWL: read word line).

[0096] The technical solution of the present application utilizes standard MOSFET process and magnetic tunnel junction (MTJ) technology for three-dimensional (3D) integration to form a 3D dual-transistor nMTJ (2TnMTJ) MRAM memory device, which can improve the integration density of SOT-MRAM devices.

[0097] Continue to refer Fig.12 As shown, in each memory cell 290, the thickness (dimension in the x-direction) of the free layer 240 changes stepwise in the z-direction to attach Fig.12 For example, the thickness of the free layer 240 increases in three steps from bottom to top, and the free layer 240 has three thickness steps. Due to the different thicknesses, the current thresholds for the magnetization direction reversal of the free layer 240 of different thickness steps are different, so the free layer 240 of three or more thickness steps of the present application can achieve multi-level operation. The reference layer 220, the isolation layer 230 and the free layer 240 constitute an MTJ structure, and the reference layers 220 of different thicknesses and the MTJ structures they constitute are marked as MTJ0, MTJ1, and MTJ2 from bottom to top.

[0098] The technical solution of the present application manufactures the free layer structure into a structure with multi-level step thickness, and uses different free layer thicknesses to control different MTJ structures to be written, thereby realizing a multi-level operation mode.

[0099] The present application provides a semiconductor structure and a method for forming the same. On the one hand, a standard MOSFET process and a magnetic tunnel junction (MTJ) technology are used for three-dimensional (3D) integration to form a 3D dual-transistor nMTJ (2TnMTJ) MRAM memory device, which can improve the integration density of SOT-MRAM devices. On the other hand, a free layer structure is made into a structure with multi-level step thickness, and different free layer thicknesses are used to control different MTJ structures to be written, thereby realizing a multi-level operation mode.

[0100] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0101] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there are no intermediate elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0102] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present application, the first element in some embodiments can be referred to as the second element in other embodiments.

[0103] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, forming a stacked layer on the surface of the substrate, the stacked layer comprising a plurality of first dielectric layers and a plurality of second dielectric layers stacked alternately in sequence, wherein the starting layer and the ending layer of the stacked layer are both the first dielectric layer; An opening is formed in the stacked layer to expose the starting layer of the stacked layer, wherein the sidewall of the opening is in a step shape, wherein each group of adjacent first dielectric layers and second dielectric layers is a step; Etching the second dielectric layer on the sidewall of the opening to form a recess, and forming a reference layer in the recess; forming an isolation layer on the sidewall and bottom of the opening, wherein the isolation layer does not change the shape of the sidewall of the opening, and filling a free layer in the opening; An initiation layer is formed in the free layer, penetrating the free layer, the isolation layer and the stacked layer, and connected to the heavy metal layer on the surface of the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer is silicon oxide, and the material of the second dielectric layer is silicon nitride.

3. The method for forming a semiconductor structure according to claim 2, wherein: The stacking number of the first dielectric layers and the second dielectric layers is seven layers, and the stacking order of the first dielectric layers and the second dielectric layers starting from the substrate surface is a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer, a second silicon nitride layer, a third silicon oxide layer, a third silicon nitride layer and a fourth silicon oxide layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method of forming an opening in the stacked layer exposing the starting layer of the stacked layer comprises: Etching the fourth silicon oxide layer and the third silicon nitride layer to form a first opening; Etching the third silicon oxide layer and the second silicon nitride layer at the bottom of the first opening to form a second opening, wherein the width of the second opening is smaller than the width of the first opening; The second silicon oxide layer and the first silicon nitride layer at the bottom of the second opening are etched to form a third opening, the width of the third opening is smaller than the width of the second opening, and the first opening, the second opening and the third opening constitute the opening.

5. The method for forming a semiconductor structure according to claim 3, wherein: After forming the isolation layer and the free layer and before forming the heavy metal layer, the method further includes: forming a mask layer on the surfaces of the fourth silicon oxide layer, the isolation layer and the free layer; Etching the mask layer, the plurality of second dielectric layers and the first dielectric layer until the surface of the substrate is exposed to form a first groove; removing the second dielectric layer on the sidewall of the first trench to expose the reference layer; A metal layer connected to the reference layer is formed in the first trench.

6. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: Etching the metal layer and the heavy metal layer to form an isolation trench exposing the substrate; A dielectric layer filling the isolation trench is formed in the isolation trench.

7. The method for forming a semiconductor structure according to claim 5, wherein: A dual transistor structure is formed in the substrate, the heavy metal layer is electrically connected to the drain of one transistor of the dual transistor structure, and the metal layer is connected to the drain of the other transistor of the dual transistor structure.

8. A semiconductor structure, characterized in that: include: A substrate, wherein the surface of the substrate comprises at least one group of stacked layers arranged opposite to each other, the opposite surfaces of the stacked layers are stepped, the stacked layers comprise a plurality of alternately stacked first dielectric layers and reference layers, wherein the starting layer and the ending layer of the stacked layers are both first dielectric layers, and each group of adjacent first dielectric layers and reference layers forms a step; an isolation layer covering the sidewalls of the stacked layers and the exposed surface of the starting layer of the stacked layers without changing the stepped shape of the opposite surface of the stacked layers; A free layer penetrates part of the stacked layers to the starting layer of the stacked layers, and the sidewall of the free layer is stepped; a heavy metal layer penetrates the free layer, the isolation layer and the starting layer of the stacked layers and is connected to the substrate surface.

9. The semiconductor structure according to claim 8, characterized in that The material of the first dielectric layer is silicon oxide.

10. The semiconductor structure according to claim 9, wherein: The stacking order of the plurality of first dielectric layers starting from the substrate surface is a first silicon oxide layer, a second silicon oxide layer, a third silicon oxide layer and a fourth silicon oxide layer.

11. The semiconductor structure according to claim 8, wherein: Also includes: The metal layer penetrates through the stacked layers to the surface of the substrate, and a sidewall of a portion of the metal layer located in the reference layer protrudes beyond a sidewall of the first dielectric layer.

12. The semiconductor structure according to claim 11, wherein: Also includes: The dielectric layer penetrates the heavy metal layer and the metal layer.

13. The semiconductor structure according to claim 12, wherein: A dual transistor structure is formed in the substrate, the heavy metal layer is electrically connected to the drain of one transistor of the dual transistor structure, and the metal layer is connected to the drain of the other transistor of the dual transistor structure.

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