Wafer-level hybrid bonding radio frequency circuit

Abstract

The present disclosure provides a method of fabricating a radio frequency (RF) circuit using a three-dimensional (3D) hybrid wafer level bonded wafer. In one aspect, a first bottom silicon-on-insulator (SOI) wafer and a second top SOI wafer are provided. Then, a complementary metal oxide semiconductor process is performed on both the first SOI wafer and the second SOI wafer to fabricate transistors and form RF circuits on each wafer. A second wafer is then bonded to the first wafer to electrically couple the RF circuits together. In one aspect, the 3D manufacturing method enables RF circuits to be designed using transistor structures stacked in a three-dimensional (3D) folded configuration using a plurality of wafers. In one aspect, the RF circuit uses mirror image portions that are folded together during a wafer bonding process. In another aspect, the RF circuit uses an asymmetric portion between the top wafer and the bottom wafer.

Description

[0001] Related Applications

[0002] This application claims the benefit of provisional patent application serial number 63 / 394,798, filed on August 3, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of integrated circuit manufacturing, and in particular to wafer-level hybrid bonding implementations of radio frequency circuits. Background Art

[0004] There is a continuing need for improvements in die size and performance of radio frequency (RF) products. Smaller die sizes allow for smaller devices, faster processing speeds, and lower power consumption for RF products. Previously, RF silicon-on-insulator technology has achieved die size and performance improvements by using more advanced complementary metal oxide semiconductor factories, processes, and tools.

[0005] However, reducing the die size of RF products presents some challenges. As the die size decreases, parasitic capacitance and resistance become more prominent because the components are now closer together. This may have a negative impact on the signal integrity, frequency response, and noise of the RF product. The reduced die size also leads to reduced thermal management efficiency because the heat generated by the RF components has a smaller area to dissipate. The reduced die size requires smaller or tighter tolerances, which requires more complex control of the manufacturing process. Therefore, these and other effects of simply reducing the die size typically increase the complexity and cost of the RF product. Therefore, it is desirable to provide alternative solutions to address these and other problems caused by the reduction in die size while maintaining the performance of the RF product. Summary of the invention

[0006] Various embodiments of the present disclosure provide a method for manufacturing RF circuits for radio frequency (RF) products using three-dimensional hybrid wafer-level bonded wafers. In one aspect, a first bottom silicon-on-insulator (SOI) wafer and a second top SOI wafer are provided. Complementary metal oxide semiconductor (CMOS) processing is then performed on both the first SOI wafer and the second SOI wafer to manufacture transistors and form RF circuits on each wafer. The second wafer is then bonded to the first wafer to electrically couple the RF circuits together. The use of SOI wafers and bonding at the wafer level enables minimum spacing and shortest interconnects in RF circuits, which can significantly reduce the layout size required for RF circuits without compromising the performance of RF circuits. Additionally, the use of CMOS processing allows the method for RF circuits to be compatible with conventional back-end processes known to logic circuits (such as metallization, passivation, packaging, etc.).

[0007] On the other hand, an RF circuit for an RF product is designed using a transistor structure stacked in a three-dimensional (3D) folded configuration using multiple wafers. In one aspect, the RF circuit uses a mirrored portion that is folded together during a wafer bonding process. On the other hand, the RF circuit uses an asymmetric portion between the top wafer and the bottom wafer to take advantage of the difference in the final structure between the wafers. On each wafer, the transistors of the RF circuit are fabricated on a two-dimensional (2D) layer of the wafer. Then, the wafers are bonded together so that the transistors on each wafer are opposite to each other in a folded manner and electrically coupled to form a folded RF circuit. By designing the RF circuit in this folded manner and stacking the wafers in a 3D manner, the third dimension (e.g., height) provides further degrees of freedom, in which the RF circuit is laid out with less space and improved performance. For example, in one aspect, two SOI wafers are stacked, which significantly reduces the area of ​​at least one of the RF circuits. Field effect transistors (FETs) are replicated on two SOI wafers, which allows the total channel width and spacing of the FETs to be significantly reduced and still maintain performance.

[0008] According to one aspect, a method of manufacturing an RF product includes: providing a first wafer; providing a first transistor on the first wafer; providing a second wafer; providing a second transistor on the second wafer; and bonding the second wafer to the first wafer to form a bonded wafer, wherein the second transistor is opposite to the first transistor.

[0009] According to another exemplary aspect, a radio frequency (RF) product includes: a first RF circuit located on a first layer of a substrate; a second RF circuit located on a second layer opposite to the first layer; and an interface layer located between the first layer and the second layer and including at least one through-hole electrically connected to the first RF circuit and the second RF circuit.

[0010] Those skilled in the art will understand the scope of the present disclosure and recognize additional aspects thereof after reading the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figures 1A to 1G An exemplary process flow for fabricating radio frequency (RF) circuits using three-dimensional hybrid wafer-level bonding wafers according to the present disclosure is illustrated.

[0013] Figure 2A is a diagram showing a bottom wafer substrate according to the present disclosure.

[0014] Figure 2Bis a diagram showing a top wafer substrate according to the present disclosure.

[0015] Figure 3 is a diagram showing an n-type field effect transistor (n-FET) region of block 3 according to the present disclosure.

[0016] Figure 4 is a diagram showing the n-FET region of block 4 according to the present disclosure.

[0017] Figure 5 is a diagram showing a top wafer being flipped and bonded to a bottom wafer according to the present disclosure.

[0018] Fig. 6A and Figure 6B is a diagram of a hybrid bonding process according to a summary of the present disclosure.

[0019] Figure 7 is a diagram showing the resulting structure after hybrid bonding according to the present disclosure.

[0020] Figure 8 is a diagram showing a structure after a silicon handle wafer is removed from a top wafer according to the present disclosure.

[0021] Fig. 9 is a diagram showing the addition of an additional layer to the backside of the top wafer to allow electrical access to circuits on both the top and bottom wafers in accordance with the present disclosure.

[0022] Fig.10 RF circuits utilizing multiple FETs stacked in series to achieve larger signals typical in RF applications are illustrated.

[0023] Fig.11A and Fig. 11B An exemplary RF circuit according to the present disclosure is illustrated, which is fabricated by the method described herein and has a mirrored FET stack disposed on a top wafer and a bottom wafer opposite to each other and connected in a 3D folded structure.

[0024] Fig. 12A and Fig. 12B An alternative exemplary RF circuit according to the present disclosure is illustrated, which is manufactured by the method described herein and has a relative FET stack of three FETs connected by folding together in 3D, but has a different configuration to exploit the difference between the top wafer and the bottom wafer.

[0025] Fig.13A and Fig. 13B According to the present disclosure, a similar FIG. 12 shows another exemplary RF circuit but with an opposing FET stack of four FETs.

[0026] Fig.14 Illustrated Fig.10 An exemplary layout of the RF circuit is shown.

[0027] Fig.15 and Fig.16 It shows that according to the present disclosure Fig.11A and FIG. 11B to FIG. 13A and Fig. 13B An exemplary side-by-side layout of an RF circuit with opposing FET stacks that can be connected by folding together in 3D is shown.

[0028] Fig.17 An exemplary cross-section of a structure resulting from the hybrid wafer bonding process described herein is shown in accordance with the present disclosure.

[0029] Fig.18A and Fig.18B An RF circuit including a plurality of FETs stacked in series and an enhancement circuit according to the present disclosure is illustrated.

[0030] Fig.19 An exemplary layout of the RF circuit shown in FIG. 18 is illustrated.

[0031] Fig. 20A and Fig. 20B as well as Fig.21A and Fig.21B A corresponding RF circuit with relative FET stacks, linearity improvement circuitry, and voltage processing circuitry that may be connected by folding together in 3D according to a hybrid wafer bonding process as described in the present disclosure is shown.

[0032] Fig.22A and Fig. 22B It shows that according to the present disclosure Fig. 20A and Fig. 20B as well as Fig.21A and Fig.21B An exemplary side-by-side layout of RF circuits is shown.

[0033] Fig.23A Shown is a side view of die singulated from a single wafer.

[0034] Fig. 23B A side-by-side view of dies from a bottom wafer and a top wafer is illustrated to illustrate the reduced layout area in accordance with the present disclosure.

[0035] Fig.24A Shows Fig.23A The same view provided in and reproduced to provide Fig. 24B comparison.

[0036] Fig. 24BAn exemplary layout of an RF product having an RF circuit for a switch fabricated using the hybrid wafer bonding process described herein and having a reduced layout area according to the present disclosure is shown.

[0037] Fig.25 An exemplary user element is shown that includes RF circuitry including, but not limited to FIG. 11A to FIG. 13B , Fig.15 and Fig.16 , FIG. 20A to FIG. 22B , Fig. 23B and Fig. 24B RF circuit schematic and layout shown. DETAILED DESCRIPTION

[0038] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0039] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0040] It should be understood that when an element such as a layer, region or substrate is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extend to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as "above another element" or "extending above another element", it can be directly above another element or directly extend above another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly above another element" or "extending directly above another element", there is no intermediate element. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0041] Relative terms such as "below" or "above" or "up" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0042] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a, an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that when used herein, the terms "comprises, comprising" and / or include, including specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0044] Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. In this way, the actual size of layers and elements may be different, and it is expected that the shapes may be different from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. For example, a region illustrated or described as a square or rectangle may have circular or curved features, and a region shown as a straight line may have some irregularities. Therefore, the region illustrated in the drawings is schematic, and its shape is not intended to illustrate the precise shape of the region of the device, and is not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be enlarged relative to other structures or regions, and therefore a structure or region is provided to illustrate the general structure of this theme, and may be drawn to scale or may not be drawn to scale. Common elements between the accompanying drawings may be shown in this article with common element numbers, and are not described subsequently.

[0045] Figures 1A to 1G A flow chart 100 describing a process for fabricating a radio frequency (RF) circuit using three-dimensional hybrid wafer-level bonding is illustrated. Figure 2A and Figures 2B to 9 An exemplary manufacturing process of an RF circuit using three-dimensional hybrid wafer-level bonding according to the process shown in flowchart 100 is illustrated. Figure 2A and Figures 2B to 9 can be better understood when described with a diagram Figures 1A to 1G .

[0046] First reference Figure 1A , describing steps 102 and 104 of flowchart 100. In this regard, a first wafer (hereinafter referred to as a bottom wafer substrate 200) and a second wafer (hereinafter referred to as a top wafer substrate 202) are provided.

[0047] like Figure 2A As shown, the bottom wafer substrate 200 may initially be an RF silicon on insulator (RFSOI) starting wafer, which includes a first silicon handle wafer 204 having a high resistivity greater than 3000Ω⋅cm, 2000Ω⋅cm, or 1500Ω⋅cm, and a first polysilicon layer 206 having a thickness in the range of 3μm to 1μm, 2.5μm to 1.5μm, or 2.25μm to 1.75μm, which is used as an epitaxially grown trap-rich layer for mitigating substrate-induced distortion. In addition, the bottom wafer substrate 200 includes a first buried oxide (BOX) layer 208, which may have a thickness in the range of 200A to 4000A, 3000A to 7000A, or 1000A to 10000A and may be as thick as 1μm. The first top silicon device layer 210 is included as part of the bottom wafer substrate 200 and may have a thickness in the range of 600A to 1500A, 500A to 2000A, or 400A to 3000A. In certain embodiments, the polysilicon (trap rich) layer 206 may be optionally excluded to reduce cost.

[0048] Figure 2B As shown in Figure 1A 100 of the present invention is a cross-sectional view of a top wafer substrate 202 used in step 104 of the manufacturing process described in flowchart 100 of FIG. The top wafer substrate 202 can be an SOI wafer. In an embodiment, the top wafer substrate 202 is a p-type silicon wafer. The top wafer substrate 202 includes a second silicon handle wafer 212, a second BOX layer 214, and a second top silicon device layer 216. Figure 2B As shown, the second silicon handle wafer 212 may have a resistivity in the range of 1 Ω⋅cm to 50 Ω⋅cm, 0.5 Ω⋅cm to 100 Ω⋅cm, or 0.1 Ω⋅cm to 200 Ω⋅cm. The second BOX layer 214 may have a thickness in the range of 2000 Å to 4000 Å, 1000 Å to 5000 Å, or 500 Å to 10000 Å, or may be as thick as 1 μm. Additionally, the second top silicon device layer 216 may have a thickness of 600 Å to 1500 Å, 500 Å to 2000 Å, or 400 Å to 3000 Å.

[0049] Reference now Figure 1B , describing step 106 of flowchart 100. In this regard, Figure 1B Describes the use of complementary metal oxide semiconductor (CMOS) process technology to manufacture such Figure 3 A bottom wafer 300 is shown. Figure 3 300 as seen after processing using CMOS process technology. This is done using front-end device processes and back-end metallization processes known to those skilled in the art. Figure 1A , Figure 2A and Figure 2B As mentioned Figure 1B and Figure 3 All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0050] In this regard, the bottom wafer 300 may include transistors, such as a first transistor Q1 and a second transistor Q2, which may be, for example, n-type field effect transistors (n-FETs). Although only n-FETs are shown as forming part of the bottom wafer 300, the scope of the present application is not limited thereto. Appropriately constructed p-type field effect transistors (p-FETs) and diodes, capacitors, resistors, and inductors may also be formed as forming part of the bottom wafer 300, which are not shown here.

[0051] A first barrier layer 302 is formed over the first BOX layer 208 and the first and second FETs Q1, Q2. The bottom wafer 300 also includes one or more first metal layers 304 and a first passivation layer 308 embedded in a first dielectric layer 306 that provides insulation and a structural surface for the first metal layers 304. First and second contacts CON1 and CON2 are fabricated and configured to provide connection paths between the first and second FETs Q1, Q2 and the first metal interconnect M1.

[0052] Metal interconnects MN (where N is a number) such as first metal interconnects M1, second metal interconnects M2, and third metal interconnects M3 are electrically coupled to corresponding first metal layers in the first metal layer 304. First vias V1 and second vias V2 may also be provided to establish connections between different first metal layers 304 or metal interconnects MN or a combination thereof. Additionally, the first metal-insulator-metal capacitor MIM1 may also form a portion of the bottom wafer 300. According to various embodiments of the present disclosure, the number, thickness, and width of the first metal layers 304 may vary. In an embodiment, the first metal layer 304 closer to the top surface of the bottom wafer 300 is thicker than the first metal layer 304 closer to the bottom surface of the bottom wafer 300 to be able to support a higher current load. In this regard, each of the first metal layers 304 may have a thickness greater than 3.2 μm, 2 μm, 1.5 μm, or 1 μm.

[0053] Additionally, specific to the bottom wafer 300, a handle wafer contact (HWC) 312 may be etched into the surface of the first silicon handle wafer 204 through the first dielectric layer 306, the first barrier layer 302, the first top silicon device layer 210, and the first BOX layer 208. The HWC 312 is used to allow the charge in the first silicon handle wafer 204 to discharge to the circuit ground to prevent the charge difference between the first silicon handle wafer 204 and the first metal interconnect M1. In one aspect, the HWC 312 is located in the die seal ring area at the outer edge of the die (not shown), but may also be used in the main die area.

[0054] The first oxide layer 310 is formed over the top surface of the bottom wafer 300. A first hybrid bonding (HB) via 314 may be formed through the first oxide layer 310 to serve as an electrical connection to the bottom wafer 300. In this regard, any number of first HB vias 314 may be added. The first HB via 314 may be 1 μm to 2 μm, 0.75 μm to 3 μm, or 0.5 μm to 4 μm wide and 0.5 μm to 1 μm, 0.4 μm to 2 μm, or 0.3 μm to 3 μm thick. These dimensions may be adjusted, but in one aspect, a smaller size and height of the first HB via 314 is utilized. The first HB via 314 may be formed using oxide / nitride etching, copper plating, and chemical mechanical polishing (CMP) processes. The manufacturing process of the first HB via 314 may be specifically adjusted to achieve a hybrid bonding process as described subsequently, such as recessing the HB via surface to be slightly lower than the surface of the first oxide layer 310 forming the topmost layer of the bottom wafer 300.

[0055] Figure 1C Step 108 of flowchart 100 is shown. In this regard, Figure 1C Describes the use of complementary metal oxide semiconductor (CMOS) process technology to manufacture such Figure 4 A top wafer 400 is shown. Figure 4 4 illustrates a cross-sectional view of the top wafer 400 as seen after processing using CMOS process technology. This is done using front-end device processes and back-end metallization processes known to those skilled in the art. Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 3 The Figure 1C and Figure 4 All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0056] In this regard, the top wafer 400 may include transistors, such as third and fourth transistors Q3 and Q4, which may be, for example, n-type field effect transistors (n-FETs). Although only n-FETs are shown as forming part of the top wafer 400, the scope of the present application is not limited thereto. Appropriately constructed p-type field effect transistors (p-FETs) and diodes, capacitors, resistors, and inductors may also be formed as forming part of the top wafer 400, which are not shown here.

[0057] The second barrier layer 402 is formed over the second BOX layer 214 and the third FET Q3 and the fourth FET Q4. The top wafer 400 also includes one or more second metal layers 404 and a second passivation layer 408 embedded in the second dielectric layer 406, which provides an insulating and structural surface. The third contact CON3 and the fourth contact CON4 are manufactured and configured to provide a connection path between the third FET Q3 and the fourth FET Q4 and the fourth metal interconnect M4. Metal interconnects MN (where N is a number) such as the fourth metal interconnect M4, the fifth metal interconnect M5, and the sixth metal interconnect M6 are electrically coupled to the second metal layer 404. A third through hole V3 and a fourth through hole V4 may also be provided between the second metal layers 404 to establish a connection between the fourth interconnect M4, the fifth interconnect M5, or the sixth metal interconnect M6, thereby establishing a connection between the second metal layers 404. Additionally, the second metal-insulator-metal capacitor MIM2 may also form a portion of the top wafer 400. According to various embodiments of the present disclosure, the number, thickness, and width of the second metal layer 404 may vary. In one embodiment, the second metal layer 404 closer to the top surface of the top wafer 400 is thicker than the second metal layer 404 closer to the bottom surface of the bottom wafer 300 to be able to support a higher current load. In this regard, each of the second metal layers 404 may have a thickness greater than 3.2 μm, 2 μm, 1.5 μm, or 1 μm.

[0058] A second oxide layer 410 is formed over the top surface of the top wafer 400. A second hybrid bonding (HB) via 412 may be formed through the second oxide layer 410 to serve as an electrical connection to the top wafer 400. In this regard, any number of second HB vias 412 may be added. The second HB vias 412 may be 1 μm to 2 μm, 0.75 μm to 3 μm, or 0.5 μm to 4 μm wide and 0.5 μm to 1 μm, 0.4 μm to 2 μm, or 0.3 μm to 3 μm thick. These dimensions may be adjusted, but in one aspect, a smaller size and height of the second HB via 412 is utilized. The second HB vias 412 may be formed using oxide / nitride etching, copper plating, and chemical mechanical polishing (CMP) processes. The manufacturing process of the second HB via 412 may be specifically adjusted to achieve a hybrid bonding process as described later, such as recessing the surface of the second HB via 412 to be slightly lower than the surface of the second oxide layer 410 forming the topmost layer of the top wafer 400 .

[0059] It is important to note that the structures and designs of the bottom wafer 300 and the top wafer 400 described above are merely exemplary, and the disclosed subject matter is not necessarily limited to these examples.

[0060] Figure 1D Step 110 of flowchart 100 is shown. In this regard, Figure 1D Describes how Figure 4 The top wafer 400 is shown placed as Figure 3 A bottom wafer 300 is shown above. Figure 5 For example, if you place Figure 3 The bottom wafer 300 is shown as seen from above Figure 4 A cross-sectional view of the top wafer 400 is shown. Figures 1A to 1C and Figure 2 to Figure 4 The Figure 1D and Figure 5 All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0061] In this regard, the top wafer 400 is flipped vertically and placed on and above the top surface of the bottom wafer 300 as part of the process 500. The positions of the first HB vias 314 of the bottom wafer 300 and the second HB vias 412 of the top wafer 400 are aligned so that they make contact and are electrically coupled when the top surface of the top wafer 400 is placed above the top surface of the bottom wafer 300. The top wafer 400 and the bottom wafer 300 may be planarized to be sufficiently flat so that when they are put together, the top surfaces of the top wafer 400 and the bottom wafer 300 are fully connected. Planarization may be accomplished by chemical mechanical polishing (CMP). The second HB vias 412 and the first HB vias 314 on the top wafer 400 and the bottom wafer 300 are aligned together using a wafer alignment process 502 to provide electrical connections between the FETs.

[0062] Figure 1E Steps 112, 114, and 116 of flowchart 100 are shown. In this regard, Figure 1E Describes the formation of Fig. 6A The oxide-oxide bonding and formation shown in Figure 6B The copper-copper bonding shown. Figures 1A to 1D and Figure 2 to Figure 5 The Figure 1E , Fig. 6A and Figure 6B All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0063] Fig. 6A The top wafer 400 with the top wafer substrate 202 and the bottom wafer 300 with the bottom wafer substrate 200 are shown as seen after the top surface of the top wafer 400 is bonded to the top surface of the bottom wafer 300 using, for example, a mixed oxide-copper bonding process. In this regard, the top wafer 400 is flipped vertically and placed over the top surface of the bottom wafer 300, the first HB via 314 and the second HB via 412 are aligned, and a heating cycle is performed. The heating cycle enables the formation of an oxide-oxide bond 602 between the first oxide layer 310 and the second oxide layer 410.

[0064] Figure 6BThe top wafer 400 with the top wafer substrate 202 and the bottom wafer 300 with the bottom wafer substrate 200 are shown as seen after a heating cycle forms copper-copper bonds 606 between the third metal interconnect M3 and the sixth metal interconnect M6 and between the first HB via 314 and the second HB via 412 to form a bonded wafer 608. The heating cycle enables the formation of copper-copper bonds 606 between the metal interconnect M3 and the metal interconnect M6 and between the HB via 314 and the HB via 412. In this manner, the bottom wafer 300 and the top wafer 400 form a bonded wafer 608. It is noted that repeated heating cycles may be performed, but are not required, to further compress the copper-copper metal bonds and bonding.

[0065] Figure 7 An enlarged view of the bonded wafer 608 is shown as seen after the top surface of the top wafer 400 having the top wafer substrate 202 is bonded to the top surface of the bottom wafer 300 having the bottom wafer substrate 200. Figures 1A to 1D As well as Figures 2 to Fig. 6A and Figure 6B The Figure 7 All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0066] In various embodiments, the semiconductor devices, circuit blocks, or interconnects of the top wafer 400 and the bottom wafer 300 may be different or configured to perform different functions. Alternatively or additionally, the semiconductor devices, circuit blocks, or interconnects of the top wafer 400 and the bottom wafer 300 are connected in parallel using a plurality of HB vias (such as the first HB via 314 and the second HB via 412) to function as two FETs that are 3D stacked and connected by folding over each other. This is particularly advantageous because it improves performance while reducing the size of the bonded wafer 608 that is configured to perform circuit functions. Note that Figure 7 608 and is a simplified diagram showing the layer structure of the bonded wafer 608 and is not intended to illustrate circuit functionality. In this regard, the designs of the top wafer 400 and the bottom wafer 300 may be mirrored during the design process or in the mask manufacturing process. In other embodiments, after the die is cut from the bonded wafer 608, the HWC 312 in the bottom wafer 300 may be part of the die seal ring at the edge of the die ( Figure 7 ). Generally, the die seal ring includes all metal layers stacked as a metal wall to prevent damage to the die during sawing / singulation and to prevent moisture from entering the die. A first HB via 314 and a second HB via 412 may also be added to the die seal ring to electrically connect the top die seal ring and the bottom die seal ring together.

[0067] Figure 1FStep 118 of flowchart 100 is shown. In this regard, Figure 1F Describes the Figure 8 The removal process 800 shown removes the second silicon handle wafer 212 of the top wafer 400. In this regard, Figure 8 The bonded wafer 608 is illustrated as seen after the second silicon handle wafer 212 of the top wafer 400 is removed by the removal process 800. Figures 1A to 1E and Figure 2 to Figure 7 The Figure 1F and Figure 8 All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0068] The removal process 800 may be accomplished by a wafer grinding process, CMP, a chemical etching process, etc., or a combination thereof. For example, a wafer grinding process may be used to substantially remove the second silicon handle wafer 212, followed by a CMP or chemical etching process to remove any residue of the second silicon handle wafer 212. In an embodiment, the final CMP or etching process may be a process selective to oxide to prevent removal or damage to the second BOX layer 214 of the top wafer 400.

[0069] Figure 1G Steps 120 through 126 of the flowchart 100 are shown. In this regard, step 120 describes forming a third dielectric layer 902 over the bottom surface of the top wafer 400 (ie, disposed above the second BOX layer 214), such as Figure 8 as shown. Step 122 describes forming a backside via 904 that extends through the third dielectric layer 902, the second BOX layer 214, and the second top silicon device layer 216 to form an electrical connection with one of the metal interconnects M4 as part of the top wafer 400. Step 124 shows the formation of a backside metal redistribution layer (RDL) 906. Step 126 describes forming a third passivation layer 908 over the top surface of the exposed surface of the third dielectric layer 902 and a portion of the backside RDL 906. In this manner, an opening is formed over the top surface of the backside RDL 906 so that the bonded wafer 608 is connected to other external circuits, signal sources, power supplies, etc., or a combination thereof. In this regard, Fig. 9 The bonded wafer 608 is illustrated as seen after forming a third dielectric layer 902, backside vias 904, backside RDL 906, and a third passivation layer 908 over the bottom surface of the top wafer 400 and on the second BOX layer 214. Figures 1A to 1F and Figure 2 to Figure 8 The Figure 1G and Fig. 9All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0070] The third dielectric layer 902 may be any suitable material, such as silicon nitride. Other dielectrics, such as silicon dioxide, may also be used. In an embodiment, silicon nitride is utilized due to its thermal conductivity, which allows heat conduction from devices on the top wafer 400 (e.g., flip chip packages). The third dielectric layer 902 may have a thickness ranging from 0.1 μm to 10 μm, 0.05 μm to 50 μm, or 0.01 μm to 100 μm. A thicker third dielectric layer 902 may be used to provide less electrical coupling between the backside metal in the metal interconnect M6 and the RF circuit.

[0071] Next, a backside via 904, such as to the metal interconnect M4, is formed through the third dielectric layer 902 to provide an electrical connection path. For example, an opening may be etched in the third dielectric layer 902 and metal may be deposited or plated to form the backside via 904. The backside via 904 may be copper, aluminum, or any other suitable material. After the backside via 904 is formed, a patterned backside RDL 906 is deposited. The formation of RDL 906 may be completed using metal deposition, etc. The patterned backside RDL 906 may be copper, aluminum, or any other suitable material. In some embodiments, a single step may be used to deposit and / or plate the backside via 904 and the backside RDL 906 to reduce costs. Next, one or more third passivation layers 908 (such as silicon dioxide, silicon nitride, etc.) are deposited over the top surface of the exposed surface of the third dielectric layer 902 and over a portion of the backside RDL 906. In this manner, openings are formed over the top surface of the backside RDL 906 so that wire bonds or solder bumps (not shown) can be formed over the bonding wafer 608. Alternatively, a third passivation layer 908 is deposited over the bottom surface of the top wafer 400, and then areas of the third passivation layer 908 are opened, such as by etching, in the areas where wire bonds or solder bumps are to be added.

[0072] In an embodiment, a process control monitor (PCM) electrical test may be performed to test the performance of the bonded wafer 608 including the bottom wafer 300 and the top wafer 400. The PCM test may include testing the FETs on the bottom wafer 300 and the top wafer 400 together or individually. The PCM test may also be done with the FETs on both the bottom wafer 300 and the top wafer 400 connected in parallel to reduce the PCM test structure area.

[0073] In this regard, based on the above-mentioned 3D RFSOI manufacturing method, RF circuits for RF products (such as switches or amplifiers) can be manufactured using 3D hybrid wafer-level bonded wafers and can be laid out more efficiently. Field effect transistors are manufactured on two SOI wafers, which allows the total channel width and spacing of the FET to be significantly reduced and still maintain performance. In one aspect, the RF circuit uses a stacked FET structure that can be connected by folding together in 3D according to the hybrid wafer-level bonding method disclosed herein. By designing the RF circuit in this folded manner and stacking the wafers in 3D, the third dimension (e.g., height) provides further degrees of freedom, in which the RF circuit is laid out with less space and improved performance. For example, in one aspect, two SOI wafers are stacked, which significantly reduces the area of ​​at least one of the RF circuits.

[0074] As previously described, in one aspect, the RF circuit uses mirrored portions that are connected by folding together in 3D during the wafer bonding process. For example, mirroring the RF circuit on the bottom wafer 300 and the top wafer 400 can ensure that it operates in a balanced manner, which may be important for RF applications. In another aspect, the RF circuit uses asymmetric portions between the top and bottom wafers to take advantage of differences in the final structure between the wafers.

[0075] In another exemplary aspect, various design techniques are disclosed to maintain the performance of the RF circuit. For example, in one aspect, the nodes of the RF circuit on both the bottom wafer 300 and the top wafer 400 are electrically connected to the FETs via the first HB via 314 and the second HB via 412 placed at specific locations to balance their operation. This ensures that the two RF circuits operate in phase with each other and maintain good voltage handling.

[0076] In another exemplary aspect, the first SOI wafer and the second SOI wafer (such as the bottom wafer 300 and the top wafer 400) may have different thermal resistances. For example, the bottom wafer 300 may remain attached to the first silicon handle wafer 204, which provides a substrate and a path for heat dissipation. Because the bottom wafer 300 is interposed, the top wafer 400 may be at a greater distance from the first silicon handle wafer 204 and therefore may have a greater thermal resistance. According to an exemplary aspect, different RF circuits may be provided in the bottom wafer and the top wafer according to the thermal characteristics of the bottom wafer 300 and the top wafer 400. Additionally, HB vias such as the first HB via 314 and the second HB via 412 and metal connections may be provided between the bottom wafer substrate 200 and the top wafer substrate 202 to provide a thermal path.

[0077] In this regard, reference will now be made to Figures 10 to 22A and Fig. 22B as well as Fig.23A , Fig. 23B , Fig.24A and Fig. 24B Various RF circuit schematics and layouts are described to illustrate various aspects of the present disclosure. In view of the many possible configurations, an overview of the presented figures is now provided to aid in describing various aspects of the present disclosure. Fig.10 An RF circuit is illustrated that utilizes multiple FETs stacked in series to achieve the larger signals typical in RF applications. Fig.11A and Fig. 11B An exemplary RF circuit is illustrated that is fabricated by the methods described herein and has a stack of mirrored FETs disposed on top and bottom wafers that are opposite to each other and that can be connected in a 3D folded structure. Fig. 12A and Fig. 12B An alternative exemplary RF circuit is illustrated that is fabricated by the methods described herein and has an opposing FET stack of three FETs connected by folding together in a 3D configuration, but with a different configuration to exploit the difference between the top wafer and the bottom wafer. Fig.13A and Fig. 13B Shows something like Fig. 12A and Fig. 12B But another exemplary RF circuit has a common bias resistor to feed a direct current (DC) bias to the center of the FET stack. Fig.14 Examples include Fig.10 An exemplary layout of the RF circuit is shown. Fig.15 shows what it would look like in the final flipped (i.e., mirrored) orientation. Fig. 12A and Fig. 12B An exemplary layout of the RF circuit is shown. Fig.16 Shows Fig.15 An alternative metallization arrangement can have more HB vias as shown in the final flipped (ie, mirrored) orientation. Fig.17 An exemplary cross-section of a structure resulting from the hybrid wafer bonding process described herein is shown. Fig.18A and Fig.18B An RF circuit for a 2D design is illustrated that has no bonding and includes multiple FETs stacked in series, a linearity improvement circuit, and a voltage handling improvement circuit. Fig.19 Illustrated Fig.18A and Fig.18B An exemplary layout of the RF circuit is shown. Fig. 20A , Fig. 20B , Fig.21A and Fig.21B A corresponding RF circuit with opposing FET stacks, linearity improvement circuitry, and voltage processing circuitry that may be connected by folding together in a 3D configuration is shown for the hybrid wafer bonding process described herein. Fig.22A and Fig. 22BShows Fig. 20A , Fig. 20B , Fig.21A and Fig.21B An exemplary side-by-side layout of RF circuits is shown. Fig.23A A side view of the dies cut from a single wafer and their final layout size is shown. Fig. 23B Side-by-side placement of dies from a bottom wafer and a top wafer is shown to illustrate the reduced layout size in accordance with the present disclosure. Fig.24A A layout of an RF product having RF circuits for switching and control circuits is shown. Fig. 24B An exemplary layout of an RF product having an RF circuit for a switch fabricated using the hybrid wafer bonding process described herein is shown. Fig.23A and Fig.24A The layout area shown is compared to the reduced layout area.

[0078] Fig.10 An exemplary circuit diagram of an RF switch 1000 that can be implemented using a single wafer is shown. Fig. 9 As mentioned Fig.10 All elements shown will continue to have the same reference numerals as the elements discussed, and will not be described here for the sake of brevity. The RF switch 1000 includes a plurality of field effect transistors (FETs) stacked in series, such as Q1, Q2, and Q3. However, the scope of the present disclosure is not limited thereto. The total number of FETs stacked in series as switches in the RF switch 1000 may vary according to the RF voltage signal desired in the RF product. In an embodiment, the total number of FETs stacked in series as switches in the RF switch 1000 may be in the range of 1 to 50 or greater than 50 according to the RF voltage signal desired in the RF product. Each of FETQ1, Q2, and Q3 includes corresponding gate terminals G1, G2, and G3 and corresponding source terminals, drain terminals, and body terminals, which are not shown for simplicity of illustration. In this regard, the source terminal of the first FET Q1 is connected to the drain terminal of the second FET Q2 to form a first source-drain node SD1. In addition, the source terminal of the second FET Q2 is connected to the drain terminal of the third FET Q3 to form a second source-drain node SD2. In this regard, the drain node of the first FET Q1 is connected to the input node SD0, and the source node of the third FET Q3 is connected to the output node SD3. In this manner, the first source-drain resistor RSD1 is coupled between the input node SD0 and the first source-drain SD1. The second source-drain resistor RSD2 is coupled between the first source-drain SD1 and the second source-drain SD2. The third source-drain resistor RSD3 is coupled between the second source-drain SD2 and the output node SD3.

[0079] The RF switch 1000 is provided between an RF_INPUT terminal 1006 connected to a first input node SD0 and an RF_OUTPUT terminal 1008 connected to an output node SD3. In this manner, the RF switch 1000 utilizes FETs Q1, Q2, and Q3 connected in series to enable processing of RF voltage signals having high values ​​that may damage or degrade the performance of a single FET.

[0080] In an embodiment, the RF voltage signal at the RF_INPUT terminal 1006 and the RF_OUTPUT terminal 1008 is divided substantially equally across the FETs Q1, Q2, and Q3. It may be desirable to minimize parasitic capacitance between the drain terminals, source terminals, body terminals, and gate terminals of the FETs Q1, Q2, and Q3 and other portions of the RF switch 1000 circuit that may alter the substantially equal division of the RF voltage signal across the FETs Q1, Q2, and Q3. Thus, as previously described with reference to FIGS. Fig. 9 As described, the RF chip produced and manufactured using the RFSOI process may have a first silicon handle wafer 204 as a portion of a bottom wafer substrate 200 having a high resistivity bottom wafer 300. In addition, the bottom wafer substrate 200 may include a first polysilicon layer 206 that minimizes depletion / inversion effects at a first BOX layer 208. Additionally, the metal conductor is formed away from the field effect transistors Q1, Q2, Q3 having a reduced length.

[0081] The gate resistors RG1, RG2 and RG3 are connected between the gate terminals G1, G2 and G3 and the DC supply voltage terminal 1012 having the gate voltage signal VG. In addition, the body resistors RB1, RB2 and RB3 are connected between the body terminals B1, B2 and B3 and the body voltage terminal 1010 having the body voltage signal VB. The values ​​of the gate resistors RG1, RG2, RG3 and the body resistors RB1, RB2, RB3 may vary in the range of 10Ω to 1000kΩ, 50Ω to 500kΩ or 100Ω and 100kΩ depending on the application. In this way, a DC bias is provided to each of the FETs Q1, Q2 and Q3 in the FET stack from the DC supply voltage terminal 1012 and the body voltage terminal 1010.

[0082] Fig.11A As shown in FIG. 1 to FIG. Fig. 9 An exemplary schematic diagram of the first RF circuit 1100 implemented in the bottom wafer 300 is shown. Fig. 11B As shown in FIG. 1 to FIG. Fig. 9An exemplary schematic diagram of the second RF circuit 1102 implemented in the top wafer 400 is shown. Fig.11A and Fig. 11B All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0083] As reference Fig.11A and Fig. 11B The first RF circuit 1100 and the second RF circuit 1102 discussed are substantially similar to those described in reference Fig.10 The RF switch 1000 described. In order to minimize the parasitic capacitance associated with the first RF circuit 1100 and the second RF circuit 1102, and to avoid the significant length of the metal conductor as part of the manufacturing process, the first RF circuit 1100 and the second RF circuit 1102 are designed as mirror copies of each other. However, each of the first RF circuit 1100 and the second RF circuit 1102 is implemented on different wafers, such as a bottom wafer 300 and a top wafer 400, which are bonded together using the above-mentioned RF-SOI hybrid wafer bonding method. In this way, the first RF circuit 1100 and the second circuit 1102 are connected in parallel to form an RF switch. In this way, the RF_INPUT terminals 1006 of the first RF circuit 1100 and the second RF circuit 1102 are connected to each other to form a single RF_INPUT terminal. In addition, the RF_OUTPUT terminals 1008 of the first RF circuit 1100 and the second RF circuit 1102 are connected to each other to form a single RF_OUTPUT terminal.

[0084] As shown, each of the first RF circuit 1100 and the second RF circuit 1102 includes a stack of FETs Q1B, Q2B, and Q3B and Q1T, Q2T, and Q3T, respectively. After bonding the bottom wafer 300 including the first RF circuit 1100 and the top wafer 400 including the second RF circuit 1102, when the top wafer 400 is flipped vertically and placed above the bottom wafer 300, the first RF circuit 1100 and the second RF circuit 1102 are connected, as previously described with reference to FIG. Figure 5As illustrated and described. In this regard, the total number of FETs is doubled while reducing the layout area. By having FETs on both the bottom wafer 300 and the top wafer 400, the total channel width associated with each FET Q1B, Q2B, and Q3B, as well as Q1T, Q2T, and Q3T can be reduced by 30%, 40%, and 50% while maintaining the same overall electrical performance. In this regard, the total 2D area associated with the first RF circuit 1100 and the second RF circuit 1102 bonded using the bottom wafer 300 and the top wafer 400 can be reduced by approximately 30%, 40%, or 50%, thereby achieving a more compact die.

[0085] The gate resistors RG1B, RG2B, RG3B, the bulk resistors RB1B, RB2B, RB3B, and the source-drain resistors RSD1B, RSD2B, RSD3B of the first RF circuit 1100 and the gate resistors RG1T, RG2T, RG3T, the bulk resistors RB1T, RB2T, RB3T, and the source-drain resistors RSD1T, RSD2T, RSD3T of the second RF circuit 1102 are as previously described with reference to Fig.10 The nodes RF_INPUT, RF_OUTPUT, VG, VB, SD0, SD1, SD2, SD3, G1, G2, G3, B1, B2, and B3 are common in the first RF circuit 1100 and the second RF circuit 1102 and have been previously described. Fig.10 In this regard, nodes RF_INPUT, RF_OUTPUT, VG, VB, SD0, SD1, SD2, SD3, G1, G2, G3, B1, B2, and B3 of the first RF circuit 1100 and the second RF circuit 1102 may be electrically coupled using one or more HB vias (such as HB vias 314, 412), when combined according to Figures 5 to 9 The HB vias are electrically connected when the hybrid wafer bonding method bonds the bottom wafer 300 and the top wafer 400. On the other hand, when the RF signal is almost equally divided on the stack of FETs Q1B, Q2B and Q3B and Q1T, Q2T and Q3T, the RF signals carried by RF_INPUT and RF_OUTPUT are maintained in phase with safe and high-level voltage processing.

[0086] Fig. 12A As shown in FIG. 1 to FIG. Fig. 9 An exemplary schematic diagram of the first RF circuit 1200 implemented in the bottom wafer 300 is shown. Fig. 12B As shown in FIG. 1 to FIG. Fig. 91 to 4. Fig.11A and Fig. 11B The Fig. 12A and Fig. 12B All elements shown will continue to have the same reference numerals as those discussed and will not be described again for the sake of brevity. Fig. 12A and Fig. 12B The first RF circuit 1200 and the second RF circuit 1202 discussed are substantially similar to those described in reference Fig.11A and Fig. 11B The first RF circuit 1100 and the second RF circuit 1102 are different in that the first RF circuit 1100 is removed from the second RF circuit 1200. Fig.11A 1 to 4, and the first RF circuit 1200 and the second RF circuit 1202 form an asymmetric connection. The nodes RF_INPUT, RF_OUTPUT, VG, VB, SD0, SD1, SD2, SD3, G1, G2, G3, B1, B2, and B3 are all connected to one or more HB vias (such as HB vias 314, 412). Fig. 9 When bonding the bottom wafer 300 and the top wafer 400 in the hybrid wafer bonding method described in the prior art, the one or more HB vias are aligned.

[0087] Asymmetric circuits can be one aspect because the FETs Q1T, Q2T, Q3T in the top wafer 400 can have a greater vertical distance from the silicon handle wafer 204 in the bottom wafer substrate 200 of the bottom wafer 400. This results in the FETs Q1T, Q2T, Q3T having greater thermal resistance than the FETs Q1B, Q2B, and Q3B that form part of the bottom wafer 300. The first RF circuit 1200 can include elements of gate resistors RG1B, RG2B, RG3B, body resistors RB1B, RB2B, RB3B, and source-drain resistors RSD1B, RSD2B, RSD3B, which can have significant current density under RF operation. Therefore, in the absence of gate resistors, body resistors, and source-drain resistors in the second RF circuit 1202, the second RF circuit 1202 can utilize a larger volume in the bottom wafer 300. Thus, using an asymmetric RF circuit connection between the first RF circuit 1200 and the second RF circuit 1202 to exploit the difference in thermal properties may result in lower resistor temperatures and ensure that the first RF circuit 1200 and the second RF circuit 1202 operate more reliably when coupled to each other.

[0088] Fig.13A As shown in FIG. 1 to FIG. Fig. 9 An exemplary first RF circuit 1300 implemented in the bottom wafer 300 is shown. Fig. 13B As shown in FIG. 1 to FIG. Fig. 9 The exemplary second RF circuit 1302 implemented in the top wafer 400 is shown in FIG. Fig. 12A and Fig. 12B The Fig.13A and Fig. 13B All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0089] In this example, the first RF circuit 1300 and the second RF circuit 1302as coupled to each other are used as a switch, which includes FETs Q1B, Q2B, Q3B and Q4B in the bottom wafer 300 and Q1T, Q2T, Q3T and Q4T in the top wafer 400. Additionally, the resistors connected between the gate nodes and body nodes of the FETs Q1B, Q2B, Q3B and Q4B and the DC power supplies VG and VB are connected in series rather than in parallel. A common body resistor RBCOM and a common gate resistor RGCOM are added between the DC power supplies VG and VB and the gate resistors and the body resistors. In one aspect, the first RF circuit 1300 and the second RF circuit 1302 may have performance advantages based on this configuration of components, such as improved insertion loss / isolation, linearity, and voltage handling. To minimize FET self-heating, metal connections including an array of HB vias 314, 412 are located on the bottom wafer 300 and the top wafer 400 to provide a thermal path (with lower thermal resistance) to allow heat to flow from the FET source-drain nodes SD0, SD1, SD2, SD3, and SD4 in the second RF circuit 1302 in the top wafer 202 to the FET source-drain nodes SD0, SD1, SD2, SD3 in the first RF circuit 1300 in the bottom wafer 300. This allows heat to flow from the transistors Q1T, Q2T, Q3T, and Q4T in the top wafer 400 to the transistors Q1B, Q2B, Q3B, and Q4B in the bottom wafer 300. The heat in the bottom wafer 300 can then move through the silicon handle wafer 204 and ultimately to the circuit board or package ( Fig.13A and Fig. 13B not shown).

[0090] Fig.14 Illustrated Fig.10 An exemplary layout 1400 of the RF switch 1000 is shown. The layout 1400 includes Fig.101, 10, and 11. The RF switch 1000 of FIG. 10 is identical to the RF switch 1000 of FIG. 10, and therefore, for the sake of brevity, a description of these elements is not included. In this regard, FETs Q1, Q2, and Q3 have a width W corresponding to a gate width of each of FETs Q1, Q2, and Q3. Gate resistors RG1, RG2, and RG3, body resistors RB1, RB2, and RB3, and source-drain resistors RSD1, RSD2, and RSD3 correspond to and are connected to Fig.10 RF switch 1000. In addition, source-drain nodes SD0, SD1, SD2, and SD3 between FETs Q1, Q2, and Q3 of RF circuit 1000 are shown in layout 1400 as metal connections.

[0091] Fig.15 An exemplary layout of a first RF circuit 1200 and a second RF circuit 1202 as shown in FIG. 12 is shown. Fig.16 yes Fig.15 In this regard, Fig.15 and Fig.16 As shown in FIG. 1 to FIG. Fig. 9 The exemplary side-by-side layouts before bonding the bottom wafer 300 and the top wafer 400 are shown. For clarity, the layouts are shown side-by-side, but these layouts are stacked on top of each other during bonding the bottom wafer 300 and the top wafer 400. As described above, according to the hybrid wafer bonding method described herein, Fig.15 The layout of 1500, 1502 and Fig.16 The layout 1600, 1602 has FET stacks Q1T, Q2T, and Q3T in the top wafer 400 opposite to the FET stacks Q1B, Q2B, and Q3B in the bottom wafer 300, which are connected together by bonding from the bottom wafer 300 and the top wafer 400. Gate resistors RG1B, RG2B, RG3B, body resistors RB1B, RB2B, RB3B, and source-drain resistors RSD1B, RSD2B, RSD3B are connected to the FETs in the bottom wafer 300 as shown. Source-drain metal connections SD0, SD1, SD2, and SD3 are connected as shown.

[0092] In one aspect, the gate widths of the FETs Q1T, Q2T, and Q3T in the top wafer 400 and Q1B, Q2B, and Q3B in the bottom wafer 300 have a width (W) that is half the width required in the layout 1400, as shown in FIG. Fig.14 The reduction in layout area is achieved by replicating the FETs Q1T, Q2T, and Q3T in the top wafer 400 to Q1B, Q2B, and Q3B in the bottom wafer 300, which allows the total channel width of each FET to be reduced by 50% and still maintain the same Fig.14 The same electrical performance as in the layout 1400. Therefore, this allows the die of the RF product to be more compact / smaller.

[0093] Note that several HB vias, such as HB vias 314, 412, connecting the bottom wafer 300 and the top wafer 400 are also shown. Metal connections with HB vias, such as HB vias 314, 412, covering a large portion of the layout area, are used to connect the source-drain nodes SD0, SD1, SD2, SD3 between the bottom wafer 300 and the top wafer 400 to provide an enhanced thermal path as previously described. Metal connections, such as HB vias (e.g., HB vias 314 and 412), can be used to connect the gate nodes G1, G2, G3 and the body nodes B1, B2, and B3 of the FETs Q1T, Q2T, and Q3T in the top wafer 400 and the FETs Q1B, Q2B, and Q3B in the bottom wafer 300. This provides DC bias to the top wafer 400 FETs Q1 , Q2 and Q3 through gate resistors RG1B, RG2B, RG3B, source-drain resistors RSD1B, RSD2B and RSD3B and bulk resistors RB1B, RB2B and RB3B located on the bottom wafer 300 .

[0094] Fig.16 Another exemplary layout 1600 for the first RF circuit 1200 and the second RF circuit 1202 as shown in FIG. 12 is shown. Fig.15 Compared to having an alternative metallization arrangement to allow more HB vias. Using the disclosed hybrid wafer bonding process, the RF switch area of ​​the RF switch in layout 1600 can be reduced by nearly 50%. Additionally, since the top wafer 400FETs Q1T, Q2T, and Q3T are relatively far away from the silicon handle wafer, the smaller RF switch area also reduces the coupling capacitance of the RF switch to its silicon handle wafer (not shown). The lower coupling capacitance to the silicon handle wafer helps to balance the RF voltage division on the top wafer 400FETs Q1T, Q2T, and Q3T, thereby improving RF voltage handling. Since the parasitic capacitance between RF_INPUT and RF_OUTPUT is lower, the lower coupling capacitance to the silicon handle wafer can also improve the off-state RF isolation. Since the resistance between RF_INPUT and RF_OUTPUT is lower, the smaller RF switch width can also improve the parasitic resistance of the metal connection to the RF switch, thereby improving the on-state RF insertion loss.

[0095] Fig.17 shows the use of Figure 1 to Fig. 9 An exemplary cross-sectional image 1700 of a bottom wafer 300 and a top wafer 400 bonded together using a hybrid bonding process is shown. Fig.17Provided to illustrate the layer structure and is not intended to indicate circuit functionality. As shown, the top wafer 400 is flipped in orientation and bonded to the bottom wafer 300 in a relative manner. This stacking of the bottom wafer 300 and the top wafer 400 enables a 3D structure that increases density and functionality in a smaller 2D layout area. Specifically, the cross-sectional image 1700 shows how the bottom wafer 300 and the top wafer 400 are folded and bonded together to connect, for example, a transistor in the bottom wafer 300 with a transistor in the top wafer 400. The bottom wafer 300 and the top wafer 400 are connected by folding vertically with each other and provide electrical connections, for example, through HB vias 314 and 412.

[0096] Fig.18A An exemplary RF circuit 1800 implemented on a single wafer supplemented with enhancement circuits 1808A to 1808F is illustrated. It is important to note that the RF circuit 1800 may include an arrangement of resistors, FETs, capacitors, diodes, or other components not shown here for simplicity. As shown, the RF circuit 1800 is similar to Fig.10 RF switch 1000 is shown. Fig.18B As previously referenced Fig.10 The exemplary RF circuit 1802 discussed.

[0097] Fig.19 is a diagram showing an exemplary layout 1900 of the RF circuit 1800 shown in FIG 18 as implemented in a single wafer. It is important to note that the RF circuit 1800 may include an arrangement of resistors, FETs, capacitors, diodes, or other elements not shown here for simplicity.

[0098] Fig. 20A and Fig. 20B as well as Fig.21A and Fig.21B A corresponding RF circuit with a relative FET stack, a linearity improvement circuit, and a voltage processing circuit that can be connected by folding together according to the hybrid wafer bonding process described herein is shown. Specifically, Fig. 20A and Fig. 20B An exemplary RF circuit 2000 is shown having an RF switch 2002 having a stack of multiple FETs Q1T, Q2T, and Q3T implemented in a top wafer 400, while Fig.21A and Fig.21B An exemplary RF circuit 2100 implemented in the bottom wafer 300 is shown. Fig. 20A and Fig. 20B18 , RF circuit 2000 may include enhancement circuits 2006A-2006F similar to enhancement circuits 1808A-1808F (shown in FIG. 18 ). As shown, enhancement portion 2004 includes enhancement circuits 2006A-2006C, which are linearity improvement circuits and may also include arrangements of resistors, FETs, capacitors, diodes, or other elements, which are not shown here for simplicity and are placed between source-drain nodes SD0, SD1, SD2, and SD3. Enhancement circuits 2006A-2006C may include linearity improvement circuits and may also include arrangements of resistors, FETs, capacitors, diodes, or other elements, which are not shown here for simplicity. The enhancement portion 2004 may also include enhancement circuits 2006D-2006F, which are voltage handling improvement circuits and may also include an arrangement of resistors, FETs, capacitors, diodes or other elements, which are not shown here for simplicity and are placed between the body nodes B1, B2 and B3 and the adjacent source-drain nodes SD0, SD1, SD2 and SD3.

[0099] Reference now Fig.21A and Fig.21B , the RF circuit 2100 is also similar to the second RF circuit 1202 (in Fig. 12A ), and includes a stacked RF switch 2102 having a plurality of FETs Q1B, Q2B, and Q3B. Additionally, Fig.21A RF circuit 2100 in may include an enhancement portion 2104 having enhancement circuits 2106A-2106F similar to enhancement circuits 1808A-1808F (as shown in FIG. 18 ). As shown, enhancement circuits 2106A-2106C may include linearity improvement circuits (not shown) placed between source-drain nodes SD0, SD1, SD2, and SD3, and may include an arrangement of resistors, FETs, capacitors, diodes, or other components. Enhancement circuits 2106D-2106F may include voltage handling improvement circuits (not shown) placed between body nodes B1, B2, and B3 and adjacent source-drain nodes SD0, SD1, SD2, SD3.

[0100] Since the enhancement circuit 2006A-2006F or 2106A-2106F (respectively in Fig. 20A and Fig.21A 18 ) are mirrored versions placed on top wafer 400 and bottom wafer 300, respectively, and the size of these components can be approximately 50% smaller in layout area compared to the enhancement circuit 1806 (shown in FIG. 18 ) implemented on a single wafer.

[0101] In this regard, Fig.22AAn exemplary layout 2200 implemented in the bottom wafer 300 is shown. Fig. 22B An exemplary layout 2202 implemented in the top wafer 400 is shown. The layout 2200 corresponds to the RF circuit 2100 shown in FIG. 21a. For clarity, the layouts 2200, 2202 are shown side by side, but these layouts are stacked on top of each other during bonding of the bottom wafer 300 and the top wafer 400. Fig.21A and Fig.21B The Fig.22A and Fig. 22B All elements shown will continue to have the same reference numerals as elements discussed and will not be described again here for the sake of brevity.

[0102] As shown, the layouts 2200, 2202 have FET stacks Q1T, Q2T, and Q3T in the top wafer 400 opposite to Q1B, Q2B, and Q3B in the bottom wafer 300, which are connected by folding together from the bonds of the bottom wafer 300 and the top wafer 400. Gate resistors RG1B, RG2B, RG3B, body resistors RB1B, RB2B, RB3B, and source-drain resistors RSD1B, RSD2B, RSD3B are connected to the FETs in the bottom wafer 300 as shown. The source-drain metal connections SD0, SD1, SD2, SD3 are also connected as shown. As previously described, the gate widths of the FETs Q1T, Q2T, and Q3T in the top wafer 400 and Q1B, Q2B, and Q3B in the bottom wafer 300 can now have a width (W) that is half the width required for the total gate width for each FET in the layout 1400, as shown. Fig.14 shown.

[0103] It is noteworthy that several HB vias, such as HB vias 314, 412, connecting the bottom wafer 300 and the top wafer 400 are also shown. Metal connections with HB vias, such as HB vias 314, 412, covering a large portion of the layout area, are used to connect the SD0, SD1, SD2, SD3 nodes between the bottom wafer 300 and the top wafer 400 to provide an enhanced thermal path as previously described. Metal connections, such as HB vias 314, 412, can also be used to connect the gate nodes G1, G2, G3 and body nodes B1, B2, B3 of the FETs Q1T, Q2T, and Q3T and the FETs Q1B, Q2B, and Q3B in the bottom wafer 300. This provides DC bias to the FETs Q1T, Q2T, and Q3T in the top wafer 400 through the gate resistors RG1B, RG2B, RG3B and body resistors RB1B, RB2B, and RB3B located on the bottom wafer 300.

[0104] Furthermore, since the enhancement circuits 2106A-2106F are implemented in the bottom wafer 300 and the enhancement circuits 2006A-2006F are implemented in the top wafer 400, these circuits now consume less 2D area. Therefore, even with the enhancement circuits 2106A-2106F and 2006A-2006F, their layout is significantly smaller than a conventional single wafer implementation and enables a smaller die. However, the linearity improvement circuits in the enhancement circuits 2106A-2106C in the top wafer 400 and 2106A-2106C in the bottom wafer 300 can be approximately 30%, 40%, or 50% smaller because these linearity improvement circuits have the same 2D area as the top wafer 400. Fig.19 The width Y / 2 is approximately halved compared to the layout 1900 shown. Additionally, the voltage handling improvement circuits in the enhancement circuits 2006D-2006F implemented in the top wafer 400 and the enhancement circuits 2106D-2106F implemented in the bottom wafer 300 may have a size that is approximately 30%, 40%, or 50% smaller because these voltage handling improvement circuits have the same Fig.19 The layout 1900 is shown with a width approximately halved by X / 2.

[0105] Fig.23A A side view of an exemplary and conventional RFSOI RF die 2300 cut from a single wafer is shown. As shown, the RFSOI RF die 2300 includes a control circuit 2302 having, for example, a digital logic interface, a switch bias voltage generator, a multiplexer, a switch driver, electrostatic discharge protection, etc., which are not shown here for the sake of brevity. The control circuit 2302 also includes a voltage VDD supply terminal 2304 and a ground GND terminal 2306. Additionally, the RFSOI RF die 2300 may include a first RF switch 2308 having a first backside metal interconnect 2312 and a second backside metal interconnect 2314, respectively. In addition, the RFSOI RF die 2300 includes a second RF switch 2310 having a third backside metal interconnect 2316 and a fourth backside metal interconnect 2318, respectively. These elements are implemented on a single wafer before being cut into the RFSOI RF die 2300.

[0106] Fig. 23BA side view of an RF switch die 2320 having a bottom die portion 2322 and a top die portion 2324 is shown. The bottom die portion 2322 includes a first bottom die RF switch 2328, a second bottom die RF switch 2326, and a bottom die control circuit 2336. The top die portion 2324 includes a first top die RF switch 2332, a second top die RF switch 2330, and a top die control circuit 2334. In this manner, based on the topology and layout shown above with reference to FIGS. 11 to 22 , the first RF switch is divided into an upper half 2332 and a lower half 2328, the second RF switch is divided into an upper half 2330 and a lower half 2326, and the control circuit is divided into an upper half 2334 and a lower half 2336. This is particularly advantageous because it enables the RF switch die 2320 to have a die area that is 30%, 40%, or 50% smaller than the RFSOI RF die 2300, as shown in FIG. Fig.23A shown.

[0107] Fig.24A The layout area of ​​an exemplary and conventional RFSOI RF switch die 2300 is illustrated. The RFSOI RF switch die 2300 includes a control circuit 2302 having, for example, a digital logic interface, a switch bias voltage generator, a multiplexer, a switch driver, electrostatic discharge protection, etc., which are shown here for simplicity. The control circuit 2302 also includes a voltage VDD supply terminal 2304 and a ground GND terminal 2306. Additionally, the RFSOI RF die 2300 may include a first RF switch 2308 having a first backside metal interconnect 2312 and a second backside metal interconnect 2314, respectively. In addition, the RFSOI RF die 2300 includes a second RF switch 2310 having a third backside metal interconnect 2316 and a fourth backside metal interconnect 2318, respectively. These elements are implemented on a single wafer before being cut into the RFSOI RF die 2300.

[0108] Fig. 24B 23. The layout area of ​​an exemplary RF switch die 2320 is shown. In this regard, the RF switch die 2320 is shown as having a bottom die 2320 and a top die 2324 (e.g., Fig. 23B As shown) For example, using reference Figures 1A to 1G and Figure 2 to Fig. 9 Thus, top portions 2326, 2330, and 2334 are disposed above bottom portions 2328, 2332, and 2336. Due to the use of 3D stacking and folding, this allows RF switch die 2320 to be bonded to RFSOI RF switch die 2300 (e.g., Fig.24A and Fig.23AThus, the RF switch die 2320 may have a die area that is 30%, 40%, or 50% smaller than the RFSOI RF die 2300, as shown in FIG. Fig.24A In an embodiment, the RF switch die 2320 has a minimal height difference relative to the RFSOI RF die 2300, for example, using conventional thinning of the silicon handle wafer 204 in the bottom wafer substrate 200 of the bottom wafer 300 (eg, Figure 2A and Figure 2B as shown).

[0109] Therefore, the 3D RFSOI hybrid wafer bonding method described in this article and FIG. 11A to FIG. 13B , Fig.15 and Fig.16 , FIG. 20A to FIG. 22B , Fig. 23B and Fig. 24B The RF circuit schematics and layouts shown can provide improved RF circuits and RF products that utilize less layout area, have little change in height, and have similar or improved performance. These aspects can be used in various applications, such as switches and amplifiers for user element devices (e.g., mobile wireless devices).

[0110] Fig.25 An exemplary user element 2500 is shown that includes RF circuitry including, but not limited to FIG. 11A to FIG. 13B , Fig.15 and Fig.16 , FIG. 20A to FIG. 22B , Fig. 23B and Fig. 24B The RF circuit schematic and layout shown. The above RF circuit can be operated as various devices (such as switches, power switches, amplifiers, filters and frequency converters), which can be integrated in user components such as communication devices, mobile phones, etc.

[0111] Continue to refer Fig.25, the above concepts can be implemented in various types of user elements 2500, such as mobile terminals, smart watches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communications (such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication). The user element 2500 will generally include a control system 2502, a baseband processor 2504, a transmission circuit 2506, a receiving circuit 2508, an antenna switching circuit 2510, a plurality of antennas 2512A-2512N, and a user interface circuit 2514. In a non-limiting example, the control system 2502 can be a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). At this point, the control system 2502 may include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receiving circuit 2508 receives radio frequency signals from one or more base stations via antennas 2512A-2512N and through the antenna switching circuit 2510. The low noise amplifier and filter of the receiving circuit 2508 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0112] The baseband processor 2504 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations. The baseband processor 2504 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0113] For transmission, the baseband processor 2504 receives digitized data that may represent voice, data, or control information from the control system 2502, and the baseband processor encodes the digitized data for transmission. The encoded data is output to the transmit circuit 2506, where a digital / analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at a desired transmission frequency or frequencies. The power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and passes the modulated carrier signal to the antenna 2512A-2512N through the antenna switching circuit 2510. Multiple antennas 2512A-2512N and duplicate transmit circuits 2506 and receive circuits 2508 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0114] It is contemplated that any of the aforementioned aspects, and / or the various individual aspects and features described herein, may be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0115] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A method of manufacturing a radio frequency (RF) circuit, comprising: providing a first silicon-on-insulator (SOI) wafer; Providing a second SOI wafer; providing a first transistor on the first SOI wafer; providing a second transistor on the second SOI wafer; as well as The second SOI wafer is bonded to the first SOI wafer to form a bonded wafer, wherein the second transistor is opposite to the first transistor. 2 . The method of claim 1 , wherein the first SOI wafer comprises a first handle wafer and the second SOI wafer comprises a second handle wafer, and further comprising removing the second handle wafer.

3. The method of claim 2, further comprising: At least one handle wafer contact is provided between the first transistor and the first handle wafer.

4. The method of claim 1, further comprising: providing a first metal layer on the first SOI wafer; forming a first via from the first metal layer electrically connected to the first transistor; providing a second metal layer on the second SOI wafer; as well as A second via is formed from the second metal layer, electrically connected to the second transistor. 5 . The method of claim 4 , wherein bonding the second SOI wafer to the first SOI wafer further comprises bonding the first via to the second via to electrically connect the first transistor to the second transistor.

6. The method of claim 4, further comprising: forming a third through hole providing a first heat dissipation path from the first metal layer; forming a fourth via from the second metal layer that provides a second heat dissipation path; as well as Bonding the second SOI wafer to the first SOI wafer further includes bonding the third via with the fourth via to thermally couple the first heat dissipation path with the second heat dissipation path.

7. The method of claim 1, further comprising forming a die from the bonded wafer, the die comprising a first RF circuit from the first transistor and a second RF circuit from the second transistor, wherein the first RF circuit and the second RF circuit are electrically coupled.

8. A radio frequency (RF) circuit, comprising: a first RF circuit, the first RF circuit being located on a first layer of a substrate; a second RF circuit located on a second layer opposite to the first layer; as well as An interface layer is located between the first layer and the second layer and includes at least one through-hole electrically connected to the first RF circuit and the second RF circuit.

9. The RF product of claim 8, wherein the substrate further comprises an insulating layer, the insulating layer being located between the first layer and the substrate.

10. The RF product of claim 8, wherein the first RF circuit mirrors the second RF circuit.

11. The RF product of claim 8, wherein: The first RF circuit includes a first field effect transistor (FET) having a first drain, a first source, and a first gate; and The second RF circuit includes a second FET having a second drain, a second source, and a second gate.

12. The RF product of claim 11, wherein: The first RF circuit also includes: a first resistor, which is connected between a gate terminal and a gate voltage terminal; a second resistor, which is connected between a first body terminal and a body voltage terminal of the first FET; and a third resistor, which is connected between the first source and the first drain.

13. The RF product of claim 12, wherein: The second RF circuit also includes: a fourth resistor, which is connected between the gate terminal and the gate voltage terminal; a fifth resistor, which is connected between the second body terminal of the second FET and the body voltage terminal; and a sixth resistor, which is connected between the second source and the second drain.

14. The RF product of claim 12, wherein the first RF circuit further comprises a seventh resistor connected between the gate voltage terminal and the first resistor; and an eighth resistor connected between the body voltage terminal and the second resistor.

15. The RF product of claim 12, wherein the first source and the second source are electrically connected through the at least one through-hole.

16. The RF product of claim 12, wherein the first drain and the second drain are electrically connected through the at least one through-hole.

17. The RF product of claim 12, wherein the first gate and the second gate are electrically connected through the at least one through-hole.

18. The RF product of claim 12, wherein the second RF circuit further comprises at least one linearity improvement circuit, the at least one linearity improvement circuit being electrically coupled to the first RF circuit through the at least one via.

19. The RF product of claim 12, wherein the second RF circuit further comprises at least one voltage handling improvement circuit, the at least one voltage handling improvement circuit being electrically coupled to the first RF circuit through the at least one through-via.

20. The RF product of claim 12, wherein the second RF circuit further comprises at least one voltage handling improvement circuit and at least one linearity improvement circuit, each of the at least one voltage handling improvement circuit and the at least one linearity improvement circuit being electrically coupled to the first RF circuit through a corresponding one of the at least one through-hole.

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