Linear and bandwidth reconfigurable current buffer or amplifier

Abstract

An apparatus comprising: a positive input for inputting a differential signal; a negative input terminal for the input differential signal; the positive electrode output end is used for outputting differential signals; a negative output terminal for the output differential signal; a first capacitor (C +) comprising a first terminal coupled to the positive output; a second capacitor (C-) comprising a first terminal coupled to the negative output; and a switching network (SWH +, SWL +, SWH-, SWL-) configured to: couple the second terminal of the first capacitor (C +) to the negative input or the positive node based on a mode signal; and coupling a second terminal of the second capacitor (C-) to the positive input or a negative node based on the mode signal (mode).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 886,887, filed on August 12, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to radio frequency (RF) and baseband (BB) circuits, and specifically to a linear and bandwidth reconfigurable current buffer or amplifier that can be used as an interface between a mixer and an analog-to-digital converter (ADC) in a receiver. Background Art

[0004] A mixer is often used in a receiver to down-convert a radio frequency (RF) signal into an intermediate signal (IF) or a baseband (BB) signal. In some applications, an analog-to-digital converter (ADC) is coupled to the output of the mixer. If the mixer is implemented as a current mode mixer, docking the ADC to the output of the current mode mixer may cause certain problems due to the relatively high input impedance of the ADC. For example, this may adversely affect the linearity of the receiver. Therefore, it may be desirable to place an interface circuit between the mixer and the ADC to solve the aforementioned problems. Summary of the invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is subsequently presented.

[0006] One aspect of the present disclosure relates to an apparatus. The apparatus includes a positive input terminal for an input differential signal; a negative input terminal for the input differential signal; a positive output terminal for an output differential signal; a negative output terminal for the output differential signal; a first capacitor, the first capacitor including a first terminal coupled to the positive output terminal; a second capacitor, the second capacitor including a first terminal coupled to the negative output terminal; and a switch network, the switch network being configured to: couple a second terminal of the first capacitor to the negative input terminal or a positive node based on a mode signal; and couple a second terminal of the second capacitor to the positive input terminal or a negative node based on the mode signal.

[0007] Another aspect of the present disclosure relates to a method. The method includes coupling a capacitor to a differential amplifier to configure the capacitor as a Miller capacitor or a gate-drain neutralization capacitor based on a mode signal.

[0008] Another aspect of the present disclosure relates to an apparatus. The apparatus includes: a first input current mirror field effect transistor (FET); a first input FET coupled in series with the first input current mirror FET, wherein the first input FET includes a source configured to receive an input signal; a first variable current source coupled in parallel with the first input current mirror FET; a first output current mirror FET including a gate coupled to a gate / drain of the first input current mirror FET; and a control circuit configured to control an impedance at the source of the first input FET, including adjusting a first current through the input current mirror FET and a second current generated by the first variable current source to control a third current through the first input FET.

[0009] Another aspect of the present disclosure relates to a method. The method includes: generating a first current through an input current mirror field effect transistor (FET); generating a second current through an output current mirror FET related to a current gain multiplied by the first current; generating a third current; and generating a fourth current through the input FET related to a sum of the first current and the third current.

[0010] To achieve the foregoing and related purposes, one or more specific implementations include the features fully described below and specifically pointed out in the claims. The following description and the accompanying illustrations set forth in detail certain illustrative aspects of the one or more specific implementations. However, these aspects are merely indicative of several of the various ways in which the principles of each specific implementation can be employed, and the specification specific implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of an example transmitter system according to an aspect of the present disclosure is illustrated.

[0012] Figure 2 A block diagram illustrating an example radio frequency (RF) to baseband (BB) interface according to another aspect of the disclosure is illustrated.

[0013] Figure 3 A schematic diagram illustrating an example buffer or amplifier according to another aspect of the disclosure is illustrated.

[0014] Figure 4 A schematic diagram illustrating an example current buffer or amplifier according to another aspect of the present disclosure is illustrated.

[0015] Figure 5A A schematic diagram illustrating another example current buffer or amplifier according to another aspect of the present disclosure is illustrated.

[0016] Figure 5B A schematic diagram illustrating another example current buffer or amplifier according to another aspect of the present disclosure is illustrated.

[0017] Figure 5C Another aspect of the present disclosure is illustrated. FIG. 5A to FIG. 5B A graph of an example gain versus frequency response associated with a current buffer or amplifier.

[0018] Figure 5D Another aspect of the present disclosure is to illustrate a method for setting FIG. 5A to FIG. 5B Table of example parameters of the bandwidth of a current buffer or amplifier.

[0019] Fig. 6A A schematic diagram illustrating another example current buffer or amplifier according to another aspect of the present disclosure is illustrated.

[0020] Figure 6B Another aspect of the present disclosure is illustrated. Fig. 6A A graph of example linearity versus effective reference current associated with a current buffer or amplifier.

[0021] Figure 6C Another aspect of the present disclosure is illustrated. Fig. 6A A graph of example input impedance versus effective reference current associated with a current buffer or amplifier.

[0022] Fig. 7A A schematic diagram illustrating another example current buffer or amplifier according to another aspect of the present disclosure is illustrated.

[0023] Figure 7B Another aspect of the present disclosure is illustrated. Fig. 7A A graph of example linearity versus effective reference current associated with a current buffer or amplifier.

[0024] Figure 7C Another aspect of the present disclosure is illustrated. Fig. 7A A graph of an example noise versus gain response associated with a current buffer or amplifier.

[0025] Figure 8 A schematic diagram illustrating another example current buffer or amplifier according to another aspect of the present disclosure is illustrated. DETAILED DESCRIPTION

[0026] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0027] Figure 1 A block diagram of an example transmitter system 100 according to an aspect of the present disclosure is illustrated. As further discussed herein, the transmitter system 100 can be configured to transmit signals in accordance with carrier aggregation, such as uplink carrier aggregation (ULCA). In carrier aggregation, a group of carriers can be used to simultaneously transmit data to one or more remote wireless devices. In addition, the transmitter system 100 includes a feedback receiver to measure and tune a group of transmit chains used to transmit data modulated carriers in accordance with carrier aggregation.

[0028] Specifically, the transmitter system 100 includes an integrated circuit (IC) 110, which may be implemented as a system on a chip (SOC). In this example, the IC 110 includes a first transmission chain, which includes a first digital pre-distortion (DPD) circuit 112-1, a first digital-to-analog converter (DAC) 114-1, a first local oscillator (LO) 120-1, a first up-conversion mixer 116-1, and a first driver amplifier (DA) 118-1 (also referred to as a preamplifier). Similarly, the IC 110 includes a second transmission chain, which includes a second DPD circuit 112-2, a second DAC 114-2, a second LO 120-2, a second up-conversion mixer 116-2, and a second DA 118-2. Although in this example, the IC 110 is shown as having two (2) transmission chains, it should be understood that the IC 110 may include more than two (2) transmission chains.

[0029] In this example, IC 110 includes a feedback receiver (FB RX) including an input stage 150, a low noise amplifier (LNA) 152, a down-conversion mixer 156, an analog-to-digital converter (ADC) 158, a measurement / tuning circuit 160, and a first set of switch devices SW1 to SW4. The measurement / tuning circuit 160 can be any processor-based circuit (e.g., a microprocessor, a microcontroller, a field programmable gate array, etc.), which can include an associated memory with instructions and / or a portion of firmware, etc.

[0030] Furthermore, according to this example, the transmitter system 100 may also include components external to the IC 110, such as a first power amplifier (PA) 121-1, a first directional coupler 122-1, and a first antenna (or antenna array) 124-1 associated with a first transmission chain. Similarly, external to the IC 110, the transmitter system 100 may also include a second PA 121-2, a second directional coupler 122-2, and a second antenna (or antenna array) 124-2 associated with a second transmission chain. Additionally, external to the IC 110, the transmitter system 100 includes a second set of switch devices SW5 to SW7. It should be understood that the division between components located within the IC 110 and components located external to the IC 110 may vary depending on design factors (and certain components of the IC 110 may be split between different ICs, such as the DPD circuit 112-2, which may be an IC different from the mixer 116-2). It should also be appreciated that transmitter system 100 may be implemented with discrete components (instead of IC 110 ) or with integrated components entirely within IC 110 .

[0031] Referring to the first transmission chain, the first digital data signal D TX1 The first DPD circuit 112-1 applies predistortion to the first digital data signal D based on a control signal from the measurement / tuning circuit 160. TX1 To generate a first predistorted digital signal D PX1 The first DAC 114-1 may receive the first predistorted digital signal D directly or via one or more components. PX1 , and the first predistortion digital signal D PX1 Converted into the first predistortion analog signal V PX1 The first mixer 116-1 converts the first predistortion analog signal V PX1 The first LO signal V generated by the first LO 120-1 LO1 Mixing (the first predistortion analog signal V PX1 Up-converting) to generate a first radio frequency (RF) signal V RF1 It should be understood that in some systems, the first mixer 116-1 converts the first predistortion analog signal V PX1 The first LO signal V generated by the first LO 120-1 LO1 Mixing (the first predistortion analog signal V PX1 Upconverting) to generate a first intermediate frequency (IF), which can then be upconverted to an RF frequency at a subsequent transmitter stage. It should be understood that one or more filters can be associated with the first mixer 116-1 to obtain a first RF signal V RF1 The unwanted signal components are essentially removed or suppressed.

[0032] The first DA 118-1 amplifies the first RF signal V based on the control signal generated by the measurement / tuning circuit 160. RF1 To generate a first pre-amplified signal V DA1 The first PA 121 - 1 amplifies the first pre-amplified signal V based on the control signal generated by the measurement / tuning circuit 160 DA1 To generate a first transmission signal V TX1 The first transmission signal V is transmitted via the first directional coupler 122-1. TX1 Provided to the first antenna 124-1 to transmit the first transmission signal V TX1 The first directional coupler 122-1 then couples out the first transmission signal V TX1 part to generate a first feedback signal V for measurement and tuning purposes FB1 , as discussed in more detail further herein.

[0033] Referring to the second transmission chain, the second digital data signal D TX2 The second DPD circuit 112-2 applies predistortion to the second digital data signal D based on the control signal from the measurement / tuning circuit 160. TX2 To generate a second predistortion digital signal D PX2 The second DAC 114-2 may receive the second predistorted digital signal D directly or via one or more components. PX2 , and the second predistortion digital signal D PX2 Converted into the second predistortion analog signal V PX2 The second mixer 116-2 converts the second predistortion analog signal V PX2 and the second LO signal V generated by the second LO 120-2 LO2 Mixing (the second predistortion analog signal V PX2 Up-converting) to generate a second RF signal V RF2 It should be understood that one or more filters may be associated with the second mixer 116-2 to extract the second RF signal V RF2 The unwanted signal components are essentially removed or suppressed.

[0034] The second DA 118-2 amplifies the second RF signal V based on the control signal generated by the measurement / tuning circuit 160. RF2 To generate a second pre-amplified signal V DA2 The second PA 121 - 2 amplifies the second pre-amplified signal V based on the control signal generated by the measurement / tuning circuit 160 . DA2 To generate the second transmission signal VTX2 The second transmission signal V TX2 Provided to the second antenna 124-2 to convert the second transmission signal V TX2 The second directional coupler 122-2 then couples out the second transmission signal V TX2 part to generate a second feedback signal V for measurement and tuning purposes FB2 , as discussed in more detail further herein.

[0035] As discussed, the feedback receiver is used to tune the first transmission chain and the second transmission chain, including tuning the predistortion applied by the first DPD circuit 112-1 and the second DPD circuit 112-2, the gain of the first DA 118-1 and the second DA 118-2, and the gain of the first PA 121-1 and the second PA 121-2. TX1 When tuning the first transmit chain, the measurement / tuning circuit 160 sets the switch devices SW1 and SW5 to their closed states and sets the switch devices SW2, SW3, SW4, and SW6 to their open states. In addition, the measurement / tuning circuit 160 sets the switch device SW7 (which can be implemented as a single-pole double-throw (SPDT) switch) so that the switch device couples the switch device SW5 to the input of the FB RX input stage 150 and decouples the switch device SW6 from the input of the FB RX input stage 150.

[0036] In this configuration, the first feedback signal V is converted to FB1 Provided to the input terminal of FB RX input stage 150 as input feedback signal V FBI FB RX input stage 150 is input with feedback signal V based on the control signal generated by measurement / tuning circuit 160 FBI Provides a desired passband, desired impedance matching at the input of LNA 152, programmable signal attenuation, and third harmonic suppression. Therefore, FB RX input stage 150 is based on the input feedback signal V FBI Generate output feedback signal V FBO . LNA 152 amplifies the output feedback signal V FBO To generate the amplified feedback signal V FBA The mixer 156 will amplify the feedback signal V FBA The first LO signal V received from the first LO 120-1 via the closed switching device SW1 LO1 Mixing (amplifying the feedback signal V FBA Down-converting) to generate the baseband feedback signal V FBADC 158 converts the baseband feedback signal V FB Converted into digital feedback signal D FB The measurement / tuning circuit 160 is based on the digital feedback signal D FB to tune the first transmit chain.

[0037] The measurement / tuning circuit 160 processes the digital feedback signal D FB To measure the first transmission signal V TX1 and controls / tunes the first DPD circuit 112-1 to apply pre-distortion to the first digital data signal D TX1 Thus reducing the first transmission signal V TX1 The measurement / tuning circuit 160 also processes the digital feedback signal D FB To determine the first transmission signal V TX1 The power level of the first DA 118-1 and / or the gain of the first PA 121-1 is thereby controlled / tuned.

[0038] Alternatively or in addition, based on the first pre-amplified signal V DA1 To tune the first transmit chain. In this regard, the measurement / tuning circuit 160 sets the switch devices SW1 and SW3 to their closed states and sets the switch devices SW2, SW4, SW5, and SW6 to their open states. Since the switch devices SW5 and SW6 are open, the measurement / tuning circuit 160 can set the switch device SW7 to any configuration, but setting it toward the first transmit chain can better reduce the signal leakage from the second transmit chain into the FB RX input stage 150. Based on the measurement, the measurement / tuning circuit 160 processes the digital feedback signal D FB To determine the first pre-amplified signal V DA1 The power level of the first DA 118-1 is thereby controlled / tuned. As discussed, the tuning of the second transmission chain may operate in a similar manner to the tuning of the first transmission chain.

[0039] Desirable characteristics of the feedback mixer-ADC 156 / 158 interface may include a wide baseband bandwidth (e.g., approximately 800 megahertz (MHz)), a tunable baseband bandwidth (e.g., from 100 MHz to 800 MHz), high linearity (e.g., third-order intermodulation distortion (IM3) of 65 decibels relative to the carrier (dBc) or better), and low noise (e.g., 200 microvolts root mean square (μVrms) or less). For example, a wide baseband bandwidth may be desired in order to properly measure the distortion of a transmit signal generated by a transmit chain. For example, the mixer-ADC interface 156 / 158 may need to operate at a baseband bandwidth of 1.5 to 2.5 times the bandwidth of the transmit signal to properly characterize the distortion in the transmit signal. If the transmit signal has a bandwidth of 300 MHz, the mixer-ADC interface 156 / 158 should operate at a baseband bandwidth of 450 MHz to 750 MHz. The baseband bandwidth should also be tunable (e.g., from 100 MHz to 800 MHz) in order to properly characterize the distortion of the transmitted signal when the bandwidth of the transmitted signal is small (e.g., 50 MHz) so as not to base the distortion on frequencies exceeding 2.5 times the bandwidth of the signal.

[0040] Furthermore, it may also be desirable for the feedback mixer-ADC 156 / 158 to have high linearity so that it does not add its own nonlinearity to the feedback signal D FB In other words, it is desirable that the measurement / tuning circuit 160 only consider the nonlinearities associated with the transmit chain when applying predistortion to the transmit digital signal, without considering the nonlinearities of the feedback receiver. In addition, it is desirable that the measured distortion be as noise-free as possible in order to achieve an accurate measurement of the distortion of the transmit signal, thereby applying accurate predistortion to the transmit digital signal. Such a mixer-ADC interface having the aforementioned properties is described below.

[0041] Figure 2 A block diagram of an example radio frequency (RF) to baseband (BB) interface 200 according to another aspect of the present disclosure is illustrated. The RF-BB interface 200 includes a current mode mixer 210, a current buffer 220, and an analog-to-digital converter (ADC) 230. With respect to the transmitter system 100, the current mode mixer 210 may correspond to the feedback mixer 156, the ADC 230 may correspond to the feedback ADC 158, and the current buffer 220 may serve as an interface between the current mode mixer 210 and the ADC 230. Although the RF to BB interface 200 is described with reference to the feedback receive path of the transmitter system 100, it should be understood that the RF to BB interface 200 can be applied to any type of receiver application, not just limited to feedback receivers.

[0042] The current mode mixer 210 includes a current mode mixer configured to receive an RF signal (eg, V FBA) of the RF differential input. The current mode mixer 210 also includes a LO signal (eg, V LO1 or V LO2 ) of the LO differential input. The current mode mixer 210 is configured to mix the RF signal with the LO signal to generate a mixed output signal at its differential output terminal. The current mode mixer 210 can perform its mixing operation in the current domain for improving linearity and noise characteristics. Therefore, the mixer output signal can be a current signal.

[0043] The current buffer 220 may perform the following operations: First, the current buffer 220 may be configured to amplify the mixer output signal based on a programmable current gain (M) to generate a BB output signal. Second, the current buffer 220 may be configured to filter the mixer output signal based on a programmable low pass filter (LPF) to remove higher frequency mixing products from the mixer output signal to generate a BB output signal. Third, the current buffer 220 may provide a relatively low and constant input impedance (e.g., approximately 20 ohms (Ω)) to maintain the current mode mixer 210 operating substantially in a linear region. That is, the voltage swing at the output of the current mode mixer 210 is the product of the mixer output current signal at the input impedance of the current buffer 220. Therefore, in order to keep the voltage swing relatively low so as to avoid operating the mixer 210 in a non-linear region, the input impedance of the current buffer 220 is required to be relatively low (e.g., additional benefits include lower FDRSB and / or GVOT). Finally, current buffer 220 can be configured to generate a BB output signal such that a specific voltage swing is produced at the input of ADC 230 to achieve a desired signal-to-noise ratio (SNR) in the analog-to-digital conversion of the BB output signal to a digital BB signal. Several example implementations of such current buffer 220 are described below.

[0044] Figure 3 A schematic diagram of an example buffer (or amplifier / filter) 300 according to another aspect of the present disclosure is illustrated. The buffer 300 is used to explain the relatively wide programmable bandwidth characteristic of the mixer-ADC interface mentioned previously. As discussed, it is desirable for the mixer-ADC interface to have a relatively wide programmable bandwidth, especially for a feedback receiver, because the transmit signal whose distortion is to be characterized may have a varying bandwidth, and in order to characterize the distortion, the bandwidth of the mixer-ADC interface should be three (3) to five (5) times the varying bandwidth of the transmit signal. Moreover, as mentioned previously, the bandwidth of the mixer-ADC interface can be as wide as 100 MHz to 800 MHz.

[0045] Buffer 300 includes an input transistor MA + and MA -A differential pair of FETs, each of which may be implemented as a field effect transistor (FET); or more specifically, as an n-channel metal oxide semiconductor (NMOS) FET (but may also be implemented as a p-channel metal oxide semiconductor (PMOS) FET). + and MA - The NMOS FET MA includes a gate configured to receive the positive component and the negative component of the input differential signal Vin+ and Vin-, respectively. + and MA - The buffer 300 includes drains configured to generate negative and positive components of the output differential signals Vout+ and Vout-, respectively. The buffer 300 may include additional components (not shown), such as active and / or passive output impedances, current sources, and bias circuits.

[0046] To achieve programmable bandwidth, buffer 300 includes a pair of variable capacitors C + and C - And a pair of single-pole double-throw (SPDT) switch devices SW + and SW - . Capacitor C + Coupled to NMOS FET MA + The gate (positive input terminal) of the switching device SW + Similarly, capacitor C - Coupled to NMOS FET MA - The gate (negative input terminal) of the switching device SW - The switching device SW + and SW - The L (which stands for low bandwidth (BW) mode) throw is coupled to the NMOS FET MA + and MA - Similarly, the switch device SW + and SW - The H (which stands for high BW mode) throw is coupled to the NMOS FET MA - and MA + The drain (positive output terminal and negative output terminal) of the switching device SW + and SW - The control input terminal is also included, which is configured to receive a mode signal from a control circuit such as a measurement / tuning circuit 160 for controlling the switching device SW + and SW - Configuration.

[0047] If the switching device SW + and SW -is configured to couple the pole to L throw (the mode signal indicates low BW mode), then capacitor C + and C - Acts as a Miller capacitor. That is, capacitor C + and C - The effective capacitance is given by C*(1+A V ) is given by, where C is the capacitor C + and C - The inherent capacitance of each of the V is the voltage gain (Vout / Vin) of buffer 300. The capacitance "amplification" is due to capacitor C + and C - The voltages on either side of each of the two swing in opposite directions. For example, considering capacitor C + When Vin+ increases, Vout- decreases; and when Vin+ decreases, Vout- increases. The same applies to capacitor C - The voltage on either side of the capacitor moving in the opposite direction has a voltage gain of one (1) plus a voltage gain A. V The factor increases the effective capacitance of the capacitor.

[0048] Via the switch device SW + and SW - The capacitor C + and C - The configuration as a Miller capacitor causes the buffer 300 to have a low pass filter (LPF) frequency response with a relatively low frequency pole. For example, if the voltage gain A of the buffer 300 is V is 10, then the effective capacitance is capacitor C + and C - This is a relatively high capacitance, which translates into a relatively low frequency pole for the LPF response of buffer 300. + and C - Variable to fine tune the pole of the LPF response of buffer 300. As a specific example, in low BW mode, the variable capacitor C + and C - The capacitance of the buffer 300 sets the pole of the LPF response between 100 MHz and 600 MHz.

[0049] If the switching device SW + and SW - is configured to couple the pole to the H throw (the mode signal indicates high BW mode), then capacitor C + and C - Serves as a gate-drain (Cgd) neutralizing capacitor. That is, capacitor C+ and C- respectively neutralize the NMOS FET MA + and M A - the capacitance of the Cgd capacitor. Neutralization of gate-drain capacitance is due to the voltage on either side of the capacitor swinging in the same direction. For example, considering capacitor C + The voltage on the capacitor C is the same as the voltage on the capacitor C. When Vin+ increases, Vout+ increases; and when Vin+ decreases, Vout+ increases. - The voltage on either side of the capacitor moving in the same direction has the effect of shifting the capacitor C + and C - With NMOS FET MA + and M A -The effect of series coupling of Cgd; thereby, neutralizing the capacitance Cgd.

[0050] Via the switch device SW + and SW - The capacitor C + and C - Configuring the Cgd neutralizing capacitor results in the buffer 300 having an LPF frequency response with a relatively high frequency pole. + and C - When variable, the pole of the LPF response of buffer 300 can be tuned to a specific high frequency. As a specific example, in high BW mode, the variable capacitor C + and C - The capacitance of the buffer 300 sets the pole of the LPF response between 600 MHz and 800 MHz.

[0051] Figure 4 A schematic diagram of an example current buffer (or amplifier) ​​400 according to another aspect of the present disclosure is illustrated. The buffer 400 is used to explain how adding a current bleeder to a current buffer allows the associated current mirror to be biased without significantly changing the input impedance. In this way, the biasing of the current mirror can be performed to achieve a particular linearity of the current buffer 400 while maintaining the input impedance relatively low so as not to affect the linearity of the preceding mixer.

[0052] Specifically, the current buffer 400 includes an input current mirror stage 410 and an output current mirror stage 420 for amplifying the differential input current I in+ / I in- To generate the load R L The output current I out For example, the differential input current I in+ / I in- Can be generated by a current mixer, and the load R LThe input current mirror stage 410 includes a first p-channel metal oxide semiconductor (PMOS) FET MA coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (eg, ground). + , the first NMOS FET MB + 、Second PMOS FET MC + and the second NMOS FET MD + Similarly, the input current mirror stage 410 includes a third PMOS FET MA coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. - 、Third NMOS FET MB - 、Fourth PMOS FET MC - and the fourth NMOS FET MD - .

[0053] More specifically, the first PMOS FET MA + is diode connected, including a source coupled to an upper voltage rail Vdd, and a gate and drain coupled together. The first PMOS FET MA + The upper side input current mirror transistor and the positive side input current mirror transistor of the input stage 410 are formed. The first NMOS FET MB + including a first PMOS FET MA coupled to + The first NMOS FET MB has a drain of the gate / drain, a gate configured to receive the first bias voltage Vbn, and a source serving as a positive input terminal of the current buffer 400. + The upper input transistor and the positive input transistor form a common gate configuration. The second PMOSFET MC + The positive input terminal (first NMOS FET MB) of the current buffer 400 is coupled to the positive input terminal (first NMOS FET MB + The second PMOS FET MC has a source electrode and a gate electrode configured to receive a second bias voltage Vbp. + The lower input transistor and the positive input transistor form a common gate configuration. The second NMOS FET MD + are diode connected, including coupled together and coupled to a second PMOS FET MC + The gate and drain of the drain of the second NMOS FETMD are coupled to the source of the lower voltage rail Vss. + The lower side input current mirror transistor and the positive side input current mirror transistor of the input stage 410 are formed.

[0054] The third PMOS FET MA -is diode connected, including a source coupled to the upper voltage rail Vdd, and a gate and drain coupled together. The third PMOS FET MA - The third NMOS FET MB forms a lower input current mirror transistor and a negative input current mirror transistor of the input stage 410. - including coupling to the third PMOS FET MA - The third NMOS FET MB has a drain of the gate / drain, a gate configured to receive the first bias voltage Vbn, and a source serving as a negative input terminal of the current buffer 400. - The upper input transistor and the negative input transistor form a common gate configuration. The fourth PMOS FET MC - The third NMOS FET MB is coupled to the negative input terminal of the current buffer 400. - The fourth PMOS FET MC has a source electrode and a gate electrode configured to receive a second bias voltage Vbp. - The lower input transistor and the negative input transistor form a common gate configuration. The fourth NMOS FET MD - are diode connected, including coupled together and coupled to the fourth PMOS FET MC - The gate and drain of the fourth NMOS FET MD are coupled to the lower voltage rail Vss. - A lower side input current mirror transistor and a negative side input current mirror transistor of the input stage 410 are formed.

[0055] In order to allow control of the linearity of the current buffer 400 while maintaining (or controlling) the input impedance of the current buffer 400 to be substantially constant and at a relatively low impedance (e.g., approximately 20Ω), the input current mirror stage 410 includes a set of variable bleeder current sources I bl1+ ,I bl1- ,I bl2+ and I bl2- . Discharge current source I bl1+ Coupled to the upper voltage rail Vdd and the first PMOS MA + between the gate / drain (e.g., between the first PMOS FET MA + parallel connection). Discharge current source I bl1- Coupled to the upper voltage rail Vdd and the third PMOS MA - between the gate / drain (e.g., with the third PMOS FET MA - parallel connection). Discharge current I bl2+ Coupled to the second NMOS FET MD +between the gate / drain of the second NMOS FET MD and the lower voltage rail Vss (e.g., + parallel connection). Discharge current I bl2- Coupled to the fourth NMOS FET MD - between the gate / drain and the lower voltage rail Vss (e.g., with the fourth NMOS FET MD - in parallel).

[0056] The output current mirror stage 420 includes a first PMOS MA + The gate / drain of the third PMOS MA - The gate / drain of the second NMOS FET MD + The gate / drain and fourth NMOS FET MD - The output current mirror stage 420 is configured to amplify the input current signal I by a gain M. in+ / I in- To generate the output current signal I out The gain M can be variable or programmable to control the load R L As discussed, the load R can represent the ADC. For example, the gain M can be controlled to L The voltage swing range is generated at the input of the ADC to achieve a specific SNR in the conversion of the ADC input signal to a digital signal. For linearity purposes, a higher gain M is usually due to the input current mirror transistor MA across the input stage 410. + 、MA - ,MD + and MD - The lower signal (voltage / current) swing results in improved linearity.

[0057] However, without the bleeder current source I bl1+ ,I bl1- ,I bl2+ and I bl2- In case of maintaining cross load R L The maximum voltage swing is essentially constant while increasing the gain M, which can be reduced through the input current mirror transistor MA + ,MD + 、MA - and MD - The DC current (and therefore, the + , MC + 、MB - and MC - The DC current of the input transistor MB is used to bias the input stage 410, thereby improving linearity. This has the effect of reducing the input transistor MB + , MC+ 、MB - and MC - This results in an increase in the input impedance of the current buffer 400. As previously discussed, increasing the input impedance of the current buffer 400 may adversely affect the linearity of the preceding mixer; this may offset the improvement in linearity due to the increase in gain M.

[0058] Therefore, when the gain M increases and the current mirror transistor MA + 、MA - ,MD + and MD - When the DC current is reduced to improve the linearity of the current mirror of the current buffer 400, the bleeder current source I bl1+ / I bl2+ and I bl1- / I bl2- To provide through the input transistor MB + / MC - and MB - / MC - The additional DC current of the transistors is maintained substantially constant; and thus, the input impedance of the current buffer 400 can be maintained substantially constant at a relatively low impedance (eg, 20Ω).

[0059] Figure 5A A schematic diagram of another example current buffer (or amplifier / filter) 500 according to another aspect of the present disclosure is illustrated. The current buffer 500 is a more detailed implementation of a bandwidth reconfigurable buffer similar to the buffer 300 previously described. That is, as discussed in further detail further herein, the current buffer 500 includes a capacitor that can be reconfigured as a Miller capacitor or a Cgd neutralizing capacitor to configure the current buffer 500 in a low BW mode or a high BW mode, respectively. Moreover, as discussed previously, in the low BW mode, the current buffer 500 can exhibit an LPF frequency response with a pole that is tunable in a first frequency range (e.g., 100 MHz to 600 MHz); and in the high BW mode, the current buffer 500 can exhibit an LPF frequency response with a pole that is tunable in a second frequency range (e.g., 600 MHz to 800 MHz), which is higher than (although possibly overlapping) the first frequency range.

[0060] More specifically, the current buffer 500 includes a first bias current source IB + A first PMOS FET M1 (which may be variable) coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (eg, ground) + . The first PMOS FET M1+ The first PMOSFET M1 is diode-connected, including a source coupled to the upper voltage rail Vdd, and a gate and drain coupled together. + With the first bias current source IB + The node between acts as a positive node for the input differential current signal, which coincides with the positive input terminal (In+) in this example. The positive node, which may coincide with the positive differential input terminal or the intermediate node, has a voltage that changes in the same direction as the positive component of the input differential signal.

[0061] The current buffer 500 also includes a second bias current source IB - A second PMOS FET M1 (which may be variable) coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss - The second PMOS FET M1 - is diode connected, including a source coupled to the upper voltage rail Vdd, and a gate and drain coupled together. The second PMOS FET M1 - With the second bias current source IB - The node between acts as a negative node, which coincides with the negative input terminal (In-) for the input differential current signal. Similarly, the negative node, which may coincide with the negative differential input or intermediate node, has a voltage that changes in the same direction as the negative component of the input differential signal.

[0062] The current buffer 500 also includes a first load R L+ A third PMOS FET M2 coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss + The third PMOS FET M2 + includes a source coupled to the upper voltage rail Vdd and coupled to the second PMOSFET M1 - The gate / drain of the third PMOS FET M2 + With the first load resistor R L+ The node between serves as the positive output terminal (Out+) for the output differential signal of the current buffer 500 .

[0063] In addition, the current buffer 500 includes a second load R L- A fourth PMOS FET M2 coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss - . The fourth PMOS FET M2 - includes a source coupled to an upper voltage rail Vdd and coupled to a first PMOS FET M1 + The gate / drain of the fourth PMOS FET M2 -With the second load resistor R L- The node between serves as the negative output terminal (Out−) for the output differential signal of the current buffer 500 .

[0064] For signal filtering operation, the current buffer 500 further includes a first capacitor C + (which may be variable) and a first set of switching devices SW H+ and SW L+ The first capacitor C + With the switch device SW L+ The first capacitor C is coupled in series between the positive output terminal (Out+) and the negative input terminal (In-) of the current buffer 500. + Also with the switch device SW H+ The first set of switch devices SW is coupled in series between the positive output terminal (Out+) and the positive input terminal (In+) of the current buffer 500. H+ and SW L+ is configured to receive a mode signal to set its configuration.

[0065] Similarly, the current buffer 500 further includes a second capacitor C - (which may be variable) and a second set of switching devices SW H- and SW L- The second capacitor C- and the switching device SW L- The second capacitor C is coupled in series between the negative output terminal (Out-) and the positive input terminal (In+) of the current buffer 500. - Also with the switch device SW H- The second set of switch devices SW is coupled in series between the negative output terminal (Out-) and the negative input terminal (In-) of the current buffer 500. H- and SW L- is configured to receive a mode signal to set its configuration.

[0066] In operation, in response to the mode signal indicating the low BW mode, if the switching device SW L+ and SW L- are set to their closed state, and the switching devices SW H+ and SW H- are set to their disconnected state, the first capacitor C + and the second capacitor C - acts as a Miller capacitor. This is because the capacitor C + and C - The voltages on either side of the capacitor are moving in opposite directions, and the effective capacitance is their inherent capacitance times one (1) plus the voltage gain A across the capacitor. VTherefore, the current buffer 500 operates in a low BW mode, where the variable capacitor C + and C - It can be tuned to achieve an LPF frequency pole within a first frequency range (eg, 100 MHz to 600 MHz).

[0067] In response to the mode signal indicating the high BW mode, if the switching device SW L+ and SW L- are set to their off state, and the switching devices SW H+ and SW H- are set to their closed state, the first capacitor C + and the second capacitor C - It is used as a Cgd neutralizing capacitor. This is because the capacitor C + and C - The voltages on either side of are moving in the same direction and are connected to neutralize the PMOS FET M2 respectively. + and M2 - Therefore, the current buffer 500 operates in a high BW mode, where the variable capacitor C + and C - It can be tuned to achieve an LPF frequency pole in a second frequency range (eg, 600 MHz to 800 MHz) that is higher than the first frequency range.

[0068] Figure 5B A schematic diagram illustrating another example current buffer (or amplifier / filter) 550 according to another aspect of the present disclosure is shown. The current buffer 550 is an NMOS FET version of the current buffer 500 discussed previously.

[0069] More specifically, the current buffer 550 includes a first NMOS FET M3 + A first bias current source IB is coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (eg, ground). + (It can be variable). First NMOS FET M3 + is diode-connected, including a gate and a drain coupled together, and a source coupled to a lower voltage rail Vss. The first bias current source IB + With the first NMOS FET M3 + The node between acts as the positive node of the input differential current signal for the current buffer 500, which in this example may coincide with the positive input terminal (In+). As previously discussed, the positive node, which may coincide with the positive differential input terminal or the intermediate node, has a voltage that varies in the same direction as the positive component of the input differential signal.

[0070] The current buffer 550 also includes a second NMOS FET M3 - A second bias current source IB is coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss - (It can be variable). Second NMOS FET M3 - is diode-connected, including a gate and drain coupled together, and a source coupled to a lower voltage rail Vss. The second bias current source IB - With the second NMOSFET M3 - The node between acts as a negative node for the input differential current signal, which in this example coincides with the negative input terminal (In-). As previously discussed, the negative node, which may coincide with the negative differential input terminal or the intermediate node, has a voltage that changes in the same direction as the negative component of the input differential signal.

[0071] The current buffer 550 also includes a third NMOS FET M4 + A first load R coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss L+ The third NMOS FET M4 + includes coupling to the second NMOS FET M3 - The gate / drain of the first load resistor R is connected to the gate of the second load resistor R and the source is coupled to the lower voltage rail Vss. L+ With the third NMOS FET M4 + The node between serves as a positive node, which can serve as a residual positive output terminal (Out+) for the output differential current signal of the current buffer 550.

[0072] In addition, the current buffer 550 includes a fourth NMOS FET M4 - A second load R is coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. L- The fourth NMOS FET M4 - includes a first NMOS FET M3 coupled to + The gate / drain of the second load resistor R L- With the fourth NMOS FET M4 - The node between serves as the negative output terminal (Out−) for the output differential current signal of the current buffer 550 .

[0073] For signal filtering operation, the current buffer 550 further includes a first capacitor C + (which may be variable) and a first set of switching devices SW H+ and SW L+The first capacitor C + With the switch device SW L+ The first capacitor C is coupled in series between the positive output terminal (Out+) and the negative input terminal (In-) of the current buffer 550. + Also with the switch device SW H+ The first set of switch devices SW is coupled in series between the positive output terminal (Out+) and the positive input terminal (In+) of the current buffer 550. H+ and SW L+ is configured to receive a mode signal to set its configuration.

[0074] Similarly, the current buffer 550 also includes a second capacitor C - (which may be variable) and a second set of switching devices SW H- and SW L- The second capacitor C- and the switching device SW L- The second capacitor C is coupled in series between the negative output terminal (Out-) and the positive input terminal (In+) of the current buffer 550. - Also with the switch device SW H- The second set of switch devices SW is coupled in series between the negative output terminal (Out-) and the negative input terminal (In-) of the current buffer 550. H- and SW L- is configured to receive a mode signal to set its configuration.

[0075] In operation, in response to the mode signal indicating the low BW mode, if the switching device SW L+ and SW L- are set to their closed state, and the switching devices SW H+ and SW H- are set to their disconnected state, the first capacitor C + and the second capacitor C - acts as a Miller capacitor. This is because the capacitor C + and C - The voltages on either side of the capacitor are moving in opposite directions, and the effective capacitance is their inherent capacitance times one (1) plus the voltage gain A across the capacitor. V Therefore, the current buffer 550 operates in a low BW mode, where the variable capacitor C + and C - It can be tuned to achieve an LPF frequency pole within a first frequency range (eg, 100 MHz to 600 MHz).

[0076] In response to the mode signal indicating the high BW mode, if the switching device SW L+ and SW L-are set to their off state, and the switching devices SW H+ and SW H- are set to their closed state, the first capacitor C + and the second capacitor C - It is used as a Cgd neutralizing capacitor. This is because the capacitor C + and C - The voltages on either side of are moving in the same direction and are connected to neutralize the NMOS FET M4 respectively. + and M4 - Therefore, the current buffer 550 operates in the high BW mode, where the variable capacitor C + and C - It can be tuned to achieve an LPF frequency pole in a second frequency range (eg, 600 MHz to 800 MHz) that is higher than the first frequency range.

[0077] Figure 5C Graphs of example gain versus frequency responses associated with current buffers 500 or 550 according to another aspect of the present disclosure are illustrated. The x-axis or horizontal axis represents a logarithmic scale of frequency ranging from 10 MHz to 1 gigahertz (GHz). The y-axis or vertical axis represents normalized gain ranging from +3 dB to -21 dB.

[0078] As shown, the transfer function of current buffer 500 or 550 can be programmed to achieve a low pass filter (LPF) response with various poles (e.g., five (5) as shown). For example, in low BW mode, capacitor C + and C - It can be tuned to achieve an LPF frequency response with poles at 100 MHz (shown as a double-dotted line), 200 MHz (shown as a dotted line), and 400 MHz (shown as a dashed line). In high BW mode, capacitor C + and C- can be tuned to achieve an LPF frequency response with poles at 600 MHz (shown as a dashed line) and 800 MHz (shown as a solid line).

[0079] Figure 5D 1 is a table illustrating example parameters for setting the bandwidth of the current buffer 500 or 550 according to another aspect of the present disclosure. The columns from left to right in the table represent the state of the high BW mode, the state of the low BW mode, the three (3) dB bandwidth (or the frequency of the LPF pole), and the capacitor C + and C - of capacitance.

[0080] As depicted in the table, in low BW mode, as indicated in the second to fourth rows of the table, the capacitor C + and C- The capacitance of the capacitor C is set to 1.65 picofarads (pF), 0.55 pF, and 0.15 pF to achieve bandwidths of 100 MHz, 200 MHz, and 400 MHz, respectively. In high BW mode, as indicated in the fifth and sixth rows of the table, the capacitor C + and C - The capacitance of is set to 0 pF and 0.35 pF to achieve bandwidths of 600 MHz and 800 MHz, respectively. Thus, the configuration of current buffer 500 or 550 allows for eight (8) times reconfigurable bandwidth with a maximum capacitance of 1.65 pF. This allows the current buffer 500 or 550 to be implemented in a circuit area efficient manner.

[0081] Fig. 6A A schematic diagram of another example current buffer (or amplifier) ​​600 according to another aspect of the present disclosure is illustrated. The current buffer 600 is a more detailed implementation of a linearity and input impedance controllable buffer similar to the previously described buffer 400. That is, as further discussed in more detail herein, the current buffer 600 includes a programmable or variable bleeder current source to maintain a substantially constant current through an input transistor to achieve a relatively low input impedance (e.g., approximately 20Ω) while varying the DC bias of the input current mirror transistor. The DC bias of the input current mirror transistor may be varied to set or improve the linearity of the current buffer 600. Specifically, the current buffer 600 includes a replica bias circuit 610, an input current mirror stage 620, and an output current mirror stage 630.

[0082] The replica bias circuit 610 includes a first current source I rb1 (which may be variable or programmable), a diode-connected NMOS FET M5, a diode-connected PMOS FET M6, and a second current source I rb2 (which may also be variable or programmable), all of which are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (eg, ground). In more detail, the first current source I rb1 The second current source I is coupled between the upper voltage rail Vdd and the gate / drain of the NMOS FET M5. The source of the NMOS FET M5 is coupled to the source of the PMOS FET M6. rb2 The replica bias circuit 610 further includes an operational amplifier 612 configured as a voltage follower or buffer, the operational amplifier including a positive input terminal configured to receive a target common mode voltage Vcm for setting the common mode voltage of the input current mirror stage 620, and a negative input terminal and an output coupled to the sources of the NMOS FET M5 and the PMOS FET M6.

[0083] As discussed in more detail herein, the first current source I rb1 The diode-connected NMOS FET M5 is a replica of the input common-gate NMOS FET of the input current mirror stage 620, the diode-connected PMOS FET M6 is a replica of the input common-gate PMOS FET of the input current mirror stage 620, and the second current source I rb2 is a replica of the lower current source of the input current mirror stage 620. The replica bias circuit 610 is configured to generate a reference current I through the NMOSFET M5 and the PMOS FET M6. REF To generate a first bias voltage cgb for the gates of the input common-gate NMOS FET and PMOS FET of the input current mirror stage 620 n and the second bias voltage cgb p The size or effective channel width to length ratio (W / L) of the input common-gate NMOS FET and PMOS FET of the input current mirror stage 620 may be N times the size or effective W / L of the NMOS FET M5 and the PMOSFET M6, so that the DC current flowing through the input NMOS FET and the PMOSFET of the input current mirror stage 620 is N*I REF .

[0084] The input current mirror stage 620 includes a positive current path including a diode-connected PMOS FET M7. + , Input common-gate NMOS FET M8 + , Input common gate PMOS FET M9 + NMOS FET M10 connected to diode + , all of which are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, PMOS FET M7 + Includes a source coupled to the upper voltage rail Vdd and a gate and drain coupled together. NMOS FET M8 + Includes coupling to PMOSFET M7 + The gate / drain of the drain and is configured to receive the first bias voltage cgb generated by the replica bias circuit 610 n The gate of PMOS FET M9 + Includes coupling to NMOS FET M8 + The source of the source of the source, and is configured to receive the second bias voltage cgb generated by the replica bias circuit 610 p Gate of NMOS FET M10 +including coupled together and coupled to the PMOS FET M9 + The positive current path also includes a gate and drain of the drain of the PMOS FET M7 coupled to the upper voltage rail Vdd and the source coupled to the lower voltage rail Vss. + The variable bleeder current source I between the gate / drain bl1+ (For example, with PMOS FET M7 + parallel); and coupled to NMOS FET M10 + The variable bleeder current source I between the gate / drain and the lower voltage rail Vss bl2+ (For example, with NMOS FET M10 + in parallel).

[0085] The input current mirror stage 620 also includes a negative current path including a diode-connected PMOS FET M7. - , Input common-gate NMOS FET M8 - , Input common gate PMOS FET M9 - NMOS FET M10 connected to diode - , all of which are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, PMOS FET M7 - Includes a source coupled to the upper voltage rail Vdd and a gate and drain coupled together. NMOS FET M8 - Includes coupling to PMOSFET M7 - The gate / drain of the drain and is configured to receive a first bias voltage cgb n The gate of PMOS FET M9 - Includes coupling to NMOS FET M8 - The source of the source of the source, and is configured to receive a second bias voltage cgb p The gate of NMOSFET M10 - including coupled together and coupled to the PMOS FET M9 - The negative current path also includes a gate and drain of the drain of the PMOS FET M7 coupled to the upper voltage rail Vdd and the source coupled to the lower voltage rail Vss. - The variable bleeder current source I between the gate / drain bl1- (For example, with PMOS FET M7 - parallel); and coupled to NMOS FET M10 - between the gate / drain and the lower voltage rail Vss (e.g., with NMOS FET M10 -The variable discharge current source I bl2- .

[0086] The output current mirror stage 630 includes a positive current path including a positive current path connected to the NMOS FET M12. + PMOS FET M11 coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss + . PMOS FET M11 + The gate of PMOSFET M7 is coupled to - Gate / drain of NMOS FET M12 + The gate of the NMOS FET M10 is coupled to - The output current mirror stage 630 includes a negative current path including a gate / drain connected to the NMOS FET M12. - PMOS FET M11 coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss - . PMOS FET M11 - The gate of the PMOS FET M7 is coupled to + Gate / drain of NMOS FET M12 - The gate of the NMOS FET M10 is coupled to + of the gate / drain.

[0087] NMOS FET M8 + and PMOS FET M9 + The source of NMOS FET M8 serves as the positive input terminal (In+) for the input differential current signal. - and PMOS FET M9 - The source of PMOS FET M11 serves as the negative input terminal (In-) for the input differential current signal. + and NMOS FET M12 + The source of PMOS FET M11 serves as the positive output terminal (Out+) for the output differential current signal. - and NMOS FET M12 - The source of the load R acts as the negative output terminal (Out-) for the output differential current signal. L (eg, the input terminal of the ADC) is coupled between the positive output terminal (Out+) and the negative output terminal (Out−) of the current buffer 600 .

[0088] The output current mirror PMOS FET M11+ / M11- and NMOS FET M12+ / M12- of the output stage 630 may have the same size or W / L as the input current mirror PMOS FET M7 of the input stage 620. + / M7 - and NMOS FET M10 + / M10 - The magnitude of or M times W / L is used to achieve a current gain M between the output differential current signal and the input differential current signal, where M is variable or programmable. The variable M can be set to L A specific voltage swing range is generated at the input of the ADC to achieve a specific SNR in the conversion of the output differential signal to a digital signal. L The maximum voltage swing at the input current mirror stage 620 is maintained constant to achieve the desired SNR, and the current gain M is increased, which can reduce the PMOS FET M7 through the input current mirror stage 620. + / M7 - and NMOS FET M10 + / M10 - The DC current is used to bias the input current mirror stage 620 to improve linearity. If the bleeder current source I bl1+ / I bl1- and I bl2+ / I bl2- does not exist, then a reduced DC current will flow through the input transistor M8 + / M8 - and M9 + / M9 - , which will increase the input impedance of the current buffer 600 .

[0089] Therefore, when the current gain M is changed to achieve a cross-load R L For a specific voltage swing and / or for a specific linearity of the current buffer 600, the bleeder current source I bl1+ / I bl1- and I bl2+ / I bl2- is programmed to generate a DC current so that through the input transistor M8 + / M8 - and M9 + / M9 - The current of is maintained substantially constant to achieve a substantially constant low impedance (eg, approximately 20Ω). For example, due to the current gain N between the input current mirror stage 620 and the replica bias circuit 610, the current through the input transistor M8 + / M8 - and M9 + / M9 -The DC current is N*I REF If SNR and / or linearity considerations are considered (where K is a number between 0 and 1), the transistor PMOS FET M7 of the input current mirror stage 620 is + / M7 - and NMOS FET M10 + / M10 - The DC current is reduced to (1-K)*N*I REF , then the discharge current source I bl1+ / I bl1- and I bl2+ / I bl2- is programmed to generate a DC current K*N*I REF , to pass through the input transistor M8 + / M8 - and M9 + / M9 - The DC current is N*I REF Maintain essentially constant.

[0090] Figure 6B 1 illustrates an example linearity versus effective reference DC current graph associated with current buffer 600 according to another aspect of the present disclosure. The x-axis or horizontal axis represents the effective reference DC current in microamperes (μA) ranging from 0 μA to 160 μA. If the bleeder current source I bl1+ / I bl1- and I bl2+ / I bl2- does not exist, the effective DC current is the current (1-K)*I flowing through the replica bias circuit 610 REF , which implements the DC current (1-K)*N*I flowing in the input current mirror stage 620 REF The y-axis or vertical axis represents the linearity of the output of the current buffer 600 in dBc, ranging from 45 dBc to 75 dBc, as represented by third order intermodulation distortion products (IM3).

[0091] The graph depicts the effective (1-K)*I for current gains M of -10 dB (shown as a double dotted line), -6 dB (shown as a dotted line), -2.5 dB (shown as a long dashed line), 0 dB (shown as a short dashed line), +3.5 dB (shown as a dashed line), and +5.75 dB (shown as a solid line). REF These responses indicate that the higher gain M is generally due to the input current mirror transistor M7 across the input stage 620. + 、M7 - 、M10 + and M10 -The lower signal (voltage / current) swing of 1 leads to improved linearity. This response also indicates that the effective reference current (1-K)*I REF Reducing to a certain point also improves the linearity of the current buffer 600. For example, maximum linearity at about 69 dBc can be achieved with an effective reference current of about 40 μA (1-K)*I REF This is because the effective reference current is reduced by (1-K)*I REF The transistor M7 of the input current mirror stage 620 is reduced + / M7 - and M10 + / M10 - The nonlinearity.

[0092] Figure 6C 1 illustrates an example input impedance versus effective reference DC current (1-K)*I associated with a current buffer 600 according to another aspect of the present disclosure. REF The x-axis or horizontal axis represents the effective reference DC current in μA ranging from 50 μA to 100 μA. The y-axis or vertical axis represents the input impedance Zin of the current buffer 600 ranging from 0Ω to 25Ω. As shown in the graph, due to the varying K, the input impedance Zin varies with the effective reference current (1-K)*I REF When changing from 50μA to 100μA, the impedance is basically constant at a relatively low impedance of about 21Ω. This is because the bleeder current source I bl1+ / I bl1- and I bl2+ / I bl2- Also provides current K*N*I REF , this current also changes with K, so that through the input transistor M8 + / M8 - and M9 + / M9 - The current of each of the input transistors M8 is maintained substantially constant. + / M8 - and M9 + The transconductance gain of / M9 remains substantially constant; and therefore, the input impedance Zin remains substantially constant and may be set to a relatively low impedance (eg, approximately 21Ω).

[0093] Fig. 7AA schematic diagram of another example current buffer (or amplifier) ​​700 according to another aspect of the present disclosure is illustrated. The current buffer 700 is similar to the current buffer 600, except that the transistors of the input current mirror stage and the output current mirror stage are stacked for improved linearity and noise characteristics. Similarly, the current buffer 700 includes a replica bias circuit 710, an input current mirror stage 720, and an output current mirror stage 730.

[0094] The replica bias circuit 710 includes a first current source I rb1 (which may be variable or programmable), a diode-connected NMOS FET M13, a diode-connected PMOS FET M14, and a second current source I rb2 (which may also be variable or programmable), all of which are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (eg, ground). In more detail, the first current source I rb1 The second current source I is coupled between the upper voltage rail Vdd and the gate / drain of the NMOS FET M13. The source of the NMOS FET M13 is coupled to the source of the PMOS FET M14. rb2 The replica bias circuit 710 further includes an operational amplifier 712 configured as a voltage follower or buffer, the operational amplifier including a positive input terminal configured to receive a target common mode voltage Vcm for setting the common mode voltage of the input current mirror stage 720, and a negative input terminal and an output coupled to the sources of the NMOS FET M13 and the PMOS FET M14.

[0095] Similarly, the first current source I rb1 The diode-connected NMOS FET M13 is a replica of the input common-gate NMOS FET of the input current mirror stage 720, the diode-connected PMOSFET M14 is a replica of the input common-gate PMOS FET of the input current mirror stage 720, and the second current source I rb2 is a replica of the lower current source of the input current mirror stage 720. The replica bias circuit 710 is configured to generate a reference current I through the NMOS FET M13 and the PMOS FET M14. REF To generate a first bias voltage cgb for the gates of the input common-gate NMOS FET and PMOSFET of the input current mirror stage 720 n and the second bias voltage cgb pThe size or effective W / L of the input common-gate NMOSFET and PMOS FET of the input current mirror stage 720 may be N times the size or effective W / L of the NMOS FET M13 and the PMOS FET M14, so that the DC current flowing through the input NMOS FET and PMOS FET of the input current mirror stage 720 is N*I REF .

[0096] The input current mirror stage 720 includes a positive current path including a diode-connected stacked PMOSFET M15 + and M16 + , Input common gate NMOS FET M17 + , Input common gate PMOS FET M18 + and diode connected stacked NMOS FET M19 + and M20 + , all of which are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, the stacked PMOS FET M15 + The source is coupled to the upper voltage rail Vdd, coupled to the stacked PMOS FET M16 + The gate and drain of the stacked PMOS FET M16 are coupled to the + The source of the drain. NMOS FET M17 + Includes coupling to stacked PMOS FET M16 + The gate / drain of the drain and is configured to receive the first bias voltage cgb generated by the replica bias circuit 710 n Gate of PMOS FET M18 + Includes coupling to NMOS FET M17 + The source of the source of the source, and is configured to receive the second bias voltage cgb generated by the replica bias circuit 710 p The gate of the stacked NMOS FET M19 + including coupled to the stacked PMOS FET M20 + The gate of the PMOS FET M18 is coupled to the + The gate and drain of the drain, and coupled to the stacked NMOS FET M20 + The source of the drain. Stacked NMOS FET M20 + The positive current path also includes a source coupled to the lower voltage rail Vss. The positive current path also includes a source coupled to the upper voltage rail Vdd and the PMOS FET M16 + The variable bleeder current source I between the gate / drain bl1+(For example, with PMOS FET M15 + and M16 + parallel); and coupled to PMOS FET M19 + The variable bleeder current source I between the gate / drain and the lower voltage rail Vss bl2+ (For example, with stacked NMOS FET M19 + and M20 + in parallel).

[0097] The input current mirror stage 720 also includes a negative current path including a diode-connected stacked PMOS FET M15. - and M16, input common-gate NMOS FET M17 - , Input common gate PMOS FET M18 - and diode connected stacked NMOS FET M19 - and M20 - , all of which are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, the stacked PMOS FET M15 - The source is coupled to the upper voltage rail Vdd, coupled to the stacked PMOSFET M16 - The gate and drain of the PMOS FET M16 are coupled to the - The source of the drain. NMOS FET M17 - Includes coupling to stacked PMOS FET M16 - The gate / drain of the drain and is configured to receive a first bias voltage cgb n Gate of PMOS FET M18 - Includes coupling to NMOS FET M17 - The source of the source of the source, and is configured to receive a second bias voltage cgb p The gate of the stacked NMOS FET M19 - including a stacked NMOS FET M20 coupled to its gate - The gate and PMOS FET M18 - The drain of the stacked NMOS FET M19 - Includes coupling to stacked NMOS FET M20 - The stacked NMOS FET M20 includes a source coupled to the lower voltage rail Vss. The negative current path also includes a source coupled to the upper voltage rail Vdd and the PMOS FET M16. - The variable bleeder current source I between the gate / drainbl1- (For example, with stacked PMOS FET M15 - and M16 - parallel); and coupled to PMOS FET M19 - The variable bleeder current source I between the gate / drain and the lower voltage rail Vss bl2- (For example, with stacked NMOS FET M19 - and M20 - in parallel).

[0098] The output current mirror stage 730 includes a positive current path including a stacked NMOS FET 734. + Stacked PMOS FET 732 coupled in series between upper voltage rail Vdd and lower voltage rail Vss + . Stacked PMOS FET 732 + The gate of the PMOS FET M16 is coupled to - Gate / Drain. Stacked NMOS FET 734 + The gate of NMOS FETM19 is coupled to - The output current mirror stage 730 also includes a negative current path including a stacked NMOSFET 734. - Stacked PMOS FET 732 coupled in series between upper voltage rail Vdd and lower voltage rail Vss - . Stacked PMOSFET 732 - The gate of the PMOS FET M16 is coupled to + Gate / Drain. Stacked NMOS FET 734 - The gate of the NMOS FET M19 is coupled to + of the gate / drain.

[0099] NMOS FET M17 + and PMOS FET M18 + The source of NMOS FET M17 serves as the positive input terminal (In+) for the input differential current signal. - and PMOS FET M18 - The source of the bottom stacked PMOS FET 732 serves as the negative input terminal (In-) for the input differential current signal. + and top stacked NMOS FET 734 + The source of the bottom stacked PMOS FET 732 serves as the positive output terminal (Out+) for the output differential current signal. -and top stacked NMOS FET 734 - The source of the load R acts as the negative output terminal (Out-) for the output differential current signal. L (eg, the input terminal of the ADC) is coupled between the positive output terminal (Out+) and the negative output terminal (Out−) of the current buffer 700 .

[0100] Stacked PMOS FET 732 of output current mirror stage 730 + / 732 - and stacked NMOS FET 734 + / 734 - The size or W / L may be the stacked PMOS FET M15 of the input current mirror stage 720 + -M16 + / M15 - -M16 - and stacked NMOSFET M19 + -M20 + / M19 - -M20 - The magnitude of or W / L is M times to achieve a current gain M between the output differential current signal and the input differential current signal, where M is variable or programmable. As in current buffer 600, variable M can be set to L The voltage swing range is generated at the input of the ADC to achieve a specific SNR in the conversion of the output differential signal to a digital signal. L The maximum voltage swing at is maintained constant to achieve the desired SNR, and the current gain M is increased, then the stacked PMOS FET M15 of the input current mirror stage 720 is + -M16 + / M15 - -M16 - and stacked NMOS FETM19 + -M20 + / M19 - -M20 - The DC current decreases. If the bleeder current source I bl1+ / I bl1- and I bl2+ / I bl2- does not exist, then a reduced DC current will flow through the input transistor M8 + / M8 - and M9 + / M9 - , which will increase the input impedance of the current buffer 700.

[0101] Therefore, when the current gain M is changed to achieve a cross-load R L For a specific maximum voltage swing and / or a specific linearity of the current buffer 700, the bleeder current source I bl1+ / I bl1- and I bl2+ / I bl2- is programmed to generate a DC current so that through the input transistor M17 + / M17 - and M18 + / M18 - The DC current of the input current mirror stage 720 is maintained substantially constant to achieve a substantially constant low impedance (e.g., approximately 20Ω), as previously discussed in detail with respect to the current buffer 600. As further discussed herein, the stacked PMOS FETs and NMOS FETs of the input current mirror stage 720 and the stacked PMOS FETs and NMOSFETs of the output current mirror stage 730 can improve the linearity and noise characteristics of the current buffer 700.

[0102] Figure 7B An example linearity versus effective reference DC current graph associated with current buffer 700 according to another aspect of the present disclosure is illustrated. The x-axis or horizontal axis represents the effective reference DC current ranging from 0 μA to 160 μA. The y-axis or vertical axis represents the linearity at the output of current buffer 700 in dBc ranging from 55 dBc to 75 dBc, as represented by IM3.

[0103] The graph depicts the IM3 response to the effective current reference for stacked input and output current mirror transistors (shown as solid lines) and non-stacked input and output current mirror transistors (shown as dashed lines). As shown, the linearity of the current buffer 700 is substantially improved for the stacked current mirror transistors compared to the non-stacked current mirror transistors. This is because the transistors in the stacked transistors that are closer to the voltage rails Vdd and Vss act as source degeneration for the other transistors in the stacked transistors. In this way, the transconductance gain of the stacked transistors that are further away from the voltage rails Vdd and Vss is reduced; thereby, the linearity of the current buffer 700 is improved. In this particular example, when the effective reference DC current is set to approximately 50μA, the best linearity of 72dBc is achieved for the stacked current mirror transistor implementation.

[0104] Figure 7CA graph of an example noise versus gain response associated with a current buffer 700 according to another aspect of the present disclosure is illustrated. The x-axis or horizontal axis of the graph represents the current gain M of the current buffer 700 ranging from 0 dB to 6 dB. The y-axis or vertical axis represents the integrated noise in a frequency range of 2 kilohertz (KHz) to 200 MHz in micro voltage root mean square (μVrms) ranging from 50 μVrms to 300 μVrms. The graph depicts the noise versus current gain M for stacked input and output current mirror transistors (shown as solid lines) and non-stacked input and output current mirror transistors (shown as dashed lines).

[0105] As shown, the noise characteristics of the current buffer 700 are significantly improved for stacked current mirror transistors compared to non-stacked current mirror transistors. For similar reasons, the improvement in noise characteristics is due to the transistors in the stacked transistors that are closer to the voltage rails Vdd and Vss acting as source degradation for other transistors in the stacked transistors. In this way, the transconductance gain of the stacked transistors that are further away from the voltage rails Vdd and Vss is reduced; thereby, the noise generated by the current buffer 700 is reduced.

[0106] Figure 8 A block diagram of another example current buffer (or amplifier / filter) 800 according to another aspect of the present disclosure is illustrated. The current buffer 800 combines many of the features discussed previously, including: (1) reconfigurable bandwidth by reusing capacitors as Miller capacitors or Cgd neutralizing capacitors; (2) a bleeder current source to control the input impedance of the current buffer 800 while changing the bias of the current mirror transistors of the input current mirror stage; (3) stacked current mirror transistors of the current mirror to improve linearity and noise characteristics; and (4) a variable or programmable current gain M and a variable or programmable effective reference current (1-K)*I REF The linearity of the current buffer 800 can be set as required. Specifically, the current buffer 800 includes a replica bias circuit 810 , an input current mirror stage 820 , an output current mirror stage 830 , a reconfigurable bandwidth circuit 840 and an output common voltage control circuit 850 .

[0107] The replica bias circuit 810 includes a first current path including a first current source I rb1 (which may be variable or programmable), a diode-connected NMOS FET M21, a diode-connected PMOS FET M22, and a second current source I rb2 (which may also be variable or programmable), all of which are coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (eg, ground). In more detail, the first current source I rb1is coupled between the upper voltage rail Vdd and the gate / drain of the NMOS FET M21. The NMOS FET M21 includes a source coupled to the source of the PMOS FET M22. The second current source I rb2 The replica bias circuit 810 further includes an operational amplifier 812 configured as a voltage follower or buffer, the operational amplifier including a positive input terminal configured to receive an input target common mode voltage Vcm_in for setting the common mode voltage of the input current mirror stage 820, and a negative input terminal and an output coupled to the sources of the NMOS FET M21 and the PMOS FET M22.

[0108] The replica bias circuit 810 also includes a second current path, which includes a diode-connected stacked PMOS FET 814, an NMOS FET M23, a PMOS FET M24, and a diode-connected stacked NMOS FET 816, all of which are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, the diode-connected stacked PMOS FET 814 is coupled between the upper voltage rail Vdd and the drain of the NMOS FET M23. The NMOS FET M23 includes a gate coupled to the gate / drain of the NMOS FET M21, and a source coupled to the source of the PMOS FET M24. The PMOS FET M24 includes a gate coupled to the gate / drain of the PMOS FET M22. The diode-connected stacked NMOS FET 816 is coupled between the drain of the PMOS FET M24 and the lower voltage rail Vss.

[0109] The first current source I rb1 The diode-connected stacked PMOS FET M25 may be the input current mirror stage 820 + / M26 + and M25 - / M26 - The diode-connected stacked PMOS FET 814 may be a replica of each of the stacked PMOS FET variable bleeder current sources 822+ and 822- of the input voltage mirror stage 820, and the NMOSFETs M21 and M23 are input common-gate NMOS FETs M27 of the input current mirror stage 820. + and M27 - PMOSFETs M22 and M24 are replicas of the input current mirror stage 820 and the output common-gate PMOS FET M28 + and M28 - A replica of the second current source Irb2 The diode-connected stacked NMOS FET M29 is the input current mirror stage 820 + / M30 + and M29 - / M30 - , and the stacked NMOS FET 816 can be a replica of each of the stacked NMOS FET variable drain current sources 824+ and 824- of the input current mirror stage 820.

[0110] The replica bias circuit 810 is configured to generate a reference current I through each of the NMOS FETs M21 / M23 and the PMOS FETs M22 / M24. REF To generate the input common-gate NMOS FET M27 + / M27 - and PMOS FETM28 + / M28 - The first gate bias voltage cgb n and the second bias voltage cgb p ; and respectively generate a stacked PMOSFET discharge current source 822 + / 822 - and stacked NMOS FET bleeder current source 824 + / 824 - The third gate bias voltage blb p and the fourth bias voltage blb n The input common-gate NMOS FET M27 of the input current mirror stage 820 + / M27 - and PMOS FETM28 + / M28 - The size or effective W / L of the input current mirror stage 820 may be N times the size or effective W / L of the NMOS FETs M21 / M23 and the PMOS FETs M22 / M24, so that the input NMOS FET M27 flowing through the input current mirror stage 820 + / M27 - and PMOS FET M28 + / M28 - The DC current is N*I REF .

[0111] The input current mirror stage 820 includes a positive current path including a stacked PMOS FET M25. + and M26 + , Input common gate NMOS FET M27 +, Input common gate PMOS FET M28 + And stacked NMOS FET M29 + and M30 + , which are all coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, the stacked PMOS FET M25 + The source is coupled to the upper voltage rail Vdd, coupled to the stacked PMOS FET M26 + The gate and drain of the stacked PMOS FET M26 are coupled to the gate and drain of the stacked PMOS FET M26. + The source of the drain. NMOS FET M27 + Includes coupling to stacked PMOS FETM26 + The gate / drain of the drain and is configured to receive the first bias voltage cgb generated by the replica bias circuit 810 n The gate of PMOS FET M28 + Includes coupling to NMOS FET M27 + The source of the source of the source, and is configured to receive the second bias voltage cgb generated by the replica bias circuit 810 p The gate of the stacked NMOS FET M29 + Includes coupled to stacked NMOS FET M30 + The gate of the PMOS FET M28 is coupled to the + The gate and drain of the drain are coupled to the stacked NMOS FET M30 + The source of the drain. Stacked NMOS FET M30 + Includes a source coupled to a lower voltage rail Vss.

[0112] The positive current path also includes a stacked PMOS FET variable bleeder current source 822 + The stacked PMOS FET variable discharge current source is coupled to the upper voltage rail Vdd and the stacked PMOS FET M26 + Between the gate / drain (e.g., with the stacked PMOS FET M25 + and M26 + parallel); and coupled to PMOS FET M29 + A stacked NMOS FET variable bleeder current source 824 between the gate / drain and the lower voltage rail Vss + (For example, with the stacked NMOS FET M29 + and M30 + Stacked PMOS FET variable discharge current source 822+ comprising a circuit configured to receive a third bias voltage blb generated by the replica bias circuit 810 p The gate of the stacked NMOS FET variable discharge current source 824 + The fourth bias voltage blb generated by the replica bias circuit 810 is configured to receive n of the gate.

[0113] The input current mirror stage 820 also includes a negative current path including stacked PMOS FETs M25 - and M26 - , Input common gate NMOS FET M27 - , Input common gate PMOS FET M28 - And stacked NMOS FET M29 - and M30 - , all of which are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss. In more detail, the stacked PMOSFET M25 - including a source coupled to the upper voltage rail Vdd and coupled to the stacked PMOS FET M26 - The gate of the NMOS FET M27 - Includes coupling to stacked PMOS FET M26 - The gate / drain of the drain and is configured to receive a first bias voltage cgb n The gate of PMOS FET M28 - Includes coupling to NMOS FET M27 - The source of the source of the source, and is configured to receive a second bias voltage cgb p The gate of the stacked NMOS FET M29 - including coupled to its gate, the gate of the stacked NMOS FET M30- and the PMOS FET M28 - The drain of the stacked NMOS FET M29 - Includes coupling to the stacked NMOS FET M30 - The source of the drain. Stacked NMOS FET M30 - Includes a source coupled to a lower voltage rail Vss.

[0114] The negative current path also includes a stacked PMOS FET M26 coupled to the upper voltage rail Vdd. - The stacked PMOS FET variable bleeder current source 822 between the gate / drain - (For example, with stacked PMOS FET M25- and M26 - parallel); and coupled to PMOS FET M29 + A stacked NMOS FET variable bleeder current source 824 between the gate / drain and the lower voltage rail Vss - (For example, with the stacked NMOS FET M29 - and M30 - Stacked PMOS FET variable discharge current source 822 - comprising a circuit configured to receive a third bias voltage blb generated by the replica bias circuit 810 p The gate of the stacked NMOS FET variable discharge current source 824 - The fourth bias voltage blb generated by the replica bias circuit 810 is configured to receive n of the gate.

[0115] The output current mirror stage 830 includes a positive current path that is coupled to a stacked NMOS FET 834. + Stacked PMOS FET 832 coupled in series between upper voltage rail Vdd and lower voltage rail Vss + . Stacked PMOS FET 832 + The gate of the PMOS FET M26 is coupled to - Gate / Drain. Stacked NMOS FET 834 + The gate of the NMOS FET M29 is coupled to - The output current mirror stage 830 also includes a negative current path including a stacked NMOS FET 834. - Stacked PMOS FET 832 coupled in series between upper voltage rail Vdd and lower voltage rail Vss - . Stacked PMOS FET832 - The gate of the PMOS FET M16 is coupled to + Gate / Drain. Stacked NMOS FET 834 - The gate of NMOSFET M29 is coupled to + of the gate / drain.

[0116] NMOS FET M27 + and PMOS FET M28 + The source of NMOS FET M27 serves as the positive input terminal (In+) for the input differential current signal. - and PMOS FET M28 -The source of the bottom stacked PMOS FET 832 acts as the negative input terminal (In-) for the input differential current signal. + and top stacked NMOS FET 834 + The drain of the FET serves as the positive output terminal (Out+) for the output differential current signal. Bottom stacked PMOS FET 832 - and top stacked NMOS FET 834 - The drain of the load R L (eg, the input terminal of the ADC) is coupled between the positive output terminal (Out+) and the negative output terminal (Out−) of the current buffer 800 .

[0117] Stacked PMOS FET 832 of output current mirror stage 830 + / 832 - and stacked NMOS FET 834 + / 834 - The size or W / L may be the stacked PMOS FET M25 of the input current mirror stage 820 + -M26 + / M25 - -M26 - And stacked NMOSFET M29 + -M30 + / M29 - -M30 - The magnitude of or M times W / L is used to achieve a current gain M between the output differential current signal and the input differential current signal, where M is variable or programmable. The variable M can be set to L A specific voltage swing range is generated at the input of the ADC to achieve a specific SNR in the conversion of the output differential signal to a digital signal. L The maximum voltage swing at is maintained constant to achieve the desired SNR, and the current gain M is increased, then the stacked PMOS FET M25 of the input current mirror stage 820 is used. + -M26 + / M25 - -M26 - and stacked NMOS FET M29 + -M30 + / M29 - -M30 - If the bleeder current source 822 + / 822 - and 824 + / 824- does not exist, then a reduced current will flow through the input transistor M27 + / M27 - and M28 + / M28 - , which will increase the input impedance of the current buffer 800.

[0118] Therefore, when the current gain M is changed to achieve a cross-load R L For a specific voltage swing and / or for a specific linearity of the current buffer 800, the bleeder current source 822 + / 822 - and 824 + / 824 - is programmed to generate a current so that through the input transistor M27 + / M27 - and M28 + / M28 - The current of is maintained substantially constant to achieve a substantially constant low input impedance (e.g., approximately 20Ω), as previously discussed. As further discussed herein, the stacked PMOSFET and NMOS FETs of the input current mirror stage 820 and the stacked PMOS FETs and NMOS FETs of the output current mirror stage 830 can improve the linearity and noise characteristics of the current buffer 800.

[0119] The reconfigurable bandwidth circuit 840 includes a set of variable capacitors C 1+ , C 2+ , C 1- and C 2- and a switch network 842. Capacitor C 1+ and C 2+ The capacitor C includes a first terminal coupled to the positive output terminal (Out+) of the current buffer 800 and a second terminal coupled to the switch network 842. Similarly, the capacitor C 1- and C 2- It includes a respective first terminal coupled to the negative output terminal (Out−) of the current buffer 800 , and a respective second terminal coupled to the switch network 842 .

[0120] The switch network 842 is configured to receive a mode signal indicating whether the bandwidth mode is low or high. As discussed in more detail below, if the mode signal indicates low BW mode, the capacitor C 1+ , C 2+ , C 1- and C 2-The second terminal of is coupled to the negative (In-) input terminal and the positive (In+) input terminal of the input current mirror stage 820 to configure the capacitor as a Miller capacitor, respectively. If the mode signal indicates the high BW mode, the capacitor C 1+ , C 2+ , C 1- and C 2- The second terminal of the input current mirror stage 820 is coupled to the positive node pd + and + and the negative node pd - and - The capacitors can be configured as Cgd neutralizing capacitors respectively.

[0121] More specifically, if the mode signal indicates the low BW mode, the switch network 842 switches the capacitor C 1+ and C 2+ The second terminal of the capacitor C is coupled to the negative input terminal (In-) of the current buffer 800, and the capacitor C 1- and C 2- The second terminal of the capacitor C is coupled to the positive input terminal (In+) of the current buffer 800. Since the voltages generated at the positive output terminal (Out+) and the negative output terminal (Out-) vary inversely with the voltages generated at the negative input terminal (In-) and the positive input terminal (In+), respectively, the capacitor C 1+ , C 2+ , C 1- and C 2- The effective capacitance is the inherent capacitance of these capacitors times one plus the voltage gain A V This creates a relatively high capacitance to position the pole of the LPF frequency response of the current buffer 800 within the first frequency range (eg, 100 MHz to 600 MHz).

[0122] If the mode signal indicates the high BW mode, the switch network 842 switches the capacitor C 1+ and C 2+ The second terminal of the capacitor C is coupled to the positive PMOS output terminal (pd+) and the positive NMOS output terminal (nd+) of the input current mirror stage 820, and the capacitor C 1- and C 2- The second terminal of the positive stacked PMOS FET and the negative NMOS FET 832 is coupled to the negative PMOS output terminal (pd-) and the negative NMOS output terminal (nd-) of the input current mirror stage 820. Since the voltage generated at the positive output terminal (Out+) and the negative output terminal (Out-) changes in the same direction as the voltage at the positive PMOS output terminal (pd+) and the positive NMOS output terminal (nd+) and the negative PMOS output terminal (pd-) and the negative NMOS output terminal (nd-), the positive stacked PMOS FET and the NMOS FET 832 are connected to the positive PMOS output terminal (pd-) and the negative NMOS output terminal (nd-).- / 834 - and negative stacked PMOS FET and NMOS FET 832 + / 834 + The gate-drain capacitances of are neutralized, respectively. This produces a relatively low capacitance to position the pole of the LPF frequency response of the current buffer 800 in a second frequency range (eg, 600 MHz to 800 MHz) that is higher than the first frequency range.

[0123] The output common voltage control circuit 850 includes an operational amplifier 852, a common mode feedback (CMFB) circuit 854, and a pair of resistors R cm+ and R cm- . The operational amplifier 852 configured as a voltage follower or buffer includes a positive input terminal configured to receive a target output common mode voltage Vcm_out for setting / controlling the common mode voltage at the output of the current buffer 800. The operational amplifier 852 includes a negative input terminal coupled to its output terminal and an input terminal of the CMFB circuit 854. The CMFB circuit 854 also includes input terminals coupled to the positive output terminal (Out+) and the negative output terminal (Out-) of the current buffer 800 to measure the current common mode voltage. Resistor R cm+ and R cm The CMFB circuit 854 is coupled in series between the positive output terminal (Out+) and the negative output terminal (Out-) of the current buffer 800. cm+ With R cm- The output terminal of the node between.

[0124] In operation, if the CMFB circuit 854 determines that the current common mode voltage at the positive output terminal (Out+) and the negative output terminal (Out-) of the current buffer 800 is lower than the target common mode voltage Vcm_out, the CMFB circuit 854 increases the resistor R cm+ With R cm 800 to increase the current common mode voltage so that it is substantially the same as the target common mode voltage Vcm_out. Similarly, if the CMFB circuit 854 determines that the current common mode voltage at the positive output terminal (Out+) and the negative output terminal (Out-) of the current buffer 800 is higher than the target common mode voltage Vcm_out, the CMFB circuit 854 reduces the resistor R cm+ With R cm to reduce the current common-mode voltage so that it is substantially the same as the target common-mode voltage Vcm_out.

[0125] The following provides an overview of various aspects of the disclosure:

[0126] Aspect 1: A device comprising: a positive input terminal for an input differential signal; a negative input terminal for the input differential signal; a positive output terminal for an output differential signal; a negative output terminal for the output differential signal; a first capacitor, the first capacitor comprising a first terminal coupled to the positive output terminal; a second capacitor, the second capacitor comprising a first terminal coupled to the negative output terminal; and a switching network, the switching network being configured to: couple the second terminal of the first capacitor to the negative input terminal or the positive node based on a mode signal; and couple the second terminal of the second capacitor to the positive input terminal or the negative node based on the mode signal.

[0127] Aspect 2: The apparatus according to aspect 1, wherein the positive node coincides with the positive input terminal, and the negative node coincides with the negative input terminal.

[0128] Aspect 3: An apparatus according to Aspect 1 or 2, wherein the switching network is configured to: couple the second terminal of the first capacitor to the negative input terminal, and couple the second terminal of the second capacitor to the positive input terminal, in response to the mode signal indicating a low bandwidth mode.

[0129] Aspect 4: An apparatus according to any one of Aspects 1 to 3, wherein the switching network is configured to: couple the second terminal of the first capacitor to the positive node, and couple the second terminal of the second capacitor to the negative node, in response to the mode signal indicating a high bandwidth mode.

[0130] Aspect 5: An apparatus according to any one of Aspects 1 to 4, wherein the apparatus further comprises: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first gate and a first drain, wherein the first gate coincides with the positive input terminal, and wherein the first drain coincides with the negative output terminal or the negative node; and a second FET, the second FET comprising a second gate and a second drain, wherein the second gate coincides with the negative input terminal, and wherein the second drain coincides with the positive input terminal or the positive node.

[0131] Aspect 6: The device according to any one of Aspects 1 to 4, the device further comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first source, a first gate, and a first drain, wherein the first source is coupled to an upper voltage rail, and wherein the first gate is coupled to the first drain; a first current source, the first current source is coupled between the first drain and the lower voltage rail, wherein the first drain coincides with the positive input terminal or the positive node; a second FET, the second FET comprising a second source, a second gate, and a second drain, wherein the second source is coupled to the upper voltage rail, and wherein the second gate is coupled to the second a drain; a second current source coupled between the second drain and the lower voltage rail, wherein the second drain coincides with the negative input terminal or the negative node; a third FET, the third FET comprising a third source, a third gate, and a third drain, wherein the third source is coupled to the upper voltage rail, wherein the third gate is coupled to the second gate, and wherein the third drain serves as a positive output terminal; and a fourth FET, the fourth FET comprising a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the upper voltage rail, wherein the fourth gate is coupled to the first gate, and wherein the fourth drain serves as the negative output terminal.

[0132] Aspect 7: According to the device of Aspect 6, the device also includes: a first load, the first load is coupled between the positive output terminal and the lower voltage rail; and a second load, the second load is coupled between the negative output terminal and the lower voltage rail.

[0133] Aspect 8: A device according to any one of Aspects 1 to 4, the device further comprising: a first current source; a first field effect transistor (FET), the first field effect transistor (FET) comprising a first source, a first gate and a first drain, wherein the first current source is coupled between an upper voltage rail and the first drain, wherein the first drain is coupled to the first gate, wherein the first source is coupled to a lower voltage rail, and wherein the first drain serves as the positive input terminal or the positive node; a second current source; a second FET, the second FET comprising a second source, a second gate and a second drain, wherein the second current source is coupled between the upper voltage rail and the second drain, wherein The second drain is coupled to the second gate, wherein the second source is coupled to the lower voltage rail, and wherein the second drain serves as the negative input terminal or the negative node; a third FET, the third FET including a third source, a third gate, and a third drain, wherein the third drain serves as the positive output terminal, wherein the third gate is coupled to the second gate, and wherein the third source is coupled to the lower voltage rail; and a fourth FET, the fourth FET including a fourth source, a fourth gate, and a fourth drain, wherein the fourth drain serves as the negative output terminal, wherein the fourth gate is coupled to the first gate, and wherein the fourth source is coupled to the lower voltage rail.

[0134] Aspect 9: According to the device of Aspect 8, the device also includes: a first load, the first load is coupled between the upper voltage rail and the positive output terminal; and a second load, the second load is coupled between the upper voltage rail and the negative output terminal.

[0135] Aspect 10: An apparatus according to claim 1, wherein the positive node includes a first positive node and a second positive node, wherein the negative node includes a first negative node and a second negative node, wherein the first capacitor includes a first group of capacitors, the first group of capacitors includes a first group of terminals coupled to the positive output terminal, wherein the second capacitor includes a second group of capacitors, the second group of capacitors includes a first group of terminals coupled to the negative output terminal, and wherein the switching network is configured to: based on the mode signal, couple the second group of terminals of the first group of capacitors to the negative input terminal or the first positive node and the second positive node, respectively; and based on the mode signal, couple the second group of terminals of the second group of capacitors to the positive input terminal or the first negative node and the second negative node, respectively.

[0136] Aspect 11: The device according to claim 10, the device further comprising: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), the first p-channel metal oxide semiconductor field effect transistor (PMOSFET) comprising a first PMOS source, a first PMOS gate and a first PMOS drain, wherein the first PMOS gate is coupled to the first PMOS drain, and wherein the first PMOS drain serves as the first anode node; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET), the first n-channel metal oxide semiconductor field effect transistor (NMOSFET) comprising a first NMOS drain, a first NMOS gate and a first NMOS source, wherein the first NMOS drain is coupled to the first PMOS drain, wherein the first NMOS gate is configured to receive a first bias voltage, and wherein the first NMOS source serves as the anode input terminal; a second PMOS FET, the second PMOS a FET including a second PMOS source, a second PMOS gate, and a second PMOS drain, wherein the second PMOS source is coupled to the first NMOS source, wherein the second PMOS gate is configured to receive a second bias voltage, and wherein the second PMOS drain serves as the second anode node; and a second NMOS FET, the second NMOS FET including a second NMOS drain, a second NMOS gate, and a second NMOS source, wherein the second NMOS drain is coupled to the second PMOS drain, and wherein the second NMOS gate is coupled to the second NMOS gate.

[0137] Aspect 12: The apparatus according to claim 11, the apparatus further comprising: a third PMOS FET, the third PMOS FET comprising a third PMOS source, a third PMOS gate, and a third PMOS drain, wherein the third PMOS gate is coupled to the third PMOS drain, and wherein the third PMOS drain serves as the first cathode node; a third NMOS FET, the third NMOS FET comprising a third NMOS drain, a third NMOS gate, and a third NMOS source, wherein the third NMOS drain is coupled to the third PMOS drain, wherein the third NMOS gate is configured to receive the first bias voltage, and wherein the third NMOS source serves as the negative input terminal; a fourth PMOS FET, the fourth PMOS FET comprising a fourth PMOS source, a fourth PMOS gate, and a fourth PMOS drain, wherein the fourth PMOS source is coupled to the third NMOS source, wherein the fourth PMOS gate is configured to receive the second bias voltage, and wherein the fourth PMOS drain serves as the second cathode node; and a fourth NMOS FET, the fourth NMOS The FET includes a fourth NMOS drain, a fourth NMOS gate, and a fourth NMOS source, wherein the fourth NMOS drain is coupled to the fourth PMOS drain, and wherein the fourth NMOS gate is coupled to the fourth NMOS gate.

[0138] Aspect 13: The apparatus according to aspect 12, the apparatus further comprising: a fifth PMOS FET, the fifth PMOSFET comprising a fifth PMOS source, a fifth PMOS gate, and a fifth PMOS drain, wherein the fifth PMOS source is coupled to an upper voltage rail, wherein the fifth PMOS gate is coupled to the first PMOS gate, and wherein the fifth PMOS drain is coupled to the first PMOS source; a sixth PMOS FET, the sixth PMOS FET comprising a sixth PMOS source, a sixth PMOS gate, and a sixth PMOS drain, wherein the sixth PMOS source is coupled to the upper voltage rail, wherein the sixth PMOS gate is coupled to the third PMOS gate, and wherein the sixth PMOS drain is coupled to the third PMOS source; a fifth NMOSFET, the fifth NMOS FET comprising a fifth NMOS drain, a fifth NMOS gate, and a fifth NMOS source, wherein the fifth NMOS drain is coupled to the second NMOS source, wherein the fifth NMOS gate is coupled to the second NMOS gate, and wherein the fifth NMOS source is coupled to a lower voltage rail; and a sixth NMOS FET, the sixth NMOS The FET includes a sixth NMOS drain, a sixth NMOS gate, and a sixth NMOS source, wherein the sixth NMOS drain is coupled to the fourth NMOS source, wherein the sixth NMOS gate is coupled to the fourth NMOS gate, and wherein the sixth NMOS source is coupled to the lower voltage rail.

[0139] Aspect 14: The device according to claim 12, the device further comprising: a fifth PMOS FET, the fifth PMOS FET comprising a fifth PMOS source, a fifth PMOS gate, and a fifth PMOS drain, wherein the fifth PMOS gate is coupled to the first cathode node, and wherein the fifth PMOS drain serves as the positive output terminal; a fifth NMOS FET, the fifth NMOS FET comprising a fifth NMOS source, a fifth NMOS gate, and a fifth NMOS drain, wherein the fifth NMOS gate is coupled to the second anode node, and wherein the fifth NMOS drain is coupled to the fifth PMOS drain; a sixth PMOS FET, the sixth PMOS FET comprising a sixth PMOS source, a sixth PMOS gate, and a sixth PMOS drain, wherein the sixth PMOS gate is coupled to the first cathode node, and wherein the sixth PMOS drain serves as the positive output terminal; and a sixth NMOS FET, the sixth NMOS FET comprising a sixth NMOS source, a sixth NMOS gate, and a sixth NMOS drain, wherein the sixth NMOS gate is coupled to the second cathode node, and wherein the sixth NMOS drain is coupled to the sixth PMOS drain.

[0140] Aspect 15: The apparatus according to claim 14, the apparatus further comprising: a seventh PMOS FET, the seventh PMOS FET comprising a seventh PMOS source, a seventh PMOS gate, and a seventh PMOS drain, wherein the seventh PMOS source is coupled to an upper voltage rail, wherein the seventh PMOS gate is coupled to the fifth PMOS gate, and wherein the seventh PMOS drain is coupled to the fifth PMOS source; an eighth PMOS FET, the eighth PMOS FET comprising an eighth PMOS source, an eighth PMOS gate, and an eighth PMOS drain, wherein the eighth PMOS source is coupled to the upper voltage rail, wherein the eighth PMOS gate is coupled to the sixth PMOS gate, and wherein the eighth PMOS drain is coupled to the sixth PMOS source; a seventh NMOS FET, the seventh NMOS FET comprising a seventh NMOS drain, a seventh NMOS gate, and a seventh NMOS source, wherein the seventh NMOS drain is coupled to the fifth NMOS source, wherein the seventh NMOS gate is coupled to the fifth NMOS gate, and wherein the seventh NMOS source is coupled to a lower voltage rail; and an eighth NMOS FET, the eighth NMOS comprising an eighth NMOS drain, an eighth NMOS gate and an eighth NMOS source, wherein the eighth NMOS drain is coupled to the sixth NMOS source, wherein the eighth NMOS gate is coupled to the sixth NMOS gate, and wherein the eighth NMOS source is coupled to the lower voltage rail.

[0141] Aspect 16: The apparatus according to any one of Aspects 11 to 15, further comprising a bias circuit configured to generate the first bias voltage and the second bias voltage.

[0142] Aspect 17: An apparatus according to Aspect 16, wherein the bias circuit includes a first current source, a diode-connected NMOS FET, a diode-connected PMOS FET, and a second current source, all of which are coupled in series between an upper voltage rail and a lower voltage rail; and a voltage follower, the voltage follower being configured to receive a target common-mode voltage and apply the target common-mode voltage to a node between the diode-connected NMOS FET and the diode-connected PMOS FET, wherein the first bias voltage is generated at a first drain / gate of the diode-connected NMOS FET, and wherein the second bias voltage is generated at a second drain / gate of the diode-connected PMOS FET.

[0143] Aspect 18: According to any one of Aspects 12 to 17, the device also includes: a first variable current source, the first variable current source is coupled between the upper voltage rail and the first PMOS drain of the first PMOS FET; a second variable current source, the second variable current source is coupled between the upper voltage rail and the third PMOS drain of the third PMOS FET; a third variable current source, the third variable current source is coupled between the second NMOS drain of the second NMOS FET and the lower voltage rail; and a fourth variable current source, the fourth variable current source is coupled between the fourth NMOS drain of the fourth NMOS FET and the lower voltage rail.

[0144] Aspect 19: The apparatus according to Aspect 18, wherein the first variable current source and the second variable current source are configured to receive a third bias voltage, and wherein the third variable current source and the fourth variable current source are configured to receive a fourth bias voltage.

[0145] Aspect 20: The apparatus according to Aspect 19, further comprising a bias circuit configured to generate the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage.

[0146] Aspect 21: An apparatus according to Aspect 20, wherein the bias circuit comprises: a first current source, a diode-connected NMOS FET, a diode-connected PMOS FET, and a second current source, all of which are coupled in series between the upper voltage rail and the lower voltage rail; a voltage follower, the voltage follower being configured to receive a target common-mode voltage and apply the target common-mode voltage to a node between the diode-connected NMOS FET and the diode-connected PMOS FET, wherein the first bias voltage is generated at a first drain / gate of the diode-connected NMOS FET, and wherein the second bias voltage is generated at a second drain / gate of the diode-connected PMOS FET; and a third current source, a fifth NMOS FET, a fifth PMOS FET, and a fourth current source, all of which are coupled in series between the upper voltage rail and the lower voltage rail, wherein the gate of the fifth NMOS FET is coupled to the gate of the diode-connected NMOSFET, wherein the gate of the fifth PMOS FET is coupled to the gate of the diode-connected NMOS FET, and wherein the third current source and the fourth current source are configured to generate the third bias voltage and the fourth bias voltage.

[0147] Aspect 22: A method, the method comprising: coupling a capacitor to a differential amplifier to configure the capacitor as a Miller capacitor or a gate-drain neutralization capacitor based on a mode signal.

[0148] Aspect 23: A method according to Aspect 22, wherein coupling the capacitor includes: coupling the capacitor to the differential amplifier to configure the capacitor as a Miller capacitor in response to the mode signal indicating a low bandwidth mode; and coupling the capacitor to the differential amplifier to configure the capacitor as a gate-drain neutralization capacitor in response to the mode signal indicating a high bandwidth mode.

[0149] Aspect 24: A device comprising: an input current mirror field effect transistor (FET); an input FET coupled in series with the input current mirror FET, wherein the input FET includes a gate configured to receive an input signal; a variable current source coupled in parallel with the input current mirror FET; an output current mirror FET, the output current mirror FET including a gate coupled to the gate / drain of the first input current mirror FET; and a control circuit configured to control the impedance at the gate of the input FET, including adjusting a first current through the first input current mirror FET and a second current generated by the first variable current source to control a third current through the input FET.

[0150] Aspect 25: The apparatus according to Aspect 24, wherein the control circuit is configured to adjust the first current and the second current so that the third current is substantially constant.

[0151] Aspect 26: An apparatus according to Aspect 24 or 25, wherein the apparatus further includes: a second input FET, the second input FET including a source coupled to the source of the first input FET; a second input current mirror FET, the second input current mirror FET coupled in series with the second input FET; a second variable current source, the second variable current source coupled in parallel with the second input current mirror FET; and a second output current mirror FET, the second output current mirror FET including a gate coupled to the gate / drain of the second input current mirror FET, wherein the control circuit is configured to control the impedance at the source of the first input FET and the second input FET, including adjusting the first current through the first input current mirror FET and the second input current mirror FET and the second current generated by the first variable current source and the second variable current source to control the third current through the first input FET and the second input FET.

[0152] Aspect 27: An apparatus according to any one of Aspects 24 to 26, the apparatus further comprising: a second input FET, the second input FET comprising a gate coupled to the gate of the first input FET, wherein the second input FET comprises a source configured to receive the input signal; a second input current mirror FET, the second input current mirror FET coupled in series with the second input FET; a second variable current source, the second variable current source coupled in parallel with the second input current mirror FET; and a second output current mirror FET, the second output current mirror FET comprising a gate coupled to the gate / drain of the second input current mirror FET, wherein the control circuit is configured to control the impedance at the source of the first input FET and the second input FET, including adjusting a fourth current through the second input current mirror FET and a fifth current generated by the second variable current source to control a sixth current through the second input FET.

[0153] Aspect 28: The apparatus according to Aspect 24, further comprising: a second input FET, the second input FET comprising a source coupled to the source of the first input FET; a second input current mirror FET, the second input current mirror FET being coupled in series with the second input FET; a second variable current source, the second variable current source being coupled in parallel with the second input current mirror FET; a second output current mirror FET, the second output current mirror FET comprising a gate coupled to the gate / drain of the second input current mirror FET; a third input FET, the third input FET comprising a gate coupled to the gate of the first input FET, wherein the third input FET comprises a source configured to receive the input signal; a third input current mirror FET, the third input current mirror FET being coupled in series with the third input FET; a third variable current source, the third variable current source being coupled in parallel with the third input current mirror FET; a third output current mirror FET, the third output current mirror FET an output current mirror FET including a gate coupled to the gate / drain of the third input current mirror FET; a fourth input FET including a source coupled to the source of the third input FET; a fourth input current mirror FET, the fourth input current mirror FET being coupled in series with the fourth input FET; a fourth variable current source, the fourth variable current source being coupled in parallel with the fourth input current mirror FET; a fourth output current mirror FET, the fourth output current mirror FET including a gate coupled to the gate / drain of the fourth input current mirror FET; wherein the control circuit is configured to control the impedance at the sources of the first input FET, the second input FET, the third input FET, and the fourth input FET, including adjusting the current through the second input current mirror FET, the third input current mirror FET, and the fourth input current mirror FET and generated by the second variable current source, the third variable current source, and the fourth variable current source.

[0154] Aspect 29: A method comprising: generating a first current through an input current mirror field effect transistor (FET); generating a second current through an output current mirror FET related to a current gain multiplied by the first current; generating a third current; and generating a fourth current through the input FET related to the sum of the first current and the third current.

[0155] Aspect 30: The method according to aspect 29, the method further comprising adjusting the first current and the third current to control the input impedance at the source of the input FET, wherein the source of the input FET is configured to receive an input signal.

[0156] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device, comprising: For the positive input terminal of the input differential signal; a negative input terminal for the input differential signal; For the positive output terminal of the output differential signal; A negative output terminal for the output differential signal; a first capacitor including a first terminal coupled to the positive output terminal; a second capacitor including a first terminal coupled to the negative output terminal; and A switch network, the switch network being configured as: coupling a second terminal of the first capacitor to the negative input or positive node based on a mode signal; and A second terminal of the second capacitor is coupled to the positive input or a negative node based on the mode signal. 2 . The apparatus of claim 1 , wherein the positive node coincides with the positive input terminal, and the negative node coincides with the negative input terminal.

3. The apparatus of claim 1 , wherein the switch network is configured to: in response to the mode signal indicating a low bandwidth mode, couple the second terminal of the first capacitor to the negative input terminal, and couple the second terminal of the second capacitor to the positive input terminal.

4. The apparatus of claim 1, wherein the switch network is configured to: couple the second terminal of the first capacitor to the positive node and couple the second terminal of the second capacitor to the negative node in response to the mode signal indicating a high bandwidth mode.

5. The device according to claim 1, further comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first gate and a first drain, wherein the first gate coincides with the positive input terminal, and wherein the first drain coincides with the negative output terminal or the negative node; and A second FET comprising a second gate and a second drain, wherein the second gate coincides with the negative input terminal, and wherein the second drain coincides with the positive input terminal or the positive node.

6. The device according to claim 1, further comprising: a first field effect transistor (FET), the first field effect transistor (FET) comprising a first source, a first gate, and a first drain, wherein the first source is coupled to an upper voltage rail, and wherein the first gate is coupled to the first drain; a first current source, the first current source being coupled between the first drain and a lower voltage rail, wherein the first drain coincides with the positive input terminal or the positive node; a second FET comprising a second source, a second gate, and a second drain, wherein the second source is coupled to the upper voltage rail, and wherein the second gate is coupled to the second drain; a second current source coupled between the second drain and the lower voltage rail, wherein the second drain coincides with the negative input terminal or the negative node; a third FET comprising a third source, a third gate, and a third drain, wherein the third source is coupled to the upper voltage rail, wherein the third gate is coupled to the second gate, and wherein the third drain serves as a positive output terminal; and A fourth FET includes a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the upper voltage rail, wherein the fourth gate is coupled to the first gate, and wherein the fourth drain serves as the negative output terminal.

7. The device according to claim 6, further comprising: a first load coupled between the positive output terminal and the lower voltage rail; and A second load is coupled between the negative output terminal and the lower voltage rail.

8. The device according to claim 1, further comprising: a first current source; a first field effect transistor (FET), the first field effect transistor (FET) comprising a first source, a first gate, and a first drain, wherein the first current source is coupled between the upper voltage rail and the first drain, wherein the first drain is coupled to the first gate, wherein the first source is coupled to a lower voltage rail, and wherein the first drain serves as the positive input terminal or the positive node; a second current source; a second FET including a second source, a second gate, and a second drain, wherein the second current source is coupled between the upper voltage rail and the second drain, wherein the second drain is coupled to the second gate, wherein the second source is coupled to the lower voltage rail, and wherein the second drain serves as the negative input terminal or the negative node; a third FET comprising a third source, a third gate, and a third drain, wherein the third drain serves as the positive output terminal, wherein the third gate is coupled to the second gate, and wherein the third source is coupled to the lower voltage rail; and A fourth FET includes a fourth source, a fourth gate, and a fourth drain, wherein the fourth drain serves as the negative output terminal, wherein the fourth gate is coupled to the first gate, and wherein the fourth source is coupled to the lower voltage rail.

9. The device according to claim 8, further comprising: a first load coupled between the upper voltage rail and the positive output terminal; and A second load is coupled between the upper voltage rail and the negative output terminal.

10. The apparatus of claim 1, wherein the positive node comprises a first positive node and a second positive node, wherein the negative node comprises a first negative node and a second negative node, wherein the first capacitor comprises a first group of capacitors comprising a first group of terminals coupled to the positive output terminal, wherein the second capacitor comprises a second group of capacitors comprising a first group of terminals coupled to the negative output terminal, and wherein the switch network is configured to: coupling a second set of terminals of the first set of capacitors to the negative input terminal or the first positive node and the second positive node, respectively, based on the mode signal; and Based on the mode signal, a second set of terminals of the second set of capacitors are coupled to the positive input terminal or the first negative node and the second negative node, respectively.

11. The device according to claim 10, further comprising: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), the first p-channel metal oxide semiconductor field effect transistor (PMOS FET) comprising a first PMOS source, a first PMOS gate, and a first PMOS drain, wherein the first PMOS gate is coupled to the first PMOS drain, and wherein the first PMOS drain serves as the first anode node; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET), the first n-channel metal oxide semiconductor field effect transistor (NMOS FET) comprising a first NMOS drain, a first NMOS gate, and a first NMOS source, wherein the first NMOS drain is coupled to the first PMOS drain, wherein the first NMOS gate is configured to receive a first bias voltage, and wherein the first NMOS source serves as the positive input terminal; a second PMOS FET comprising a second PMOS source, a second PMOS gate, and a second PMOS drain, wherein the second PMOS source is coupled to the first NMOS source, wherein the second PMOS gate is configured to receive a second bias voltage, and wherein the second PMOS drain serves as the second anode node; and A second NMOS FET includes a second NMOS drain, a second NMOS gate, and a second NMOS source, wherein the second NMOS drain is coupled to the second PMOS drain, and wherein the second NMOS drain is coupled to the second NMOS gate.

12. The device according to claim 11, further comprising: a third PMOS FET, the third PMOS FET comprising a third PMOS source, a third PMOS gate, and a third PMOS drain, wherein the third PMOS gate is coupled to the third PMOS drain, and wherein the third PMOS drain serves as the first cathode node; a third NMOS FET, the third NMOS FET comprising a third NMOS drain, a third NMOS gate, and a third NMOS source, wherein the third NMOS drain is coupled to the third PMOS drain, wherein the third NMOS gate is configured to receive the first bias voltage, and wherein the third NMOS source serves as the negative input terminal; a fourth PMOS FET, the fourth PMOS FET comprising a fourth PMOS source, a fourth PMOS gate, and a fourth PMOS drain, wherein the fourth PMOS source is coupled to the third NMOS source, wherein the fourth PMOS gate is configured to receive the second bias voltage, and wherein the fourth PMOS drain serves as the second cathode node; and a fourth NMOS FET comprising a fourth NMOS drain, a fourth NMOS gate, and a fourth NMOS source, wherein the fourth NMOS drain is coupled to the fourth PMOS drain, and wherein the fourth NMOS drain is coupled to the fourth NMOS gate.

13. The device according to claim 12, further comprising: a fifth PMOS FET comprising a fifth PMOS source, a fifth PMOS gate, and a fifth PMOS drain, wherein the fifth PMOS source is coupled to an upper voltage rail, wherein the fifth PMOS gate is coupled to the first PMOS gate, and wherein the fifth PMOS drain is coupled to the first PMOS source; a sixth PMOS FET comprising a sixth PMOS source, a sixth PMOS gate, and a sixth PMOS drain, wherein the sixth PMOS source is coupled to the upper voltage rail, wherein the sixth PMOS gate is coupled to the third PMOS gate, and wherein the sixth PMOS drain is coupled to the third PMOS source; a fifth NMOS FET comprising a fifth NMOS drain, a fifth NMOS gate, and a fifth NMOS source, wherein the fifth NMOS drain is coupled to the second NMOS source, wherein the fifth NMOS gate is coupled to the second NMOS gate, and wherein the fifth NMOS source is coupled to a lower voltage rail; and a sixth NMOS FET comprising a sixth NMOS drain, a sixth NMOS gate, and a sixth NMOS source, wherein the sixth NMOS drain is coupled to the fourth NMOS source, wherein the sixth NMOS gate is coupled to the fourth NMOS gate, and wherein the sixth NMOS source is coupled to the lower voltage rail.

14. The apparatus according to claim 12, further comprising: a fifth PMOS FET, the fifth PMOS FET comprising a fifth PMOS source, a fifth PMOS gate, and a fifth PMOS drain, wherein the fifth PMOS gate is coupled to the first anode node, and wherein the fifth NMOS drain serves as the negative output terminal; a fifth NMOS FET comprising a fifth NMOS source, a fifth NMOS gate, and a fifth NMOS drain, wherein the fifth NMOS gate is coupled to the second anode node, and wherein the fifth NMOS drain is coupled to the fifth PMOS drain; a sixth PMOS FET including a sixth PMOS source, a sixth PMOS gate, and a sixth PMOS drain, wherein the sixth PMOS gate is coupled to the first cathode node, and wherein the sixth PMOS drain serves as the positive output terminal; and a sixth NMOS FET comprising a sixth NMOS source, a sixth NMOS gate, and a sixth NMOS drain, wherein the sixth NMOS gate is coupled to the second cathode node, and wherein the sixth NMOS drain is coupled to the sixth PMOS drain.

15. The device according to claim 14, further comprising: a seventh PMOS FET comprising a seventh PMOS source, a seventh PMOS gate, and a seventh PMOS drain, wherein the seventh PMOS source is coupled to an upper voltage rail, wherein the seventh PMOS gate is coupled to the fifth PMOS gate, and wherein the seventh PMOS drain is coupled to the fifth PMOS source; an eighth PMOS FET comprising an eighth PMOS source, an eighth PMOS gate, and an eighth PMOS drain, wherein the eighth PMOS source is coupled to the upper voltage rail, wherein the eighth PMOS gate is coupled to the sixth PMOS gate, and wherein the eighth PMOS drain is coupled to the sixth PMOS source; a seventh NMOS FET comprising a seventh NMOS drain, a seventh NMOS gate, and a seventh NMOS source, wherein the seventh NMOS drain is coupled to the fifth NMOS source, wherein the seventh NMOS gate is coupled to the fifth NMOS gate, and wherein the seventh NMOS source is coupled to a lower voltage rail; and an eighth NMOS FET comprising an eighth NMOS drain, an eighth NMOS gate, and an eighth NMOS source, wherein the eighth NMOS drain is coupled to the sixth NMOS source, wherein the eighth NMOS gate is coupled to the sixth NMOS gate, and wherein the eighth NMOS source is coupled to the lower voltage rail. 16 . The apparatus of claim 12 , further comprising a bias circuit configured to generate the first bias voltage and the second bias voltage.

17. The apparatus of claim 16 , wherein the bias circuit comprises a first current source, a diode-connected NMOS FET, a diode-connected PMOS FET, and a second current source, all of which are coupled in series between an upper voltage rail and a lower voltage rail; and a voltage follower configured to receive a target common-mode voltage and apply the target common-mode voltage to a node between the diode-connected NMOS FET and the diode-connected PMOS FET, wherein the first bias voltage is generated at a first drain / gate of the diode-connected NMOS FET, and wherein the second bias voltage is generated at a second drain / gate of the diode-connected PMOS FET.

18. The apparatus according to claim 12, further comprising: a first variable current source coupled between an upper voltage rail and the first PMOS drain of the first PMOS FET; a second variable current source coupled between the upper voltage rail and the third PMOS drain of the third PMOS FET; a third variable current source, the third variable current source coupled between the second NMOS drain of the second NMOSFET and a lower voltage rail; and A fourth variable current source is coupled between the fourth NMOS drain of the fourth NMOSFET and the lower voltage rail. 19 . The apparatus of claim 18 , wherein the first variable current source and the second variable current source are configured to receive a third bias voltage, and wherein the third variable current source and the fourth variable current source are configured to receive a fourth bias voltage. 20 . The apparatus of claim 19 , further comprising a bias circuit configured to generate the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage.

21. The apparatus of claim 20, wherein the bias circuit comprises: a first current source, a diode-connected NMOS FET, a diode-connected PMOSFET, and a second current source, all coupled in series between the upper voltage rail and the lower voltage rail; a voltage follower configured to receive a target common mode voltage and to apply the target common mode voltage to a node between the diode-connected NMOS FET and the diode-connected PMOS FET, wherein the first bias voltage is generated at a first drain / gate of the diode-connected NMOS FET, and wherein the second bias voltage is generated at a second drain / gate of the diode-connected PMOS FET; as well as a third current source, a fifth NMOS FET, a fifth PMOS FET, and a fourth current source, all of which are coupled in series between the upper voltage rail and the lower voltage rail, wherein a gate of the fifth NMOS FET is coupled to a gate of the diode-connected NMOSFET, wherein a gate of the fifth PMOS FET is coupled to a gate of the diode-connected NMOSFET, and wherein the third current source and the fourth current source are configured to generate the third bias voltage and the fourth bias voltage.

22. A method comprising: The capacitor is coupled to a differential amplifier based on a mode signal to configure the capacitor as a Miller capacitor or a gate-drain neutralization capacitor.

23. The method of claim 22, wherein coupling the capacitor comprises: coupling the capacitor to the differential amplifier to configure the capacitor as a Miller capacitor in response to the mode signal indicating a low bandwidth mode; and coupling the capacitor to the differential amplifier to configure the capacitor as a gate-drain neutralization capacitor in response to the mode signal indicating a high bandwidth mode.

24. A device, comprising: a first input current mirror field effect transistor (FET); a first input FET coupled in series with the first input current mirror FET, wherein the first input FET includes a source configured to receive an input signal; a first variable current source coupled in parallel with the first input current mirror FET; a first output current mirror FET including a gate coupled to a gate / drain of the first input current mirror FET; and A control circuit is configured to control the impedance at the source of the first input FET, including adjusting a first current through the first input current mirror FET and a second current generated by the first variable current source to control a third current through the first input FET.

25. The apparatus of claim 24, wherein the control circuit is configured to adjust the first current and the second current such that the third current is substantially constant.

26. The apparatus according to claim 24, further comprising: a second input FET including a source coupled to the source of the first input FET; a second input current mirror FET coupled in series with the second input FET; a second variable current source coupled in parallel with the second input current mirror FET; and a second output current mirror FET comprising a gate coupled to a gate / drain of the second input current mirror FET, wherein the control circuit is configured to control the impedance at the sources of the first input FET and the second input FET, including adjusting the first current through the first input current mirror FET and the second input current mirror FET and the second current generated by the first variable current source and the second variable current source to control the third current through the first input FET and the second input FET.

27. The apparatus according to claim 24, further comprising: a second input FET including a gate coupled to a gate of the first input FET, wherein the second input FET includes a source configured to receive the input signal; a second input current mirror FET coupled in series with the second input FET; a second variable current source coupled in parallel with the second input current mirror FET; and a second output current mirror FET comprising a gate coupled to a gate / drain of the second input current mirror FET, wherein the control circuit is configured to control the impedance at the sources of the first input FET and the second input FET, including adjusting a fourth current through the second input current mirror FET and a fifth current generated by the second variable current source to control a sixth current through the second input FET.

28. The apparatus according to claim 24, further comprising: a second input FET including a source coupled to the source of the first input FET; a second input current mirror FET coupled in series with the second input FET; a second variable current source coupled in parallel with the second input current mirror FET; a second output current mirror FET including a gate coupled to the gate / drain of the second input current mirror FET; a third input FET including a gate coupled to the gate of the first input FET, wherein the third input FET includes a source configured to receive the input signal; a third input current mirror FET coupled in series with the third input FET; a third variable current source coupled in parallel with the third input current mirror FET; a third output current mirror FET including a gate coupled to the gate / drain of the third input current mirror FET; a fourth input FET including a source coupled to the source of the third input FET; a fourth input current mirror FET coupled in series with the fourth input FET; a fourth variable current source coupled in parallel with the fourth input current mirror FET; a fourth output current mirror FET comprising a gate coupled to the gate / drain of the fourth input current mirror FET; wherein the control circuit is configured to control the impedance at the source of the first input FET, the second input FET, the third input FET and the fourth input FET, including adjusting the current passing through the second input current mirror FET, the third input current mirror FET and the fourth input current mirror FET and generated by the second variable current source, the third variable current source and the fourth variable current source.

29. A method comprising: generating a first current through an input current mirror field effect transistor (FET); generating a second current through an output current mirror FET related to a current gain multiplied by the first current; generating a third current; as well as A fourth current is generated through the input FET that is related to a sum of the first current and the third current.

30. The method of claim 29, further comprising adjusting the first current and the third current to control an input impedance at a source of the input FET, wherein the source of the input FET is configured to receive an input signal.

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