Electronic device for simultaneously reproducing multiple videos and control method thereof

Abstract

A method, an apparatus, and a computer readable medium for reproducing a plurality of streams are provided. In some embodiments, an electronic device includes: a decoder that decodes a plurality of streams; a plurality of buffers divided into a plurality of buffer groups corresponding to the plurality of streams; a first processor acquiring one frame; and at least one second processor. The at least one second processor: identifies an additional utilization of the first processor sufficient to render the additional stream; and control the first processor to downsample each of the plurality of streams and at least one of the additional streams based on a second determination that the additional usage of the first processor exceeds an available usage of the first processor.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices and control methods thereof, and more particularly, to electronic devices for playing multiple videos simultaneously and control methods thereof. Background Art

[0002] With the development of electronic technology, various types of electronic devices are being developed. For example, the latest progress in the performance of hardware and / or software of display devices may allow multiple videos to be played simultaneously and / or substantially simultaneously.

[0003] However, resource management of a processor (eg, a digital signal processor (DSP)) used for image processing may be an important factor for playing multiple videos simultaneously and / or substantially simultaneously. Summary of the invention

[0004] Technical Solution According to one aspect of the present disclosure, an electronic device for playing multiple streams is provided. The electronic device includes a decoder, a plurality of buffers, a first processor, and at least one second processor. The decoder is configured to decode the multiple streams. The plurality of buffers are divided into a plurality of buffer groups corresponding to the multiple streams. The first processor is configured to obtain a frame by relocating decoded data output from each of the plurality of buffer groups. The at least one second processor is communicatively coupled with the decoder, the plurality of buffers, and the first processor, and is configured to control the electronic device. The at least one second processor is further configured to: based on a first determination that an additional stream will be played, identify an additional usage rate of the first processor sufficient to play the additional stream. The at least one second processor is further configured to: determine whether the additional usage rate of the first processor exceeds the available usage rate of the first processor. The at least one second processor is further configured to: based on a second determination that the additional usage rate of the first processor exceeds the available usage rate of the first processor, control the first processor to downsample each of the multiple streams and at least one of the additional streams.

[0005] In some embodiments, the at least one second processor may be further configured to identify a number of streams to be downsampled based on the available usage of the first processor and the additional usage of the first processor.

[0006] In some embodiments, the at least one second processor may be further configured to identify a downsampling rate of the stream to be downsampled based on the available usage of the first processor and the additional usage of the first processor.

[0007] In some embodiments, the at least one second processor may also be configured to: based on determining that the resolution of at least one of the streams to be downsampled that has been downsampled at the downsampling rate is less than a predetermined minimum resolution threshold, downsample the at least one of the streams to be downsampled to the predetermined minimum resolution threshold, and increase the number of the streams to be downsampled.

[0008] In some embodiments, the at least one second processor may be further configured to, based on a second determination that the additional usage of the first processor exceeds the available usage of the first processor, control the first processor to downsample each of the multiple streams and the at least one of the additional streams according to the corresponding resolutions of each of the multiple streams and each of the at least one of the additional streams.

[0009] In some embodiments, the at least one second processor may be further configured to control the first processor to downsample at least one of the plurality of streams based on a second determination that the additional usage of the first processor exceeds the available usage of the first processor.

[0010] In some embodiments, the at least one second processor may include a resource manager configured to identify the available usage rate and the additional usage rate, and a sampling operation unit configured to identify a downsampling rate based on the available usage rate and the additional usage rate.

[0011] In some embodiments, the electronic device may further include at least one scaler. In such an embodiment, the at least one second processor may further be configured to control the at least one scaler to upsample each of the plurality of streams and the at least one downsampled stream in the additional stream.

[0012] In some embodiments, the at least one scaler may be configured to use a neural network model.

[0013] In some embodiments, the decoder may comprise a multi-format decoder.

[0014] In some embodiments, each buffer in the plurality of buffer groups may include four buffers.

[0015] According to one aspect of the present disclosure, a control method for an electronic device for playing multiple streams is provided. The control method includes: decoding the multiple streams. The control method also includes: storing the multiple streams in corresponding multiple buffer groups. The control method also includes: acquiring a frame by a first processor of the electronic device by repositioning decoded data output from each of the multiple buffer groups. The control method also includes: based on determining that an additional stream will be played, identifying an additional usage rate of the first processor sufficient to play the additional stream by a second processor of the electronic device. The control method also includes: determining whether the additional usage rate of the first processor exceeds the available usage rate of the first processor. The control method also includes: based on determining that the additional usage rate of the first processor exceeds the available usage rate of the first processor, the second processor controls the first processor to downsample each of the multiple streams and at least one of the additional streams.

[0016] In some embodiments, the control method may further include identifying a number of streams to be downsampled based on the available usage rate of the first processor and the additional usage rate of the first processor.

[0017] In some embodiments, the control method may further include identifying a down-sampling rate of the stream to be down-sampled based on the available usage rate of the first processor and the additional usage rate of the first processor.

[0018] In some embodiments, the control method may further include: based on determining that the resolution of at least one of the streams to be downsampled that has been downsampled at the downsampling rate is less than a predetermined minimum resolution threshold, downsampling the at least one of the streams to be downsampled to the predetermined minimum resolution threshold, and increasing the number of the streams to be downsampled.

[0019] In some embodiments, the control method may also include: based on determining that the additional usage of the first processor exceeds the available usage of the first processor, and the corresponding resolutions of each of the multiple streams and each of the at least one of the additional streams, the second processor controls the first processor to downsample each of the multiple streams and the at least one of the additional streams.

[0020] In some embodiments, the control method may further include: based on determining that the additional usage rate of the first processor exceeds the available usage rate of the first processor, controlling the first processor by the second processor to downsample at least one of the plurality of streams.

[0021] In some embodiments, the control method may further include upsampling each of the plurality of streams and the at least one downsampled stream of the additional streams.

[0022] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer executable instructions for playing a plurality of streams is provided. The computer executable instructions, when executed by at least one processor of an electronic device, cause the electronic device to decode the plurality of streams. The computer executable instructions also cause the electronic device to perform the following operations: the plurality of streams are stored in corresponding plurality of buffer groups. The computer executable instructions also cause the electronic device to perform the following operations: a first processor of the electronic device acquires a frame by relocating decoded data output from each of the plurality of buffer groups. The computer executable instructions also cause the electronic device to perform the following operations: based on a first determination that an additional stream will be played, a second processor of the electronic device identifies an additional usage rate of the first processor sufficient to play the additional stream. The computer executable instructions also cause the electronic device to perform the following operations: determine whether the additional usage rate of the first processor exceeds the available usage rate of the first processor. The computer executable instructions also cause the electronic device to perform the following operations: based on a second determination that the additional usage rate of the first processor exceeds the available usage rate of the first processor, the second processor controls the first processor to downsample each of the plurality of streams and at least one of the additional streams.

[0023] In some embodiments, the computer executable instructions further cause the electronic device to perform the following operations: based on the available usage of the first processor and the additional usage of the first processor, identify at least one of the number of streams to be downsampled and the downsampling rate of the streams to be downsampled.

[0024] Additional aspects may be set forth in part in the description which follows and, in part, may be obvious from the description, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which: Figure 1a to Figure 1c is a diagram for illustrating a method of processing a plurality of streams according to one or more embodiments of the present disclosure.

[0026] Figure 2 is a block diagram illustrating a configuration of an electronic device according to one or more embodiments of the present disclosure.

[0027] Figure 3is a block diagram illustrating an example configuration of an electronic device according to one or more embodiments of the present disclosure.

[0028] Figure 4 is a diagram for schematically illustrating the operation of a first processor according to one or more embodiments of the present disclosure.

[0029] Figures 5 to 7 is a diagram for illustrating resource management of a first processor according to one or more embodiments of the present disclosure.

[0030] Figure 8 is a flowchart for illustrating a control method of an electronic device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] The exemplary embodiments of the present disclosure may be modified in various ways. Therefore, specific exemplary embodiments are shown in the drawings and described in detail in the detailed description. However, it should be understood that the present disclosure is not limited to specific exemplary embodiments, but may include all modifications, equivalents, and substitutions without departing from the scope and spirit of the present disclosure. Alternatively or additionally, well-known functions and / or configurations may not be described in detail if the description would obscure the present disclosure with unnecessary details.

[0032] The present disclosure provides an electronic device and a control method thereof for potentially improving processing efficiency of multiple streams through resource management of a processor (eg, a digital signal processor (DSP)) for image processing.

[0033] As the terms used in the embodiments of the present disclosure, in view of the functions described in the present disclosure, general terms that are currently widely used may have been selected as much as possible. However, these terms may change according to the intentions of those skilled in the art working in the relevant fields, previous court decisions, the emergence of new technologies, etc. Alternatively or additionally, there may be terms that may have been specified by the applicant himself, and in such a case, the meaning of the terms may be described in the relevant descriptions in the present disclosure. Therefore, the terms used in the present disclosure should be defined based on the meaning of the terms and the overall content of the present disclosure, rather than just based on the names of the terms.

[0034] Alternatively or additionally, in the present disclosure, expressions such as but not limited to “having”, “may have”, “including” and “may include” may indicate the presence of such characteristics (for example, elements such as numbers, functions, operations, and components), and may not exclude the presence of additional characteristics.

[0035] Furthermore, the expression “at least one of A and / or B” should be interpreted as meaning any one of “A” or “B” or “A and B”.

[0036] In addition, the expressions "first", "second", etc. used in the present disclosure may be used to describe various elements, regardless of any order and / or degree of importance. Alternatively or additionally, such expressions may only be used to distinguish one element from another element and may not be intended to limit the element.

[0037] It should be understood that, unless clearly defined differently in the context, singular expressions include plural expressions. In addition, in the present disclosure, terms such as "including" and "consisting of" should be interpreted as specifying the presence of such characteristics, numbers, steps, operations, elements, components, or combinations thereof described in the present disclosure, rather than excluding in advance the possibility of the presence or addition of one or more of other characteristics, numbers, steps, operations, elements, components, or combinations thereof.

[0038] In addition, in the present disclosure, the term “user” may refer to a person using an electronic device and / or a device (eg, an artificial intelligence (AI) electronic device) using the electronic device.

[0039] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0040] Figure 1a to Figure 1c is a diagram for illustrating a method of processing a plurality of streams according to one or more embodiments of the present disclosure.

[0041] In an embodiment, the electronic device can be Figure 1a The DVDE codec shown in is used to decode the image data. For example, Figure 1a The DVDE codec shown in may be a type of multi-format decoder. For purposes of explanation, Figure 1a The DVDE codec shown in is shown as having one stream, however, the present disclosure is not limited thereto. For example, the DVDE codec may be and / or may include a multi-format decoder that may receive and / or decode multiple streams.

[0042] The DVDE codec may output decoded image data to four separate buffers (eg, first buffer A, second buffer B, third buffer C, and fourth buffer D) for optimizing loading and latency to a memory (such as, but not limited to, a double data rate (DDR) memory).

[0043] The hardware, which may be and / or may include a video decoding (VDEC) interface, may generate one frame by repositioning the image data stored in the four buffers and then output the generated frame to a scaler (not shown).

[0044] The scaler may scale the received frames to correspond to the resolution of the display.

[0045] In an embodiment, the image data may be relocated by using a DSP instead of hardware (eg, a VDEC interface). In such an embodiment, image frames may be acquired without using hardware (such as, but not limited to, a VDEC interface).

[0046] In an embodiment, when a DSP is used, multiple streams may be processed, such as Figure 1b For example, Figure 1c As shown, the DSP may receive a first stream 1, a second stream 2, a third stream 3, and a fourth stream 4. Alternatively or additionally, the DSP may output a first stream 1 of 2k resolution, a second stream 2 of 2k resolution, a third stream 3 of 2k resolution, and a fourth stream 4 of 2k resolution.

[0047] In an optional or additional embodiment, when the usage of the DSP does not have enough margin compared to the performance of the DVDE codec, a limit may be placed on the number of streams that can be relocated. In such an embodiment, even if additional streams need to be played, additional streams may not be played and / or the previous stream may have to be stopped.

[0048] Figure 2 is a block diagram illustrating a configuration of an electronic device 100 according to one or more embodiments of the present disclosure.

[0049] The electronic device 100 may be and / or may include a device that performs image processing of multiple streams. For example, the electronic device 100 may be and / or may include such a device: may include but is not limited to a display, such as a television (TV), a desktop personal computer (PC), a laptop computer, a video wall, a large-size display (LFD), a digital signage, a digital information display (DID), a projector display, a smart phone, a tablet PC, etc. Alternatively or additionally, the electronic device 100 may perform image processing of multiple streams, and then may display multiple streams that have been image processed. Alternatively or additionally, the electronic device 100 may be a device that provides multiple streams that have been image processed to a device including a display, such as, but not limited to, a set-top box (STB), etc.

[0050] However, the present disclosure is not limited thereto, and any device may be the electronic device 100 if the device can perform image processing of a plurality of streams.

[0051] according to Figure 2 , the electronic device 100 may include a decoder 110 , a plurality of buffers 120 , a first processor 130 , and a second processor 140 .

[0052] The decoder 110 may decode a plurality of encoded streams. For example, the decoder 110 may decode a plurality of encoded streams according to the DVDE codec standard.

[0053] However, the present disclosure is not limited thereto, and the decoder 110 may be implemented as a type of multi-format decoder that may be configured to comply with various codec standards, such that the decoder 110 may receive a plurality of streams encoded using the various codec standards and decode the received plurality of streams.

[0054] The plurality of buffers 120 may include a plurality of buffer groups corresponding to the plurality of streams. For example, the number of the plurality of buffers 120 may be a total of sixteen (16). In such an example, the plurality of buffers 120 may include four (4) groups, and each group of the plurality of buffers 120 may include four buffers. However, the present disclosure is not limited thereto, and the plurality of buffers 120 may be implemented using other numbers of buffers and / or groupings of buffers. For example, the number of buffers included in one buffer group may vary according to design constraints.

[0055] In an embodiment, each of a plurality of buffer groups may store one stream. For example, four (4) buffers included in one buffer group may divide and store one stream. Alternatively or additionally, data included in one stream may be sequentially stored in such a manner that a first buffer of four buffers included in one buffer group may store information about a first pixel, a second buffer may store information about a second pixel that may be located next to the first pixel, a third buffer may store information about a third pixel that may be located next to the second pixel, and a fourth buffer may store information about a fourth pixel that may be located next to the third pixel. However, the present disclosure is not limited thereto, and various other methods may be used to store one stream in one buffer group.

[0056] In an embodiment, the first processor 130 may obtain a frame by repositioning the decoded data output from each buffer group in the plurality of buffer groups. In an optional or additional embodiment, the first processor 130 may be implemented as a DSP. In such an embodiment, the first processor 130 may obtain a frame by repositioning the data sequentially received from the four buffers included in the first group of the plurality of buffer groups. Alternatively or additionally, the first processor 130 may obtain a frame by repositioning the data sequentially received from the four buffers included in the second group of the plurality of buffer groups. For another example, the first processor 130 may obtain a frame by repositioning the data sequentially received from the four buffers included in the third group of the plurality of buffer groups. For another example, the first processor 130 may obtain a frame by repositioning the data sequentially received from the four buffers included in the fourth group of the plurality of buffer groups.

[0057] However, the present disclosure is not limited thereto, and the first processor 130 may have other configurations in which the first processor 130 can acquire multiple frames by relocating multiple streams. For example, the first processor 130 may be implemented as a central processing unit (CPU) and acquire multiple frames by relocating multiple streams through a software method.

[0058] In an embodiment, the second processor 140 may control the overall operation of the electronic device 100. That is, the second processor 140 may be connected (e.g., communicatively coupled) to each component of the electronic device 100, and may control the overall operation of the electronic device 100. For example, the second processor 140 may be connected to components such as the decoder 110, the plurality of buffers 120, the first processor 130, and may control the operation of the electronic device 100.

[0059] The at least one second processor 140 may be and / or may include, but is not limited to, one or more of a CPU, a graphics processing unit (GPU), an accelerated processing unit (APU), an integrated many-core (MIC), a neural processing unit (NPU), a hardware accelerator, a machine learning accelerator, etc. The at least one second processor 140 may control one or any combination of other components of the electronic device 100, and may perform operations related to communication and / or data processing. The at least one second processor 140 may execute one or more programs and / or instructions stored in a memory. For example, the at least one second processor 140 may execute a method according to one or more embodiments of the present disclosure by executing one or more instructions stored in a memory.

[0060] When the method according to one or more embodiments of the present disclosure includes multiple operations, the multiple operations may be performed by one processor, and / or may be performed by multiple processors. For example, when the first operation, the second operation, and the third operation are performed by the method according to one or more embodiments, the first operation, the second operation, and the third operation may all be performed by the first processor, and / or the first operation and the second operation may be performed by the first processor (e.g., a general-purpose processor) and the third operation may be performed by the second processor (e.g., an AI-specific processor).

[0061] In an embodiment, at least one second processor 140 may be implemented as a single-core processor including one core. Alternatively or additionally, at least one second processor 140 may be implemented as one or more multi-core processors including multiple cores (e.g., multi-cores of the same kind and / or multi-cores of different kinds). When at least one second processor 140 is implemented as a multi-core processor, each of the multiple cores included in the multi-core processor may include an internal memory of the processor (such as a cache memory, an on-chip memory, etc.), and / or a public cache shared by multiple cores may be included in the multi-core processor. Alternatively or additionally, each of the multiple cores included in the multi-core processor (and / or some of the multiple cores) may independently read a program instruction for implementing a method according to one or more embodiments of the present disclosure and execute the instruction, and / or multiple cores (and / or some of the cores) may be linked to each other, and read a program instruction for implementing a method according to one or more embodiments of the present disclosure and execute the instruction.

[0062] When the method according to one or more embodiments of the present disclosure includes multiple operations, the multiple operations may be performed by one of the multiple cores included in the multi-core processor, and / or may be performed by multiple cores. For example, when the first operation, the second operation, and the third operation are performed by the method according to one or more embodiments, all of the first operation, the second operation, and the third operation may be performed by the first core included in the multi-core processor, and / or the first operation and the second operation may be performed by the first core included in the multi-core processor and the third operation may be performed by the second core included in the multi-core processor.

[0063] In some embodiments of the present disclosure, at least one second processor 140 may be and / or may include, but is not limited to, a system on chip (SoC) that may integrate at least one processor and other electronic components, a single-core processor, a multi-core processor, a core included in a single-core processor and / or a multi-core processor, etc. For example, the core may be implemented as a CPU, a GPU, an APU, a MIC, an NPU, a hardware accelerator, a machine learning accelerator, etc., but the embodiments of the present disclosure are not limited thereto. In the following, for ease of explanation, the expression "second processor 140" may be used to explain the operation of the electronic device 100. However, the present disclosure is not limited thereto, and the operations described as being performed by the second processor 140 may be understood as operations to be performed by the electronic device 100.

[0064] When an additional stream needs to be played in addition to the plurality of streams already being played, the second processor 140 may identify an additional usage rate of the first processor 130 that is necessary (e.g., sufficient to play the additional stream) to play the additional stream without stopping the playback of the streams already being played. For example, if an instruction for playing stream 5 is executed while the first processor 130 is processing streams 1, 2, 3, and 4, the second processor 140 may identify the additional usage rate of the first processor 130 for playing stream 5 as 20%.

[0065] If the remaining (e.g., available) usage of the first processor 130 is less than the additional usage, the second processor 140 may control the first processor 130 to downsample at least one of the multiple streams and / or the additional streams. For example, if the current usage of the first processor 130 is 100%, the remaining (e.g., available) usage of the first processor 130 is 0%, and the remaining (e.g., available) usage is less than the additional usage of 20% for playing stream 5, the second processor 140 may control the first processor 130 to downsample at least one of the multiple streams and / or the additional streams.

[0066] In an embodiment, the first processor 130 may perform downsampling by controlling a method of reading from a buffer. Figure 1a Assuming that the first processor 130 receives decoded data from buffer A to buffer D, the first processor 130 may perform downsampling by reading information about the first pixel from buffer A, not reading information about the second pixel next to the first pixel from buffer B, reading information about the third pixel next to the second pixel from buffer C, and not reading information about the fourth pixel next to the third pixel from buffer D.

[0067] However, the present disclosure is not limited thereto, and there may be any of various methods for the first processor 130 to perform down-sampling.

[0068] Through the above-described downsampling, the remaining (eg, available) utilization rate of the first processor 130 may be improved (eg, increased).

[0069] In an embodiment, the second processor 140 may identify at least one of the number of streams to be downsampled and the downsampling rates of the streams to be downsampled based on the remaining (eg, available) usage rate and the additional usage rate.

[0070] For example, if the first processor 130 processes streams 1, 2, 3, and 4 and the current usage of the first processor 130 is 100%, the remaining (e.g., available) usage of the first processor 130 is 0%, and the remaining (e.g., available) usage is less than the additional usage of 20% for playing stream 5, the second processor 140 may improve (e.g., increase) the remaining (e.g., available) usage by downsampling stream 4. For example, the second processor 140 may identify a downsampling rate for stream 4 that increases the remaining (e.g., available) usage to 20%. Alternatively or additionally, if the remaining (e.g., available) usage becomes higher by 10% each time by downsampling one stream, the second processor 140 may downsample both streams.

[0071] If at least one of the plurality of streams and / or the additional streams is downsampled to a resolution smaller than a predetermined minimum resolution threshold based on the downsampling rate, the second processor 140 may downsample at least one of the plurality of streams and / or the additional streams to the predetermined minimum resolution threshold and increase the number of streams to be downsampled. For example, when stream 4 is downsampled to 1 / 4, if stream 4 is downsampled to a resolution smaller than the predetermined minimum resolution threshold, the second processor 140 may downsample stream 4 to the predetermined minimum resolution threshold and additionally downsample stream 3. If a stream is downsampled to a resolution smaller than the predetermined minimum resolution threshold, the image quality may become quite low even if upscaling is performed later. Therefore, the image quality of the downsampled stream may be maintained at a certain level or higher by the operation as described above.

[0072] If the remaining (e.g., available) usage of the first processor 130 is less than the additional usage, the second processor 140 may control the first processor 130 to downsample at least one of the multiple streams and / or the additional stream based on the resolution of each of the multiple streams and the resolution of the additional stream. For example, if the remaining (e.g., available) usage of the first processor 130 is less than the additional usage, the second processor 140 may control the first processor 130 to downsample the stream having the highest resolution among the resolution of each of the multiple streams and the resolution of the additional stream.

[0073] If the remaining (e.g., available) usage of the first processor 130 is less than the additional usage, the second processor 140 may control the first processor 130 to downsample one of the multiple streams. For the additional stream, the user may have requested to play the additional stream, so it can be considered that the user's viewing intention is strong, and therefore, the second processor 140 may control the first processor 130 to downsample one of the multiple streams without downsampling the additional stream.

[0074] In an embodiment, the second processor 140 may include a resource manager configured to identify a remaining (e.g., available) usage rate and an additional usage rate. Alternatively or additionally, the second processor 140 may include a sampling operation unit configured to identify a downsampling rate based on the remaining (e.g., available) usage rate and the additional usage rate. For example, the resource manager may identify the remaining (e.g., available) usage rate and the additional usage rate, and the sampling operation unit may identify a downsampling rate that can be implemented in a hardware configuration based on the remaining (e.g., available) usage rate and the additional usage rate. However, the present disclosure is not limited thereto, and the second processor 140 may control the first processor 130 based on a software module that performs operations of each of the resource manager and the sampling operation unit.

[0075] The electronic device 100 may further include at least one scaler, and the second processor 140 may control the at least one scaler to upsample the at least one downsampled stream. In an embodiment, the at least one scaler may perform upsampling using a neural network model.

[0076] The second processor 140 may control at least one scaler to upsample at least one downsampled stream based on the resolution of the display of the electronic device 100. Alternatively or additionally, the second processor 140 may control at least one scaler to upsample at least one downsampled stream based on the resolution of the display device, and provide the upsampled stream to the display device. Hereinafter, the resolution of the display of the electronic device 100 and / or the display device may be referred to as a target resolution.

[0077] Alternatively or additionally, the second processor 140 may upsample at least one downsampled stream by using a scaler corresponding to the target resolution among the at least one scaler. For example, if the target resolution is full high definition (FHD), the second processor 140 may upsample at least one downsampled stream by using the first scaler. For another example, if the target resolution is ultra high definition (UHD), the second processor 140 may upsample at least one downsampled stream by using the second scaler. In an embodiment, each of the first scaler and the second scaler may perform upsampling using a neural network model.

[0078] Alternatively or additionally, the second processor 140 may use one of the at least one scaler based on at least one of the resolution of the downsampled stream and / or the target resolution. For example, if the upsampling rate is less than a predetermined rate based on the resolution of the downsampled stream and the target resolution, the second processor 140 may upsample the downsampled stream by using a third scaler. Alternatively or additionally, if the upsampling rate is greater than or equal to the predetermined rate, the second processor 140 may upsample the downsampled stream by using a fourth scaler.

[0079] Alternatively or additionally, the second processor 140 may use one of the at least one scaler based on the type of the downsampled stream. For example, if the type of the downsampled stream is a movie type, the second processor 140 may upsample the downsampled stream by using a fifth scaler. Alternatively or additionally, if the type of the downsampled stream is an advertisement type, the second processor 140 may upsample the downsampled stream by using a sixth scaler.

[0080] The above operation for selecting at least one scaler may be implemented in any of various combinations.

[0081] In an embodiment, AI-related functions according to the present disclosure may be operated through the second processor 140 and the memory.

[0082] The second processor 140 may be composed of one processor and / or multiple processors. In an embodiment, the one processor and / or multiple processors may be and / or may include a general-purpose processor (e.g., CPU, AP, DSP, etc.), a graphics-specific processor (e.g., GPU, visual processing unit (VPU)), an AI-specific processor (e.g., NPU), etc.

[0083] A processor and / or multiple processors may perform control to process input data according to predefined operating rules and / or AI models stored in the memory. Alternatively or additionally, in the case where the processor and / or multiple processors are AI dedicated processors, the AI ​​dedicated processor may be designed as a hardware structure dedicated to processing a specific AI model. The predefined operating rules and / or AI models may be characterized in that the predefined operating rules and / or AI models can be formulated through learning.

[0084] As used herein, formulation through learning may refer to a basic artificial intelligence model that can be formulated through a learning algorithm using a plurality of learning data training models, and thereby formulates predefined operating rules and / or AI model sets to perform desired characteristics (e.g., purposes). Such learning may be performed in the device itself that can perform artificial intelligence according to the present disclosure, and / or by a separate server and / or system. Examples of learning algorithms that can be used to formulate AI models may include, but are not limited to, supervised learning, unsupervised learning, semi-supervised learning, and reinforcement learning. However, the learning algorithms used in the present disclosure may not be limited to the aforementioned examples.

[0085] According to an embodiment, the artificial intelligence model may be composed of a plurality of neural network layers. Each of the plurality of neural network layers may have a plurality of weight values, and the neural network operation may be performed by the operation result of the previous layer and the operation in the plurality of weight values. The plurality of weight values ​​included by the plurality of neural network layers may be optimized by the learning result of the artificial intelligence model. For example, the plurality of weight values ​​may be updated so that the loss value and / or cost value obtained at the artificial intelligence model during the learning process may be reduced and / or minimized.

[0086] The artificial neural network may include, but is not limited to, a deep neural network (DNN), a convolutional neural network (CNN), a deep neural network (DNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a generative adversarial network (GAN), or a deep Q network, etc. However, the present disclosure may not be limited to the foregoing examples.

[0087] Figure 3 is a block diagram showing an example configuration of an electronic device 100 according to one or more embodiments of the present disclosure. Figure 3 , the electronic device 100 may include a decoder 110, a plurality of buffers 120, a first processor 130 and a second processor 140. Optionally or additionally, according to Figure 3 , the electronic device 100 may further include a scaler 150 , a communication interface 160 , a memory 170 , a display 180 , and a user interface 190 . Figure 3 The electronic device 100 may include and / or may be similar in many respects to the above referenced Figure 2 The electronic device 100 described above may include additional features not mentioned above. Figure 3 The components of the electronic device 100 include and / or are similar in many respects to Figure 2 In the case of corresponding components of the electronic device 100, repeated explanations may be omitted for the sake of brevity.

[0088] The communication interface 160 may be configured to perform communication with various types of external devices according to various types of communication methods. For example, the electronic device 100 may perform communication with a streaming server or the like through the communication interface 160.

[0089] In an embodiment, the communication interface 160 may include but is not limited to a wireless fidelity (Wi-Fi) module, a Bluetooth TM At least one of a wireless communication module, an infrared data association (IrDA) module, a near field communication (NFC) module, a wireless communication module, etc. For example, each communication module may be implemented in the form of at least one hardware chip.

[0090] For another example, the Wi-Fi module and the Bluetooth module may perform communication by the Wi-Fi method and the Bluetooth method, respectively. In the case of using the Wi-Fi module and / or the Bluetooth module, various types of connection information, such as but not limited to a service set identifier (SSID) and / or a session key, may be first sent and / or received, and a communication connection may be performed by using the connection information. Subsequently, various types of information may be sent and / or received thereafter. The infrared communication module may perform communication according to the IrDA technology to wirelessly send and / or receive data in a near field by using infrared rays between visible light and millimeter waves.

[0091] In an embodiment, the wireless communication module may include at least one communication chip that can perform communication according to various wireless communication protocols, such as but not limited to Zigbee, third generation (3G), third generation partnership project (3GPP), long term evolution (LTE), advanced LTE (LTE-A), fourth generation (4G), fifth generation (5G), 5G new radio (NR), etc.

[0092] Alternatively or additionally, the communication interface 160 may include a wired communication interface such as a high-definition multimedia interface (HDMI), a display port (DP) interface, a Thunderbolt interface, a universal serial bus (USB) interface, a red, green, and blue (RGB) interface, a D-subminiature (D-SUB) interface, a digital visual interface (DVI), etc.

[0093] Alternatively or additionally, the communication interface 160 may include at least one of a local area network (LAN) module, an Ethernet module, and / or a wired communication module for performing communication by using a pair cable, a coaxial cable, an optical fiber cable, or the like.

[0094] The memory 170 may refer to hardware that can store information such as programs, data, etc. in an electronic and / or magnetic form so that the second processor 140, etc. can access the information. For example, the memory 170 may be implemented as at least one hardware of a nonvolatile memory, a volatile memory, a flash memory, a hard disk drive (HDD), a solid state drive (SSD), a random access memory (RAM), a read-only memory (ROM), etc.

[0095] In an embodiment, the memory 170 may store at least one instruction required for the operation of the electronic device 100 and / or the second processor 140. As used herein, an instruction may be a code unit that instructs the operation of the electronic device 100 and / or the second processor 140, which may have been written in a machine language that can be understood (e.g., executed) by a computer. Alternatively or additionally, the memory 170 may store a plurality of instructions that can perform specific tasks of the electronic device 100 and / or the second processor 140 as an instruction set.

[0096] Alternatively or additionally, the memory 170 may store data in units of bits and / or bytes, and the data may indicate characters, numbers, images, etc. For example, the memory 170 may store an up-sampling module, etc.

[0097] In an embodiment, the memory 170 is accessible by the second processor 140. For example, the second processor 140 may perform at least one of reading, recording, correcting, deleting, updating, etc. of an instruction, an instruction set, and / or data.

[0098] The display 180 may be configured to display an image. In an embodiment, the display 180 may be implemented as at least one of various forms of displays, such as, but not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display panel (PDP), etc. The display 180 may include a driving circuit that may be implemented in a form such as, but not limited to, an amorphous silicon (a-Si) thin film transistor (TFT) display, a low temperature polycrystalline silicon (LTPS) TFT, an organic TFT (OTFT), etc. Alternatively or additionally, the display 180 may include a backlight unit, etc. In an embodiment, the display 180 may be implemented as a touch screen combined with a touch sensor, a flexible display, a 3-dimensional (3D) display, etc.

[0099] The user interface 190 may be implemented as a button, a touch pad, a mouse, a keyboard, etc. Alternatively or additionally, the user interface 190 may be implemented as a touch screen that can perform a display function and a manipulation input function together. In an embodiment, the button may be at least one of various types of buttons, such as but not limited to a mechanical button, a touch pad, a scroll wheel, etc., and the button may be formed in any one of a plurality of regions of the electronic device 100, such as but not limited to a front surface portion and / or a side surface portion, a rear surface portion, etc., of the exterior of the body of the electronic device 100.

[0100] In alternative or additional embodiments, the electronic device 100 may further include a microphone, a speaker, a camera, etc.

[0101] For example, the microphone may be configured to receive an input of sound and / or convert the sound into an audio signal. Alternatively or additionally, the microphone may be electrically connected to the second processor 140 and may receive the sound through the control of the second processor 140.

[0102] For example, the microphone may be formed in an integrated type that can be integrated into the upper side, the front surface direction, the side surface direction, etc. of the electronic device 100. Alternatively or additionally, the microphone may be provided in a remote controller or the like that is separate from the electronic device 100. In such an embodiment, the remote controller may receive sound through the microphone, and / or may provide the received sound to the electronic device 100.

[0103] The microphone may include various components, such as a microphone that can collect sound in analog form, an amplifier circuit that can amplify the collected sound, an analog / digital (A / D) conversion circuit that can sample the amplified sound and convert the sound into a digital signal, a filter circuit that can remove noise components from the converted digital signal, and the like.

[0104] In an embodiment, the microphone may also be implemented in the form of a sound sensor. For example, the microphone may be of any type that can collect sound.

[0105] In an embodiment, the speaker may be configured to output various audio data processed at the second processor 140 and / or various notification sounds and / or voice messages, etc.

[0106] In an optional or additional embodiment, the electronic device 100 may include a camera. The camera may be configured to take (e.g., capture) still images and / or moving images. For example, the camera may take still images at a specific point in time. For another example, the camera may take still images continuously.

[0107] The camera may include at least one of a lens, a shutter, an aperture, a solid-state imaging element, an analog front end (AFE), and a timing generator (TG). For example, the shutter may adjust the time at which light reflected on a subject may enter the camera. The aperture may adjust the amount of light introduced into the lens by mechanically increasing and / or decreasing the size of the opening through which the light enters. When the light reflected on the subject accumulates as photocharges, the solid-state imaging element may output the phase caused by the photocharges as an electronic signal. The TG may output a timing signal for reading out pixel data of the solid-state imaging element. The AFE may sample and / or digitize the electronic signal output from the solid-state imaging element.

[0108] In some embodiments, the electronic device 100 can process multiple streams by various methods through resource management of a processor (e.g., DSP) for image processing. Therefore, user convenience can be improved when compared with related electronic devices. Alternatively or additionally, the electronic device 100 can minimize image quality degradation by upsampling at least one downsampled stream using at least one scaler using a neural network model.

[0109] In the following, please refer to Figures 4 to 7 The operation of the electronic device 100 is described. Figures 4 to 7 In the present invention, for the convenience of explanation, a single embodiment may be explained. However, Figures 4 to 7 The individual embodiments described in the drawings may be implemented in any combination.

[0110] Figure 4 is a diagram for schematically illustrating the operation of the first processor 130 according to one or more embodiments of the present disclosure.

[0111] The first processor 130 may obtain a frame by relocating the decoded data output from each of the plurality of buffer groups. Figure 4 As shown, the first processor 130 may receive decoded data (e.g., stream 1) from four buffers included in the first buffer group, and may obtain stream 1 with a 2k resolution by relocating the decoded data. For another example, the first processor 130 may receive decoded data (e.g., stream 2) from four buffers included in the second buffer group, and may obtain stream 2 with a 2k resolution by relocating the decoded data. For another example, the first processor 130 may receive decoded data (e.g., stream 3) from four buffers included in the third buffer group, and may obtain stream 3 with a 2k resolution by relocating the decoded data. For another example, the first processor 130 may receive decoded data (e.g., stream 4) from four buffers included in the fourth buffer group, and may obtain stream 4 with a 2k resolution by relocating the decoded data.

[0112] However, the present disclosure is not limited thereto, and the number of streams processed by the first processor 130, the resolution of the processed streams, etc. may be varied in various ways without departing from the scope of the present disclosure.

[0113] like Figure 4 As shown, the second processor 140 may include a resource manager 141 and / or a sampling operation unit 142. The resource manager 141 may identify a current usage rate of the first processor 130, and / or identify a remaining (e.g., available) usage rate based on the current usage rate. Alternatively or additionally, the resource manager 141 may identify an additional usage rate of the first processor 130 that is necessary (e.g., sufficient to play the additional stream). The sampling operation unit 142 may identify a downsampling rate based on the remaining (e.g., available) usage rate and the additional usage rate.

[0114] Figures 5 to 7 is a diagram for illustrating resource management of the first processor 130 according to one or more embodiments of the present disclosure.

[0115] Decoder 110 can decode multiple streams. Figure 5 As shown, decoder 110 may output stream 1, stream 2, stream 3, and stream 4. Although for ease of explanation, the streams are shown in Figure 5 In the example, the plurality of streams are indicated as stream 1, stream 2, stream 3 and stream 4, but the plurality of streams may be stored in a plurality of buffer groups, respectively. Optionally or additionally, each of the plurality of streams may be in a decoding state.

[0116] The first processor 130 may acquire one frame by repositioning a plurality of streams output from each of the plurality of buffer groups. For example, the first processor 130 may reposition a plurality of streams output from each of the plurality of buffer groups and output stream 1 with a 2k resolution, stream 2 with a 2k resolution, stream 3 with a 2k resolution, and stream 4 with a 2k resolution.

[0117] The resource manager 141 may identify the current usage 520 of the first processor 130, and may identify the remaining (e.g., available) usage of the first processor 130 based on the current usage. For example, if the current usage is 100%, the resource manager 141 may identify the remaining (e.g., available) usage of the first processor 130 as 0%.

[0118] Subsequently, if an instruction for playing an additional stream is received, the resource manager 141 may identify an additional usage rate necessary for playing the additional stream (e.g., sufficient for playing the additional stream), and request an operation for securing a downsampling rate of the resource from the sampling operation section 142. The sampling operation section 142 may identify the downsampling rate based on the remaining (e.g., available) usage rate and the additional usage rate. For example, if an instruction for playing stream 5 (510) is received, the resource manager 141 may identify an additional usage rate necessary for playing stream 5 (e.g., sufficient for playing stream 5) as 20%, and the sampling operation section 142 may identify the downsampling rate based on the remaining (e.g., available) usage rate 0% and the additional usage rate 20%.

[0119] The sampling operation part 142 may transmit a signal for downsampling at least one of the plurality of streams or the additional stream to the first processor 130. For example, the sampling operation part 142 may transmit a signal for repositioning streams 4 and 5 to 1k resolution to the first processor 130.

[0120] The first processor 130 may reposition the stream 4 to a 1k resolution, such as Figure 6 As shown, therefore, the utilization rate 610 of processing the stream 4 among the utilization rates of the first processor 130 may be reduced to half, and the remaining (eg, available) utilization rate 620 may be ensured.

[0121] When the remaining (eg, available) usage is ensured, the first processor 130 may reposition the stream 5 to a 1k resolution, such as Figure 7 As shown, therefore, the remaining (eg, available) utilization of the first processor 130 may be converted into a utilization 710 for processing stream 5.

[0122] The electronic device 100 may further include at least one scaler 150 , and the at least one downsampled stream may be upsampled by the at least one scaler 150 .

[0123] For example, a first scaler in the at least one scaler 150 may receive stream 4 at a 1k resolution and upsample the stream to a 2k resolution, and a second scaler in the at least one scaler 150 may receive stream 5 at a 1k resolution and upsample the stream to a 2k resolution. In an embodiment, the first scaler and the second scaler may perform upsampling using a neural network model.

[0124] Through the above operation, the first processor 130 can reduce quality degradation by using the scaler of the neural network model while processing 5 streams.

[0125] although Figures 5 to 7 The case where there is one additional stream is described, but the present disclosure is not limited thereto. For example, in the case where there are two additional streams, the first processor 130 may reposition streams 3 and 4 to 1k resolution, and reposition additional streams 5 and 6 to 1k resolution. In such an embodiment, stream 3 at 1k resolution, stream 4 at 1k resolution, stream 5 at 1k resolution, and stream 6 at 1k resolution may be upsampled to 2k resolution by four scalers.

[0126] Figure 8 is a flowchart for illustrating a control method of an electronic device according to one or more embodiments of the present disclosure.

[0127] In operation S810, a plurality of streams may be decoded. In operation S820, the plurality of streams may be stored in a plurality of buffer groups, respectively. In operation S830, a first processor included in the electronic device 100 may acquire a frame by relocating decoded data output from each of the plurality of buffer groups. In operation S840, when an additional stream needs to be played, a second processor of the electronic device 100 may identify an additional usage rate of the first processor necessary for playing the additional stream (e.g., sufficient to play the additional stream). If the remaining (e.g., available) usage rate of the first processor is less than the additional usage rate, in operation S850, the second processor may control the first processor to downsample at least one of the plurality of streams or the additional stream.

[0128] In operation S850, at least one of the number of streams to be downsampled and a downsampling rate of the streams to be downsampled may be identified based on the remaining (eg, available) usage rate and the additional usage rate.

[0129] Alternatively or additionally, in operation S850, if at least one of the multiple streams and / or additional streams is downsampled to less than a predetermined minimum resolution threshold based on the downsampling rate, at least one of the multiple streams and / or additional streams may be downsampled to the predetermined minimum resolution threshold, and the number of streams to be downsampled may be increased.

[0130] In an embodiment, in operation S850, if the remaining (e.g., available) usage of the first processor is less than the additional usage, the first processor may be controlled to downsample at least one of the multiple streams and / or the additional stream based on a resolution of each of the multiple streams and a resolution of the additional stream.

[0131] Alternatively or additionally, in operation S850, if the remaining (eg, available) usage rate of the first processor is less than the additional usage rate, the first processor may be controlled to downsample one of the plurality of streams.

[0132] In an embodiment, the second processor may include a resource manager configured to identify a remaining (eg, available) usage and an additional usage, and a sampling operation unit configured to identify a downsampling rate based on the remaining (eg, available) usage and the additional usage.

[0133] Alternatively or additionally, the control method may further include controlling at least one scaler to upsample at least one downsampled stream.

[0134] In an embodiment, at least one scaler may be configured to use a neural network model.

[0135] In an embodiment, in the decoding operation S810, a plurality of streams may be decoded by a multi-format decoder.

[0136] Alternatively or additionally, each of the plurality of buffer groups may include four buffers.

[0137] According to one or more embodiments of the present disclosure as described above, an electronic device may process a plurality of streams by various methods via resource management of a processor (eg, DSP) for image processing, thereby improving user convenience compared to related electronic devices.

[0138] That is, when the electronic device downsamples and processes at least one of the plurality of streams, the number of the plurality of streams increases, and thus the content that the user can simultaneously view can increase.

[0139] Alternatively or additionally, the electronic device may minimize image quality degradation by upsampling the at least one downsampled stream using at least one scaler using a neural network model.

[0140] According to one or more embodiments of the present disclosure, the various embodiments described above may be implemented as software including instructions stored in a machine-readable storage medium, which can be read by a machine (e.g., a computer). As used herein, a machine may refer to a device that calls instructions stored in a storage medium, and may operate according to the called instructions. Alternatively or additionally, a device may include an electronic device (e.g., electronic device A) according to an embodiment disclosed herein. In the case where the instruction is executed by a processor, the processor may perform a function corresponding to the instruction by itself, or perform a function corresponding to the instruction by using other components under its control. The instruction may include code generated or executed by a compiler or interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, the term "non-transitory" may refer to a storage medium that does not include a signal and is tangible, but does not indicate whether the data is stored in the storage medium semi-permanently or temporarily.

[0141] Alternatively or additionally, according to one or more embodiments of the present disclosure, the methods according to the various embodiments disclosed herein may be provided while being included in a computer program product. A computer program product may refer to a product that can be traded between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disk read-only memory (CD-ROM)), and / or distributed online through an application store (e.g., PlayStore™). In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored in a storage medium (such as a memory of a manufacturer's server, an application store's server, and a relay server), or may be temporarily generated.

[0142] In addition, according to one or more embodiments of the present disclosure, the various embodiments described above can be implemented in a recording medium that can be read by a computer or a computer-like device by using software, hardware, or a combination thereof. In some cases, the embodiments described in the present disclosure can be implemented as a processor itself. According to the implementation by software, embodiments such as the processes and functions described in the present disclosure can be implemented as separate software modules. Each of the software modules can perform one or more functions and operations described in the present disclosure.

[0143] In an embodiment, computer instructions for executing the processing operations of the device according to the aforementioned various embodiments may be stored in a non-transitory computer-readable medium. When the instructions are executed by a processor of a specific machine, the computer instructions stored in such a non-transitory computer-readable medium cause the processing operations of the device according to the aforementioned various embodiments to be executed by the specific machine. A non-transitory computer-readable medium refers to a medium that stores data semi-permanently and can be read by a machine, but not a medium that stores data for a short time, such as a register, a cache, and a memory. As specific examples of non-transitory computer-readable media, CDs, DVDs, hard disks, Blu-ray discs, USBs, memory cards, ROMs, etc. may be used.

[0144] Alternatively or additionally, each of the components (e.g., modules or programs) according to the aforementioned various embodiments may be composed of a single object or multiple objects. In addition, in the aforementioned corresponding subcomponents, some subcomponents may be omitted, or other subcomponents may be further included in various embodiments. Alternatively or additionally, some components (e.g., modules or programs) may be integrated as objects, and the functions performed by each component before integration are performed identically or in a similar manner. In addition, the operations performed by the modules, programs or other components according to the various embodiments may be performed sequentially, in parallel, repeatedly or heuristically. Alternatively or additionally, at least some of the operations may be performed in a different order, omitted, and / or other operations may be added.

[0145] In addition, although the embodiments of the present disclosure have been shown and described, the present disclosure is not limited to the aforementioned specific embodiments. It is obvious that various modifications may be made by a person of ordinary skill in the art to which the present disclosure belongs without departing from the scope of the present disclosure as claimed in the appended claims. In addition, it is intended that such modifications are not interpreted independently of the technical concept or prospect of the present disclosure.

Claims

1. An electronic device, comprising: a decoder configured to decode the plurality of streams; a plurality of buffers divided into a plurality of buffer groups corresponding to the plurality of streams; a first processor configured to acquire a frame by repositioning decoded data output from each of the plurality of buffer groups; as well as at least one second processor communicatively coupled to the decoder, the plurality of buffers, and the first processor and configured to control the electronic device, Wherein, the at least one second processor is further configured to: based on the first determination that an additional stream is to be played, identifying additional usage of the first processor sufficient to play the additional stream; determining whether the additional usage of the first processor exceeds the available usage of the first processor; and Based on a second determination that the additional usage of the first processor exceeds the available usage of the first processor, the first processor is controlled to downsample each of the plurality of streams and at least one of the additional streams.

2. The electronic device according to claim 1, wherein: The at least one second processor is further configured to: A number of streams to be downsampled is identified based on the available usage of the first processor and the additional usage of the first processor.

3. The electronic device according to claim 1, wherein: The at least one second processor is further configured to: A downsampling rate of the stream to be downsampled is identified based on the available usage of the first processor and the additional usage of the first processor.

4. The electronic device according to claim 3, wherein: The at least one second processor is further configured to: Based on determining that the resolution of at least one of the streams to be downsampled that has been downsampled at the downsampling rate is less than a predetermined minimum resolution threshold, downsample the at least one of the streams to be downsampled to the predetermined minimum resolution threshold, and increase the number of the streams to be downsampled.

5. The electronic device according to claim 1, wherein: The at least one second processor is further configured to: Based on a second determination that the additional usage of the first processor exceeds the available usage of the first processor, and according to a corresponding resolution of each of the multiple streams and each of the at least one of the additional streams, control the first processor to downsample each of the multiple streams and the at least one of the additional streams.

6. The electronic device according to claim 1, wherein: The at least one second processor is further configured to: Based on a second determination that the additional usage of the first processor exceeds the available usage of the first processor, the first processor is controlled to downsample at least one of the plurality of streams.

7. The electronic device according to claim 1, wherein: The at least one second processor comprises: a resource manager configured to identify the available usage and the additional usage; and The sampling operation unit is configured to identify a down-sampling rate based on the available usage rate and the additional usage rate.

8. The electronic device according to claim 1, further comprising: At least one scaler, The at least one second processor is further configured to: control the at least one scaler to upsample each of the multiple streams and the at least one downsampled stream in the additional stream.

9. The electronic device according to claim 8, wherein: The at least one scaler is configured to use a neural network model.

10. The electronic device according to claim 1, wherein: The decoder comprises a multi-format decoder.

11. The electronic device according to claim 1, wherein: Each buffer in the plurality of buffer groups includes four buffers.

12. A control method for an electronic device, the control method comprising: Decode multiple streams; storing the plurality of streams in a corresponding plurality of buffer groups; acquiring, by a first processor of the electronic device, a frame by repositioning decoded data output from each of the plurality of buffer groups; Based on determining that an additional stream is to be played, identifying, by a second processor of the electronic device, additional usage of the first processor sufficient to play the additional stream; determining whether the additional usage of the first processor exceeds the available usage of the first processor; as well as Based on determining that the additional usage of the first processor exceeds the available usage of the first processor, the second processor controls the first processor to downsample each of the plurality of streams and at least one of the additional streams.

13. The control method according to claim 12, wherein: The step of controlling the first processor comprises: A number of streams to be downsampled is identified based on the available usage of the first processor and the additional usage of the first processor.

14. The control method according to claim 12, wherein: The step of controlling the first processor comprises: A downsampling rate of the stream to be downsampled is identified based on the available usage of the first processor and the additional usage of the first processor.

15. The control method according to claim 14, wherein: The step of controlling the first processor further comprises: Based on determining that the resolution of at least one of the streams to be downsampled that has been downsampled at the downsampling rate is less than a predetermined minimum resolution threshold, downsample the at least one of the streams to be downsampled to the predetermined minimum resolution threshold, and increase the number of the streams to be downsampled.

Images