Wiring board

Abstract

A wiring board according to an embodiment includes: a first wiring board (11) including a first insulating layer (111), a first conductor layer (112), and a first via conductor (113); and a second wiring board (12) including a second insulating layer (211), a second conductor layer (212), and a second via conductor (213). The second wiring substrate (12) is mounted on the first wiring substrate (11), the minimum value of the wiring width of the wiring (FW2) included in the second conductor layer (212) is smaller than the minimum value of the wiring width of the wiring (FW1) included in the first conductor layer (112), the minimum value of the wiring interval of the wiring (FW2) is smaller than the minimum value of the wiring interval of the wiring (FW1), the wiring width of the wiring (FW2) is 3 [mu] m or less, and the wiring width of the wiring (FW1) is 3 [mu] m or less. The wiring interval of the wiring (FW2) is 3 [mu] m or less, and the aspect ratio of the wiring (FW2) is 2.0-4.0 (inclusive).

Description

Technical Field

[0001] The present invention relates to a wiring substrate. Background Art

[0002] Patent Document 1 discloses a semiconductor package having a first wiring substrate and a second wiring substrate. The second wiring substrate is bonded to the first wiring substrate to form an integrated whole. The second wiring substrate is an organic wiring substrate having an organic insulating film as a base material and has a finer wiring layer than the first wiring substrate.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-191323 Summary of the invention

[0006] Problems to be solved by the invention

[0007] It is considered that the aspect ratio of wiring included in the wiring layer of the semiconductor package including the first wiring substrate and the second wiring substrate disclosed in Patent Document 1 is relatively low, and reliability of the wiring may be relatively low.

[0008] Means for solving problems

[0009] The wiring substrate of the present invention comprises: a first wiring substrate comprising a first insulating layer and a first conductor layer alternately stacked and a first via conductor penetrating the first insulating layer; and a second wiring substrate comprising a second insulating layer and a second conductor layer alternately stacked and a second via conductor penetrating the second insulating layer. The second wiring substrate is mounted on one surface of the first wiring substrate, the minimum value of the wiring width of the wiring included in the second conductor layer is smaller than the minimum value of the wiring width of the wiring included in the first conductor layer, the minimum value of the wiring spacing of the wiring included in the second conductor layer is smaller than the minimum value of the wiring spacing of the wiring included in the first conductor layer, the wiring width of the wiring included in the second conductor layer is 3 μm or less, the wiring spacing of the wiring included in the second conductor layer is 3 μm or less, and the aspect ratio of the wiring included in the second conductor layer is 2.0 or more and 4.0 or less.

[0010] According to the embodiment of the present invention, it can be considered that a wiring substrate including wirings with relatively high reliability is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a cross-sectional view showing an example of a wiring substrate as an embodiment of the present invention.

[0012] Figure 2 It is shown Figure 1A partially enlarged cross-sectional view of an example of a wiring substrate shown.

[0013] Figure 3 It is shown Figure 2 A partially enlarged view of another example of the wiring substrate shown.

[0014] Figure 4A It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0015] Figure 4B It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0016] Figure 4C It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0017] Figure 4D It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0018] Figure 5A It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0019] Figure 5B It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0020] Figure 5C It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0021] Figure 5D It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0022] Figure 5E It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0023] Fig. 5F It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0024] Figure 5G It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0025] Figure 5H It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0026] Fig.5I It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0027] Figure 5J It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0028] Figure 5KIt is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0029] Figure 5L It is a diagram showing an example of a method for manufacturing a wiring substrate according to an embodiment.

[0030] Figure 6 It is a diagram showing another example of the method for manufacturing the wiring substrate according to the embodiment. DETAILED DESCRIPTION

[0031] A wiring substrate according to an embodiment will be described with reference to the drawings. Figure 1 1 is a cross-sectional view showing a wiring substrate 1 as an example of a wiring substrate according to an embodiment. The wiring substrate 1 shown in the figure is merely an example of a wiring substrate according to the present embodiment. In addition, in the referenced drawings, it is not intended to show the exact ratio of each component, but it is depicted in a manner that makes it easy to understand the features of the present invention.

[0032] like Figure 1 As shown, the wiring substrate 1 includes a first wiring substrate 11 and a second wiring substrate 12. In the example shown in the figure, the first wiring substrate 11 has a core substrate 100 including an insulating layer (core insulating layer) 101 and a conductor layer (core conductor layer) 102 formed on both sides of the core insulating layer 101. Insulating layers and conductor layers are alternately stacked on both sides of the core substrate 100. In the example shown in the figure, a plurality of insulating layers 111 and a plurality of conductor layers 112 are alternately stacked on the first surface F1 of the core substrate 100 and on the second surface F2 of the core substrate 100.

[0033] The first wiring substrate 11 has one surface 11FA and another surface 11FB on the side opposite to the one surface 11FA as the outermost surface (exposed surface) extending perpendicularly to the thickness direction thereof. The second wiring substrate 12 has a plurality of insulating layers 211 and a plurality of conductor layers 212 alternately stacked. The second wiring substrate 12 has an A surface 12FA and a B surface 12FB on the side opposite to the A surface 12FA as the outermost surface (exposed surface) extending perpendicularly to the thickness direction thereof.

[0034] The A surface 12FA of the second wiring substrate 12 is smaller than the one surface 11FA of the first wiring substrate 11. Specifically, the projection area of ​​the second wiring substrate 12 when projected onto the horizontal plane of the wiring substrate 1 (the plane of the wiring substrate 1 extending perpendicularly to the thickness direction) is smaller than the projection area of ​​the first wiring substrate 11 when projected onto the horizontal plane of the wiring substrate 1. For example, the shape of the second wiring substrate when projected onto the horizontal plane of the wiring substrate 1 is a square with a side of 50 mm, and its projection area is 250 mm. 2For example, the shape of the first wiring substrate when projected onto the horizontal plane of the wiring substrate 1 is a square with a side of 70 mm, and its projected area is 490 mm. 2 .

[0035] The second wiring substrate 12 is mounted on one surface 11FA of the first wiring substrate 11. Specifically, in the example shown in the figure, the conductor pad 112pA constituting the one surface 11FA of the first wiring substrate 11 and the conductor pad 212pB constituting the B surface 12FB of the second wiring substrate 12 are electrically connected via the conductive connecting member BM. That is, the wiring substrate of the embodiment includes the first wiring substrate 11 and the second wiring substrate 12 mounted on the one surface 11FA of the first wiring substrate 11.

[0036] The insulating layer 111 constituting the first wiring substrate 11 is also referred to as the first insulating layer 111, and the conductive layer 112 constituting the first wiring substrate 11 is also referred to as the first conductive layer 112. The insulating layer 211 constituting the second wiring substrate 12 is also referred to as the second insulating layer 211, and the conductive layer 212 constituting the second wiring substrate 12 is also referred to as the second conductive layer 212.

[0037] In the example shown in the figure, the first wiring substrate 11 has a cover insulating layer 11SRA constituting one surface 11FA and a cover insulating layer 11SRB constituting the other surface 11FB. The cover insulating layers 11SRA and 11SRB may be, for example, solder resist layers constituting the outermost insulating layer of the wiring substrate 1. An opening 11SRAo is formed in the cover insulating layer 11SRA, and a conductor pad 112pA is exposed in the opening 11SRAo. The opening 11SRAo is a through hole that penetrates the cover insulating layer 11SRA in the thickness direction, and a connecting member BM is arranged in the opening 11SRAo. An opening 11SRBo is formed in the cover insulating layer 11SRB, and a conductor pad 112pB constituting the other surface 11FB of the first wiring substrate 11 is exposed from the opening 11SRBo.

[0038] In the example shown in the figure, the A surface 12FA of the second wiring substrate 12, which is the opposite side of the B surface 12FB that faces the first wiring substrate 11, is formed by the cover insulating layer 12SRA. The cover insulating layer 12SRA is formed with an opening 12SRAo that exposes the conductor pad 212pA, and the connection element 12MP is formed in the opening 12SRAo. The connection element 12MP can function as a conductor post connected to the connection pads E1p and E2p of the components E1 and E2 that can be mounted on the second wiring substrate 12. That is, in the example shown in the figure, the A surface 12FA of the second wiring substrate 12, which is formed by the cover insulating layer 12SRA and the connection element 12MP, is configured as the component mounting surface of the wiring substrate 1.

[0039] The insulating layers 101, 111, 211 constituting the wiring substrate 1 can be formed using insulating resins such as epoxy resins and phenolic resins. The insulating layers 101, 111, 211 can also use fluororesins, liquid crystal polymers (LCP), polytetrafluoroethylene resins (PTFE), polyester resins (PE), and modified polyimide resins (MPI). Each insulating layer 101, 111, 211 sometimes contains reinforcing materials (core materials) such as glass fibers. Each insulating layer 101, 111, 211 can contain inorganic fillers such as silica and alumina. The cover insulating layers 11SRA, 11SRB, and 12SRA, which can be solder resist layers, can be formed using, for example, photosensitive epoxy resins or polyimide resins.

[0040] In addition, when the insulating layers 111 and 211 contain inorganic fillers, the size of the contained inorganic fillers may differ depending on the insulating layers 111 and 211. Specifically, the maximum particle size of the inorganic filler that can be contained in the second insulating layer 211 constituting the second wiring substrate 12 is sometimes smaller than the maximum particle size of the inorganic filler contained in the first insulating layer 111 constituting the first wiring substrate. In addition, the relative dielectric constant and dielectric loss tangent values ​​of the second insulating layer 211 constituting the second wiring substrate 12 are sometimes different from the relative dielectric constant and dielectric loss tangent values ​​of the first insulating layer 111 constituting the first wiring substrate 11.

[0041] A through-hole conductor 103 is formed on the insulating layer 101 constituting the core substrate 100, penetrating the insulating layer 101 in the thickness direction and connecting the conductor layer 102 constituting the first surface F1 and the conductor layer 102 constituting the second surface F2 in the core substrate 100. The interior of the through-hole conductor 103 is filled with a resin body 103i containing epoxy resin or the like. A via-hole conductor 113 is formed on the first insulating layer 111, connecting the conductor layers sandwiching the first insulating layer 111 to each other. A via-hole conductor 213 is formed on the second insulating layer 211, connecting the conductor layers sandwiching the second insulating layer 211 to each other. The via-hole conductor 113 formed on the first insulating layer 111 is also referred to as a first via-hole conductor 113, and the via-hole conductor 213 formed on the second insulating layer 211 is also referred to as a second via-hole conductor 213.

[0042] The conductor layers 102, 112, 212, via-hole conductors 113, 213, through-hole conductors 103, and connection elements 12MP are formed using any metal such as copper or nickel, and can be composed of metal foil such as copper foil and / or a metal film formed by plating or sputtering. The conductor layers 102, 112, 212, via-hole conductors 113, 213, through-hole conductors 103, and connection elements 12MP are formed using any metal such as copper or nickel. Figure 1Although shown as a single-layer structure, it can have a multilayer structure including more than two metal layers. For example, the conductor layer 102 formed on the surface of the insulating layer 101 can have a five-layer structure including a metal foil layer (preferably a copper foil), a chemically plated film layer (preferably a chemically plated copper film) and an electroplated film layer (preferably an electroplated copper film). In addition, the conductor layers 112, 212, the via conductors 113, 213, the through-hole conductor 103 and the connecting element 12MP can have a double-layer structure including a metal film layer as a chemically plated film or a sputtered film and an electroplated film layer. In addition, a functional layer BL that can function as a bonding layer between the components E1, E2 and the connecting element 12MP can be formed on the upper surface of the connecting element 12MP (the end surface on the side opposite to the conductor layer 212). The functional layer BL can be formed by a plated film such as nickel, tin, palladium or gold.

[0043] Each conductor layer 102, 112, 212 included in the wiring substrate 1 is patterned to have a predetermined conductor pattern. In the example shown in the figure, the first conductor layer 112 includes the first wiring FW1, and the second conductor layer 212 includes the second wiring FW2. In the wiring substrate of the embodiment, in particular, the wiring FW2 included in the second conductor layer 212 is formed as a finer wiring than the wiring FW1 included in the first conductor layer 112.

[0044] Specifically, the minimum value of the wiring width of the second wiring FW2 included in the second conductor layer 212 is smaller than the minimum value of the wiring width of the first wiring FW1 included in the first conductor layer 112. The minimum value of the wiring interval (distance between wirings) of the second wiring FW2 included in the second conductor layer 212 is smaller than the minimum value of the wiring interval of the first wiring FW1 included in the first conductor layer 112. In other words, the second wiring substrate 12 includes the finest second wiring FW2 among the wirings that can be included in the conductor layer constituting the wiring substrate 1.

[0045] The conductor pads 212pA included in the second conductor layer 212 closest to the A surface 12FA of the second wiring substrate 12 can be electrically connected to the electronic components that can be mounted on the wiring substrate 1 via the connection elements 12MP. Among the multiple conductor pads 212pA shown in the figure, the connection elements 12MP formed on the two conductor pads 212pA shown on the left are located in the first component mounting area EA1, and the connection elements 12MP formed on the two conductor pads 212pA shown on the right are located in the second component mounting area EA2. The component mounting areas EA1 and EA2 are areas where components E1 and E2 can be mounted, respectively. As components E1 and E2, electronic components such as active components such as semiconductor integrated circuit devices and transistors (for example, logic chips, memory elements) are exemplified. As shown in the figure, the connection elements 12MP located in these different component mounting areas EA1 and EA2 are sometimes connected by wiring included in the second wiring substrate 12. That is, the second conductor layer 212 sometimes includes so-called bridge wiring that electrically connects multiple connection elements 12MP constituting different component mounting areas. When the wiring substrate 1 is in use, a plurality of electronic components that can be mounted on the wiring substrate 1 can be electrically connected to each other via the second wiring substrate 12 through a relatively short path.

[0046] In addition, in particular, the thickness of the second conductor layer 212 constituting the second wiring substrate 12 may be different from the thickness of the conductor layers 102 and 112 constituting the first wiring substrate 11. Specifically, the thickness of the second conductor layer 212 may sometimes be smaller than the thickness of the conductor layers 102 and 112 constituting the first wiring substrate 11. For example, in the case where the minimum value of the thickness of the conductor layers 112 and 102 is 10 μm or more, the maximum value of the thickness of the second conductor layer 212 may be 7 μm or less.

[0047] Next, refer to Figure 2 , the structure of the second wiring substrate 12 constituting the wiring substrate 1 is described in detail. Figure 2 yes Figure 1 An enlarged view of region II surrounded by a single-dot chain line in FIG.

[0048] As described above, the second conductor layer 212 included in the second wiring substrate 12 includes the finest wiring FW2 among the wiring included in the wiring substrate 1. Specifically, the wiring FW2 included in the second conductor layer 212 is formed so that the minimum value of the wiring width is 3 μm or less and the minimum value of the wiring interval is 3 μm or less. In addition, the wiring FW2 included in the second conductor layer 212 is formed so that the aspect ratio is 2.0 or more and 4.0 or less. In this way, the second wiring substrate 12 includes the wiring FW2 with a relatively small wiring width and wiring interval and a relatively high aspect ratio, thereby providing a wiring substrate 1 with a relatively high density in the surface layer and a high reliability wiring that reduces the occurrence of defects such as disconnection. In addition, the second via-hole conductor 213 formed integrally with the conductor layer 212 included in the second wiring substrate 12 can be formed so that its aspect ratio (depth from the upper surface of the insulating layer 211 to the bottom of the via-hole conductor 213 / diameter of the upper side of the via-hole conductor 213 (the upper surface side of the insulating layer 211)) is 0.5 or more and 1.0 or less. In addition, the “diameter” in the description of the via-hole conductor 213 refers to the distance between the two longest points on the outer periphery in a horizontal cross section perpendicular to the depth direction of the via-hole conductor 213 .

[0049] In addition, as described above, the size of the inorganic filler that can be included in the second insulating layer 211 constituting the second wiring substrate 12 can be different from the size of the inorganic filler that can be included in the other insulating layers constituting the wiring substrate 1. The maximum particle size of the inorganic filler that can be included in the second insulating layer 211 is sometimes smaller than the maximum particle size of the inorganic filler that can be included in the other insulating layers constituting the wiring substrate 1. In the case where the second insulating layer 211 that contacts the wiring FW2 formed at a relatively high density contains an inorganic filler, when the inorganic filler with a relatively large particle size is located between adjacent wirings, a short circuit between the wirings sometimes occurs due to migration through the surface of the filler. Therefore, since the maximum particle size of the filler that can be included in the insulating layer 211 is relatively small, the possibility of a short circuit in the wiring FW2 can be reduced. In addition, the term "particle size" in the description of the filler refers to the straight-line distance between the two most distant points on the outer surface of the filler. Specifically, for example, the maximum particle size of the inorganic filler that can be included in the second insulating layer 211 can be 1 μm or less.

[0050] In the example shown in the figure, the first conductor layer 112 and the second conductor layer 212 have a two-layer structure of a metal film layer and an electroplated film layer. In the figure, the first conductor layer 112 includes a metal film layer 112np and an electroplated film layer 112ep, and the second conductor layer 212 includes a metal film layer 212np and an electroplated film layer 212ep. The metal film layer 112np included in the first conductor layer 112 can be a chemically plated copper film layer formed by chemical plating. The electroplated film layer 112ep can be an electroplated copper film layer formed by using the metal film layer 112np as a power supply layer. In particular, the metal film layer 212np constituting the second conductor layer 212 can be, for example, a sputtered film layer formed by sputtering with copper as a target. The metal film layer 212np as a sputtered film layer has relatively good adhesion to the upper surface of the insulating layer 211 and can have a more uniform thickness. The electroplated film layer 212ep may be an electroplated copper film layer formed by using the metal film layer 212np as a power supply layer.

[0051] In detail, regarding the manufacturing method of the wiring substrate, as described later, the second conductor layer 212 included in the second wiring substrate 12 sometimes includes a step of grinding the upper surface during its formation. Therefore, the upper surface of the second conductor layer 212 is a flat grinding surface with a relatively small roughness, so the conductor layer 212 (particularly the second wiring FW2) can have a relatively uniform thickness. Specifically, the upper surface of the second conductor layer 212 has an arithmetic mean roughness Ra of less than 0.3 μm. Since the thickness of the second wiring FW2 is formed to be relatively uniform, the insertion loss (insertion loss) of the signal transmitted by the wiring FW2 can be suppressed to a small value. It is believed that good signal transmission can be achieved through the wiring FW2.

[0052] The second wiring FW2 included in the second conductor layer 212 can be a wiring for high-frequency signal transmission. Therefore, the insulating layer 211 in contact with the wiring FW2 preferably has excellent high-frequency characteristics. From the viewpoint of achieving good signal transmission quality of the signal transmitted by the wiring FW2, it is preferred that the relative dielectric constant and dielectric loss tangent of the second insulating layer 211 have relatively low values. In the case where the insulating layer in contact with the wiring has a relatively high value of dielectric constant and dielectric loss tangent, the dielectric loss (transmission loss) of the high-frequency signal transmitted by the wiring is relatively large. Therefore, the insulating layer 211 in contact with the wiring FW2 is preferably composed of a material with a relatively small dielectric constant and dielectric loss tangent, and preferably has a relative dielectric constant of less than 0.005 and a dielectric loss tangent of less than 4.0 at a frequency of 5.8 GHz.

[0053] exist Figure 3 The structure of the second conductor layer 212 is shown in FIG. Figure 2 In other examples different from the example shown, Figure 2 The corresponding cross-sectional view of the area. Figure 2 In the example shown, the second conductive layer 212 has a shape protruding upward from the upper surface of the insulating layer 211. Figure 3 The second conductor layer 212 shown in FIG. 1 is buried (embedded) in the insulating layer 211 from the upper surface of the insulating layer 211. Specifically, Figure 3 In the embodiment, the second conductor layer 212 is composed of a conductor (metal film layer 212np and plated film layer 212ep) filling the groove G formed in the lower insulating layer 211. The second wiring FW2 included in the conductor layer 212 is formed as a wiring buried in the insulating layer 211 (buried wiring).

[0054] like Figure 3 The conductor layer 212 shown as being buried from the upper surface of the insulating layer 211 to the lower side may include forming a groove G in the insulating layer 211 by laser irradiation and filling the groove G with a conductor (which may be a metal film layer 212np and a plated film layer 212ep of a sputtered film layer). In addition, the process of filling the groove G with a conductor may include removing the metal film layer 212np and the plated film layer 212ep formed above the depth of the groove G by grinding. Therefore, as with reference Figure 2 The conductor layer 212 is similarly Figure 3 In the second conductive layer 212 having the form of burying the insulating layer 211 shown, the upper surface of the conductive layer 212 can also be set as a polished surface.

[0055] In particular, as shown in the figure, when the second wiring FW2 has the form of buried wiring, the size of the inorganic filler that can be included in the insulating layer 211 is a relatively small particle size (specifically, the maximum particle size of the filler is relatively small), thereby there is a case where the transmission quality of the signal transmitted by the second wiring FW2 is improved. Specifically, when the groove G is formed in the formation of the wiring FW2, there is a case where the inorganic filler is exposed in the groove G, and in this case, since the particle size of the inorganic filler is relatively small, there is a case where the change in the cross-sectional area in the length direction of the formed wiring FW2 is suppressed. It is possible to further reduce the insertion loss of the signal transmitted by the second wiring FW2.

[0056] In addition, as an example of a wiring substrate of the embodiment, the wiring substrate 1 including the first wiring substrate 11 and the second wiring substrate 12 is described above, but the second wiring substrate included in the wiring substrate of the embodiment may also include components mounted on the second wiring substrate. When the components E1 and E2 are included in the wiring substrate, the connection pads E1p and E2p of the components E1 and E2 are connected to the connection element 12MP, and the components E1 and E2 are sealed with a sealing resin M including epoxy resin, etc., and can be integrally combined with the second wiring substrate 12 (see Figure 1). That is, the wiring substrate of the embodiment sometimes includes a second wiring substrate having the form of a multi-chip package device. In this case, the thermal expansion coefficient of the sealing resin M is sometimes greater than the thermal expansion coefficient of the first wiring substrate and smaller than the thermal expansion coefficient of the second wiring substrate. The degree of thermal deformation of the wiring substrate 1 relative to temperature changes is mitigated and sometimes suppressed to a relatively small deformation.

[0057] Next, refer to Figure 4A to Figure 5L , to manufacture Figure 1 The method of manufacturing a wiring substrate will be described by taking the case of the wiring substrate 1 shown as an example.

[0058] Reference Figure 4A to Figure 4D , a method for manufacturing the first wiring substrate 11 is described. In manufacturing the first wiring substrate 11, first, Figure 4A As shown, a core substrate 100 is prepared. For example, a double-sided copper-clad laminate including a core insulating layer 101 is prepared. A through hole is formed on the double-sided copper-clad laminate, for example, by drilling. A chemically plated film layer, for example, is formed on the inner wall of the through hole and the upper surface of the metal foil, and an electroplated film layer is formed on the chemically plated film layer using the chemically plated film layer as a power supply layer. As a result, although shown as a single layer in the figure, a through-hole conductor 103 having a two-layer structure of a chemically plated film layer and an electroplated film layer and covering the inner wall of the through hole is formed. The inside of the through-hole conductor 103 is filled with a resin body 103i, for example, by injecting epoxy resin. After the filled resin body 103i is cured, a chemically plated film layer and an electroplated film layer are further formed on the upper surfaces of the resin body 103i and the electroplated film layer. As a result, although shown as a single layer in the figure, the conductor layer 102 having a five-layer structure of metal foil, chemical plating film layer, electroplating film layer, chemical plating film layer, and electroplating film layer is formed on both sides of the insulating layer 101. Then, the conductor layer 102 is patterned by a subtractive method to obtain a core substrate 100 having a predetermined conductor pattern.

[0059] Then, if Figure 4B As shown, an insulating layer 111 is formed on the first surface F1 and the second surface F2 of the core substrate 100, and a conductor layer 112 is formed on the upper side (the side away from the core substrate 100) of the insulating layer 111. For example, each insulating layer 111 is formed by hot pressing a film-like insulating resin on the core substrate 100. The insulating layer 111 is sometimes formed of a material containing an inorganic filler. The conductor layer 112 is formed by using any conductor pattern forming method such as a semi-additive method together with the first via conductor 113 that fills the opening 113a that can be formed by a laser in the insulating layer 111.

[0060] Then, if Figure 4CAs shown, lamination of insulating layer 111 and conductive layer 112 is further repeated as many times as necessary on first surface F1 and second surface F2 of core substrate 100. Conductive layer 112 is formed to include wiring FW1 as its conductive pattern.

[0061] Then, if Figure 4D As shown, an insulating layer 11SRA is formed on the conductor layer 112 farthest from the core substrate 100 on the first surface F1 side of the core substrate 100, and an insulating layer 11SRB is formed on the conductor layer 112 farthest from the core substrate 100 on the second surface F2 side. Openings 11SRAo and 11SRBo are formed in the covering insulating layers 11SRA and 11SRB to expose the conductor pads 112pA and 112pB. For example, a photosensitive epoxy resin film is formed by spraying, curtain coating, or film bonding, thereby forming the covering insulating layers 11SRA and 11SRB, and the openings 11SRAo and 11SRBo can be formed by exposure and development. The manufacture of the first wiring substrate 11 is completed.

[0062] Next, refer to Figure 5A to Figure 5L The manufacturing method of the second wiring substrate 12 is described. Figure 5A As shown, a support body 3 is prepared, and a conductor layer 212 is formed on one side 3a thereof. The support body 3 includes a substrate 31 , a first metal film layer 32 , a release layer 33 , and a second metal film layer 34 .

[0063] The conductor layer 212 is formed, for example, by pattern plating using electroplating. On the second metal film layer 34 constituting one side 3a of the support body 3, a plating resist (not shown) having openings corresponding to the formation positions of conductor patterns such as the conductor pad 212pB that the conductor layer 212 should include is provided. Then, by electroplating the second metal film layer 34 as a power supply layer, a metal such as copper is precipitated in the openings of the plating resist, thereby forming a conductor layer 212 including a conductor pattern formed by the precipitated metal. Thereafter, the plating resist is removed. In addition, before removing the plating resist, the upper surface (the surface on the side opposite to the support body 3) of the conductor layer 212 may be polished by any method such as chemical mechanical polishing (CMP). The conductor layer 212 may be formed to a thickness of, for example, 7 μm or less.

[0064] Then, if Figure 5BAs shown, an insulating layer 211 covering the conductor layer 212 is formed on the second metal film layer 34. The insulating layer 211 is formed, for example, by stacking a film of epoxy resin on the second metal film layer 34 and the conductor layer 212 and performing thermocompression bonding. In addition to epoxy resin, the insulating layer 211 can also be formed using a thermosetting resin such as BT resin, phenolic resin, or a thermoplastic resin such as fluororesin, LCP, etc. The insulating layer 211 can be formed, for example, using a material having a relative dielectric constant of less than 0.005 and a dielectric loss tangent of less than 4.0 at a frequency of 5.8 GHz. In addition, the insulating layer 211 can be formed from a material containing an inorganic filler having a maximum particle size smaller than the maximum particle size of the inorganic filler that can be contained in the insulating layer 111 constituting the first wiring substrate 11. For example, in the formation of the insulating layer 211, a material containing an inorganic filler having a maximum particle size of less than 1 μm can be used. In addition, in Figure 5B And the following references Figure 5C to Figure 5L In the figure, the depiction of the side opposite to the one surface 3 a of the support 3 is omitted.

[0065] The via conductor 213 (see Figure 1 ) is formed at a formation position by irradiation with a carbon dioxide laser or the like. Depending on the size of the via conductor 213 to be formed, the opening 213a can be formed, for example, so that the depth from the upper surface of the insulating layer 211 to the bottom of the opening 213a / the diameter of the upper side of the opening 213a (the side opposite to the conductor layer 212) is greater than 0.5 and less than 1.0. After the opening 213a is formed, it is preferred to perform a desmearing treatment to remove the resin scraps (stains) remaining in the opening 213a. The desmearing treatment may be a wet treatment including immersion in a liquid such as a permanganate solution, or a dry treatment such as a plasma treatment using a plasma gas such as argon, tetrafluoromethane, a mixture of tetrafluoromethane and oxygen, or sulfur hexafluoride.

[0066] A metal film layer 212np made of, for example, copper or nickel is formed by, for example, sputtering or chemical plating in the opening 213a and on the entire surface of the insulating layer 211. If the metal film layer 212np is formed by sputtering, the metal film layer 212np may have high adhesion to the insulating layer 211.

[0067] Then, if Figure 5C As shown, a plating resist R1 having an opening R1a is provided on the metal film layer 212np. The plating resist R1 is formed, for example, by laminating a dry film resist on the metal film layer 212np, and the opening R1a is formed, for example, by photolithography. The opening R1a is formed in a manner similar to that of the conductor layer 212 (see FIG. 2 ) formed on the insulating layer 211. Figure 1 ) should include a pattern corresponding to the conductor pattern formed.

[0068] As described above, the wiring FW2 (see Figure 1 ) and other conductor patterns have a wiring width of less than 3 μm and a wiring spacing of less than 3 μm. Each opening R1a is formed with an opening width corresponding to the wiring width that each conductor pattern such as the wiring FW2 formed in each opening R1a should have and an opening distance (the spacing between adjacent openings R1a) corresponding to the wiring spacing. In addition, as described above, the wiring FW2 included in the conductor layer 212 has an aspect ratio of greater than 2.0 and less than 4.0. Therefore, in Figure 5C In the illustrated method, the plating resist R1 is formed to have a thickness (height) greater than or equal to the thickness (height) that satisfies the aspect ratio that the wiring FW2 to be formed should have.

[0069] By using the metal film layer 212np as a power supply layer for electroplating, a plated film layer 212ep made of, for example, copper, nickel, etc. is formed in the opening R1a of the plating resist R1. A via conductor 213 is formed in the opening 213a of the insulating layer 211. The plated film layer 212ep is formed as shown in FIG. Figure 5C As in the example of , the opening R1a can be completely filled and can be formed to have a curved upper surface that protrudes upward from the upper surface of the plating resist R1.

[0070] like Figure 5D As shown, a portion of the upper surface side of the electroplated film layer 212ep is removed by grinding. At least the portion of the electroplated film layer 212ep protruding from the upper surface of the plating resist R1 can be removed. The electroplated film layer 212ep can be ground to, for example, 7 μm or less until the total thickness together with the metal film layer 212np reaches the thickness of the conductor layer 212 formed on the insulating layer 211 (see Figure 5E ) required thickness. A portion of the upper surface side of the plating resist R1 may also be removed together with a portion of the electroplated film layer 212ep. The grinding of the electroplated film layer 212ep may be performed by any method such as CMP. As a result of the grinding, the upper surface of the electroplated film layer 212ep may have an arithmetic mean roughness of less than 0.3 μm.

[0071] After the electroplating film layer 212ep is polished, the plating resist R1 is removed. In addition, the portion of the metal film layer 212np not covered by the electroplating film layer 212ep is removed by, for example, rapid etching. As a result, Figure 5E As shown in FIG. 1 , a conductor layer 212 including a predetermined conductor pattern is obtained. Figure 5E In, with Figure 1 Similarly, although the conductor layer 212 is depicted as being composed of one layer, the conductor layer 212 is composed of Figure 5D The metal film layer 212np shown and as described above from Figure 5D The electroplated film layer 212ep is formed by removing a portion of the electroplated film layer 212ep.

[0072] like Fig. 5F As shown, on the insulating layer 211 and the conductive layer 212 , the insulating layer 211 and the conductive layer 212 are further alternately formed by the same method as the above-mentioned method of forming the insulating layer 211 and the conductive layer 212 on the insulating layer 211 .

[0073] Then, if Figure 5G to Figure 5I As shown, a cover insulating layer 12SRA and a connection element 12MP are formed (see Fig.5I The connection element 12MP can be formed by a general conductor layer forming method such as a semi-additive method, but Figure 5G to Figure 5I 2 shows a method including the same polishing as the method for forming the conductor layer 212 described above. First, as Figure 5G As shown, a cover insulating layer 12SRA is formed on the conductor layer 212 and the insulating layer 211. The cover insulating layer 12SRA is formed by, for example, thermocompression bonding of a film-like epoxy resin in the same manner as the formation of the insulating layer 211. When the cover insulating layer 12SRA is an insulating layer that functions as a solder resist, it may be formed by a method different from that of the insulating layer 211, for example, by spraying or curtain coating using an epoxy resin or polyimide resin containing a photosensitive agent.

[0074] The opening 12SRAo is formed in the formed cover insulating layer 12SRA by, for example, irradiation with a carbon dioxide laser or photolithography. The opening 12SRAo is formed at a location where the connection element 12MP is to be formed (see Fig.5I ) at a position where the conductor pad 212pA is exposed at its bottom. After the opening 12SRAo is formed, a desmear treatment may be performed by plasma treatment or the like. A metal film layer Mnp, for example, made of copper, nickel, or the like, is formed on the entire inner surface of the opening 12SRAo and the surface of the covering insulating layer 12SRA by sputtering or chemical plating.

[0075] Then, if Figure 5H As shown, a plating resist R2 is formed on the metal film layer Mnp by lamination of a dry film resist, for example. An opening R2a corresponding to the connection element 12MP is formed in the plating resist R2 by photolithography or the like. On the inner surface of the opening R2a and in the opening 12SRAo exposed in the opening R2a, a metal such as copper and nickel is deposited by electroplating using the metal film layer Mnp as a power supply layer, thereby forming an electroplated film layer Mep. The inside of the opening R2a and the opening 12SRAo is filled with the electroplated film layer Mep. As shown in the figure, the electroplated film layer Mep can be formed to have a curved upper surface that protrudes upward from the upper surface of the plating resist R2.

[0076] Next, if Fig.5IAs shown, for example, a portion of the upper surface side of the electroplated film layer Mep is removed by CMP. A portion of the upper surface side of the plating resist R2 may also be removed together with a portion of the metal film layer Mep. The electroplated film layer Mep is ground until the height from the upper surface of the conductor layer 212 in contact with the metal film layer Mnp to the upper surface of the electroplated film layer Mep reaches the specified height required by the connection element 12MP. As a result, a connection element 12MP having a specified height and composed of the metal film layer Mnp and the ground electroplated film layer Mep is formed.

[0077] Then, if Figure 5J As shown, the functional layer BL can be formed on the surface of the connection element 12MP by electroplating using the metal film layer Mnp as a power supply layer. For example, one or more metal films made of nickel, tin, palladium or gold are formed as the functional layer BL.

[0078] Next, the plating resist R2 is removed, and the portion of the metal film layer Mnp exposed by removing the plating resist R2 and not covered by the electroplating film layer Mep is removed, for example, by rapid etching. Figure 5K As shown, a plurality of electrically separated connection elements 12MP are obtained. Figure 5G to Figure 5J In FIG. 1 , the metal film layer Mnp and the electroplated film layer Mep constituting the connection element 12MP are shown as different layers, but in FIG. Figure 5K to Figure 5L as well as Figure 6 In, with Figure 1 Likewise, the metal film layer Mnp and the plated film layer Mep constituting the connection element 12MP are collectively shown as a single layer.

[0079] Next, the support 3 is removed. Figure 5L As shown, for example, by heating, ultraviolet irradiation, etc., the base material 31 and the first metal film layer 32 are separated from the second metal film layer 34 when the adhesiveness of the release layer 33 of the support 3 is lost or the release layer 33 itself is softened.

[0080] Next, the second metal film layer 34 is removed by etching or the like. The surfaces of the conductor layer 212 including the conductor pad 212pB and the insulating layer 211 are exposed. Figure 1 The second wiring substrate 12 of the example shown.

[0081] Next, the second wiring substrate 12 is mounted on the first wiring substrate 11. Figure 1The manufacturing of the wiring substrate 1 shown is completed. Specifically, the B surface 12FB of the second wiring substrate 12 is arranged to face the one surface 11FA of the first wiring substrate 11, and the conductor pad 212pB of the second wiring substrate 12 is connected to the conductor pad 112pA of the first wiring substrate 11 via the connecting member BM. For example, after the connecting member BM, which is a solder ball, is arranged on the conductor pad 112pA, the conductor pad 212pB of the second wiring substrate 12 is arranged on the connecting member BM, and the reflow process is performed, the second wiring substrate 12 can be mounted on the first wiring substrate 11. Figure 1 The manufacture of the wiring substrate 1 of the example shown is completed.

[0082] exist Figure 6 The wiring substrate includes components E1 and E2 mounted on the surface (A surface 12FA) of the second wiring substrate 12 (see Figure 1 ) is an example of a state in the manufacturing process of a wiring substrate. Figure 6 As shown, in the manufacturing process of the second wiring substrate 12 having the form of a multi-chip package device, Figure 5K After the state in the process shown, the first component E1 and the second component E2 such as a microcomputer, a memory, etc. are mounted on the second wiring substrate 12 by reflow processing, flip chip bonding, etc. That is, the first component E1 and the second component E2 are mounted on the second wiring substrate 12 in a state with the support body 3. Since the second wiring substrate 12 is supported by the support body 3, the first component E1 and the second component E2 can be mounted in a stable state.

[0083] exist Figure 6 In the example of FIG. 1 , the first component E1 and the second component E2 can be sealed and combined by using a sealing resin M including epoxy resin or the like. The first component E1 and the second component E2 are sealed by, for example, transfer molding or compression molding. The sealing process can also be performed in a state where the second wiring substrate 12 has the support body 3.

[0084] Figure 6 The second wiring substrate 12 on which the first component E1 and the second component E2 are mounted is shown in FIG. Figure 5L In the same manner as described above, the support member 3 is removed and mounted on the first wiring substrate 11. The formation of the wiring substrate including the first member E1 and the second member E2 is completed.

[0085] The wiring substrate of the embodiment is not limited to the structure, shape and material illustrated in the drawings and in this specification. For example, the first wiring substrate and the second wiring substrate can each have any number of insulating layers and conductive layers. In the description of the embodiment, an example is shown in which the first wiring substrate has a core substrate, but the first wiring substrate may also be a coreless substrate that does not include a core substrate.

[0086] Description of symbols

[0087] 1: wiring substrate; 11: first wiring substrate; 12: second wiring substrate; 100: core substrate; 101: insulation layer (core insulation layer); 102: conductor layer (core conductor layer); 103: through-hole conductor; 111: insulation layer (first insulation layer); 112: conductor layer (first conductor layer); 113: via conductor (first via conductor); 211: insulation layer (second insulation layer); 212: conductor layer (second conductor layer); 213: via conductor (second via conductor); 11FA: one surface; 11F B: another surface; 12FA: surface A; 12FB: surface B; 11SRA, 11SRB, 12SRA: covering insulating layer; 12MP: connecting element; F1: first surface; F2: second surface; BM: connecting component; EA1: component mounting area (first component mounting area); EA2: component mounting area (second component mounting area); E1: component (first component); E2: component (second component); FW1: wiring (first wiring); FW2: wiring (second wiring); M: sealing resin.

Claims

1. A wiring substrate, comprising: a first wiring substrate including first insulating layers and first conductor layers alternately stacked, and first via conductors penetrating the first insulating layers; and a second wiring substrate including a second insulating layer and a second conductor layer alternately stacked, and a second via conductor penetrating the second insulating layer; in, The second wiring substrate is mounted on one surface of the first wiring substrate, The minimum value of the wiring width of the wiring included in the second conductor layer is smaller than the minimum value of the wiring width of the wiring included in the first conductor layer, The minimum value of the wiring interval of the wiring included in the second conductor layer is smaller than the minimum value of the wiring interval of the wiring included in the first conductor layer, The wiring width of the wiring included in the second conductor layer is 3 μm or less, and the wiring interval of the wiring included in the second conductor layer is 3 μm or less. The aspect ratio of the wiring included in the second conductive layer is greater than or equal to 2.0 and less than or equal to 4.

0.

2. The wiring substrate according to claim 1, wherein: The first insulating layer and the second insulating layer respectively contain inorganic fillers, The maximum particle size of the inorganic filler included in the second insulating layer is smaller than the maximum particle size of the inorganic filler included in the first insulating layer.

3. The wiring substrate according to claim 1, wherein The second via-hole conductor has an aspect ratio of 0.5 to 1.

0.

4. The wiring substrate according to claim 1, wherein: The wiring included in the second conductor layer is formed of a conductor filling a groove formed in the second insulating layer.

5. The wiring substrate according to claim 1, wherein The thickness of the second conductor layer is less than 7 μm. The thickness of the first conductor layer is greater than 10 μm.

6. The wiring substrate according to claim 1, wherein The upper surface of the wiring included in the second conductor layer is a polished surface, The surface roughness of the upper surface of the wiring included in the second conductive layer is 0.3 μm or less in terms of arithmetic mean roughness.

7. The wiring substrate according to claim 1, wherein: The second insulating layer has a dielectric loss tangent of 0.005 or less at a frequency of 5.8 GHz, and a relative dielectric constant of 4.0 or less.

8. The wiring substrate according to claim 1, wherein The wiring included in the first conductor layer and the second conductor layer has a metal film layer and a plated film layer. The metal film layer of the wiring included in the first conductor layer is a chemically plated film layer. The metal film layer of the wiring included in the second conductor layer is a sputtered film layer.

9. The wiring substrate according to claim 1, wherein: A projection area of ​​the second wiring substrate onto a surface extending perpendicularly to the thickness direction of the wiring substrate is smaller than a projection area of ​​the first wiring substrate onto a surface extending perpendicularly to the thickness direction of the wiring substrate.

10. The wiring substrate according to claim 1, wherein The surface of the second wiring substrate opposite to the first substrate has at least a first component mounting area and a second component mounting area. The component mounting pads included in the first component mounting region and the component mounting pads included in the second region are connected via the second conductor layer.

11. The wiring substrate according to claim 10, wherein: The wiring substrate further includes a first component mounted in the first component mounting area and a second component mounted in the second component mounting area. The first member and the second member are integrally bonded by a sealing resin.

12. The wiring substrate according to claim 11, wherein The thermal expansion coefficient of the sealing resin is larger than the thermal expansion coefficient of the first wiring substrate and smaller than the thermal expansion coefficient of the second wiring substrate.

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