Back side contact of semiconductor device

Abstract

A backside contact surrounding the source / drain region provides an increased contact area for an electrical connection between the field effect transistor and the metallization layer. A cavity formed in the device layer exposes the sidewall of the selected source / drain region. A back side contact extends within this cavity and adjoins the sidewall surface and the bottom surface of the selected source / drain region.

Description

Background Art

[0001] The present invention relates generally to the electrical, electronic and computer fields, and more particularly to FET structures having backside contacts and methods of forming such backside contacts.

[0002] As the size of various integrated circuit components decreases, transistors such as field effect transistors (FETs) have experienced significant improvements in performance and power consumption. These improvements can be attributed primarily to the reduction in the size of the components used therein, which generally translates into reduced capacitance, resistance, and increased through-current from the transistor. Metal oxide semiconductor field effect transistors (MOSFETs) are well suited for use in high density integrated circuits. As the size of MOSFETs and other devices decreases, the size of the source / drain region, channel region, and gate electrode of the device also decreases.

[0003] FinFETs, nanosheets, and vertical transfer FETs are already being developed for possible use in tight pitch applications. A nanosheet FET includes multiple channel layers, each separated by a gate stack that includes a conductive gate material layer and a gate dielectric layer. The gate stack wraps around all sides of the channel layer, forming a gate-all-around (GAA) structure. The epitaxial regions at the ends of the nanosheet channel layers form the source / drain regions of the nanosheet FET.

[0004] Using both front side contacts and back side contacts can facilitate the manufacture and performance of the integrated circuit. By providing contacts on both sides of the chip, the contact spacing can be greater than if only one side (e.g., the front side) included all the contacts for the FETs. The back side power rail can be electrically connected to the back side source / drain contacts. Summary of the invention

[0005] A monolithic semiconductor structure according to one aspect of the present invention includes a device layer having a front side and a back side, an interlayer dielectric layer, and a field effect transistor. The field effect transistor includes a channel region and a first and a second source / drain region in the interlayer dielectric layer and extending laterally from the channel region. A back-end-of-line layer above the front side of the device layer is electrically connected to the field effect transistor. A back-side contact having a width greater than the bottom surface of the first source / drain region extends from the back side of the device layer. The back-side contact is electrically connected to the first source / drain region and contacts the first and second sidewall surfaces of the first source / drain region.

[0006] The second monolithic semiconductor structure includes a device layer, which includes a front side and a back side. The device layer includes: an nFET region including an nFET transistor, a pFET region including a pFET transistor, and an interlayer dielectric layer. The nFET transistor and the pFET transistor are located in the interlayer dielectric layer. The back-end process layer on the front side of the device layer is electrically connected to one or more of the nFET transistor and the pFET transistor. One or more back-side contacts extend from the back side of the device layer. Each of the one or more back-side contacts is electrically connected to a first source / drain region of one of the nFET transistor and the pFET transistor, respectively. Each of the one or more back-side contacts has a width greater than the bottom surface of the first source / drain region and contacts the first and second sidewall surfaces of the first source / drain region.

[0007] A method of manufacturing a semiconductor structure including a backside contact includes: forming a sacrificial placeholder in a substrate; forming a device layer having a front side and a back side above the substrate, the device layer including an interlayer dielectric layer, a semiconductor channel region, and first and second source / drain regions in the interlayer dielectric layer and extending laterally from the channel region. The first source / drain region and a portion of the interlayer dielectric layer adjacent to the first source / drain region are formed directly above the sacrificial placeholder. The method also includes forming a back-end process interconnect layer above the front side of the device layer, removing the sacrificial placeholder to expose a bottom surface of the first source / drain region and a portion of the interlayer dielectric layer adjacent to the first source / drain region, forming a recess in the interlayer dielectric layer to expose a first sidewall and a second sidewall of the first source / drain region, and forming a backside contact above the bottom surface, the first sidewall, and the second sidewall of the first source / drain region and extending from the back side of the device layer.

[0008] The techniques and structures disclosed herein can provide substantially beneficial technical effects. By way of example only and not limitation, one or more embodiments can provide one or more of the following advantages:

[0009] Manufacturing flexibility;

[0010] Benefits of rear-side power delivery network technology;

[0011] Increased rear contact area;

[0012] Wrap around rear contact.

[0013] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following drawings are presented by way of example only, and not limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:

[0015] Figure 1 is a top plan view of a layout including a sacrificial gate on a nanosheet stack according to an exemplary embodiment, showing x, y-1 and y-2 cross sections;

[0016] Figure 1A is along Figure 1 A schematic cross-sectional view of the y-1 section;

[0017] Figure 1B is a schematic cross-sectional view thereof taken along the y-2 section;

[0018] Figure 1C is a schematic cross-sectional view thereof taken along the x-cross section;

[0019] Figure 2A is a schematic cross-sectional view along the y-1 section, showing the bottom layer of the nanosheet stack after removal. Figure 1A The structure shown in;

[0020] Figure 2B is a schematic cross-sectional view thereof taken along the y-2 section;

[0021] Figure 2C is a schematic cross-sectional view thereof taken along the x-cross section;

[0022] Figure 3A yes Figure 2A A schematic cross-sectional view of the structure shown after forming a spacer layer;

[0023] Figure 3B yes Figure 3A A schematic cross-sectional view of the structure shown taken along the y-2 section;

[0024] Figure 3C yes Figure 3A A schematic cross-sectional view of the structure shown taken along an x-section;

[0025] Figure 4A yes Figure 3A A schematic cross-sectional view of the structure shown in after depositing and recessing an organic planarization layer;

[0026] Figure 4B is a schematic cross-sectional view taken along the y-2 section;

[0027] Figure 4C is a schematic cross-sectional view thereof taken along the x-cross section;

[0028] Figure 5A is a diagram showing the structure after partially removing the spacer layer and forming the protective gate spacer Figure 4A A schematic cross-sectional view of the structure of;

[0029] Figure 5B is a schematic cross-sectional view thereof taken along the y-2 section;

[0030] Figure 5C is a schematic cross-sectional view thereof taken along the x-cross section;

[0031] Fig. 6A After further recessing the organic planarization layer and removing the spacer material from the sidewalls of the nanosheet stack Figure 5A A schematic cross-sectional view of the structure shown;

[0032] Figure 6B is a schematic cross-sectional view thereof taken along the y-2 cross section after the sacrificial layer is exposed;

[0033] Figure 6C is a schematic cross-sectional view thereof taken along the x-cross section;

[0034] Fig. 7A yes Fig. 6A A schematic cross-sectional view of the structure shown after internal spacer formation;

[0035] Figure 7B is a schematic cross-sectional view thereof taken along the y-2 section;

[0036] Figure 7C is a schematic cross-sectional view thereof taken along the x-cross section;

[0037] Fig. 8A After deposition of another organic planarization layer and patterning of placeholder trenches Fig. 7A A schematic cross-sectional view of the structure shown;

[0038] Figure 8B is a schematic cross-sectional view thereof taken along the y-2 section;

[0039] Figure 8C is a schematic cross-sectional view thereof taken along the x-cross section;

[0040] Fig. 9A yes Fig. 8A A schematic cross-sectional view of the structure shown in taken along the y-1 cross section after depositing and recessing the placeholder material;

[0041] Fig. 9B is a schematic cross-sectional view thereof taken along the y-2 section;

[0042] Fig. 9C is a schematic cross-sectional view thereof taken along the x-cross section;

[0043] Fig. 10A yes Fig. 9A A schematic cross-sectional view of the structure shown after source / drain epitaxy and deposition of an interlayer dielectric layer;

[0044] Fig. 10B is a schematic cross-sectional view thereof taken along the y-2 section;

[0045] Fig. 10C is a schematic cross-sectional view thereof taken along the x-cross section;

[0046] Fig.11A After replacement gate formation, contact and interconnect formation, and carrier wafer bonding Fig. 10A A schematic cross-sectional view of the structure shown;

[0047] Fig. 11B is a schematic cross-sectional view thereof taken along the y-2 section;

[0048] Fig. 11C is a schematic cross-sectional view thereof taken along the x-cross section;

[0049] Fig. 12A After the wafer is flipped and the semiconductor substrate is removed Fig.11A A schematic cross-sectional view of the structure shown;

[0050] Fig. 12B is a schematic cross-sectional view thereof taken along the y-2 section;

[0051] Fig. 12C is a schematic cross-sectional view thereof taken along the x-cross section;

[0052] Fig.13A yes Fig. 12A A schematic cross-sectional view of the structure shown after deposition and planarization of a capping layer;

[0053] Fig. 13B is a schematic cross-sectional view thereof taken along the y-2 section;

[0054] Fig. 13C is a schematic cross section thereof taken along the x-cross section;

[0055] Fig.14A yes Fig.13A a schematic cross-sectional view of the structure shown after selective removal of the sacrificial placeholder;

[0056] Fig. 14B yes Fig.14A A schematic cross-sectional view of the structure shown taken along the y-2 section;

[0057] Fig. 14C is a schematic cross-sectional view thereof taken along the x-cross section;

[0058] Fig.15A yes Fig.14A A schematic cross-sectional view of the structure shown after exposing selected source / drain regions;

[0059] Fig. 15B is a schematic cross-sectional view thereof taken along the y-2 section;

[0060] Fig. 15C is a schematic cross-sectional view thereof taken along the x-cross section;

[0061] Fig.16A yes Fig.15A A schematic cross-sectional view of the structure shown after rear side contact metallization;

[0062] Fig. 16B is a schematic cross-sectional view thereof taken along the y-2 section;

[0063] Fig. 16C is a schematic cross-sectional view thereof taken along the x-cross section;

[0064] Fig.17A After forming the backside power rail and backside power delivery network (BS-PDN) Fig.16A A schematic cross-sectional view of the structure shown in ;

[0065] Fig. 17B is a schematic cross-sectional view taken along the y-2 section; and

[0066] Fig. 17C is a schematic cross-sectional view thereof taken along the x-section.

[0067] It should be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-known elements that may be useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of the illustrated embodiments. DETAILED DESCRIPTION

[0068] The principles of the present invention will be described herein in the context of illustrative embodiments. However, it should be understood that the specific embodiments and / or methods illustratively shown and described herein should be considered exemplary and not restrictive. In addition, it will be apparent to those skilled in the art that many modifications may be made to the illustrated embodiments under the teachings given herein, and these modifications are within the scope of the claims. That is, no limitation on the embodiments illustrated and described herein is intended or should be inferred.

[0069] The use of backside contacts can facilitate the fabrication and performance of integrated circuits, particularly those that include relatively small components and increased packaging density. Gate-all-around (GAA) transistors such as nanosheet transistors and fin field effect transistors (FinFETs) are among the components employed in high-density, high-performance applications.

[0070] Figure 1 An exemplary sequence of steps that may be used to fabricate an integrated circuit including backside contacts is shown in and subsequent figures. Figure 1The schematic top plan view of provides a perspective view of the orientation of the x, y-1 and y-2 cross sections relative to the fin, which includes the nanosheet stack 20 and the sacrificial gate 22 extending perpendicularly relative to the fin. It will be understood that the technology as described herein is applicable to architectures including FinFETs as well as those including nanosheet transistors.

[0071] Figure 1 , Figure 1A , Figure 1B and Figure 1C The monolithic structure shown in FIG. 1 comprises a stack 20 of nanosheets including a semiconductor channel layer 21 formed on a substrate 34, which may be formed, for example, on a semiconductor-on-insulator substrate. Figure 1A , Figure 1B and Figure 1C , the substrate 34 includes a silicon layer 24 , a silicon germanium top layer 26 having a relatively high germanium content, and a buried oxide (BOX) layer 28 between the silicon layer and the silicon germanium top layer 26 .

[0072] In one or more exemplary embodiments, the semiconductor nanosheet (channel) layers 21 each have a thickness in the range of four to ten nanometers (4-10nm). The number of semiconductor (channel) layers in the semiconductor layer stack can vary depending on the desired use and capabilities of the nanosheet transistor to be manufactured. The semiconductor channel layer 21 is essentially a single crystal silicon layer and is spaced ten to twenty nanometers (10-20nm) apart in some embodiments. The width of each semiconductor channel layer 21 in the top fin portion of the exemplary monolithic structure is fifteen nanometers (15nm) or greater in some embodiments (as seen in the y-1 and y-2 cross sections). The size of the channel layer and the vertical spacing of the channel layer should be considered exemplary and not restrictive.

[0073] The silicon and silicon germanium layers 21, 26' can be epitaxially grown on the semiconductor substrate in an alternating sequence to obtain a stack of silicon (channel) layers having a desired number. The terms "epitaxial growth and / or deposition" and "epitaxial growth and / or deposition" refer to the growth of semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material of the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of atoms of the deposition surface. Therefore, the epitaxial semiconductor material has the same crystal properties as the deposition surface on which the epitaxial semiconductor material is formed.

[0074] Figure 1 , Figure 1A , Figure 1B and Figure 1CThe monolithic structure shown in FIG is obtained by first growing silicon and silicon germanium nanosheet layers in an alternating sequence on a substrate 34, wherein the sacrificial silicon germanium layer 26', which is later replaced by a metal gate and a gate dielectric material in the process, may have a thickness in the range of six to twenty nanometers (6-20 nm). The size ranges of the channel layer and the sacrificial silicon germanium layer should be considered exemplary and not limiting. The silicon germanium layer 26' may have a composition of Si 1-x Ge x , where x is between 0.2 and 0.3 to allow for selective etching relative to silicon and the underlying silicon germanium top layer 26. In one exemplary embodiment, the sacrificial silicon germanium layer 26' has a composition of Si 1-x Ge x , where x is about 0.3, and the top substrate layer 26 has a composition Si 1-x Ge x , where x is approximately 0.55. The thickness of the top silicon germanium substrate layer 26 can be the same or different from the thickness of the sacrificial silicon germanium layer 26' adjacent to the silicon channel layer 21. Using a patterned hard mask (e.g., silicon nitride), an initial reactive ion etch (RIE) is performed up to the BOX layer 28 to obtain a top multi-layer, fin-shaped semiconductor structure with a dielectric cap (not shown) formed by the hard mask. The multi-layer, fin-shaped semiconductor structure (nanosheet stack 20) ​​extends vertically from the substrate 34, and the remaining portion of the hard mask is removed.

[0075] A sacrificial gate layer is formed on the stack of nanosheet layers 20 and the BOX layer 28, and the sacrificial gate layer may include, for example, amorphous silicon (A-Si) or polycrystalline silicon (poly-Si). The sacrificial gate material used to form the sacrificial gate layer may be formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. A hard mask (e.g., SiNx or SiNx and SiO2) is deposited and patterned on the top surface of the sacrificial gate layer. 2 The sacrificial gate layer is then subjected to reactive ion etching down to the BOX layer 28, and the resulting structure includes a sacrificial gate 22 extending vertically relative to the parallel nanosheet stack 20, and a patterned gate hard mask 32 abutting the top surface of the sacrificial gate. Figure 1B As shown, a portion of the nanosheet stack is embedded in the sacrificial gate. The sacrificial gate extends through the nFET and pFET regions of the exemplary structure, as shown in FIG. Figure 1 shown.

[0076] The top substrate layer 26 is selectively removed, thereby forming a space 36 between the BOX layer 28 and the nanosheet stack 20. As described above, the top substrate layer 26 has a higher germanium content than the sacrificial silicon germanium layer 26' within the nanosheet stack 20, and can therefore be selectively etched relative to such layers. A selective etching process, such as dry HCl etching, can be used to selectively remove the top substrate layer 26 to have selectivity to the silicon channel layer 21 and the sacrificial silicon germanium layer 26'. Figure 2A , Figure 2B and Figure 2C A cross-sectional view of the resulting structure is provided.

[0077] A dielectric layer is deposited on the resulting structure and fills the space 36 between the BOX layer 28 and the nanosheet stack 20. The dielectric gate spacer may include, for example, SiN, SiBCN, SiOCN and / or SiCO, or other suitable dielectric materials. Such materials may be deposited using ALD (atomic layer deposition). In an exemplary embodiment, a silicon nitride liner is deposited on the monolithic structure. The silicon nitride liner is selectively etched back to remove its unprotected horizontal portion, thereby forming a vertical top sidewall gate spacer 38 on the sidewalls of the nanosheet stack 20 and the sacrificial gate 22, and the spacer material below the nanosheet stack is protected and remains in the spacer 36 after etching back, thereby forming a bottom dielectric isolation layer. Figure 3A , Figure 3B and Figure 3C A cross-sectional view of the resulting structure including vertical gate spacers 38 and a bottom dielectric isolation layer (horizontal spacers 38A) beneath the nanosheet stack 20 is provided.

[0078] An organic planarization layer (OPL) 42 is deposited and then recessed to obtain Figure 4A , Figure 4B and Figure 4C The structure 40 shown. Figure 4C As shown in the x-cross-section provided, after the OPL is recessed, portions of the hard mask 32 and vertical gate spacers 38 extend above the top surface of the OPL 42. The exposed portions of the gate spacers 38 are then selectively removed down to the level of the top surface of the OPL.

[0079] Please refer to Figure 5C In the structure 50 shown in the X-section view in FIG. 1 , gate protection sidewall spacers 44 are formed on the sidewalls of the top of the hard mask 32, and in some embodiments, oxide sidewall spacers are formed. Aluminum oxide, titanium oxide, and titanium nitride are other optional materials that can include gate protection sidewall spacers 44 in embodiments where the vertical gate spacers 38 are silicon nitride spacers. The gate protection sidewall spacers 44 abut the top surface of the gate sidewall spacers 38 adjacent to the sacrificial gate 22. As shown in FIG. Figure 5AAs shown in the y-1 section in FIG. 4 , the gate sidewall spacer 38 adjacent to the nanosheet stack 20 remains embedded within the OPL 42 .

[0080] The OPL 42 is removed to expose the gate sidewall spacer 38 adjacent to the nanosheet stack 20. Ashing or other suitable processes may be used to remove the OPL. The unprotected portion of the gate sidewall spacer 38 is then removed to obtain a nanosheet stack 20. Fig. 6A , Figure 6B and Figure 6C Structure 60 is schematically shown. Reactive ion etching can be used for this removal. The gate sidewall spacers 38 below the gate protection sidewall spacers 44 remain intact, while those adjacent to the nanosheet stack are removed. Spacers 38A that form the bottom dielectric isolation layer below the nanosheet stack 20 also remain intact.

[0081] refer to Fig. 7A , 7B and 7C, reactive ion etching is performed on the portion of the nanosheet stack 20 outside the area protected by the sacrificial gate 22 and the hard mask 32, etching down to the horizontal spacer 38A. The resulting structure is subjected to a timed wet etching process to selectively recess the silicon germanium layer 26' within the nanosheet stack 20. In some embodiments, hydrogen chloride gas is used to selectively remove silicon germanium, leaving the silicon nanosheet (channel) layer 21 substantially intact. Alternatively, a wet etching process containing ammonia and hydroperoxide can be used to selectively etch SiGe relative to other materials. Each exposed end of the silicon germanium layer 26' can be recessed, for example, by three to seven nanometers (3-7nm). After the timed etching, the width of the silicon germanium layer 26' is less than the width of the silicon (channel) layer 21. Therefore, the stack of semiconductor nanosheet layers includes a dent between the ends of each pair of silicon (channel) layers 21.

[0082] A dielectric spacer material is deposited in the trenches created by the reactive ion etching of the semiconductor layer stack. The dielectric spacer material is etched back to form an inner spacer 46 within each recess in the stack of nanosheet semiconductor layers. A selective wet etch may be employed to remove the dielectric inner spacer material outside of the recesses between the silicon layers. Fig. 7A , 7Band structure 70 schematically shown in 7C. The internal spacer 46 of the structure may include, for example, a low-k dielectric material. In some embodiments, silicon oxynitride, SiBCN (silicon boron carbon nitride), SiOCN (silicon carbon nitride oxide), and / or SiOC (silicon carbide oxide) internal spacers may be formed. If used to form the internal spacer, phosphoric acid, for example, may be used to selectively etch the relatively low-k silicon nitride-based material. Various techniques for forming internal spacers for nanosheet transistors have been discussed in the literature and continue to be developed. Therefore, the specific materials and steps discussed with respect to the formation of the internal spacer should be considered exemplary and not restrictive.

[0083] Another OPL 42' is deposited over structure 70 and patterned using, for example, a photolithographically patterned hard mask (not shown) formed thereon. Fig. 8A and 8C As shown, a placeholder trench 48 is formed extending through the BOX layer 28 and partially within the semiconductor substrate layer 24. The sidewalls adjacent to the placeholder trench are substantially vertical. Using another OPL 42' as a mask, reactive ion etching or a sequence of reactive ion etching is used to form the placeholder trench 48. When forming the placeholder trench 48, the end of the silicon nanosheet (channel) layer 21 on one side of the nanosheet stack 20 is exposed, as shown in FIG. Figure 8C The opposite side of the nanosheet stack of the resulting structure 80 is adjacent to another OPL 42'.

[0084] The other OPL 42' is removed, and a placeholder material layer is deposited in the placeholder trench 48, so that the placeholder material layer is recessed to form a Fig. 9A , Fig. 9B and Fig. 9C The structure 90 is schematically shown. The placeholder material layer includes a sacrificial placeholder 52, which is later replaced by a backside contact, as described below. The sidewalls of the sacrificial placeholder are substantially vertical. Silicon germanium, aluminum oxide, and titanium oxide are among the materials that can constitute the sacrificial placeholder 52.

[0085] Source / drain regions 56-1, 56-2 are epitaxially grown on the exposed edges of the silicon nanosheet channel layer 21, one of the source / drain regions 56-1 of each FET is grown on one of the sacrificial placeholders 52, and the source / drain region 56-2 grown on the opposite side of each FET is grown on the BOX layer 28, as shown in FIG. Fig. 10A and Fig. 10C The width of the sacrificial placeholder 52 is respectively greater than the width of the source / drain region 56-1 grown thereon, as shown in the y-1 cross section ( Fig. 10A). The epitaxial growth of the source / drain regions 56-1, 56-2 is timed to control the height and width dimensions. As is known in the art, dopants can be introduced in situ using appropriate precursors. "In situ" refers to the introduction of dopants that determine the conductivity type of the doped layer during a process step (e.g., epitaxial deposition) to form the doped layer. As used herein, the term "conductivity type" indicates that the dopant region is p-type or n-type. As used herein, "p-type" refers to the addition of impurities to an intrinsic semiconductor, which creates a defect in valence electrons. In silicon-containing substrates, examples of p-type dopants, i.e., impurities, include, but are not limited to: boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In silicon-containing substrates, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. Exemplary epitaxial growth processes suitable for forming silicon and / or silicon germanium epitaxy include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Figure 1 , the nFET region includes transistors with n-type source / drain regions, while the pFET region includes p-type source / drain regions. The source / drain regions of the nanosheet device are usually grown before the RMG process.

[0086] An interlayer dielectric (ILD) layer 58 is deposited on the source / drain regions using a deposition technique including, but not necessarily limited to, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), radio frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD) and / or liquid source mist chemical deposition (LSMCD), spin coating, sputtering and / or electroplating. The ILD layer may include, but is not necessarily limited to, a low-k material (e.g., k less than about 4.0), such as porous silicates, carbon-doped oxides, silicon dioxide, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and porous variants thereof, silsesquioxanes, siloxanes, or other dielectric materials having, for example, a dielectric constant of about 2 to about 4. Such dielectric films may be deposited using PECVD. In some embodiments, the ILD layer may include an ultra-low-k (ULK) dielectric material having a dielectric constant of 2.5 or less. In some embodiments, the ILD layer includes a plurality of layers. The resulting structure is planarized using CMP or other suitable techniques to remove excess ILD material and remove hard mask 32. Fig. 10A , Fig. 10B and Fig. 10C The structure 100 is schematically shown in FIG.

[0087] The sacrificial gate layer 22 is removed from the structure 100. The silicon germanium layer 26' is then selectively removed, leaving a stack of silicon (channel) layers 21 separated by spacers (not shown). In some embodiments, hydrogen chloride gas is used to selectively remove the silicon germanium, leaving substantially intact silicon nanosheets. Alternatively, a wet etching process containing ammonia and hydroperoxide can be used to selectively etch SiGe relative to other materials. The gate stack 62 is formed in an adjacent relationship to the nanosheet (channel) layer 21. The gate dielectric layer forms part of the gate stack, which replaces the sacrificial silicon germanium layer. The gate stack is adjacent to the silicon nanosheet channel layer 21, and non-limiting examples of suitable materials for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k gate dielectric materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials may also include dopants such as lanthanum and aluminum. The gate dielectric layer may be formed by an appropriate deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the gate dielectric material may vary depending on the deposition process and the composition and amount of the high-k dielectric material used. In an exemplary embodiment, a high-k dielectric layer having a thickness of 2.5 nm is used. In some embodiments, the gate dielectric layer includes a plurality of dielectric layers.

[0088] The conductive gate material is deposited in the space previously filled by the silicon germanium nanosheet layer 26'. The deposited metal gate material forms the metal gate of the nanosheet field effect transistor of the resulting structure 110. In some embodiments, the conductive gate includes a work function metal (WFM) layer. The WFM has a dual purpose: Vt setting and gate conductor. Non-limiting examples of suitable work function metals include p-type work function metal materials and n-type work function metal materials. P-type work function materials include components such as ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, titanium nitride or any combination thereof. N-type metal materials include, for example, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide and aluminum carbide), aluminides or any combination thereof. The work function metal can be deposited by a suitable deposition process (e.g., a conformal ALD process).

[0089] In one exemplary embodiment, an n-type WFM layer having a thickness of three nanometers (3 nm) may be formed on the gate dielectric layer. The thickness of the WFM layer may, for example, be in the range of two to ten nanometers (2-10 nm), with thinner layers being used as device size decreases. The n-type WFM layer is used in conjunction with an n-type transistor. The portion of the n-type WFM layer that may also be deposited in the pFET region may be replaced later in the process accordingly. The n-type WFM layer and the gate dielectric may fill the space between the silicon channel layer 21 and the area previously occupied by the sacrificial gate 22.

[0090] The n-type WFM layer in the nFET region may be protected by a patterned OPL (not shown). The exposed portion of the n-type WFM layer in the pFET region is removed, leaving an open space between the silicon channel layer 21 in the pFET region. Thus, the gate metal is removed from the pFET region while the protected nFET region remains intact. SC1 etching or other suitable etching processes may be used to selectively remove the gate metal while leaving the gate dielectric layer substantially intact. The etching duration sufficient to allow all gate metal to be removed from the pFET region does not affect the gate metal in the nFET region. After the initially deposited n-type WFM layer is removed from the pFET region, a new gate metal deemed suitable for a pFET transistor is deposited. In embodiments where the first deposited metal is n-type, a p-type WFM layer is deposited. It should be appreciated that in some alternative embodiments, the process may be reversed and n-type metal may be deposited after the p-type metal. Chemical mechanical planarization may be used to remove excess metal to complete the front-end process (FEOL) processing. Thus, a FEOL layer including FETs and possible other electronic devices (not shown) within the ILD layer 58 is provided. A gate cut region 67 ( Fig. 11B ) to separate the gates at the cell boundaries.

[0091] Reference again Fig.11A , Fig. 11B and Fig. 11C , forming front-side contacts in the middle of the line (MOL) process. Silicon-based devices typically include multiple interconnect metallization layers above the device (front-end process / FEOL) layer containing field effect transistors (FETs) and / or other electronic structures. FEOL processing includes high temperature steps for manipulating semiconductor conductivity. Middle of the line (MOL) processes include steps for making metal contacts of logic circuit components such as field effect transistors (FETs), resistors, diodes, and capacitors. MOL processing may include medium temperature steps for forming semiconductor-metal compounds (e.g., silicides, germanium silicides) for electrical contacts. Back-end of the line (BEOL) processing involves forming metal interconnects that connect the devices formed in the FEOL processing to form circuits and may include silicidation as discussed above with respect to MOL processing.

[0092] A first set of contacts 64-2 formed in the ILD layer 58 are electrically connected to the source / drain regions 56-2. A metal gate contact 66 formed during the MOL process is electrically connected to the gate stack 62. The top (front side) source / drain contacts 64-2 and gate contacts 66 may include conductive materials, including but not limited to, silicide layers such as Ti, Ni, NiPt, and metal adhesion layers such as TiN, TaN, and conductive metal fillers such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material, and combinations thereof. A metal silicide layer may be formed on the source / drain regions 64-2 by depositing a metal liner such as a titanium liner thereon before depositing the barrier layer and the metal fill layer. This titanium liner may be deposited using physical vapor deposition (PVD) and then annealed at a temperature between about two hundred degrees Celsius and eight hundred degrees Celsius to form a metal silicide.

[0093] The FEOL processing described above provides a device layer 75 having a front side and a back side. The device layer includes a FET including a channel region (silicon nanosheet channel layer 21 ), source / drain regions 56 - 1 , 56 - 2 , and a gate stack 62 , all embedded within an ILD layer 58 .

[0094] After MOL processing, metal interconnects are formed in one or more BEOL interconnect layers 68, which connect the devices in the FEOL (device) layer 75 to form a circuit. The BEOL interconnect layer is formed on the front side of the device layer 75, and the metal lines including the interconnects are sequentially deposited (e.g., M1, M2, M3, etc.) on the FEOL layer and include a dielectric layer. The interconnect wires in each metal line are electrically connected to the interconnect wires in other metal lines and are electrically connected to the devices in the FEOL (device) layer 75. BEOL processing typically includes low temperature steps for forming metal lines and preserving temperature-sensitive FEOL and MOL structures. BEOL processing involves forming an interconnect layer on the MOL layer. A chip can have multiple BEOL interconnect layers. Each interconnect layer with a wiring scheme is connected to another interconnect layer through vias. The wires and vias are in the dielectric layer, and one or more of the dielectric layers may include low-k materials.

[0095] A carrier wafer 72 is bonded to the resulting structure and abuts the BEOL layers 68. Fig.11A , Fig. 11B and Fig. 11C The illustrated monolithic structure 110 includes a FEOL (device) layer 75 including nFET and pFET transistors, a MOL layer including front side contacts 64 - 2 , 66 , a BEOL layer 68 electrically connected to the devices in the device layer, and a carrier wafer 72 .

[0096] The monolithic structure 110 is flipped over and the silicon substrate layer 24 is removed therefrom. Ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) may be used for such removal because of their high selectivity for silicon germanium. (As described above, the sacrificial placeholder 52 may include silicon germanium.) Fig. 12A , Fig. 12B and Fig. 12C A monolithic structure 120 is shown schematically.

[0097] A dielectric cap layer 74 is deposited on the back side of structure 120 and is planarized down to the top surface of sacrificial placeholder 52. In some embodiments, a silicon nitride cap layer is used. Thus, a structure such as Fig.13A , Fig. 13B and Fig. 13C The structure 130 schematically shown in FIG. 1 is then selectively removed from the sacrificial placeholder 52. A cavity 78 is formed above the source / drain region 56-1, thereby exposing its bottom, rear-side oriented surface 56-1'. The width of the cavity 78 exceeds the width of the cavity 78 as shown in the y-1 section ( Fig.14A ) and thus exposes portions of the ILD layer 58 on both sides of the source / drain region 56-1. Fig.14A , Fig. 14B and Fig. 14C An exemplary structure 140 resulting after removal of the sacrificial placeholder is shown.

[0098] Cavity 78 extends within ILD layer 58 to expose the sidewalls of source / drain region 56-1. A dry etch (e.g., reactive ion etch) may be used to form cavity extension 78'. The etch selectively removes a portion of ILD layer 58 without etching capping layer 74. The etch may be timed so that cavity extension 78' does not extend as deep as source / drain region 56-1 within ILD layer 58. Cavity 78 and cavity extension 78' form a recess that exposes the bottom surface (now facing the top) and sidewalls of source / drain region 56-1. A relatively large area of ​​source / drain region 56-1 is exposed for subsequent processing. A process such as Fig.15A , Fig. 15B and Fig. 15C An exemplary structure 150 is shown.

[0099] Backside contact metallization and metal cover removal are performed to obtain Fig.16A , Fig. 16B and Fig. 16CStructure 160 is schematically shown. The backside source / drain contacts 64-1 may or may not include the same metal / metal silicide used to form the frontside source / drain contacts 64-2, and the presence of the BEOL layers 68 at this stage of the process may preclude a high temperature thermal anneal. The relatively large contact area between the source / drain regions 56-1 and the backside source / drain contacts 64-1 helps mitigate potential contact resistance issues due to the absence of a high temperature thermal anneal during the backside metallization process. Each backside source / drain contact 64-1 has a width CD that is greater than the width CD of the bottom surface (the "bottom" surface is now on top after the wafer is flipped) of the corresponding source / drain region 56-1, as shown in FIG. Fig.16A During the FEOL processing stage, the backside source / drain contact 64-1 extends within the ILD layer 58 deposited on the source / drain regions 56-1, 56-2. Therefore, part of the backside source / drain contact 64-1 is located between the ILD layer 58 and the sidewalls of the source / drain region 56-1.

[0100] A backside power rail 82 and a backside power delivery network (BSPDN) 84 are formed on the capping layer 74, and the backside power rail is electrically connected to one or more backside source / drain contacts 64-1. Fig.17A , Fig. 17B and Fig. 17C A monolithic structure 170 is schematically shown in FIG.

[0101] The monolithic structure 170 includes a device layer having a front side and a back side. The device layer includes an interlayer dielectric layer 58, a field effect transistor, and optionally other electronic devices. In an exemplary embodiment, the field effect transistor includes a channel region, which includes a stacked semiconductor nanosheet layer 21. First and second source / drain regions 56-1, 56-2 extend laterally from each channel region. A back-end process layer 68 is located on the front side of the device layer and is electrically connected to the field effect transistor. A back-end contact 64-1 having a width greater than the bottom surface of the first source / drain region 56-1 extends from the back side of the device layer, the back-end contact being electrically connected to the first source / drain region 56-1 and contacting the first and second sidewall surfaces of the first source / drain region 56-1. The front side contact 64-2 connects the second source / drain region 56-2 to the BEOL layer 68. As shown Fig.17A As shown, a first portion 64-1 of the backside contact extends between the interlayer dielectric layer 58 and the first sidewall surface of the first source / drain region 56-1, and a second portion of the backside contact extends between the interlayer dielectric layer 58 and the second sidewall surface of the first source / drain region 56-1. Thus, a relatively large contact area is formed between the backside contact 64-1 and the first source / drain region. The backside contact is electrically connected to a power rail (e.g., a VDD rail), which in turn is electrically connected to the BSPDN 84.

[0102] The accompanying drawings as described above depict exemplary processing steps / stages in the manufacture of exemplary structures. Although the entire manufacturing method and the structure formed thereby are completely novel, some of the individual processing steps required to implement the method can utilize traditional semiconductor manufacturing techniques and traditional semiconductor manufacturing tools. These techniques and tools are already familiar to those of ordinary skill in the relevant field given the teachings herein. In addition, in many easily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition (Silicon VLSI Technology: Basic Principles, Practice and Modeling 1st Edition), Prentice Hall, 2001, which are incorporated herein by reference. It is emphasized that although some individual processing steps are described herein, these steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives that will be applicable.

[0103] It should be understood that the various layers and / or regions shown in the drawings may not be drawn to scale. In addition, for ease of explanation, one or more semiconductor layers of the type commonly used in such integrated circuit devices or other layers may not be explicitly shown in a given figure. This does not mean that semiconductor layers or other layers not explicitly shown are omitted in actual integrated circuit devices.

[0104] At least a portion of the above techniques can be implemented in an integrated circuit. In forming an integrated circuit, identical bare chips are typically fabricated in a repeating pattern on the surface of a semiconductor wafer. Each die includes the devices described herein and may include other structures and / or circuits. Individual dies are cut or sliced ​​from the wafer and then packaged as an integrated circuit. Those skilled in the art will know how to cut wafers and package dies to produce an integrated circuit.

[0105] Those skilled in the art will appreciate that the exemplary structures described above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips) as bare chips, distributed in a packaged form, or incorporated as part of an intermediate or final product that benefits from having, for example, FET devices and contacts formed in accordance with one or more exemplary embodiments.

[0106] There are many techniques used by those skilled in the art to remove materials at various stages of creating semiconductor structures. As used herein, these processes are generally referred to as "etching". For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, which are all known techniques for removing selected materials when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are readily understood by those skilled in the art, and therefore, a more detailed description of these processes is not provided herein.

[0107] The descriptions of the embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all elements and features of the devices and systems that may utilize the circuits and techniques described herein. Based on the teachings herein, many other embodiments will become apparent to those skilled in the art; other embodiments are utilized and derived therefrom so that structural and logical substitutions and changes can be made without departing from the scope of the present invention. It should also be noted that in some alternative implementations, some steps of the exemplary method may not occur in the order shown in the figures. For example, two steps shown in succession may actually be performed substantially simultaneously, or certain steps may sometimes be performed in the opposite order, depending on the functions involved. The drawings are also merely representative and are not drawn to scale. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0108] In this document, if more than one embodiment is actually shown, the embodiments may be referred to individually and / or collectively as the term "embodiment", which is merely for convenience and is not intended to limit the scope of the present application to any single embodiment or inventive concept. Therefore, although specific embodiments have been shown and described herein, it should be understood that arrangements that achieve the same purpose may replace the specific embodiment(s) shown. Combinations of the above embodiments and other embodiments not specifically described herein will become apparent to those skilled in the art under the teachings of this document.

[0109] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "include" and / or "comprise" when used in this specification specify the presence of stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof. Terms such as "above" and "below" and "vertical" are used to indicate the relative positioning of elements or structures relative to each other, in contrast to relative height. If the layer of a structure is described herein as being "above" another layer, it will be understood that there may or may not be an intermediate element or layer between two specified layers. If a layer is described as "directly on another layer", direct contact of the two layers is indicated.

[0110] The corresponding structures, materials, actions, and equivalents of any means or step plus function elements in the following claims are intended to include any structure, material, or action for performing a function in combination with other claimed elements as specifically claimed. Descriptions of various embodiments have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments are selected and described in order to best explain the principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications that are suitable for the specific purposes contemplated.

[0111] The Abstract is provided to comply with 37 CFR § 1.72(b). It should be understood that it is not used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that in order to make the disclosure flow, various features are grouped together in a single embodiment. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than those expressly recited in each claim. On the contrary, as reflected in the appended claims, the claimed subject matter may lie in less than all the features of a single embodiment. Therefore, the following claims are hereby incorporated into the Detailed Description, with each claim independently serving as a separately claimed subject matter.

[0112] Given the teachings provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of the technology and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.

[0113] In a preferred embodiment of the invention described herein, a monolithic semiconductor structure is provided, comprising: a device layer including a front side and a back side, the device layer including: an nFET region including an nFET transistor; a pFET region including a pFET transistor; and an inter-level dielectric layer, the nFET transistor and the pFET transistor being located within the inter-level dielectric layer; a back-end process interconnect layer over the front side of the device layer, the back-end process interconnect layer being electrically connected to one or more of the nFET transistor and the pFET transistor; one or more back-side contacts extending from the back side of the device layer, each of the one or more back-side contacts being electrically connected to a first source / drain region of one of the nFET transistor and the pFET transistor, respectively, each of the one or more back-side contacts having a width greater than a bottom surface of the first source / drain region and contacting a first sidewall surface and a second sidewall surface of the first source / drain region. Preferably, a first portion of each back-side contact extends between the inter-level dielectric layer and a first sidewall surface of the first source / drain region of one of the nFET transistor and the pFET transistor, respectively, and a second portion of each back-side contact extends between the inter-level dielectric layer and a second sidewall surface of the first source / drain region of one of the nFET transistor and the pFET transistor, respectively. Preferably, the structure further comprises front-side contacts electrically connecting a plurality of nFET transistors and pFET transistors to a back-end process interconnect layer. Preferably, the structure further comprises one or more power rails over the back-end of the device layer and electrically connected to the one or more back-end contacts. Preferably, each of the nFET transistors and pFET transistors comprises a channel region comprising a stack of nanosheet semiconductor layers. Preferably, the structure further comprises: an oxide layer on the back-end of the device layer; and a dielectric capping layer on the oxide layer, one or more back-end contacts extending through the oxide layer and the dielectric capping layer. Preferably, the structure further comprises a plurality of front-side contacts extending through the interlayer dielectric layer and electrically connecting one or more of the nFET transistors and pFET transistors to the back-end process layer. Preferably, each of the nFET transistors and pFET transistors comprises a gate metal, further comprising a gate contact electrically connecting the gate metal to the back-end process layer.

Claims

1. A monolithic semiconductor structure comprising: A device layer having a front side and a back side, the device layer comprising: an interlayer dielectric layer; and A field effect transistor, the field effect transistor comprising a channel region and a first source / drain region and a second source / drain region in the interlayer dielectric layer, the first source / drain region and the second source / drain region extending laterally from the channel region; a back-end process interconnect layer over the front side of the device layer; A backside contact having a width greater than a bottom surface of the first source / drain region and extending from the backside of the device layer, the backside contact being electrically connected to the first source / drain region and contacting a first sidewall surface and a second sidewall surface of the first source / drain region.

2. A monolithic semiconductor structure according to claim 1, wherein a first portion of the backside contact extends between the interlayer dielectric layer and the first sidewall surface of the first source / drain region, and a second portion of the backside contact extends between the interlayer dielectric layer and the second sidewall surface of the first source / drain region. 3 . The monolithic semiconductor structure of claim 2 , further comprising a front side contact electrically connecting the second source / drain region and the back end process interconnect layer. 4 . The monolithic semiconductor structure of claim 3 , further comprising a power rail over the back side of the device layer and electrically connected to the back side contact.

5. The monolithic semiconductor structure of claim 3, wherein the channel region comprises a stack of nanosheet semiconductor layers.

6. The monolithic semiconductor structure of claim 5, further comprising: an oxide layer on the back side of the device layer; as well as A dielectric cap layer is on the oxide layer, the backside contact extending through the oxide layer and the dielectric cap layer. 7 . The monolithic semiconductor structure of claim 5 , further comprising a front side contact extending through the interlayer dielectric layer and electrically connecting a front surface of the second source / drain region to the back end process interconnect layer.

8. The monolithic semiconductor structure of claim 7, wherein the field effect transistor further comprises a gate metal, the monolithic semiconductor structure further comprising a gate contact, the gate contact electrically connecting the gate metal to the back-end process interconnect layer.

9. A method of manufacturing a semiconductor structure including a backside contact, comprising: forming a sacrificial placeholder within the substrate; forming a device layer having a front side and a back side over the substrate, the device layer comprising an interlayer dielectric layer, a semiconductor channel region, and a first source / drain region and a second source / drain region within the interlayer dielectric layer and extending laterally from the semiconductor channel region, the first source / drain region and a portion of the interlayer dielectric layer adjacent to the first source / drain region being formed directly on the sacrificial placeholder; forming a back-end process interconnect layer over the front side of the device layer; removing the sacrificial placeholder to expose a bottom surface of the first source / drain region and a portion of the interlayer dielectric layer adjacent to the first source / drain region; forming a recess in the interlayer dielectric layer to expose a first sidewall and a second sidewall of the first source / drain region; as well as A backside contact is formed over the bottom surface of the first source / drain region, the first sidewall, and the second sidewall and extends from the backside of the device layer.

10. The method of claim 9, wherein the substrate comprises a semiconductor layer, the method further comprising: removing the semiconductor substrate; forming a backside dielectric layer over the backside of the device layer; Wherein removing the sacrificial placeholder forms a cavity extending through the backside dielectric layer, the cavity having a width greater than the bottom surface of the first source / drain region.

11. The method according to claim 9, further comprising: A carrier wafer is bonded to the back end process interconnect layer prior to removing the semiconductor substrate.

12. The method according to claim 9, further comprising: A gate stack is formed within the device layer, the gate stack adjoining the channel region.

13. The method of claim 9, wherein the channel region comprises a stack of nanosheet semiconductor layers.

14. The method of claim 9, further comprising forming a backside power rail electrically connected to the backside contact.

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