Deposition mask and method for manufacturing a deposition mask

Abstract

The invention relates to a deposition mask and a method for manufacturing the deposition mask. According to an embodiment, a method for manufacturing a deposition mask may include: forming an inorganic film pattern on a silicon substrate; depositing a metal layer on the inorganic film pattern and the opening of the inorganic film pattern; etching a portion of the metal layer deposited on the opening of the inorganic film pattern; depositing a protective layer on the inorganic film pattern and the opening of the inorganic film pattern; removing a portion in the cell region of the silicon substrate and the inorganic film pattern disposed in the cell region; and removing the protective layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0128857 filed in the Korean Intellectual Property Office on September 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a deposition mask and a method for manufacturing the deposition mask. Background Art

[0004] Wearable devices that have the form of glasses or helmets and form a focal point in front of the user's eyes at a distance close to the user's eyes have now been developed. For example, the wearable device may be a head-mounted display (HMD) device or augmented reality (AR) glasses. Such a wearable device provides an augmented reality (hereinafter referred to as "AR") screen or a virtual reality (hereinafter referred to as "VR") screen to the user.

[0005] Wearable devices such as HMD devices or AR glasses use a display specification of at least 2000 PPI (pixels per inch) so that users can use the wearable device for a long time without dizziness. For this reason, organic light emitting diode on silicon (OLEDoS) technology has emerged as a small organic light emitting display device with high resolution. Organic light emitting diode on silicon (OLEDoS) technology is a technology for providing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided.

[0006] In order to achieve a high resolution of 2000 PPI or more, a high-resolution deposition mask is used. To this end, a silicon mask that can be formed with the precision of a semiconductor process has been studied and developed. A silicon mask is a mask that allows an inorganic film pattern deposited and formed on a silicon substrate to be used as a mask film. However, such a silicon mask may have a problem of being damaged when the mask is cleaned due to the small thickness of the mask film. Summary of the invention

[0007] Aspects of embodiments of the present disclosure provide a deposition mask and a method for manufacturing the deposition mask capable of increasing the rigidity of a mask film and easily adjusting the thickness of the mask by forming the mask film using a metal.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a deposition mask may include: forming an inorganic film pattern on a silicon substrate; depositing a metal layer on the inorganic film pattern and an opening of the inorganic film pattern; etching a portion of the metal layer deposited on the opening of the inorganic film pattern; depositing a protective layer on the inorganic film pattern and the opening of the inorganic film pattern; removing a portion of a unit area of ​​the silicon substrate and the inorganic film pattern disposed in the unit area; and removing the protective layer.

[0009] The silicon substrate may include a plurality of cell regions and a mask frame region excluding the plurality of cell regions, and the mask frame region may include a mask lip region separating the plurality of cell regions and an outer frame region disposed at an outermost portion of the silicon substrate.

[0010] Forming the inorganic film pattern may include forming the inorganic film pattern in each unit region of the silicon substrate.

[0011] Depositing the metal layer may include depositing a first metal layer including a first metal and depositing a second metal layer including a second metal on the first metal layer.

[0012] The first metal may include at least one selected from vanadium (V), tantalum (Ta), and niobium (Nb).

[0013] The second metal may include titanium nitride (TiN).

[0014] Depositing the metal layer may include a sputtering process.

[0015] Removing the portion of the silicon substrate in the cell region and the inorganic film pattern disposed in the cell region may include forming a mask film in which only the metal layer remains by removing the inorganic film pattern from a structure in which the metal layer is stacked on the inorganic film pattern.

[0016] The cross-section of the mask film may have an inverse tapered shape whose width increases from a bottom surface toward an upward direction.

[0017] The cross section of the mask film may have a bowl shape in which a space where the inorganic film pattern is removed is surrounded by the metal layer and is open in an upward direction, and the upward direction is a direction from the deposition mask toward the substrate to be deposited.

[0018] The inorganic film pattern may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of.

[0019] Etching the portion of the metal layer deposited on the opening of the inorganic film pattern may include dry-etching the portion of the metal layer.

[0020] The protective layer may be an organic film including at least one selected from acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0021] Removing the portion of the silicon substrate in the cell region and the inorganic film pattern disposed in the cell region may include wet-etching a portion of the silicon substrate.

[0022] According to an embodiment of the present disclosure, a deposition mask may include: a silicon substrate including a plurality of unit areas and a mask frame area other than the plurality of unit areas, the mask frame area including a mask lip area separating the plurality of unit areas and an outer frame area disposed at the outermost portion of the silicon substrate; and a mask film disposed in each unit area and including a metal layer. The cross section of the mask film may have a bowl shape in which a space opened in an upward direction is surrounded by a metal layer in a lateral direction and a downward direction.

[0023] The cross section of the mask film may have a bowl shape in which a space is open in an upward direction, and the upward direction is a direction from the deposition mask toward the substrate to be deposited.

[0024] The cross-section of the mask film may have an inverse tapered shape whose width increases from a bottom surface toward an upward direction.

[0025] The metal layer may include a first metal layer including a first metal and a second metal layer covering the first metal layer in a downward direction and including a second metal.

[0026] The first metal may include at least one selected from vanadium (V), tantalum (Ta), and niobium (Nb).

[0027] The second metal may include titanium nitride (TiN).

[0028] According to the method for manufacturing a deposition mask, by forming a mask film using a metal, the rigidity of the mask film can be increased and the thickness of the mask can be easily adjusted.

[0029] In some embodiments, by allowing the mask film to have an inverse tapered shape, shadow defects may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of embodiments of the present disclosure will become more apparent by describing example embodiments in more detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a perspective view showing a head mounted display device according to an example embodiment;

[0032] Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head mounted display device;

[0033] Figure 3 is a perspective view showing a head mounted display device according to an example embodiment;

[0034] Figure 4 is an exploded perspective view showing a display device according to an example embodiment;

[0035] Figure 5 is a cross-sectional view showing an example of cutting off a portion of a display panel according to an example embodiment;

[0036] Figure 6 is a perspective view of a mask according to an example embodiment;

[0037] Figure 7 is a schematic plan view of a mask according to an example embodiment;

[0038] Figure 8 is a flow chart illustrating a method for manufacturing a mask according to an exemplary embodiment;

[0039] Figures 9 to 14 are cross-sectional views illustrating processes of a method for manufacturing a mask according to example embodiments;

[0040] Fig.15 is a schematic cross-sectional view of a mask according to an example embodiment; and

[0041] Fig.16 is a view illustrating a concept of a shadow area of ​​a mask according to example embodiments. DETAILED DESCRIPTION

[0042] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, in which example embodiments of the present disclosure are shown. However, the subject matter of the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0043] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the spirit or scope of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0045] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other, and may interact or interconnect with each other in different technical aspects, and the various embodiments may be implemented independently of each other, or may be implemented together in association with each other.

[0046] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0047] Figure 1 is a perspective view illustrating a head mounted display device according to an example embodiment. Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head-mounted display device.

[0048] refer to Figure 1 and Figure 2 According to the example embodiment, the head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device housing portion 110, a housing portion cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted band 140, a middle frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0049] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the one to be referred to. Figure 4 and Figure 5 Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to as Figure 4 and Figure 5 Provide a description instead.

[0050] The first optical member 151 may be between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0051] The middle frame 160 may be between the first display device 10_1 and the control circuit board 170 and between the second display device 10_2 and the control circuit board 170. The middle frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0052] The control circuit board 170 may be between the middle frame 160 and the display device housing portion 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data and transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0053] The control circuit board 170 may send digital video data corresponding to a left eye image suitable for the user's left eye or an optimized left eye image to the first display device 10_1, and send digital video data corresponding to a right eye image suitable for the user's right eye or an optimized right eye image to the second display device 10_2. In some embodiments, the control circuit board 170 may send the same digital video data to the first display device 10_1 and the second display device 10_2.

[0054] The display device housing portion 110 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170 and the connector. The housing portion cover 120 is provided to cover the opening surface (e.g., the exposed surface) of the display device housing portion 110. The housing portion cover 120 may include a first eyepiece 131 corresponding to the left eye of the user and a second eyepiece 132 corresponding to the right eye of the user. Figure 1 and Figure 2 It has been shown in FIG. 1 that the first eyepiece 131 and the second eyepiece 132 are provided separately, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into one eyepiece.

[0055] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 151 through the first eyepiece 131, and view the image of the second display device 10_2 magnified as a virtual image by the second optical member 152 through the second eyepiece 132.

[0056] The head-mounted strap 140 is used to fix the display device housing portion 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing portion cover 120 can be maintained in a state where they correspond to the left eye and the right eye of the user, respectively. When the display device housing portion 110 is implemented to have a light weight and a small size, the head-mounted display device 1 may include a Figure 3 , rather than the headband 140 .

[0057] In some embodiments, the head mounted display device 1 may further include a battery for providing power, an external memory slot for accommodating an external memory (e.g., an external memory card or an external storage device), an external connection port, and a wireless communication module for receiving an image source. The external connection port may include a universal serial bus (USB) terminal, a display port, and / or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may include a 5G communication module, a 4G communication module, a wireless fidelity (WiFi) module, and / or a Bluetooth module.

[0058] Figure 3 is a perspective view illustrating a head mounted display device according to an example embodiment.

[0059] refer to Figure 3 The head mounted display device 1_1 according to the example embodiment may be a glasses type display device in which the display device housing portion 120_1 is implemented as a light weight and small size. The head mounted display device 1_1 according to the example embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing portion 120_1.

[0060] Figure 3 The display device 10_3 shown in FIG. 1 is substantially the same as that to be referred to in Figure 4 and Figure 5 Therefore, the description of the display device 10_3 will be referred to as Figure 4 and Figure 5 Provide a description instead.

[0061] The display device housing portion 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. An image displayed on the display device 10_3 may be enlarged by the optical member 320, converted in an optical path by the optical path conversion member 330, and provided to the right eye of the user through the right eye lens 312. For this reason, the user may view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 312 are combined with each other through his / her right eye.

[0062] exist Figure 33 has shown that the display device housing portion 120_1 is disposed at the right end of the support frame 350, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the display device housing portion 120_1 may be disposed at the left end of the support frame 350, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. In some embodiments, the display device housing portion 120_1 may be disposed at both the left and right ends of the support frame 350, and in this case, the user may view the image displayed on the display device 10_3 through both his / her left eye and right eye.

[0063] Figure 4 is an exploded perspective view illustrating a display device according to an example embodiment.

[0064] refer to Figure 4 , the display device 10 according to the example embodiment is a device for displaying a moving image or a still image. The display device 10 according to the example embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit for a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IOT) device. In some embodiments, the display device 10 can be applied to a smart watch, a watch phone, and / or a head-mounted display (HMD) for realizing virtual reality and / or augmented reality.

[0065] The display device 10 according to the exemplary embodiment includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0066] In a plan view, the display panel 410 may have a shape similar to a rectangular shape. For example, in a plan view, the display panel 410 may have a shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 410, the corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a set or predetermined curvature, or may form a right angle. The shape of the display panel 410 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10 in a plan view may follow the shape of the display panel 410 in a plan view, but embodiments of the present disclosure are not limited thereto.

[0067] The display panel 410 includes a display area where an image is displayed and a non-display area where no image is displayed.

[0068] The display area includes a plurality of pixels, each of which includes a plurality of sub-pixels SP1, SP2 and SP3 (see Figure 5 ). The plurality of sub-pixels SP1, SP2, and SP3 include a plurality of pixel transistors. The plurality of pixel transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 5 ). For example, a plurality of pixel transistors may be formed as a complementary metal oxide semiconductor (CMOS).

[0069] The heat dissipation layer 420 may overlap the display panel 410 in a third direction DR3, which is a thickness direction of the display panel 410. The heat dissipation layer 420 may be on one surface (e.g., a rear surface) of the display panel 410. The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include a metal layer such as graphite, silver (Ag), copper (Cu), and / or aluminum (Al) having high thermal conductivity.

[0070] The circuit board 430 may be electrically connected to the plurality of pads of the pad area of ​​the display panel 410 using a conductive adhesive member such as an anisotropic conductive film (eg, a conductive adhesive member). The circuit board 430 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 4 4 shows that the circuit board 430 is not bent, but the circuit board 430 may be bent. In some embodiments, one end of the circuit board 430 may be on the rear surface of the display panel 410. The one end of the circuit board 430 may be an end opposite to the other end of the plurality of pads of the pad area of ​​the circuit board 430 connected to the display panel 410 using a conductive adhesive member.

[0071] The driving circuit 440 may receive digital video data and a timing signal from the outside, and may generate a scanning timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signal.

[0072] The power circuit 450 may generate a plurality of panel driving voltages according to an external source voltage.

[0073] Each of the driving circuit 440 and the power supply circuit 450 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 430 .

[0074] Figure 5 is a cross-sectional view showing an example of cutting off a portion of a display panel according to an example embodiment. For example, Figure 5 The diagram includes a plurality of sub-pixels SP1, SP2 and SP3 (see Figure 5 )'s partial cross-sectional structure of the display area.

[0075] refer to Figure 5 The display panel 410 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL including a cover layer CVL, and a polarizing plate.

[0076] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively.

[0077] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions may be provided in the upper surface of the semiconductor substrate SSUB. The plurality of well regions may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. In some embodiments, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0078] Each of the plurality of well regions includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH between the source region SA and the drain region DA.

[0079] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be on one side of the gate electrode GE, and the drain region DA may be on the other side of the gate electrode GE.

[0080] Each of the plurality of well regions further includes a first low-concentration impurity region between the channel region CH and the source region SA and a second low-concentration impurity region between the channel region CH and the drain region DA. The first low-concentration impurity region may be a region having a lower impurity concentration than the source region SA. The second low-concentration impurity region may be a region having a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, and thus perforation and hot carrier phenomena caused by a short channel may be prevented (or the likelihood of their occurrence may be reduced).

[0081] The first semiconductor insulating film SINS1 may be formed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed based on silicon carbon nitride (SiCN) and / or silicon oxide (SiOx ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0082] The second semiconductor insulating film SINS2 may be formed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be formed based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0083] A plurality of contact terminals CTE may be on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA selected from each of the pixel transistors PTR through a hole passing through the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy thereof.

[0084] The third semiconductor insulating film SINS3 may be formed on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0085] The semiconductor substrate SSUB may be replaced with a glass substrate and / or a polymer resin substrate such as a polyimide substrate. In some embodiments, the thin film transistor may be on a glass substrate and / or a polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent and / or curved.

[0086] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In some embodiments, the light emitting element back plate EBP includes a plurality of interlayer insulating films INS1 to INS10 between the first to eighth metal layers ML1 to ML8, respectively.

[0087] The first to eighth metal layers ML1 to ML8 are used to implement a circuit of the first sub-pixel SP1 by connecting a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to one another.

[0088] The first interlayer insulating film INS1 may be on the semiconductor backplane SBP. Each of the first vias VA1 may pass through the first interlayer insulating film INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be on the first interlayer insulating film INS1 and connected to the first vias VA1.

[0089] The second interlayer insulating film INS2 may be on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may pass through the second interlayer insulating film INS2 to be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be on the second interlayer insulating film INS2 and connected to the second vias VA2.

[0090] The third interlayer insulating film INS3 may be on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may pass through the third interlayer insulating film INS3 to be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be on the third interlayer insulating film INS3 and connected to the third vias VA3.

[0091] The fourth interlayer insulating film INS4 may be on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may pass through the fourth interlayer insulating film INS4 to be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be on the fourth interlayer insulating film INS4 and connected to the fourth vias VA4.

[0092] The fifth interlayer insulating film INS5 may be on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may pass through the fifth interlayer insulating film INS5 to be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be on the fifth interlayer insulating film INS5 and connected to the fifth vias VA5.

[0093] The sixth interlayer insulating film INS6 may be on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may pass through the sixth interlayer insulating film INS6 to be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be on the sixth interlayer insulating film INS6 and connected to the sixth vias VA6.

[0094] The seventh interlayer insulating film INS7 may be on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may pass through the seventh interlayer insulating film INS7 to be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be on the seventh interlayer insulating film INS7 and connected to the seventh vias VA7.

[0095] The eighth interlayer insulating film INS8 may be on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may pass through the eighth interlayer insulating film INS8 to be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be on the eighth interlayer insulating film INS8 and connected to the eighth vias VA8.

[0096] The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be made of substantially the same material. Each of the first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) and / or an alloy thereof. The first through hole VA1 to the eighth through hole VA8 may be made of substantially the same material. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed as a silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0097] Each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than each of the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same as each other.

[0098] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. Each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be greater than each of the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other.

[0099] The ninth interlayer insulating film INS9 may be on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0100] Each of the ninth via holes VA9 may pass through the ninth interlayer insulating film INS9 to be connected to the exposed eighth metal layer ML8. Each of the ninth via holes VA9 may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy thereof.

[0101] Each of the first reflective electrodes RL1 may be on the ninth interlayer insulating film INS9 and connected to the ninth via VA9. Each of the first reflective electrodes RL1 may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy thereof.

[0102] Each of the second reflective electrodes RL2 may be on the first reflective electrode RL1. Each of the second reflective electrodes RL2 may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy thereof. For example, each of the second reflective electrodes RL2 may be made of titanium nitride (TiN).

[0103] In the first sub-pixel SP1, the step layer STPL may be on the second reflective electrode RL2. The step layer STPL may not be provided in each of the second sub-pixel SP2 and the third sub-pixel SP3. The step layer STPL may be formed based on silicon carbon nitride (SiCN) and / or silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0104] In the first subpixel SP1, the third reflective electrode RL3 may be on the second reflective electrode RL2 and the step layer STPL. In the second subpixel SP2 and the third subpixel SP3, the third reflective electrode RL3 may be on the second reflective electrode RL2. Each of the third reflective electrodes RL3 may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy thereof.

[0105] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0106] Each of the fourth reflective electrodes RL4 may be on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity so as to be advantageous or beneficial in reflecting light. Each of the fourth reflective electrodes RL4 may be made of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), silver (Ag), palladium (Pd), an APC alloy as an alloy of copper (Cu), and / or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but embodiments of the present disclosure are not limited thereto.

[0107] The tenth interlayer insulating film INS10 may be on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be formed based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0108] Each of the tenth through holes VA10 may pass through the tenth interlayer insulating film INS10 to be connected to the exposed fourth reflective electrode RL4. Each of the tenth through holes VA10 may be made of any one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy thereof. Due to the step layer STPL, the thickness of the tenth through hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth through hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0109] The light emitting element layer EML may be on the light emitting element backplane EBP and may include a pixel defining film PDL and light emitting elements each including a first electrode AND, an intermediate layer IL (eg, including first, second and third intermediate layers IL1, IL2 and IL3), and a second electrode CAT.

[0110] The first electrode AND of each of the light emitting elements may be on the tenth interlayer insulating film INS10 and connected to the tenth through hole VA10. The first electrode AND of each of the light emitting elements may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth through hole VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first through hole VA1 to the ninth through hole VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the first electrode AND of each of the light emitting elements may be made of titanium nitride (TiN).

[0111] The pixel defining film PDL may be on a partial area of ​​the first electrode AND of each of the light emitting elements. The pixel defining film PDL may cover the edge of the first electrode AND of each of the light emitting elements. The pixel defining film PDL is used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0112] The first emission area EA1 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0113] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be on the edge of the first electrode AND of each of the light emitting elements, the second pixel definition film PDL2 may be on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be formed based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0114] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0115] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0116] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are stacked in sequence. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are stacked in sequence. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are stacked in sequence.

[0117] The intermediate layer IL may cover the first electrode AND at the opening of the pixel defining film PDL and cover the pixel defining film PDL between the sub-pixels SP1 , SP2 , and SP3 disposed adjacent to each other, and may be partially disconnected.

[0118] In an example embodiment, by disconnecting the intermediate layer IL between adjacent sub-pixels SP1, SP2, and SP3, leakage current between adjacent sub-pixels SP1, SP2, and SP3 can be prevented or reduced, and a color interference phenomenon can be prevented (or the possibility of its occurrence is reduced). The color interference phenomenon refers, for example, to a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is unintentionally turned on while the blue sub-pixel emits blue light. The color interference phenomenon occurs due to leakage current, and may occur when a blue sub-pixel and a red sub-pixel having a large difference in voltage for driving the pixel are adjacent to each other. For example, leakage current is a phenomenon in which a portion of the driving current is transferred to the red sub-pixel through at least some conductive layers (e.g., conductive layers) of the intermediate layer IL while the driving current is provided to the light-emitting element of the blue sub-pixel to turn on the blue sub-pixel. When leakage current occurs, the red sub-pixel may be unintentionally turned on while the blue sub-pixel is turned on.

[0119] The number of the intermediate layers IL1, IL2, and IL3 emitting different lights is not limited to Figure 5 . For example, the intermediate layer IL may include two intermediate layers. In some embodiments, any one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In some embodiments, a charge generation layer that provides electrons to any one intermediate layer and provides charges to the other intermediate layer may be between the two intermediate layers.

[0120] Already in Figure 5 , it is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the embodiments of the present disclosure are not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first emission area EA1, and may not be disposed in the second emission area EA2 and the third emission area EA3. In some embodiments, the second intermediate layer IL2 may be disposed in the second emission area EA2, and may not be disposed in the first emission area EA1 and the third emission area EA3. In some embodiments, the third intermediate layer IL3 may be disposed in the third emission area EA3, and may not be disposed in the first emission area EA1 and the second emission area EA2. In some embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0121] The second electrode CAT may be on the third intermediate layer IL3. The second electrode CAT may be on the third pixel defining film PDL3 in each of the plurality of grooves formed between the sub-pixels. The second electrode CAT may be made of a transparent conductive material (TCO) capable of transmitting light such as ITO and / or indium zinc oxide (IZO) or a semi-transmissive conductive material (e.g., a semi-transmissive conductive material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is made of a semi-transmissive conductive material, the emission efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be increased by the microcavity.

[0122] The encapsulation layer TFE may be on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic film to prevent or reduce oxygen and / or moisture from penetrating into the light emitting element layer EML. In some embodiments, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0123] The first encapsulation inorganic film TFE1 may be on the second electrode CAT, the encapsulation organic film TFE2 may be on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed of a material selected from silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layer. The encapsulated organic film TFE2 may be made of a monomer. In some embodiments, the encapsulated organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and / or the like.

[0124] The adhesive layer ADL may be a layer that bonds the encapsulation layer TFE and the optical layer OPL to each other. The adhesive layer ADL may be a double-sided adhesive member. In some embodiments, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive and / or a transparent adhesive resin.

[0125] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be on the adhesive layer ADL.

[0126] The first color filter CF1 may overlap with the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light of a blue wavelength band). The blue wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0127] The second color filter CF2 may overlap with the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color (e.g., light of a green wavelength band). The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second emission area EA2.

[0128] The third color filter CF3 may overlap with the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color (e.g., light of a red wavelength band). The red wavelength band may be approximately 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0129] Each of the plurality of lenses LNS may be on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing a ratio of light guided to the front surface of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0130] The filling layer FIL may be on the plurality of lenses LNS. The filling layer FIL may have a set or predetermined refractive index so that light propagates in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. In some embodiments, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and / or the like.

[0131] The covering layer CVL may be on the filling layer FIL. The covering layer CVL may be a glass substrate and / or a polymer resin such as resin. When the covering layer CVL is a glass substrate, the covering layer CVL may be attached to the filling layer FIL. In some embodiments, the filling layer FIL may be used to adhere the covering layer CVL. When the covering layer CVL is a glass substrate, the covering layer CVL may be used as a packaging substrate. When the covering layer CVL is a polymer resin such as resin, the covering layer CVL may be directly applied to the filling layer FIL.

[0132] The polarizing plate may be on one surface of the cover layer CVL. The polarizing plate may be a structure that prevents or reduces degradation of visibility due to external light reflection. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the embodiments of the present disclosure are not limited thereto. However, when visibility due to external light reflection is appropriately or sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0133] Figure 6 is a perspective view of a mask according to example embodiments. Figure 7 is a schematic plan view of a mask according to example embodiments. Figure 6 1 is a perspective view showing a state in which one unit mask UM among a plurality of unit masks is separated. Figure 6 and Figure 7 The mask of the example embodiment shown in FIG. 1 can be used to deposit reference Figure 5 In the process of at least a portion of the intermediate layer IL of the display panel 410 described above, for example, the intermediate layer IL may be configured to emit light of a different color from each of the sub-pixels SP1, SP2, and SP3.

[0134] refer to Figure 6 and Figure 7 , the mask MK according to example embodiments may be a shadow mask in which the mask film MM is on the silicon substrate 700. The mask MK according to example embodiments may be referred to as a 'silicon mask'.

[0135] According to example embodiments, the mask MK may include a silicon substrate 700, and the mask film MM may be on the silicon substrate 700. The mask film MM may be disposed in cell regions 710 arranged in a matrix form, and each cell region 710 may be surrounded by a mask lip region 721. The mask lip region 721 may be a region in which a portion of the silicon substrate 700 may be disposed, and may be used to support the mask film MM.

[0136] The mask film MM may be a portion of the cell mask UM disposed in each of the plurality of cell regions 710. The mask film MM is formed of a metal layer 1010 (see Fig.10 The mask film MM includes a metal material and thus may be referred to as a “metal mask film MM”.

[0137] The silicon substrate 700 may include a plurality of cell regions 710 and a mask frame region 720 excluding the plurality of cell regions 710. The mask frame region 720 may include a mask lip region 721 surrounding the respective cell regions 710 and an outer frame region 722 disposed at the outermost portion of the silicon substrate 700. The mask frame MF may be disposed in the mask frame region 720 and may include a mask lip surrounding the cell regions 710.

[0138] The mask lip region 721 may be a region that separates the plurality of unit regions 710. For example, the plurality of unit regions 710 may be arranged in a matrix form, and the mask lip region 721 may be provided to surround the respective unit regions 710.

[0139] A cell opening COP and a unit mask UM masking at least a portion of the cell opening COP may be provided in each of the plurality of cell regions 710 of the silicon substrate 700 .

[0140] The plurality of cell openings COP may pass through the mask frame MF along a thickness direction (eg, third direction DR3) of the mask MK. The plurality of cell openings COP may be formed by etching a portion of the silicon substrate 700 from a rear surface direction.

[0141] Each unit mask UM may include a mask film MM, and the mask film MM may include a mask opening OP. Fig.14 ) may be disposed in a matrix form within each unit mask UM, and the mask openings OP may be between the mask shadow portions 1410. For example, the mask shadow portions 1410 may be disposed to surround the respective mask openings OP.

[0142] When the deposition material is deposited from the deposition source DS (see Fig.15 ) is evaporated, the mask shadow portion 1410 can be used as a blocking portion to mask the substrate to be deposited (e.g., the display panel 410 or the backplane substrate). Therefore, the deposition material generated from the deposition source DS can be deposited on the surface of the substrate to be deposited (e.g., the display panel 410 or the backplane substrate) through the mask opening OP of the mask film MM.

[0143] The mask opening OP of the mask film MM may be referred to as a “hole” or a “mask hole.” The mask opening OP may pass through the unit mask UM along a thickness direction (eg, third direction DR3 ) of the mask MK.

[0144] One unit mask UM may be used in a deposition process of one display panel 410. In the embodiment of the present disclosure, the term "unit mask UM" may be replaced with a term such as a mask unit UM or a unit mask UM.

[0145] Figure 8 is a flowchart illustrating a method for manufacturing a mask according to an exemplary embodiment.

[0146] Figures 9 to 14 are cross-sectional views for describing processes of a method for manufacturing a mask according to an exemplary embodiment.

[0147] In the following, reference will be made to Figures 8 to 14 as well as Figure 7 A method for manufacturing a mask according to example embodiments is described. The following description is only a description of some of the processes for manufacturing a mask, and a process for forming a component described with reference to the present disclosure may be additionally performed before or after each step. In some embodiments, any suitable process for manufacturing a mask commonly used in the art may be additionally performed before or after each step to be described below.

[0148] refer to Figure 8 and Fig. 9 In step 810, an inorganic film pattern 910 may be formed on a silicon substrate 700. The silicon substrate 700 includes a plurality of cell regions 710 and a mask frame region 720 excluding the plurality of cell regions 710. The mask frame region 720 includes a mask lip region 721 separating the plurality of cell regions 710 and an outer frame region 722 disposed at the outermost portion of the silicon substrate 700. Step 810 may be a step of forming an inorganic film pattern 910 in each cell region 710 of the silicon substrate 700.

[0149] According to example embodiments, the inorganic film pattern 910 may be disposed at intervals on the silicon substrate 700 in each cell region 710 . Thus, the inorganic film pattern 910 may include a plurality of openings 911 in each cell region 710 .

[0150] According to example embodiments, the inorganic film pattern 910 may have a regular tapered shape. This is to ensure that when the metal layer 1010 is deposited on the inorganic film pattern 910 in a subsequent process, the deposited metal layer 1010 becomes the mask film MM having an inverse tapered shape.

[0151] The inorganic film pattern 910 may be formed by depositing an inorganic film on the silicon substrate 700 and then patterning the deposited inorganic film.

[0152] The inorganic film pattern 910 may include a material selected from silicon (Si), silicon nitride (SiNx ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one of.

[0153] refer to Figure 8 and Fig.10 In step 820, a metal layer 1010 may be deposited on the inorganic film pattern 910 and the opening 911 of the inorganic film pattern 910. The metal layer 1010 may include a plurality of films including a first metal layer 1011 and a second metal layer 1012. For example, the step of depositing the metal layer 1010 may include a step of depositing the first metal layer 1011 including a first metal and a step of depositing the second metal layer 1012 including a second metal on the first metal layer 1011.

[0154] In the method for manufacturing a mask according to an example embodiment, a mask film MM is formed using a metal layer 1010 deposited by a sputtering process. In this example embodiment, the mask film MM may be manufactured to have a thickness smaller than that of the mask film according to the comparative example formed using a plating film. For example, the mask film MM according to the example embodiment may have a thickness less than about 0.3 μm.

[0155] According to an example embodiment, the first metal included in the first metal layer 1011 includes at least one selected from vanadium (V), tantalum (Ta), and niobium (Nb). The second metal included in the second metal layer 1012 includes titanium nitride (TiN). The first metal layer 1011 is made of at least one selected from vanadium (V), tantalum (Ta), and niobium (Nb), and thus, resistance to acidic chemicals in a subsequent process of etching the silicon substrate 700 can be increased, and dry etching can be easily performed. The second metal layer 1012 is made of titanium nitride (TiN), and thus, can have a Young's modulus of about 550 MPa to prevent or reduce warping and have strong scratch resistance.

[0156] refer to Figure 8 and Fig.11 In step 830, a portion of the metal layer 1010 deposited on the opening 911 of the inorganic film pattern 910 may be etched. For example, the metal layer 1010 may be removed in the opening 911 of the inorganic film pattern 910. The process of removing the metal layer 1010 includes a step of dry etching a portion of the metal layer 1010. After performing the process according to step 830, the metal layer 1010 remains only on the surface of the inorganic film pattern 910.

[0157] refer to Figure 8 and Fig.12In step 840, a protective layer 1210 may be deposited. The protective layer 1210 may be an organic film including at least one selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The protective layer 1210 may cover the opening 911 of the inorganic film pattern 910 and the metal layer 1010 deposited on the inorganic film pattern 910. After depositing the protective layer 1210, the silicon substrate 700 may be turned over. For example, after depositing the protective layer 1210, the silicon substrate 700 may be turned over so that the protective layer 1210 points to the downward direction DR4.

[0158] refer to Figure 8 and Fig.13 In step 850, the silicon substrate 700 and the inorganic film pattern 910 disposed in each cell area 710 may be removed. After flipping the silicon substrate 700, the silicon substrate 700 and the inorganic film pattern 910 corresponding to each cell area 710 are removed. In some embodiments, a mask film MM in which only the metal layer 1010 is retained may be formed by removing the inorganic film pattern 910 from a structure in which the metal layer 1010 is stacked on the inorganic film pattern 910, thereby removing the silicon substrate 700 and the inorganic film pattern 910 disposed in the cell area 710. The step of removing the silicon substrate 700 disposed in each cell area 710 includes the step of wet etching a portion of the silicon substrate 700. During the wet etching of the silicon substrate 700, the metal layer 1010 may have strong resistance. This is because, as described above, the first metal layer 1011 is made of at least one selected from vanadium (V), tantalum (Ta), and niobium (Nb).

[0159] refer to Figure 8 and Fig.14 In step 860, the protective layer 1210 may be removed. After the protective layer 1210 is removed, only the metal layer 1010 substantially remains in each cell region 710. The metal layer 1010 is used as a mask film MM in each cell region 710.

[0160] The cross section of the mask film MM (e.g., the cross section of the mask shadow portion 1410) has an inverted tapered shape whose width increases from the bottom surface directed in the downward direction DR4 toward the upward direction DR3. For example, the cross section of the mask film MM has a bowl shape in which a space where the inorganic film pattern 910 is removed is surrounded by the metal layer 1010 and is open in the upward direction DR3. Here, the upward direction DR3 is from the deposition mask toward the substrate to be deposited (e.g., Fig.16 410) direction.

[0161] Fig.15 is a schematic cross-sectional view of a mask according to an example embodiment. Figures 8 to 14 The manufacturing process described above, the mask according to the example embodiment may finally have the following Fig.15The cross-sectional structure shown in .

[0162] refer to Fig.15 as well as Figure 7 In the mask MK according to the example embodiment, a mask film MM disposed in each unit area 710 and including a metal layer 1010 is provided. The cross section of the mask film MM (e.g., the cross section of the mask shadow portion 1410) has a bowl shape in which a space opened in the upward direction DR3 is surrounded by the metal layer 1010 in the lateral direction and the downward direction DR4. Here, the downward direction DR4 is a direction in which the deposition source DS is disposed.

[0163] Fig.16 is a view showing the concept of a shadow area of ​​a mask according to an example embodiment. For example, Fig.16 Shown is a reference Figures 8 to 15 The mask and the substrate to be deposited are aligned with each other. Fig.16 , reference numeral 410 denotes a display panel 410 as a substrate to be deposited.

[0164] refer to Fig.16 as well as Figure 7 In the mask MK according to the example embodiment, the cross section of the mask film MM (e.g., the cross section of the mask shadow portion 1410) has an inverted tapered shape, and thus, the area of ​​the shadow region 1610 may be reduced. For example, the cone angle of the cross section of the mask shadow portion 1410 formed by the metal layer 1010 may be less than or equal to the deposition incident angle, which is the minimum angle from the deposition source DS to the mask opening OP, and thus, the area of ​​the shadow region 1610 may be reduced.

[0165] With the method for manufacturing a deposition mask according to example embodiments, by forming a mask film using a metal, the rigidity of the mask film may be increased and the thickness of the mask may be easily adjusted.

[0166] In some embodiments, by allowing the mask film to have an inverse tapered shape, shadow defects may be reduced.

[0167] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense only, and not for a limiting purpose.

Claims

1. A method for manufacturing a deposition mask, the method comprising: forming an inorganic film pattern on a silicon substrate; depositing a metal layer on the inorganic film pattern and the opening of the inorganic film pattern; etching a portion of the metal layer deposited on the opening of the inorganic film pattern; depositing a protective layer on the inorganic film pattern and the opening of the inorganic film pattern; removing a portion of the silicon substrate in a cell region and the inorganic film pattern disposed in the cell region; as well as The protective layer is removed.

2. The method according to claim 1, wherein: The silicon substrate includes a plurality of unit regions and a mask frame region excluding the plurality of unit regions, and The mask frame region includes a mask lip region separating the plurality of unit regions and an outer frame region disposed at an outermost portion of the silicon substrate.

3. The method according to claim 2, wherein: Forming the inorganic film pattern includes forming the inorganic film pattern in each unit region of the silicon substrate.

4. The method according to claim 3, wherein: Depositing the metal layer comprises: depositing a first metal layer comprising a first metal; and A second metal layer including a second metal is deposited on the first metal layer.

5. The method according to claim 4, wherein: The first metal includes at least one selected from vanadium, tantalum and niobium.

6. The method according to claim 5, wherein: The second metal includes titanium nitride.

7. The method according to claim 4, wherein: Depositing the metal layer includes a sputtering process.

8. The method according to claim 1, wherein: Removing a portion of the silicon substrate in the cell region and the inorganic film pattern provided in the cell region includes forming a mask film in which only the metal layer remains by removing the inorganic film pattern from a structure in which the metal layer is stacked on the inorganic film pattern.

9. The method according to claim 8, wherein: The cross section of the mask film has an inverse tapered shape whose width increases from a bottom surface toward an upward direction.

10. Deposition mask, including: A silicon substrate including a plurality of unit regions and a mask frame region other than the plurality of unit regions, the mask frame region including a mask lip region separating the plurality of unit regions and an outer frame region disposed at an outermost portion of the silicon substrate; as well as a mask film disposed in each cell region and including a metal layer, Herein, a cross section of the mask film has a bowl shape in which a space opened in an upward direction is surrounded by the metal layer in a lateral direction and a downward direction.

Images