Chip pin flatness detection method and system and electronic equipment

Abstract

The invention provides a chip pin flatness detection method and system and electronic equipment. The chip pin flatness detection method comprises the following steps: acquiring a contour image of each pin of a to-be-detected chip based on a pre-acquired image of the to-be-detected chip; obtaining the total number of pins, the distance between every two adjacent pins and the width of each pin according to the contour image of each pin of the chip to be detected; and determining the pin flatness of the to-be-detected chip according to the acquired total number of the pins, the distance between every two adjacent pins and the width of each pin. The chip pin flatness detection system comprises a pin contour image acquisition module, a pin flatness evaluation data acquisition module and a pin flatness evaluation module which are used for realizing the steps in a one-to-one correspondence manner. The electronic equipment comprises a processor and a memory, and the processor implements the chip pin flatness detection method when executing a computer program stored in the memory.

Description

Technical Field

[0001] The present application relates to chip quality detection, and more specifically, to a chip pin flatness detection method, system and electronic equipment. Background Art

[0002] Modern microelectronics manufacturing processes require extremely high precision, especially high-density pin packaging processes, such as ball grid array packaging, square flat package, etc. For chips using high-density pin packaging processes, errors in chip pin flatness may lead to serious welding defects such as poor welding, short circuit or open circuit. Therefore, pin flatness detection after chip packaging is very important to ensure the stability and reliability of chip quality, and is also an important detection content of existing chip packaging tests.

[0003] Existing chip pin flatness inspection usually adopts manual sampling, that is, first randomly select a predetermined number of chips to be inspected from a batch of chips, and then the inspector determines whether the chip pin flatness is qualified through visual inspection and based on relevant judgment standards. This manual chip pin flatness inspection method mainly has the following two problems: 1. Waste of manpower and low detection efficiency; 2. Although the inspectors determine whether the chip pin flatness is qualified based on relevant judgment standards, there are still situations where subjective factors affect the chip pin flatness judgment results. In addition, in the case of long-term testing, visual inspection results are prone to errors, which in turn affects the accuracy of chip pin flatness detection.

[0004] Therefore, it is necessary to propose an efficient, high-precision, non-contact chip pin flatness detection method. Summary of the invention

[0005] The purpose of the present invention is to solve the problem that the existing manual chip pin flatness detection method has low efficiency and low detection result accuracy.

[0006] In order to achieve the above-mentioned purpose, the present invention provides a chip pin flatness detection method, system and electronic equipment.

[0007] According to a first aspect of the present invention, a chip pin flatness detection method is provided, the method comprising the following steps: Acquire a contour image of each pin of the chip to be inspected based on a pre-acquired image of the chip to be inspected; Acquire the total number of pins, the distance between every two adjacent pins, and the width of each pin according to the contour image of each pin of the chip to be detected; The flatness of the pins of the chip to be tested is determined according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin.

[0008] Optionally, determining the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin includes: The pin flatness index of the chip to be tested is determined according to a predetermined chip pin flatness index calculation formula, and the chip pin flatness index calculation formula is: F = f(s1) × [K2 × g(s2) + K3 × h(s3)] In the above formula, F is the pin flatness index; f(s1) = 1 - |s1 - snum| / snum, s1 is the total number of pins, snum is the total number of pins threshold; g(s2) = exp(-σ(s2) / μ(s2)), σ(s2) is the standard deviation of the distance between two adjacent pins, and μ(s2) is the average distance between two adjacent pins; h(s3) = exp(-σ(s3) / μ(s3)), σ(s3) is the standard deviation of the width of each pin, and μ(s3) is the average width of each pin; K2 is the spacing weight and K3 is the width weight.

[0009] Optionally, the step of determining the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin further includes: The pin flatness level of the chip to be detected is determined according to the pin flatness index of the chip to be detected.

[0010] Optionally, acquiring the contour image of each pin of the chip to be inspected based on the pre-acquired image of the chip to be inspected includes: Preprocessing the image of the chip to be detected; Locating a chip ROI image in the preprocessed chip image based on the contour features of the chip to be detected; Performing angle correction on the chip ROI image according to the chip template image; Segment the chip body area based on the chip ROI image after angle correction; Setting a chip pin to-be-detected area based on the chip body area; Segmenting a pin threshold map based on the chip pin area to be detected; A contour image of each pin is extracted based on the pin threshold map.

[0011] Optionally, the preprocessing of the image of the chip to be detected includes: The image of the chip to be detected is subjected to filtering, denoising and histogram equalization processing.

[0012] Optionally, the performing angle correction on the chip ROI image according to the chip template image includes: Matching the appearance features of the chip ROI image with the appearance features of the chip template image to obtain a rotation angle of the chip ROI image relative to the chip template image; Angle correction is performed on the chip ROI image according to a rotation angle of the chip ROI image relative to the chip template image.

[0013] Optionally, matching the shape features of the chip ROI image with the shape features of the chip template image to obtain a rotation angle of the chip ROI image relative to the chip template image includes: Determine the best chip template image; Extracting feature points of the chip ROI image and feature points of the optimal chip template image; Performing matching detection on the feature points of the chip ROI image and the feature points of the optimal chip template image to obtain matching feature points; Calculating the affine transformation matrix of the matched feature points; The rotation angle is determined according to the affine transformation matrix.

[0014] Optionally, determining the best chip template image includes: The image gradient of the shape feature of the chip ROI image after pyramid downsampling and the image gradient of the shape feature of the standard chip template image after pyramid downsampling are respectively calculated; The pixel points in the standard chip template image whose image gradient amplitude is greater than a predetermined threshold are retained, and the gradient direction of each pixel point is quantified in five directions; Obtain the retained pixel positions and gradient quantization direction information of the chip template image at different scales and rotation angles; Obtaining the similarity between each retained pixel point of each chip template image and the corresponding pixel point in the chip ROI image in five gradient quantization directions, and taking the sum of the similarities corresponding to each retained pixel point of the chip template image as the similarity between the chip template image and the chip ROI image; The chip template image having the highest similarity to the chip ROI image is used as the optimal chip template image.

[0015] According to a second aspect of the present invention, a chip pin flatness detection system is provided, the system comprising the following functional modules: A pin outline image acquisition module, used for acquiring an outline image of each pin of the chip to be detected based on a pre-acquired image of the chip to be detected; A pin flatness evaluation data acquisition module is used to acquire the total number of pins, the distance between every two adjacent pins, and the width of each pin according to the contour image of each pin of the chip to be tested; The pin flatness evaluation module is used to determine the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin.

[0016] According to a third aspect of the present invention, there is provided an electronic device comprising a processor and a memory, wherein the processor implements any of the above-mentioned chip pin flatness detection methods when executing a computer program stored in the memory.

[0017] The beneficial effects of the present invention are: The chip pin flatness detection method of the present invention firstly obtains the contour image of each pin of the chip to be detected based on the pre-acquired image of the chip to be detected; secondly, obtains the total number of pins, the distance between every two adjacent pins and the width of each pin according to the contour image of each pin of the chip to be detected; finally, determines the pin flatness of the chip to be detected according to the obtained total number of pins, the distance between every two adjacent pins and the width of each pin.

[0018] The chip pin flatness detection method of the present invention can be automatically implemented based on relevant hardware equipment. Compared with the existing manual chip pin flatness detection method, the chip pin flatness detection method of the present invention not only saves manpower but is also more efficient. At the same time, the present invention determines the pin flatness of the chip to be detected based on the acquired chip pin flatness evaluation data, that is, the total number of pins, the distance between every two adjacent pins, and the width of each pin, and combines the relevant chip pin flatness evaluation standards, so that the chip pin flatness detection result is not affected by the subjective factors of personnel, and also avoids the influence of personnel visual errors on the detection results.

[0019] It can be seen that the chip pin flatness detection method of the present invention can effectively solve the problem of low efficiency and low accuracy of detection results of the existing manual chip pin flatness detection method.

[0020] The chip pin flatness detection system and electronic device of the present invention belong to a general inventive concept as well as the above-mentioned chip pin flatness detection method, and have at least the same beneficial effects as the above-mentioned chip pin flatness detection method, and the beneficial effects are not repeated here.

[0021] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flowchart of a chip pin flatness detection method according to an embodiment of the present invention is shown; Figure 2 A flowchart for obtaining a pin outline image according to an embodiment of the present invention is shown; Figure 3 A schematic diagram of a chip ROI image according to an embodiment of the present invention is shown; Figure 4 A schematic diagram showing a chip pin area to be detected according to an embodiment of the present invention; Figure 5 A principle block diagram of a chip pin flatness system according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0024] Throughout the specification and claims, the following terms have at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples of the terms. In the description of the present invention, the phrase "in one embodiment" does not necessarily refer to the same embodiment, although it may refer to the same embodiment. Similarly, the phrase "in some embodiments" as used herein, when used multiple times, does not necessarily refer to the same embodiment, although it may refer to the same embodiment. As used herein, the term "or" is an inclusive "or" operator and is equivalent to the term "and / or", unless the context clearly dictates otherwise. The term "based on" is not exclusive and allows for additional factors not described, unless the context clearly dictates otherwise. The word "exemplary" means "used as an example, instance or illustration" in this article. Any embodiment described herein as "exemplary" is not necessarily interpreted as being superior or superior to other embodiments. The scope of the present invention is limited only by the scope of the appended claims, and any examples set forth in this specification are not intended to be limiting, but only to set forth some of the many possible embodiments of the claimed invention. The various embodiments provided by the present invention should not be interpreted as limiting the scope of protection of the present invention.

[0025] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0027] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0029] Example: Figure 1 FIG. 1 is a flowchart showing a method for detecting the flatness of a chip pin according to an embodiment of the present invention. Figure 1 The chip pin flatness detection method of the embodiment of the present invention comprises the following steps: Step S100, acquiring contour images of each pin of the chip to be inspected based on the pre-acquired image of the chip to be inspected; Step S200, acquiring the total number of pins, the distance between every two adjacent pins, and the width of each pin according to the contour image of each pin of the chip to be detected; Step S300: Determine the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin.

[0030] Specifically, in the embodiment of the present invention, the total number of pins is equal to the number of pin contour images, the spacing between every two adjacent pins is the distance between the center points of the contour images of every two adjacent pins, and the width of the pin is the width of the inscribed rectangle of the contour image of the pin.

[0031] Further, in the embodiment of the present invention, the step S300 of determining the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin includes: Step S310, determining the pin flatness index of the chip to be tested according to a predetermined chip pin flatness index calculation formula; Step S320 : determining the pin flatness level of the chip to be tested according to the pin flatness index of the chip to be tested.

[0032] Furthermore, in step S310 of the embodiment of the present invention, the chip pin flatness index calculation formula is specifically: F = f(s1) × [K2 × g(s2) + K3 × h(s3)] In the above formula, F is the pin flatness index; f(s1) = 1 - |s1 - snum| / snum, s1 is the total number of pins, snum is the total number of pins threshold; g(s2) = exp(-σ(s2) / μ(s2)), σ(s2) is the standard deviation of the distance between two adjacent pins, and μ(s2) is the average distance between two adjacent pins; h(s3) = exp(-σ(s3) / μ(s3)), σ(s3) is the standard deviation of the width of each pin, and μ(s3) is the average width of each pin; K2 is the spacing weight and K3 is the width weight.

[0033] Specifically, in the embodiment of the present invention, K2 preferably takes a value of 0.6, and K3 preferably takes a value of 0.4; when |s1 - snum|≤the allowable error range, f(s1) is close to 1, and when |s1 - snum|>the allowable error range, f(s1) decays rapidly to close to 0.

[0034] Specifically, in the embodiment of the present invention, the pin flatness level of the chip to be tested is determined according to a predetermined chip pin flatness evaluation standard. The chip pin flatness evaluation standard is specifically: When the pin flatness index F>0.95, the chip pin flatness level is extremely high; When 0.85<pin flatness index F≤0.95, the chip pin flatness level is high; When 0.70<pin flatness index F≤0.85, the chip pin flatness level is good; When 0.50<pin flatness index F≤0.70, the chip pin flatness level is qualified; When the pin flatness index F≤0.50, the chip pin flatness level is unqualified.

[0035] Further, Figure 2 FIG. 1 is a flowchart of the implementation of the pin outline image acquisition of an embodiment of the present invention. Figure 2 In the embodiment of the present invention, the step S100 of acquiring the contour image of each pin of the chip to be detected based on the pre-acquired image of the chip to be detected includes: Step S110, preprocessing the image of the chip to be detected; Step S120, locating a chip ROI image in the preprocessed chip image based on the contour features of the chip to be detected; Step S130, performing angle correction on the chip ROI image according to the chip template image; Step S140, segmenting the chip body area based on the chip ROI image after angle correction; Step S150, setting a chip pin to-be-detected area based on the chip body area; Step S160, segmenting a pin threshold map based on the chip pin area to be detected; Step S170: extracting a contour image of each pin based on the pin threshold map.

[0036] Specifically, in the embodiment of the present invention, in step S120, locating the chip ROI image in the preprocessed chip image based on the contour features of the chip to be detected means determining the position of the chip to be detected in the chip image to ensure the accuracy of subsequent processing. This is set because the preprocessed chip image contains not only the image of the chip to be detected itself, but also the background part. An exemplary chip ROI image located is as follows: Figure 3As shown. In step S130, the chip ROI image is used to characterize the specific position of the chip to be detected in the image taken by the camera. The angle correction of the chip ROI image according to the chip template image is to adjust the position of the chip to be detected in the image to be the same as the chip template image. In step S140, the chip body area is the chip body part, which is the part of the chip to be detected except the pins. In step S150, the chip pin area to be detected includes all the pins of the chip to be detected. An exemplary image of the chip pin area to be detected is shown as follows: Figure 4 shown.

[0037] Furthermore, in the embodiment of the present invention, the preprocessing of the image of the chip to be detected in step S110 includes: The image of the chip to be inspected is subjected to filtering, denoising and histogram equalization processing.

[0038] Specifically, in the embodiment of the present invention, filtering and denoising the image of the chip to be inspected can reduce the interference of textures other than contours in the image and the noise formed in the imaging process due to uneven illumination. Histogram equalization is used to improve the contrast of the image.

[0039] Furthermore, in the embodiment of the present invention, the step S130 of performing angle correction on the chip ROI image according to the chip template image includes: Matching the shape features of the chip ROI image with the shape features of the chip template image to obtain a rotation angle of the chip ROI image relative to the chip template image; The chip ROI image is angle-corrected according to the rotation angle of the chip ROI image relative to the chip template image.

[0040] Furthermore, in the embodiment of the present invention, the process of obtaining the rotation angle of the chip ROI image relative to the chip template image is specifically as follows: Determine the best chip template image; Extracting feature points of chip ROI image and feature points of optimal chip template image; Matching and detecting the feature points of the chip ROI image with the feature points of the best chip template image to obtain matching feature points; Calculate the affine transformation matrix of the matching feature points; Determine the rotation angle based on the affine transformation matrix.

[0041] Furthermore, in the embodiment of the present invention, the process of determining the best chip template image is specifically as follows: The image gradient of the shape feature of the chip ROI image after pyramid downsampling and the image gradient of the shape feature of the standard chip template image after pyramid downsampling are respectively calculated; The pixel points in the standard chip template image whose image gradient amplitude is greater than a predetermined threshold are retained, and the gradient direction of each pixel point is quantified in five directions; Obtain the retained pixel positions and gradient quantization direction information of the chip template image at different scales and rotation angles; Obtain the similarity between each retained pixel point of each chip template image and the corresponding pixel point in the chip ROI image in five gradient quantization directions, and take the sum of the similarities corresponding to each retained pixel point of the chip template image as the similarity between the chip template image and the chip ROI image; The chip template image with the highest similarity to the chip ROI image is taken as the best chip template image.

[0042] The chip pin flatness detection method of the embodiment of the present invention adopts image processing technology to realize non-contact automatic detection, avoids the low efficiency and human interference problems of traditional manual detection, and can adapt to the real-time online detection needs of large-scale production lines; by segmenting the pins and extracting the pin contours, the number, spacing and width of the chip pins can be accurately calculated, so as to determine whether the chip is flat; from image acquisition, preprocessing, area positioning, template matching, correction, area segmentation to contour extraction, a complete detection process is formed to ensure the comprehensiveness and accuracy of the detection.

[0043] The chip pin flatness detection method of the embodiment of the present invention can solve the problems of insufficient accuracy, low efficiency, susceptibility to interference from human factors, and inability to adapt to the real-time online detection requirements of high-precision and high-speed production lines in modern microelectronics manufacturing in the prior art. By implementing the chip pin flatness detection method of the embodiment of the present invention, efficient, accurate, and automated detection of chip pin flatness can be achieved, meeting the high requirements of modern microelectronics manufacturing, significantly improving production efficiency, reducing defective product rates, and saving costs.

[0044] Accordingly, based on the chip pin flatness detection method of the embodiment of the present invention, the embodiment of the present invention further proposes a chip pin flatness detection system.

[0045] Figure 5 The implementation flow chart of the chip pin flatness detection method is shown. Figure 5 The chip pin flatness detection system of the embodiment of the present invention includes the following functional modules: A pin outline image acquisition module, used for acquiring outline images of each pin of the chip to be detected based on the pre-acquired image of the chip to be detected; A pin flatness evaluation data acquisition module is used to acquire the total number of pins, the distance between every two adjacent pins, and the width of each pin according to the contour image of each pin of the chip to be tested; The pin flatness evaluation module is used to determine the pin flatness of the chip to be tested based on the total number of pins obtained, the distance between every two adjacent pins, and the width of each pin.

[0046] Accordingly, based on the chip pin flatness detection method of the embodiment of the present invention, the embodiment of the present invention also proposes an electronic device, which includes a processor and a memory, and the processor implements the above-mentioned chip pin flatness detection method when executing the computer program stored in the memory.

[0047] In the above-mentioned embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The steps shown in the relevant flow chart can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flow chart, in some cases, the steps shown or described can be executed in an order different from that here. In other words, the order of steps described in the foregoing embodiments is only an example, and it is also within the scope of protection of the embodiments of the present application to reasonably adjust the order of steps based on the content of the embodiments of the present application.

[0048] The sequence of serial numbers or introduction of the embodiments of the present application is for description only and does not represent the superiority or inferiority of the embodiments.

[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0050] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A chip pin flatness detection method, characterized in that: include: Acquire a contour image of each pin of the chip to be inspected based on a pre-acquired image of the chip to be inspected; The step of acquiring the contour image of each pin of the chip to be detected based on the pre-acquired image of the chip to be detected comprises: pre-processing the image of the chip to be detected; Locating a chip ROI image in the preprocessed chip image based on the contour features of the chip to be detected; Performing angle correction on the chip ROI image according to the chip template image; Segment the chip body area based on the chip ROI image after angle correction; Setting a chip pin to-be-detected area based on the chip body area; Segmenting a pin threshold map based on the chip pin area to be detected; Extracting a contour image of each pin based on the pin threshold map; The performing angle correction on the chip ROI image according to the chip template image comprises: Matching the appearance features of the chip ROI image with the appearance features of the chip template image to obtain a rotation angle of the chip ROI image relative to the chip template image; Performing angle correction on the chip ROI image according to a rotation angle of the chip ROI image relative to the chip template image; The step of matching the shape features of the chip ROI image with the shape features of the chip template image to obtain a rotation angle of the chip ROI image relative to the chip template image includes: Determine the best chip template image; Extracting feature points of the chip ROI image and feature points of the optimal chip template image; Performing matching detection on the feature points of the chip ROI image and the feature points of the optimal chip template image to obtain matching feature points; Calculating the affine transformation matrix of the matched feature points; Determining the rotation angle according to the affine transformation matrix; Determining the best chip template image comprises: The image gradient of the shape feature of the chip ROI image after pyramid downsampling and the image gradient of the shape feature of the standard chip template image after pyramid downsampling are respectively calculated; The pixel points in the standard chip template image whose image gradient amplitude is greater than a predetermined threshold are retained, and the gradient direction of each pixel point is quantified in five directions; Obtain the retained pixel positions and gradient quantization direction information of the chip template image at different scales and rotation angles; Obtaining the similarity between each retained pixel point of each chip template image and the corresponding pixel point in the chip ROI image in five gradient quantization directions, and taking the sum of the similarities corresponding to each retained pixel point of the chip template image as the similarity between the chip template image and the chip ROI image; Using the chip template image with the highest similarity to the chip ROI image as the best chip template image; Acquire the total number of pins, the distance between every two adjacent pins, and the width of each pin according to the contour image of each pin of the chip to be detected; The flatness of the pins of the chip to be tested is determined according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin.

2. The chip pin flatness detection method according to claim 1, characterized in that: Determining the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin includes: The pin flatness index of the chip to be tested is determined according to a predetermined chip pin flatness index calculation formula, and the chip pin flatness index calculation formula is: F = f(s1) × [K2 × g(s2) + K3 × h(s3)] In the above formula, F is the pin flatness index; f(s1) = 1 - |s1 - snum| / snum, s1 is the total number of pins, snum is the total number of pins threshold; g(s2) = exp(-σ(s2) / μ(s2)), σ(s2) is the standard deviation of the distance between two adjacent pins, and μ(s2) is the average distance between two adjacent pins; h(s3) = exp(-σ(s3) / μ(s3)), σ(s3) is the standard deviation of the width of each pin, and μ(s3) is the average width of each pin; K2 is the spacing weight and K3 is the width weight.

3. The chip pin flatness detection method according to claim 2, characterized in that: The step of determining the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin further includes: The pin flatness level of the chip to be detected is determined according to the pin flatness index of the chip to be detected.

4. The chip pin flatness detection method according to claim 1, characterized in that: The preprocessing of the image of the chip to be detected comprises: The image of the chip to be detected is subjected to filtering, denoising and histogram equalization processing.

5. A chip pin flatness detection system, characterized in that: include: A pin outline image acquisition module, used for acquiring an outline image of each pin of the chip to be detected based on a pre-acquired image of the chip to be detected; A pin flatness evaluation data acquisition module is used to acquire the total number of pins, the distance between every two adjacent pins, and the width of each pin according to the contour image of each pin of the chip to be tested; The pin flatness evaluation module is used to determine the pin flatness of the chip to be tested according to the acquired total number of pins, the distance between every two adjacent pins, and the width of each pin.

6. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the processor implements the chip pin flatness detection method according to any one of claims 1 to 4 when executing a computer program stored in the memory.

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