Chip test analysis method and device

Abstract

The invention provides a chip test analysis method and device, and the method comprises the steps: enabling a to-be-tested chip and a pin array to be disposed on a first surface of a circuit board in a design mode of reverse pin implantation, enabling the pin array to be electrically connected with a test tool, carrying out the electrical test of the chip, and enabling the circuit board to be provided with a light-transmitting region which penetrates through the first surface and a second surface, the back surface of the chip faces the light-transmitting area so that electrical failure analysis can be performed on the chip through the second surface of the circuit board, the test analysis difficulty is reduced, the test analysis accuracy is improved, and the product yield is improved.

Description

Technical Field

[0001] The invention relates to a chip testing and analyzing method and device. Background Art

[0002] Since there are countless steps in the chip manufacturing process that may introduce defects, even in the same batch of wafers and packaged products, some chips are good and some are bad, so screening is needed, that is, evaluating chip performance through various tests, analyzing failure causes, and improving product yield.

[0003] At present, the industry generally adopts the chip testing method and testing device of positive implant needle, such as Figure 1 As shown, the chip 102 is arranged on one side of the circuit board 101, and the implant needle array 103 is arranged on the other side of the circuit board 101. The implant needle array 103 is electrically connected to the test fixture (not shown) for electrical testing, such as ESD (electrostatic discharge test). However, when a failure problem is found through electrical testing, or a failure problem is found through other methods, EFA (electrical failure analysis) needs to be performed. The existing positive implant needle method has application defects: EFA requires observing the back side (semiconductor substrate surface) 102b of the chip in the test environment of power-on / power-off instructions. Due to the design of the positive implant needle, when the implant needle array 103 is electrically connected to the test fixture, the back side 102b of the chip will be blocked by the circuit board 101 and cannot be observed. If the back side 102b of the chip is to be exposed, the probe array 103 cannot be used for electrical connection, and additional wires need to be welded on the circuit board 101. It is estimated that each chip needs to add hundreds of wires, which not only significantly affects the signal transmission rate, but also makes the test environment very complicated and unstable, and cannot stably reproduce the failure phenomenon, affecting the accuracy of the analysis results. Summary of the invention

[0004] The purpose of the present invention is to provide a chip testing and analysis method and device to reduce the difficulty of testing and analysis, improve the accuracy of testing and analysis, and increase product yield.

[0005] Based on the above considerations, the present invention provides a chip testing and analysis method, including: providing a test fixture; providing a circuit board, the circuit board having a first surface and a second surface relative to each other, and a light-transmitting area penetrating the first surface and the second surface; arranging a chip to be tested on the first surface of the circuit board, the front side of the chip is electrically connected to the circuit board, and is electrically connected to the test fixture through a needle array arranged on the first surface of the circuit board, so as to perform electrical testing on the chip; the back side of the chip faces the light-transmitting area, so that electrical failure analysis of the chip can be performed through the second surface of the circuit board.

[0006] Preferably, the circuit board and the test fixture are connected via a connector, and the connector is provided with a slot array corresponding to the needle array.

[0007] Preferably, the front side of the chip is covered with a protective cover, and when the implant needle array is inserted into the corresponding slot array, the protective cover maintains a certain gap with the connector.

[0008] Preferably, a mapping relationship between each slot in the slot array and each implant needle in the implant needle array is formed by a control unit of the test fixture.

[0009] Preferably, the pads on the front side of the chip are connected to the pads on the first side of the circuit board via metal wires.

[0010] Another aspect of the present invention provides a chip testing and analysis device, comprising: a test fixture; a circuit board, the circuit board having a first surface and a second surface opposite to each other, and a light-transmitting area penetrating the first surface and the second surface; the first surface of the circuit board is used to set the chip to be tested, the front side of the chip is electrically connected to the circuit board, and is electrically connected to the test fixture through a needle array arranged on the first surface of the circuit board so as to perform electrical testing on the chip; the back side of the chip faces the light-transmitting area so that electrical failure analysis can be performed on the chip through the second surface of the circuit board.

[0011] Preferably, the chip testing and analyzing device further comprises a connector for connecting the circuit board and the test fixture, and the connector is provided with a slot array corresponding to the needle array.

[0012] Preferably, the front side of the chip is covered with a protective cover, and when the implant needle array is inserted into the corresponding slot array, the protective cover maintains a certain gap with the connector.

[0013] Preferably, the test fixture comprises a control unit for forming a mapping relationship between each slot in the slot array and each implant needle in the implant needle array.

[0014] Preferably, the pads on the front side of the chip are connected to the pads on the first side of the circuit board via metal wires.

[0015] The chip testing and analysis method and device of the present invention adopt a reverse needle design, and the chip to be tested and the needle array are arranged on the first side of the circuit board. The needle array is electrically connected to the test fixture to perform electrical testing on the chip, and a light-transmitting area that runs through the first side and the second side is arranged on the circuit board. The back side of the chip faces the light-transmitting area so that electrical failure analysis of the chip can be performed through the second side of the circuit board, thereby reducing the difficulty of testing and analysis, improving the accuracy of testing and analysis, and increasing the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0017] Figure 1 It is a cross-sectional schematic diagram of a chip testing and analysis device in the prior art; Figure 2-Figure 4 It is a cross-sectional schematic diagram of the chip testing and analyzing device of the present invention; Figure 5 It is a plan view of the chip testing and analyzing device of the present invention.

[0018] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0019] In order to solve the problems in the above-mentioned prior art, the present invention provides a chip testing and analysis method and device, which adopts a reverse needle design, and arranges the chip to be tested and the needle array on the first side of the circuit board, and electrically connects the needle array to the test fixture to perform electrical testing on the chip, and arranges a light-transmitting area running through the first side and the second side on the circuit board, and the back of the chip faces the light-transmitting area so that electrical failure analysis of the chip can be performed through the second side of the circuit board, thereby reducing the difficulty of test analysis, improving the accuracy of test analysis, and increasing product yield.

[0020] In the following specific description of the preferred embodiments, reference will be made to the attached drawings which constitute a part of the present invention. The attached drawings show by way of example specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present invention. Therefore, the following specific description is not restrictive, and the scope of the present invention is limited by the appended claims.

[0021] Figure 2A preferred embodiment of the chip testing and analysis device of the present invention is shown, and the chip testing and analysis device includes a circuit board 201, and the circuit board 201 has a first surface 201a and a second surface 201b opposite to each other, and a light-transmitting area 204 that penetrates the first surface 201a and the second surface 201b. Preferably, a hollow area can be formed in the circuit board 201 and a light-transmitting material, such as glass, is inlaid, so as to form a light-transmitting area 204 that penetrates the first surface 201a and the second surface 201b of the circuit board. A chip 202 to be tested is arranged on the first surface 201a of the circuit board, and the front surface 202a of the chip is electrically connected to the circuit board 201. In this embodiment, the pad 205 of the front surface 202a of the chip is connected to the pad 206 of the first surface 201a of the circuit board through a metal wire 208 to form a COB package (chip on board package) or COM package (chip on module package) component. Of course, the chip testing and analysis device of the present invention is also applicable to chips of other package forms not shown for testing and analysis.

[0022] Different from the positive needle implantation method of the prior art, the chip testing and analysis device of the present invention adopts a reverse needle implantation design, and the needle implantation array 203 is arranged on the first surface 201a of the circuit board, that is, the needle implantation array 203 and the chip to be tested 202 are located on the same surface 201a of the circuit board 201. The chip testing and analysis device of the present invention also includes a test fixture not shown, and the needle implantation array 203 arranged on the first surface 201a of the circuit board is electrically connected to the test fixture to perform electrical testing on the chip 202, such as ESD testing; the back side 202b of the chip faces the light-transmitting area 204, so the device status of the back side 202b of the chip can be directly observed through the second surface 201b of the circuit board, so as to perform EFA analysis on the chip 202. Due to the reverse needle implantation design, there is no need to weld wires on the circuit board 201, and the back side 202b of the chip can be observed while the power is on, and EFA analysis can be performed, which avoids the adverse effects of welding wires on signal transmission rate and test environment stability, thereby reducing the difficulty of test analysis, improving the accuracy of test analysis, and improving product yield.

[0023] like Figure 3 , Figure 4As shown, preferably, the chip testing and analysis device of the present invention also includes a connector 300, and the connector 300 is provided with a slot array 301 corresponding to the implant needle array 203. The implant needles on the circuit board 201 are respectively inserted into the corresponding slots on the connector 300 to achieve electrical connection between the circuit board 201 and the connector 300, and then connected to the test fixture through the connector 300. In order to protect the chip 202 and prevent accidental scratches or contamination during the test and analysis process, a protective cover 207 can be covered on the front side 202a of the chip. Preferably, by reasonably setting the height and / or diameter of the implant needles and / or the slots, the protective cover 207 is avoided so that when the implant needle array 203 is inserted into the corresponding slot array 301, a certain gap 209 is maintained between the protective cover 207 and the connector 300 to ensure the smooth connection and installation of the circuit board 201 and the connector 300.

[0024] Figure 5 A plan view of the first side 201a of the circuit board and a plan view of the connector 300 in the chip test and analysis device of the present invention are shown. Since the circuit board 101 of the prior art adopts a positive pin design and is placed on the connector 300 with the chip 102 facing upward and the pin array 103 facing downward, while the circuit board 201 of the present invention adopts a reverse pin design and needs to be flipped and placed on the connector 300 with the chip 202 facing downward and the pin array 203 facing downward, in the chip test and analysis device of the present invention, the connection relationship between the test pad 205 of the chip 202 and the slot of the connector 300 is different from the connection relationship of the prior art (usually should be mirror symmetric). In order to better be compatible with the test environment and software of the prior art, preferably, the test fixture also includes a control unit for forming a mapping relationship between each slot in the slot array 301 and each pin in the pin array 201, for example, the pin A11 in the pin array 203 corresponds to the slot B11 of the slot array 301, so as to simplify the test and analysis steps. Of course, those skilled in the art may also re-encode all of them and re-establish the corresponding relationship between the slots in the slot array 301 and the pads 205 to be tested of the chip 202 .

[0025] See also Figure 2-Figure 5The present invention also provides a chip testing and analysis method, comprising: providing a circuit board 201, wherein the circuit board 201 has a first surface 201a and a second surface 201b opposite to each other, and a light-transmitting area 204 penetrating the first surface 201a and the second surface 201b; preferably, a hollow area can be formed in the circuit board 201 and a light-transmitting material, such as glass, is inlaid to form the light-transmitting area 204 penetrating the first surface 201a and the second surface 201b of the circuit board. A chip 202 to be tested is arranged on the first surface 201a of the circuit board, and the front surface 202a of the chip is electrically connected to the circuit board 201; preferably, a pad 205 on the front surface 202a of the chip is connected to a pad 206 on the first surface 201a of the circuit board by a metal wire 208 to form a COB package (chip on board package) or COM package (chip on module package) component. Of course, the chip testing and analysis method of the present invention is also applicable to chips of other package forms not shown for testing and analysis.

[0026] The chip testing and analysis method of the present invention also includes: providing a test fixture (not shown), electrically connecting the test fixture through the implant needle array 203 disposed on the first surface 201a of the circuit board, so as to conduct electrical testing on the chip 202; the back side 202b of the chip faces the light-transmitting area 204, so as to conduct electrical failure analysis on the chip 202 through the second surface 201b of the circuit board. Due to the design of reverse implant needles, there is no need to solder wires on the circuit board 201, and the back side 202b of the chip can be observed while powering on to conduct EFA analysis, thereby avoiding the adverse effects of solder wires on signal transmission rate and test environment stability, thereby reducing the difficulty of test analysis, improving the accuracy of test analysis, and increasing product yield.

[0027] Preferably, the circuit board 201 and the test fixture can be connected through the connector 300. Specifically, the connector 300 is provided with a slot array 301 corresponding to the pin array 203. The circuit board 201 is electrically connected to the connector 300 by inserting the pins on the circuit board 201 into the corresponding slots on the connector 300, and then connected to the test fixture through the connector 300. In order to protect the chip 202 and prevent accidental scratches or contamination during the test and analysis process, a protective cover 207 can be covered on the front side 202a of the chip. Preferably, the protective cover 207 is avoided by reasonably setting the height and / or diameter of the pins and / or slots, so that when the pin array 203 is inserted into the corresponding slot array 301, a certain gap 209 is maintained between the protective cover 207 and the connector 300 to ensure the smooth connection and installation of the circuit board 201 and the connector 300.

[0028] In addition, since the circuit board 201 of the present invention adopts a reverse pin design, it needs to be flipped and placed on the connector 300 with the chip 202 facing downward and the pin array 203 facing downward, the connection relationship between the pad 205 to be tested of the chip 202 and the slot of the connector 300 is different from the connection relationship of the positive pin method (usually it should be mirror-symmetric). In order to better be compatible with the test environment and software of the prior art, preferably, a mapping relationship between each slot in the slot array 301 and each pin in the pin array 201 can also be formed by the control unit of the test fixture. For example, the pin A11 in the pin array 203 corresponds to the slot B11 of the slot array 301, so as to simplify the test analysis steps. Of course, those skilled in the art can also re-encode everything and re-establish the corresponding relationship between the slot in the slot array 301 and the pad 205 to be tested of the chip 202.

[0029] To summarize, the chip testing and analysis method and device of the present invention adopts a reverse needle design, and the chip to be tested and the needle array are arranged on the first side of the circuit board, and the chip is electrically connected to the test fixture through the needle array to perform electrical testing on the chip, and a light-transmitting area running through the first side and the second side is arranged on the circuit board, and the back of the chip faces the light-transmitting area so that electrical failure analysis of the chip can be performed through the second side of the circuit board, thereby reducing the difficulty of testing and analysis, improving the accuracy of testing and analysis, and increasing product yield.

[0030] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, in any case, the embodiments should be considered exemplary and non-restrictive. Furthermore, it is apparent that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The words first, second, etc. are used to indicate names and do not indicate any particular order.

Claims

1. A chip testing and analysis method, characterized in that: include: Provide test fixtures; Providing a circuit board, the circuit board having a first surface and a second surface opposite to each other, and a light-transmitting area penetrating the first surface and the second surface; A chip to be tested is arranged on the first surface of the circuit board, the front surface of the chip is electrically connected to the circuit board, and is electrically connected to the test fixture through a needle array arranged on the first surface of the circuit board, so as to perform electrical testing on the chip; The back side of the chip faces the light-transmitting area so that an electrical failure analysis can be performed on the chip through the second side of the circuit board.

2. The chip testing and analysis method according to claim 1, characterized in that: The circuit board and the test fixture are connected via a connector, and the connector is provided with a slot array corresponding to the implant pin array.

3. The chip testing and analysis method according to claim 2, characterized in that: The front side of the chip is covered with a protective cover, and when the implant needle array is inserted into the corresponding slot array, a certain gap is maintained between the protective cover and the connector.

4. The chip testing and analysis method according to claim 2, characterized in that: A mapping relationship between each slot in the slot array and each implant needle in the implant needle array is formed by the control unit of the test fixture.

5. The chip testing and analysis method according to claim 1, characterized in that: The pads on the front side of the chip are connected to the pads on the first side of the circuit board through metal wires.

6. A chip testing and analysis device, characterized in that: include: Test fixtures; A circuit board, the circuit board having a first surface and a second surface opposite to each other, and a light-transmitting area penetrating the first surface and the second surface; The first surface of the circuit board is used to set the chip to be tested, the front side of the chip is electrically connected to the circuit board, and is electrically connected to the test fixture through the implant needle array set on the first surface of the circuit board, so as to perform electrical testing on the chip; The back side of the chip faces the light-transmitting area so that an electrical failure analysis can be performed on the chip through the second side of the circuit board.

7. The chip testing and analyzing device according to claim 6, characterized in that: It also includes a connector for connecting the circuit board and the test fixture, and the connector is provided with a slot array corresponding to the implant needle array.

8. The chip testing and analyzing device according to claim 7, characterized in that: The front side of the chip is covered with a protective cover, and when the implant needle array is inserted into the corresponding slot array, a certain gap is maintained between the protective cover and the connector.

9. The chip testing and analyzing device according to claim 7, characterized in that: The test fixture comprises a control unit for forming a mapping relationship between each slot in the slot array and each implant needle in the implant needle array.

10. The chip testing and analyzing device according to claim 6, characterized in that: The pads on the front side of the chip are connected to the pads on the first side of the circuit board through metal wires.

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