Chip reliability testing device and method

Abstract

The invention provides a chip reliability test device and method, and the device comprises a test controller and a serial port output module which are electrically connected. The test controller is electrically connected with the tested chip, and the serial port output module is electrically connected with the test controller; the test controller is used for analyzing the received test program file and obtaining a corresponding test mode, and sending the obtained test mode to the tested chip so as to carry out an open / short circuit test on each pin of the tested chip; the test controller is also used for sending the test process information and the test result to the serial port output module; wherein the test mode comprises an open-short circuit pin test mode, and the test result comprises an open-short circuit test result of the tested chip; and the serial port output module is used for outputting the test process information and the test result information. According to the invention, manpower and time cost can be obviously saved, and the chip reliability test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip reliability testing, and in particular to a chip reliability testing device and method. Background Art

[0002] Chip reliability testing is an important step before a chip enters the market. When conducting chip reliability testing, not only will the chip under test experience long-term high temperature and high pressure as well as low temperature and high pressure, but the motherboard and sub-board (i.e., the sub-board and motherboard of the chip testing system, referred to as the motherboard and sub-board in this article) on which the chip under test is placed will also experience high temperature and high pressure as well as low temperature and high pressure. Long-term high temperature and high pressure as well as low temperature and high pressure will have adverse effects on chip reliability testing, such as causing aging, short circuit, open circuit, poor contact effect and other problems. Problematic motherboards and sub-boards will affect the state of the chip under test during the chip reliability test. Therefore, it is very necessary to predict the state of the motherboard and sub-board and the contact state of the chip under test with the motherboard and sub-board before the chip reliability test.

[0003] In related technologies, chip reliability testing often uses the EVB (Evaluation Board) mode, which is the normal user application mode. Since the EVB mode is closer to the actual application scenario, it is widely used. In the EVB mode, good contact between the motherboard and the chip under test is a prerequisite for chip reliability testing.

[0004] In the prior art, the commonly used method for determining whether the motherboard has a fault is to use a multimeter to measure the components or visually check whether the motherboard has physical damage during the hardware preparation stage of the reliability test to determine whether the motherboard can be used for chip reliability testing. However, this method cannot determine whether there is a contact problem between the motherboard and the chip under test, nor can it determine whether the contact state between the motherboard and the chip under test will affect the subsequent chip reliability test. In addition, this method is labor-intensive and time-consuming, and is inefficient.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide a chip reliability testing device and method to address one or more of the problems in the prior art, such as the inability to determine whether there are contact problems between the motherboard and the chip under test before the chip reliability test and the low efficiency. The present invention can quickly determine the contact status between the motherboard and the chip under test, and quickly locate the cause of the contact problem, thereby laying a good foundation for subsequent chip reliability testing, thereby improving the efficiency of the chip reliability test and saving manpower and material resources.

[0007] To achieve the above object, the present invention is implemented by the following technical scheme: a chip reliability test device, the chip reliability test device comprises an electrically connected test controller and a serial port output module; the test controller is electrically connected to the chip under test;

[0008] The test controller is used to parse the received test program file and obtain the corresponding test mode, and send the obtained test mode to the chip under test to perform an open-short circuit test on each pin of the chip under test; the test controller is also used to send the test process information and the test result to the serial port output module; wherein the test mode includes an open-short circuit pin test mode, and the test result includes an open-short circuit test result of the chip under test;

[0009] The serial port output module is used to output the test process information and the test result information.

[0010] Optionally, the test mode also includes a logic module status detection mode and a reliability detection mode;

[0011] The test controller is used to send the acquired logic module state detection mode to the chip under test to test the contact state between the chip under test and the daughter board of the chip test system and the mother board; and / or the test controller is used to send the acquired reliability detection mode to the chip under test to perform reliability test on the chip under test;

[0012] The test controller is further used to send the test result information to the serial port output module; wherein the test result information also includes contact status information between the chip under test and the motherboard and / or reliability test result information.

[0013] Optionally, the test controller is electrically connected to the chip under test via a JTAG interface;

[0014] The test controller is used to send the acquired test mode to the chip under test, including: sending the test mode and a test vector corresponding to the test mode to the chip under test;

[0015] The test controller inputs the test vector to the chip under test through the TDI of the JTAG interface, and receives the test process information and the test result fed back by the chip under test through the TDO of the JTAG interface.

[0016] Optionally, the test controller further includes a test mode control module and an instruction decoding circuit corresponding to the test mode, wherein:

[0017] The corresponding test mode control module is configured to generate a test stimulus control signal corresponding to the test mode under the control of the test clock input signal and the test mode selection signal of the JTAG interface;

[0018] The instruction decoding circuit is used to parse the test stimulus control signal and the test instruction to obtain the test mode;

[0019] The corresponding test mode control module parses the test program file to generate the test vector corresponding to the test mode.

[0020] Optionally, the chip reliability testing device also includes a human-computer interaction module electrically connected to the test controller, and the human-computer interaction module is used to configure test parameters and / or input the test program file into the test controller; the test parameters include: the operating frequency of the chip under test, the operating voltage of the chip under test, the test start address, the test end address and the test data.

[0021] Optionally, the test controller is arranged on a motherboard of the chip test system.

[0022] Optionally, the chip reliability testing device and the chip testing system host computer are used to output the test result information.

[0023] In order to achieve the above object, the present invention further provides a chip reliability testing method, the chip reliability testing method comprising:

[0024] Parsing the received test program file and acquiring a corresponding test mode, wherein the test mode includes an open-short pin test mode;

[0025] According to the acquired test mode, an open-short circuit test is performed on each pin of the chip under test; wherein the test result includes an open-short circuit test result of the chip under test;

[0026] The test process information and the test result information are output through a serial port output module.

[0027] Optionally, the test mode further includes a logic module state detection mode and a reliability detection mode; the test result information further includes contact state information between the chip under test and the motherboard and / or reliability test result information;

[0028] Before outputting the test process information and the test result information through the serial port output module, the chip reliability test method further includes:

[0029] When the acquired test mode is a logic module status detection mode, the contact status between the chip under test and the daughter board and the mother board is tested; and / or when the acquired test mode is a reliability detection mode, the reliability test is performed on the chip under test.

[0030] Optionally, before testing the contact state between the chip under test and the daughter board and the mother board or performing reliability testing on the chip under test, the chip reliability testing method further includes:

[0031] Set test parameters; the test parameters include: the working frequency of the chip under test, the working voltage of the chip under test, the test start address, the test end address and the test data.

[0032] Compared with the prior art, the chip reliability testing device and method provided by the present invention have the following beneficial effects:

[0033] The chip reliability test device provided by the present invention sends the acquired test mode to the chip under test through the test controller to perform an open-short circuit test on each pin of the chip under test; the test controller sends the test process information and the test result to the serial port output module, and the serial port output module outputs the test process information and the test result information. The tester can judge the pin function status of the chip under test without relying on the ATE (Automatic Test Equipment, integrated circuit automatic test machine) machine, so as to quickly locate whether the chip under test has an open-short circuit problem before the chip reliability test begins, which lays a solid foundation for ensuring the reliability test of the chip under test and can improve the reliability test efficiency. Further, the chip reliability test device provided by the present invention has a simple structure and is easy to implement, and does not need to change the existing mother-child board connection method, and will not increase the modification cost. Further, the chip reliability test device provided by the present invention does not rely on the host computer interface to query the chip status, so even if the host computer unexpectedly flashes back and the monitoring test status is abnormal, the serial port output module can also output the test process information and the test result information, which is more convenient for the tester to obtain the test status and the test result.

[0034] Furthermore, in the chip reliability testing device provided by the present invention, the test mode also includes a logic module state detection mode and a reliability detection mode; the test controller is used to send the acquired logic module state detection mode to the chip under test to test the contact state between the chip under test and the sub-board and the motherboard; the test controller is also used to send the test result information to the serial port output module; the test result information also includes the contact state between the chip under test and the sub-motherboard. Therefore, the chip reliability testing device provided by the present invention can quickly determine whether there is a problem with the contact state between the chip under test and the sub-motherboard before the chip reliability test begins, which lays a solid foundation for further ensuring the reliability test of the chip under test and can further improve the efficiency of the reliability test.

[0035] In summary, the chip reliability testing device provided by the present invention realizes the self-check of the contact status between the motherboard and the chip under test, which can significantly save manpower and time costs and improve the efficiency of chip reliability testing.

[0036] Since the chip reliability testing method provided by the present invention and the chip reliability testing device provided by the present invention belong to the same inventive concept, the chip reliability testing method provided by the present invention at least has all the advantages of the chip reliability testing device provided by the present invention. For more details, please refer to the relevant description of the advantages of the chip reliability testing device provided by the present invention above. Here, they will not be described one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of a chip reliability testing device provided by one embodiment of the present invention;

[0038] Figure 2 A specific example diagram of using the chip reliability testing device provided by the present invention to perform chip reliability testing;

[0039] Figure 3 A schematic flow chart of a chip reliability testing method provided by another embodiment of the present invention;

[0040] Figure 4 A specific example diagram of the chip reliability testing method provided by the present invention;

[0041] The reference numerals are described as follows:

[0042] Motherboard-110, daughterboard-120, host computer-130, test controller-210, test mode control module-211, instruction decoding circuit-212|, serial port output module-220, human-computer interaction module-230;

[0043] Chip under test - DUT, test clock input signal - TCK, test mode selection signal - TMS, test data input channel - TDI, test data output channel - TDO, test stimulus control signal - update, clock, shift. DETAILED DESCRIPTION

[0044] In order to make the purpose, advantages and features of the present invention clearer, the chip reliability testing device and method proposed in the present invention are further described in detail in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific environment to be applied and used. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0045] Where appropriate, these terms used in this way are interchangeable. Similarly, if the method described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that when an element is referred to as being "electrically connected," "connected to," or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. On the contrary, when an element is referred to as being "directly connected to" other elements, there is no intervening element.

[0046] In order to facilitate a better understanding of the present invention, before specifically describing the chip reliability testing device and method proposed in the present invention, the research process of the chip reliability testing device and method proposed in the present invention is roughly described as follows:

[0047] After investigation, it was found that when the relevant technology is conducting chip reliability testing, the daughterboard and the motherboard of the chip testing system are mostly connected through a device called "board-to-board connector". This connection method can conveniently and flexibly support reliability testing of chips of various packaging types and sizes. Although the convenient plug-in and unplug method can support the testing of chips of various packaging types, it has been found through research that the disadvantages of this connection method are also obvious. Repeated plug-in and unplugging accelerates the wear between the daughterboard and the board-to-board connector and between the board-to-board connector and the test motherboard. Wear can cause many problems, such as poor contact between the daughterboard and the motherboard, and poor contact between the chip under test and the daughterboard. In order to ensure that the reliability test can proceed smoothly, it is often necessary to manually use a multimeter to measure the components or visually check whether the daughterboard and the motherboard are physically damaged to determine whether the daughterboard and the motherboard can be used for chip reliability testing, which greatly reduces the test efficiency of the chip under test. Furthermore, the motherboard, board-to-board connector, daughter board and chip under test all need to experience high temperature and high pressure as well as low temperature and high pressure. Long-term high temperature and high pressure or low temperature and high pressure will cause aging of the motherboard, board-to-board connector and daughter board, resulting in short circuit, open circuit and poor contact between the chip under test and the chip testing system, which will also increase the difficulty of chip reliability testing.

[0048] However, there is currently no better alternative to replace the connection method between the daughter board and the motherboard through the board-to-board connector. Based on this, the core idea of ​​the present invention is to optimize the detection method of the contact status between the daughter board and the motherboard and the chip under test, so as to solve the problem of low efficiency in judging whether the daughter board and the motherboard can be used for chip reliability testing before chip reliability testing in the prior art.

[0049] In order to realize the above idea, the present invention provides a chip reliability testing device and method, which can quickly determine the contact status between the motherboard and the chip under test, and quickly locate the cause of the contact problem, thereby laying a good foundation for subsequent chip reliability testing, thereby improving the efficiency of chip reliability testing and saving manpower and material resources.

[0050] The specific implementation of the reliability testing device and method provided by the present invention is described in detail below.

[0051] One embodiment of the present invention provides a reliability testing device for a chip testing system. Figure 1 and Figure 2 ,in, Figure 1 The structure diagram of the chip reliability testing device provided in this embodiment is schematically given. Figure 2 A specific example diagram of using the chip reliability testing device provided by the present invention to perform chip reliability testing is schematically provided. Figure 1It can be seen that the chip test system includes a motherboard 110 and at least one daughterboard 120 arranged on the motherboard 110, and the chip under test DUT is electrically connected to the motherboard 110 through the daughterboard 120. The reliability test device provided in this embodiment includes an electrically connected test controller 210 and a serial port output module 220 (such as a serial port assistant, etc.); the test controller 210 is electrically connected to the chip under test DUT. Specifically, the test controller 210 is used to parse the received test program file and obtain the corresponding test mode, and send the obtained test mode to the chip under test DUT to perform an open-short circuit test on each pin of the chip under test DUT; the test controller 210 is also used to send the test process information and the test result to the serial port output module 220; wherein, the test mode includes an open-short circuit pin test mode, and the test result includes an open-short circuit test result of the chip under test DUT; the serial port output module 220 is used to output the test process information and the test result information.

[0052] It can be seen that the chip reliability test device provided in this embodiment sends the acquired test mode to the chip DUT under test through the test controller 210 to perform an open and short circuit test on each pin of the chip DUT under test; the test controller 210 sends the test process information and the test result to the serial port output module 220, and the serial port output module 220 outputs the test process information and the test result information. The tester can judge the pin function status of the chip DUT under test without relying on the ATE (Automatic Test Equipment, integrated circuit automatic test machine) machine, so as to quickly locate whether the chip DUT under test has an open and short circuit problem before the chip reliability test begins, which lays a solid foundation for ensuring the reliability test of the chip DUT under test and can improve the reliability test efficiency. Furthermore, the chip reliability test device provided in this embodiment has a simple structure and is easy to implement, and does not need to change the existing connection method of the motherboard 110, and will not increase the modification cost. Furthermore, the chip reliability testing device provided in this embodiment does not rely on the host computer 130 interface to query the chip status. Therefore, even if the host computer 130 crashes unexpectedly and the monitoring test status is abnormal, the serial port output module 220 can still output the test process information and test result information, making it easier for the tester to obtain the test status and test results (for example, when the host computer 130 fails, the test status and test results can be obtained through the serial port output module 220). In summary, the chip reliability testing device provided in this embodiment realizes the self-check of the contact status between the motherboard 110 and the chip under test DUT, which can significantly save manpower and time costs and improve the efficiency of chip reliability testing.

[0053] It should be noted that those skilled in the art should be able to understand that the present invention does not limit the specific implementation of the test controller 210, which can be implemented in hardware or software, preferably, it can be implemented in a combination of software and hardware. Exemplarily, the test controller 210 can be implemented in the form of FPGA (Field Programmable Gate Array, programmable logic device) or MCU (Microcontroller Unit, micro control unit, such as a 32-bit MCU). For more detailed information about the working principle of FPGA or the working principle of MCU, please refer to the relevant technical adaptability understanding known to those skilled in the art. Here, due to space limitations, no further details will be given. Further, the present invention does not limit the specific input method of the test program file received by the test controller 210. Exemplarily, in some embodiments, it can be input through the human-computer interaction module 230 described below (for example, the tester inputs the test program file through the human-computer interaction module 230); in some other embodiments, it can also be input through the host computer of the chip test system; in other embodiments, it can also be pre-stored in the storage module of the test controller 210. Furthermore, the present invention does not limit the specific format and content of the test program file. In fact, those skilled in the art should be able to understand that as long as the parsing method of the test controller 210 corresponds to the format of the test program file. The content of the test program file is related to the purpose of the test. For example, if an open-short circuit test is performed, the content of the test program file should include an open-short circuit test. No further explanation is given here. However, it is important that the test program file includes information related to the test mode so that the test controller 210 can obtain the test mode through parsing.

[0054] It should be further explained that, as can be understood by those skilled in the art, the chip reliability testing device provided by the present invention does not impose too many restrictions on the number of daughter boards 120 connected to the mother board 110 and the layout of the daughter boards 120. In other words, Figure 1 and Figure 2Although the example of 10 sub-boards 120 on the motherboard 110 is used, it is obvious that this is only an exemplary description and not a limitation of the present invention. In other embodiments, the number of the sub-boards 120 can also be any value other than 10, such as 1, 2, 3, or more. Further, the chip reliability test device provided by the present invention does not limit the type of the chip DUT under test. In some embodiments, the chip DUT under test can be a microcontroller. For example, the microcontroller can include but is not limited to CPU, GPU, FPGA, MCU and AI, etc.; in other embodiments, the chip DUT under test can be a storage chip. For example, the storage chip can include but is not limited to DRAM, SDRAM, ROM, NAND and FLASH, etc. In some other embodiments, the chip DUT under test can also be a sensing chip. For example, the sensing chip can include but is not limited to MEMS, fingerprint, microphone and camera, etc. Of course, the chip DUT under test can also be a communication chip, such as Bluetooth, WIFI, NB-IOT, broadband, USB interface, Ethernet interface, HDMI interface and drive control chip, etc. In addition, the chip under test DUT can also be an energy chip, such as a power chip, DC-AC and LDO, etc., which are not listed one by one. Furthermore, the present invention does not limit the specific application field of the chip under test DUT. For example, the chip under test DUT is a microcontroller, and the chip under test DUT can be but not limited to industrial control microcontrollers, automotive electronic microcontrollers, home appliance microcontrollers, and smart wearable microcontrollers.

[0055] Please continue to see Figure 1 In some exemplary implementations, the test controller 210 is disposed on the motherboard 110. Therefore, the chip reliability test device provided in this embodiment adopts the design mode that the test controller 210 is disposed on the motherboard 110, and does not need to change the structure of the existing chip test system too much, and does not increase the size of the overall structure of the chip test system. This compact design mode does not increase the complexity of the chip reliability test, thereby laying a good foundation for improving the efficiency of the chip reliability test.

[0056] It should be noted that, as those skilled in the art can understand, this is merely an exemplary description of a preferred embodiment, and not a limitation of the present invention. In other embodiments, the test controller 210 may not be disposed on the motherboard 110, for example, it may be disposed separately on an auxiliary test board.

[0057] Preferably, in some exemplary implementations, the test mode also includes a logic module status detection mode; in some specific examples, the test controller 210 is used to send the acquired logic module status detection mode to the chip under test DUT to test the contact status between the chip under test DUT and the sub-board 120 and the sub-mother board 110. The test controller 210 is also used to send the test result information to the serial port output module 220; at this time, the test result information also includes the contact status information between the chip under test DUT and the sub-mother board 110. It can be seen that the chip reliability testing device provided in this embodiment can quickly determine whether there is a problem with the contact status between the chip under test DUT and the sub-mother board 110 before the chip reliability test begins, which lays a solid foundation for further ensuring the reliability test of the chip under test DUT and can further improve the reliability test efficiency. Specifically, after confirming that the contact state between the chip DUT under test and the motherboard 110 is good, the reliability test of the chip DUT under test can be performed, which can ensure that the test result of the reliability test of the chip DUT under test is only related to the reliability of the chip DUT under test. Correspondingly, if the test result of the contact state test between the chip DUT under test and the motherboard 110 is that there is a contact problem, the reliability test of the chip DUT under test can be performed after the contact problem is solved, thereby improving the accuracy of the test result of the reliability test of the chip DUT under test.

[0058] In some other specific examples, the test mode also includes a reliability detection mode; the test controller 210 is used to send the obtained reliability detection mode to the chip under test DUT to perform a reliability test on the chip under test DUT. Correspondingly, the test controller 210 is also used to send the test result information to the serial port output module 220; wherein the test result information also includes reliability test result information.

[0059] Configured in this way, the chip reliability testing device provided by the present invention can also perform chip reliability testing by determining the test mode, and can output test process information and test result information through the serial port output module 220, thereby overcoming the deficiency in the prior art that the host computer 130 can only display the current test status results and the test status results of each chip under test DUT, but cannot display the test process information, and is more conducive to the tester to quickly and accurately locate the problem when performing chip reliability testing.

[0060] Please continue to see Figure 1In some exemplary embodiments, the test controller 210 is electrically connected to the chip under test DUT via a JTAG interface (not shown in the figure). The test controller 210 is used to send the acquired test mode to the chip under test DUT, including: sending the test mode and the test vector corresponding to the test mode to the chip under test DUT; wherein the test controller 210 inputs the test vector to the chip under test DUT via the TDI (i.e., test data input channel) of the JTAG interface, and receives the test process information and the test result fed back by the chip under test DUT via the TDO (i.e., test data output channel) of the JTAG interface. Therefore, the chip reliability test device provided by the present invention, in which the test controller 210 is electrically connected to the chip under test DUT via a JTAG interface (not shown in the figure), is more convenient for information interaction with the chip under test DUT, and this modular design method makes better use of the implementation and application of the chip reliability test device provided by the present invention.

[0061] It should be noted that JTAG (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible), mainly used for chip internal testing. For more details about the JTAG interface, please refer to the relevant technologies known to those skilled in the art. Due to space limitations, it will not be described in detail here.

[0062] Please continue to see Figure 2In some exemplary embodiments, the test controller 210 further includes a test mode control module 211 and an instruction decoding circuit 212 corresponding to the test mode. Wherein: the corresponding test mode control module 211 is configured to generate test stimulus control signals update, clock, shift corresponding to the test mode under the control of the test clock input signal TCK and the test mode selection signal TMS of the JTAG interface; the instruction decoding circuit 212 is used to parse the test stimulus control signals update, clock, shift and the test instructions to obtain the test mode; the corresponding test mode control module 211 parses the test program file to generate the test vector corresponding to the test mode. Specifically, the test stimulus control signals update, clock, shift and the test instructions are decoded by the instruction decoding circuit 212 to form the test mode, and the corresponding test vector is input by the test data input channel TDI, and the test data is finally output through the test data output channel TDO. In addition, as can be understood by those skilled in the art, the test instruction is obtained by parsing the program file under test by the test mode control module 211. The test mode control module 211 is located between the pins of the chip under test DUT and the core logic inside the chip under test DUT. Therefore, this modular design method further utilizes the implementation and application of the chip reliability test device provided by the present invention.

[0063] In addition, as a preference, the test mode control module 211 may be a hardware unit of the test controller 210 disposed between the pins of the chip under test DUT and the internal logic processing module (such as a test logic processing unit) of the chip under test DUT. Exemplarily, the test mode control module 211 may be a DBM (digital boundary scan unit) and an ABM (analog boundary scan unit), etc. For more details about DBM and ABM, please refer to the prior art known to those skilled in the art, which will not be described here due to space limitations.

[0064] It should be particularly noted that, for the test controller 210, the number of the test mode control modules 211 can be one, two or three, and the number of the test mode control modules 211 is closely related to the test modes that the test controller 210 can support. More specifically, the number of the test mode control modules 211 corresponds one-to-one to the test modes that the test controller 210 can support.

[0065] Specifically, the test controller 210 (more specifically, the test mode control module 211) is the core module for detecting the state of the reliability test chip and controls the state of the entire test cycle. Its basic working principle is that under the control of the timing signal of the test clock input signal TCK and the test mode selection signal TMS, the test controller 210 can switch the state. The specific switching method is: when the test clock input signal TCK is at the rising edge, when the high and low levels of the test mode selection signal TMS change, the state of the test controller 210 also changes accordingly. In the process of converting between different states, the test controller 210 will also generate corresponding test stimulus control signals update, clock, shift (see Figure 2 ), and these test stimulus control signals update, clock, and shift are moved into the control bus of the corresponding chip under test DUT (i.e. Figure 2 The internal bus of the chip under test DUT in the test) controls the working status of these chips under test DUT, transmits the corresponding output feedback through the test data output port, and finally outputs the test process information and test result information through the serial port output module 220.

[0066] More specifically, a chip under test DUT (such as a microcontroller) with a JTAG Debug port can access the internal registers of the microcontroller and the registers of its built-in modules, such as UART, Timers, GPIO, etc., through the JTAG interface as long as the clock is normal. Taking the boundary scan technology as an example, its basic idea is to add an instruction register and a data register to the input / output pins of the test controller 210 close to the chip under test DUT. As can be understood by those skilled in the art, the instruction register may include a shift register or a scan register, and the data register may include a boundary scan register (Boundary-Scan Register), etc. The boundary scan registers on the input / output pins of the chip under test DUT can be connected to each other, so that a boundary scan chain (Boundary-Scan Chain) is formed around the chip under test DUT. The boundary scan chain can be serially input and output, and through the corresponding clock signal and control signal, the chip under test DUT in the debugging state can be easily observed and controlled.

[0067] Please continue to see Figure 1 ,from Figure 1It can be seen that the chip reliability test device provided by some exemplary embodiments further includes a human-computer interaction module 230 electrically connected to the test controller 210, and the human-computer interaction module 230 is used to configure test parameters and / or input the test program file to the test controller 210; the test parameters include but are not limited to the working frequency of the chip DUT under test, the working voltage of the chip DUT under test, the test start address, the test end address and the test data. Therefore, through the human-computer interaction module 230, it is more convenient to control the reliability test of the chip DUT under test according to different test modes, thereby further improving the test efficiency of the chip reliability test.

[0068] It should be noted that those skilled in the art should be able to understand that the present invention does not limit the specific implementation of the human-computer interaction module 230. Specifically, the human-computer interaction module 230 can be but not limited to a touch screen, a keyboard, a mouse, a voice input, etc. Further, in some embodiments, the human-computer interaction module 230 can also be integrated on the host computer 130 of the chip test system.

[0069] Please continue to see Figure 1 ,from Figure 1 It can be seen that some of the exemplary embodiments provide chip reliability testing devices further including a host computer 130 for outputting the test result information. The host computer 130 is preferably a host computer 130 of a chip testing system, and preferably, the host computer 130 is electrically connected to the motherboard 110 .

[0070] In order to facilitate the understanding of the present invention, the following is a brief description of the method for using the chip reliability testing device provided by the present invention:

[0071] First, the chip reliability test device provided by the present invention is connected to the chip test system and powered on, the package of the chip DUT under test is selected through the human-computer interaction module 230, and then the power supply and ground pins are input through the human-computer interaction module 230, and then the test mode of the chip DUT under test is determined to be the open short circuit pin test mode, that is, the chip DUT under test is subjected to an OS (Open Short, open short circuit) test. The test process information and the test results are output through the serial port output module 220, and it can be determined whether each pin of the chip DUT under test has an open short circuit problem according to the output of the serial port output module 220. If not (for example, the serial port output module 220 does not output Fail), it is determined that the chip DUT under test is placed correctly, and each pin of the chip DUT under test functions normally, and the test of other modes can be continued.

[0072] Next, if it is determined that the chip DUT under test is placed correctly, the functions of each pin of the chip DUT under test are correct. The test mode of the chip DUT under test can be determined to be a logic module state detection mode through the human-computer interaction module 230, that is, the contact state between the chip DUT under test and the sub-board 120 and the mother-sub board 110 is tested. The chip reliability test device provided by the present invention is connected to the chip test system and powered on (if the chip reliability test device has been connected and powered on, this step can be omitted), and the test parameters are configured through the human-computer interaction module 230, wherein the test parameters include but are not limited to the operating frequency of the chip DUT under test, the operating voltage of the chip DUT under test, the test start address, the test end address and the test data. Then, the test program can be run, and the test vector is transmitted through the JTAG interface, and the test process information and the test results are output through the serial port output module 220. According to the output of the serial port output module 220, it can be determined whether there is a contact problem between the chip DUT under test and the test mother-sub board 110. If it does exist (for example, the serial port output module 220 outputs Fail), it can be determined that there is a contact problem between the chip DUT under test and the motherboard 110. Next, the problem can be located and solved based on the test process information output by the serial port output module 220, until it is determined that there is no contact problem between the chip DUT under test and the test motherboard 110, and the chip reliability test can continue.

[0073] Finally, if it is determined that the contact between the chip DUT under test and the test motherboard 110 is good, the reliability test of the chip DUT under test is performed. As mentioned above, the chip reliability test device provided by the present invention is connected to the chip test system and powered on (if the chip reliability test device has been connected and powered on, this step can be omitted), the test mode of the chip DUT under test can be determined to be a reliability detection mode through the human-computer interaction module 230, and the test parameters are configured through the human-computer interaction module 230, then the test program can be run, and the test vector is transmitted through the JTAG interface, and the test process information and test results are output through the serial port output module 220. According to the output of the serial port output module 220, it can be determined whether the reliability of the chip DUT under test meets the requirements. For more detailed information about the chip reliability test, please refer to the related technology known to those skilled in the art, which will not be described here. However, it should be emphasized that the reliability test of the related technology relies on the host computer 130 to display the current test status results and the status results of each chip DUT under test. It cannot reflect the current test process and test module process. Moreover, the host computer 130 may crash, freeze, or stop working due to poor robustness, network and other environmental factors. However, when the chip test system with the chip reliability test device provided by the present invention is used, the tester can still use the serial port output module 220 to see the test process information of the module and output the test process information and test results through the serial port output module 220, which is more convenient to quickly locate and solve the problem.

[0074] Another embodiment of the present invention provides a chip reliability testing method. Specifically, see Figure 3 ,from Figure 3 It can be seen that the chip reliability testing method provided in this embodiment includes:

[0075] S100: parsing a received test program file and acquiring a corresponding test mode, wherein the test mode includes an open-short pin test mode;

[0076] S210: performing an open-short circuit test on each pin of the chip under test according to the acquired test mode; wherein the test result includes an open-short circuit test result of the chip under test;

[0077] S300: Output the test process information and the test result information through a serial port output module.

[0078] Since the chip reliability testing method provided in this embodiment and the chip reliability testing device provided in the above embodiment belong to the same inventive concept, the chip reliability testing method provided in this embodiment at least has all the advantages of the chip reliability testing device provided in the above embodiment. For more details, please refer to the relevant description of the advantages of the chip reliability testing device provided in the above embodiment. Here, no further description will be given. Preferably, the chip reliability testing method provided in the present invention can be applied to the chip reliability testing device provided in the present invention.

[0079] Please continue to see Figure 3 In some exemplary embodiments, the test mode also includes a logic module state detection mode and a reliability detection mode; the test result information also includes contact state information between the chip under test and the motherboard and / or reliability test result information. Correspondingly, before outputting the test process information and the test result information through the serial port output module in step S300, the chip reliability test method also includes step S220 and / or step S230:

[0080] Wherein, step S220 specifically includes: when the test mode obtained is the logic module state detection mode, the contact state between the chip under test and the daughter board and the mother board is tested. Step S230 specifically includes: when the test mode obtained is the reliability detection mode, the reliability test is performed on the chip under test.

[0081] It should be noted that, as mentioned above, the present invention does not limit the test program file. Figure 3 As shown, the type of the test program file corresponds to the test mode one by one. When the test program file received by the test controller is an open-short pin test program file, the test mode obtained by parsing is an open-short pin test mode; when the test program file received by the test controller is a logic module status detection program file, the test mode obtained by parsing is a logic module status detection mode; when the test program file received by the test controller is a reliability detection program file, the test mode obtained by parsing is a reliability detection mode.

[0082] Preferably, before testing the contact state between the chip under test and the daughter board and the mother board or performing reliability testing on the chip under test, the chip reliability testing method further includes:

[0083] S211: Setting test parameters; the test parameters include: operating frequency of the chip under test, operating voltage of the chip under test, test start address, test end address and test data.

[0084] It should be noted that, those skilled in the art should be able to understand that the chip reliability testing method provided in this embodiment has the same basic principle as the chip reliability testing device provided in the above embodiment. In order to avoid redundancy, it will not be expanded here. For more detailed content, please refer to the relevant description of the chip reliability testing device above for adaptability understanding.

[0085] In order to make it easier to understand the reliability testing method provided by the present invention, a specific example of applying the chip reliability testing method provided by the present invention to the chip reliability testing device provided by the present invention is briefly described as follows.

[0086] Specifically, see Figure 4 , which schematically shows a specific example diagram of the chip reliability testing method provided by the present invention. Figure 4 It can be seen that after the chip reliability test device is connected to the chip test system and powered on, it can enter the test mode (exemplarily, by inputting different test program files) to select the required test mode control module for verification testing. For example, if the input test program file is an open-short pin test program file, an open-short test is performed; if the input test program file is a logic module status detection program file, an initialization logic module status test is performed (i.e., the contact status between the chip under test and the sub-board and the mother-sub-board is tested); if the input test program file is a reliability detection program file, a reliability test is performed on the chip under test. As the core module for detecting the status of the reliability test chip, the test controller can parse the test program file through the test mode control module and the instruction decoding circuit, so as to realize different test processes: specifically, the test controller obtains the test information, the basic information of the chip under test and the test mode, etc., generates the corresponding test vector, and then inputs the test vector into the corresponding chip under test through the test data input channel, so that the chip under test executes the test vector and outputs the test information through the test data output channel. Finally, the test process information and test results received by the serial port output module can be displayed (for example, through the PC side), and the test ends.

[0087] It should be noted that for more detailed information about the test vector, please refer to the relevant technologies known to those skilled in the art. Due to limited space, the description will not be expanded.

[0088] It can be seen that the chip reliability testing device and method provided by the present invention have the following beneficial effects:

[0089] 1. The chip reliability test device provided by the present invention sends the acquired test mode to the chip under test through the test controller to perform an open-short circuit test on each pin of the chip under test; the test controller sends the test process information and the test result to the serial port output module, and the serial port output module outputs the test process information and the test result information. The tester can judge the pin function status of the chip under test without relying on the ATE (Automatic Test Equipment, integrated circuit automatic test machine) machine, so as to quickly locate whether the chip under test has an open-short circuit problem before the chip reliability test begins, which lays a solid foundation for ensuring the reliability test of the chip under test and can improve the reliability test efficiency.

[0090] 2. The chip reliability test device provided by the present invention has a simple structure and is easy to implement, and does not require changes to the existing mother-sub board connection method, which does not increase the modification cost. Furthermore, the chip reliability test device provided by the present invention does not rely on the host computer interface to query the chip status. Therefore, even if the host computer unexpectedly crashes and the monitoring test status is abnormal, the serial port output module can output the test process information and test result information, which is more convenient for the tester to obtain the test status and test results.

[0091] 3. The chip reliability test device provided by the present invention, the test mode also includes a logic module state detection mode and a reliability detection mode; the test controller is used to send the acquired logic module state detection mode to the chip under test to test the contact state between the chip under test and the sub-board and the motherboard; the test controller is also used to send the test result information to the serial port output module; the test result information also includes the contact state between the chip under test and the sub-motherboard. Therefore, the chip reliability test device provided by the present invention can quickly determine whether there is a problem with the contact state between the chip under test and the sub-motherboard before the chip reliability test begins, which lays a solid foundation for further ensuring the reliability test of the chip under test and can further improve the efficiency of reliability testing.

[0092] In summary, the chip reliability testing device provided by the present invention realizes the self-check of the contact status between the motherboard and the chip under test, which can significantly save manpower and time costs and improve the efficiency of chip reliability testing.

[0093] Since the chip reliability testing method provided by the present invention and the chip reliability testing device provided by the present invention belong to the same inventive concept, the chip reliability testing method provided by the present invention at least has all the advantages of the chip reliability testing device provided by the present invention. For more details, please refer to the relevant description of the advantages of the chip reliability testing device provided by the present invention above. Here, they will not be described one by one.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0095] In summary, the above embodiments have detailed descriptions of different configurations of chip reliability testing devices and methods. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention, and are not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the scope of protection of the claims.

Claims

1. A chip reliability testing device, characterized in that: Used in a chip testing system, the chip reliability testing device comprises an electrically connected test controller and a serial port output module; The test controller is electrically connected to the chip under test; The test controller is used to parse the received test program file and obtain the corresponding test mode, and send the obtained test mode to the chip under test to perform an open-short circuit test on each pin of the chip under test; The test controller is also used to send the test process information and the test result to the serial port output module; wherein the test mode includes an open-short circuit pin test mode, and the test result includes an open-short circuit test result of the chip under test; The serial port output module is used to output the test process information and the test result information.

2. The chip reliability testing device according to claim 1, characterized in that: The test mode also includes a logic module status detection mode and a reliability detection mode; The test controller is used to send the acquired logic module state detection mode to the chip under test to test the contact state between the chip under test and the daughter board and the mother board of the chip test system; and / or the test controller is used to send the acquired reliability detection mode to the chip under test to perform reliability test on the chip under test; The test controller is further used to send the test result information to the serial port output module; wherein the test result information also includes contact status information between the chip under test and the motherboard and / or reliability test result information.

3. The chip reliability testing device according to claim 1, characterized in that: The test controller is electrically connected to the chip under test via a JTAG interface; The test controller is used to send the acquired test mode to the chip under test, including: sending the test mode and a test vector corresponding to the test mode to the chip under test; The test controller inputs the test vector to the chip under test through the TDI of the JTAG interface, and receives the test process information and the test result fed back by the chip under test through the TDO of the JTAG interface.

4. The chip reliability testing device according to claim 3, characterized in that: The test controller further includes a test mode control module and an instruction decoding circuit corresponding to the test mode, wherein: The corresponding test mode control module is configured to generate a test stimulus control signal corresponding to the test mode under the control of the test clock input signal and the test mode selection signal of the JTAG interface; The instruction decoding circuit is used to parse the test stimulus control signal and the test instruction to obtain the test mode; The corresponding test mode control module parses the test program file to generate the test vector corresponding to the test mode.

5. The chip reliability testing device according to claim 1, characterized in that: It also includes a human-computer interaction module electrically connected to the test controller, the human-computer interaction module is used to configure test parameters and / or input the test program file to the test controller; The test parameters include: the working frequency of the chip under test, the working voltage of the chip under test, the test start address, the test end address and the test data.

6. The chip reliability testing device according to any one of claims 1 to 5, characterized in that: The test controller is arranged on the motherboard of the chip test system.

7. The chip reliability testing device according to claim 1, characterized in that: The host computer of the chip testing system is also used to output the test result information.

8. A chip reliability testing method, characterized in that: include: Parsing the received test program file and acquiring a corresponding test mode, wherein the test mode includes an open-short pin test mode; According to the acquired test mode, an open-short circuit test is performed on each pin of the chip under test; wherein the test result includes an open-short circuit test result of the chip under test; The test process information and the test result information are output through a serial port output module.

9. The chip reliability testing method according to claim 8, characterized in that: The test mode also includes a logic module state detection mode and a reliability detection mode; the test result information also includes contact state information between the chip under test and the motherboard and / or reliability test result information; Before outputting the test process information and the test result information through the serial port output module, the chip reliability test method further includes: When the acquired test mode is a logic module state detection mode, the contact state between the chip under test and the daughter board and the mother board is tested; And / or when the acquired test mode is a reliability detection mode, a reliability test is performed on the chip under test.

10. The chip reliability testing method according to claim 8, characterized in that: Before testing the contact state between the chip under test and the daughter board and the mother board or performing reliability testing on the chip under test, the chip reliability testing method further includes: Set test parameters; the test parameters include: the working frequency of the chip under test, the working voltage of the chip under test, the test start address, the test end address and the test data.

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