Chip testing method and system, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a chip testing method and system, electronic equipment and a storage medium, and the method comprises the steps that a signal codec sends a first level data stream received from a testing terminal to a parser of a chip through a first pin; the analyzer sends a first level signal to the at least one processing module according to the first level data stream, and then receives a second level data stream sent by the analyzer through the first pin, and the second level data stream is obtained by coding according to a second level signal received from the at least one processing module by the signal codec; and the second level data stream is sent to the test terminal, so that the levels of various signals in the chip are written and read through the first pin in the chip test process, the pins required for testing the internal module of the chip are reduced, and the chip test can be carried out on the chip with fewer external pins.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing method, system, electronic equipment and storage medium. Background Art

[0002] During chip testing, it is usually necessary to read and write the levels of various internal signals. The traditional method is to connect the signals of various internal IPs (modules) to the chip pins, and then input and output level signals and clock signals on the pins.

[0003] However, when signal interactions between modules are frequent, this method requires a large number of pins, which is difficult to implement on chips with a limited number of pins. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a chip testing method, system, electronic device and storage medium that overcome the above problems or at least partially solve the above problems.

[0005] In order to solve the above problem, an embodiment of the present invention discloses a chip testing method, characterized in that the chip includes a parser, at least one processing module and a first pin, the parser is connected to each of the processing modules, the parser is connected to a signal codec through the first pin, the first pin is used to transmit a level data stream, the method is applied to the signal codec, and the method includes:

[0006] Receive the string data sent by the test terminal;

[0007] When the character string data is identified as a level data stream, sending a first level data stream to the parser through the first pin, so that the parser sends a first level signal to the at least one processing module according to the first level data stream;

[0008] receiving a second level data stream sent by the parser, where the second level data stream is obtained by the parser through encoding according to a second level signal received from the at least one processing module;

[0009] The second level data stream is sent to the test terminal.

[0010] Optionally, the chip further includes a second pin, the second pin is used to output a clock signal, the signal codec is connected to the parser via the second pin, and the method further includes:

[0011] When the character string data is identified as a control command, the working state of the second pin is controlled according to the control command.

[0012] Accordingly, an embodiment of the present invention discloses a chip testing method, wherein the chip includes a parser, at least one processing module and a first pin, wherein the parser is connected to each of the processing modules, and the parser is connected to a signal codec through the first pin, and the first pin is used to transmit a level data stream. The method is applied to the parser, and the method includes:

[0013] receiving a first level data stream sent by the signal codec through the first pin;

[0014] Sending a first level signal to the at least one processing module according to the first level data stream;

[0015] receiving a second level signal sent by the at least one processing module;

[0016] Perform encoding according to the second level signal to obtain a second level data stream;

[0017] The second level data stream is sent to the signal codec.

[0018] Optionally, the first level data stream includes at least one first data section and a first end section, and sending the first level signal to the at least one processing module according to the first level data stream includes:

[0019] After receiving the first data node, parsing the first data node to obtain first level signal information, and loading the first level signal information into a cache of a corresponding channel; one first data node corresponds to one channel;

[0020] After receiving the first end section, a first level signal is sent to the corresponding processing module through a corresponding signal line according to the first level signal information in the buffer of the channel; one processing module is connected to the parser through one signal line, and one channel corresponds to one signal line.

[0021] Optionally, the first level data stream further includes at least one first receiving node; and the receiving the second level signal sent by the at least one processing module includes:

[0022] After receiving the first receiving node, configuring the channel corresponding to the first receiving node to a receiving state; one receiving node corresponds to one channel;

[0023] After receiving the first end section, a second level signal sent by the corresponding processing module is received through a signal line of a channel configured in a receiving state.

[0024] Optionally, the first data section is in a preset format, and the preset format includes channel number information, bit width information of a level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of a starting level, information on the number of clock cycles required for level switching, and section end flag bit information; parsing the first data section to obtain first level signal information, and loading the first level signal information into a cache of a corresponding channel includes:

[0025] Determine the corresponding channel according to the channel number information of the first data node;

[0026] Determine the first level signal information according to the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, and the number of clock cycles required for level switching;

[0027] The first level signal information is loaded into the buffer of the corresponding channel.

[0028] Optionally, the second-level data stream includes a second data section and a second end section, and encoding is performed according to the second-level signal to obtain the second-level data stream including:

[0029] Parse the second level signal to obtain channel number information in a preset binary format, bit width information of a level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of a starting level, information on the number of clock cycles required for level switching, and section end flag bit information;

[0030] The second data section is determined according to the channel number information in the preset binary format, the bit width information of the level change frame, the high bit information of the number of level change frames, the low bit information of the number of level change frames, the high and low bit information of the starting level, the number of clock cycles required for level switching and the section end flag information.

[0031] Accordingly, an embodiment of the present invention discloses a chip test system, the system comprising a chip and a signal codec, the chip comprising a parser, at least one processing module and a first pin, the parser is connected to each of the processing modules, the parser is connected to the signal codec via the first pin, and the first pin is used to transmit a level data stream;

[0032] The signal codec is used to receive character string data sent by the test terminal; when identifying the character string data as a level data stream, send a first level data stream to the parser through the first pin, so that the parser sends a first level signal to the at least one processing module according to the first level data stream; receive a second level data stream sent by the parser, the second level data stream is obtained by the parser encoding according to the second level signal received from the at least one processing module; and send the second level data stream to the test terminal;

[0033] The parser is used to receive the first level data stream sent by the signal codec through the first pin; send a first level signal to the at least one processing module according to the first level data stream; receive a second level signal sent by the at least one processing module; encode according to the second level signal to obtain a second level data stream; and send the second level data stream to the signal codec.

[0034] Optionally, the chip further includes a second pin, the second pin is used to output a clock signal, and the signal codec is connected to the parser via the second pin;

[0035] The signal codec is used to control the working state of the second pin according to the control command when recognizing that the character string data is a control command.

[0036] Optionally, the first level data stream includes at least one first data section and a first end section;

[0037] The parser is used to parse the first data node to obtain first level signal information after receiving the first data node, and load the first level signal information into the cache of the corresponding channel; one first data node corresponds to one channel; after receiving the first end node, according to the first level signal information in the cache of the channel, send the first level signal to the corresponding processing module through the corresponding signal line; one processing module is connected to the parser through one signal line, and one channel corresponds to one signal line.

[0038] Optionally, the first level data stream further includes at least one first receiving node;

[0039] The parser is used to configure the channel corresponding to the first receiving node to a receiving state after receiving the first receiving node; one receiving node corresponds to one channel; after receiving the first ending node, receive the second level signal sent by the corresponding processing module through the signal line of the channel configured to the receiving state.

[0040] Optionally, the first data section is in a preset format, and the preset format includes channel number information, bit width information of the level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of the starting level, number of clock cycles required for level switching, and section end flag bit information;

[0041] The parser is used to determine the corresponding channel according to the channel number information of the first data node; determine the first level signal information according to the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level and the number of clock cycles required for level switching; and load the first level signal information into the cache of the corresponding channel.

[0042] Optionally, the second level data stream includes a second data section and a second end section;

[0043] The parser is used to parse the second level signal to obtain the channel number information in a preset base format, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information; determine the second data section according to the channel number information in the preset base format, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information.

[0044] Correspondingly, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the various steps of the above-mentioned chip testing method embodiment when executed by the processor.

[0045] Accordingly, an embodiment of the present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each step of the above-mentioned chip testing method embodiment is implemented.

[0046] The embodiments of the present invention include the following advantages:

[0047] A chip testing method according to an embodiment of the present invention comprises a parser, at least one processing module and a first pin, wherein the parser is connected to each processing module, the parser is connected to a signal codec through the first pin, the first pin is used to transmit a level data stream, the method is applied to the signal codec, receives character string data sent by a test terminal, and then sends a first level data stream to the parser through the first pin when the character string data is identified as a level data stream, so that the parser sends a first level signal to at least one processing module according to the first level data stream, and then receives a second level data stream sent by the parser, the second level data stream is obtained by encoding the signal codec according to the second level signal received from at least one processing module, and then sends a second level data stream to the test terminal. The signal codec sends the first level data stream received from the test terminal to the parser of the chip through the first pin, and then receives the second level data stream sent by the parser through the first pin, and sends the second level data stream to the test terminal, so that in the process of chip testing, the levels of various signals inside the chip are written and read through the first pin, thereby reducing the pins required for testing the internal modules of the chip, and chip testing can also be performed on chips with fewer external pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flowchart of a chip testing method according to an embodiment of the present invention;

[0049] Figure 2 is a schematic structural diagram of a chip testing method according to an embodiment of the present invention;

[0050] Figure 3 is a flowchart of another chip testing method according to an embodiment of the present invention;

[0051] Figure 4 is a schematic diagram of a first level data stream format according to an embodiment of the present invention;

[0052] Figure 5 is a schematic diagram of a level change waveform according to an embodiment of the present invention;

[0053] Figure 6 It is a schematic diagram of a second level data stream format according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] During chip testing, it is usually necessary to read and write the levels of various internal signals. The traditional method is to connect the signals of various internal IPs (modules) to the chip pins, and then input and output level signals and clock signals on the pins.

[0056] However, when signal interactions between modules are frequent, this method requires a large number of pins, which is difficult to implement on chips with a limited number of pins.

[0057] One of the core concepts of an embodiment of the present invention is that the signal codec sends a first level data stream received from a test terminal to a parser of the chip through a first pin, then receives a second level data stream sent by the parser through the first pin, and sends the second level data stream to the test terminal, so that during the chip testing process, the levels of various signals inside the chip are written and read through the first pin, thereby reducing the pins required for testing the internal modules of the chip, and chip testing can also be performed on chips with fewer external pins.

[0058] Reference Figure 1 , shows a flow chart of the steps of a chip testing method according to an embodiment of the present invention, the chip includes a parser, at least one processing module and a first pin, the parser is connected to each processing module, the parser is connected to a signal codec through the first pin, the first pin is used to transmit a level data stream, the method is applied to the signal codec, and specifically may include the following steps:

[0059] Step 101: Receive character string data sent by a test terminal.

[0060] Specifically, the test terminal may be a computer terminal, and the signal codec receives the character string data sent by the test terminal. Exemplarily, the test terminal may transmit the character string data to the signal codec via a USB (Universal Serial Bus).

[0061] Step 102: When the character string data is identified as a level data stream, a first level data stream is sent to the parser through the first pin, so that the parser sends a first level signal to the at least one processing module according to the first level data stream.

[0062] Specifically, after the signal codec receives the string data sent by the test terminal, it identifies the string data. When it is identified that the string data is a level data stream, it sends the first level data stream to the parser in serial form through the first pin. The first level data stream is the string data sent by the received test terminal, wherein the content of the string data is a level data stream. The signal codec sends the first level data stream to the parser of the chip so that the parser of the chip sends a first level signal to at least one processing module of the chip according to the first level data stream. The processing module can be an IP (Intellectual Property Module) module of the chip.

[0063] Step 103: receiving a second level data stream sent by the parser, where the second level data stream is encoded by the parser according to a second level signal received from the at least one processing module.

[0064] Specifically, after sending the first level data stream to the parser, the signal codec receives the second level data stream sent by the parser, that is, the signal codec receives the second level data stream fed back by the parser based on the received first level data stream, and the second level data stream is obtained by encoding the parser according to the second level signal received from at least one processing module, and the data format of the first level data stream is the same as the data format of the second level data stream.

[0065] Step 104: Send the second level data stream to the test terminal.

[0066] Specifically, after receiving the second level data stream, the signal codec sends the second level data stream to the test terminal. Exemplarily, the second level data stream may be sent to the test terminal via a USB.

[0067] In this way, the test terminal sends a first level data stream to the signal codec, and the signal codec sends the first level data stream to the chip parser through the first pin. The chip parser sends a first level signal to at least one processing module according to the first level data stream, thereby realizing the writing of the levels of various internal signals during chip testing. Then the chip parser receives a second level signal sent by at least one processing module, and the parser encodes the second level signal to obtain a second level data stream, and then sends the second level data stream to the signal codec through the first pin. The signal codec sends the received second level data stream to the test terminal, thereby realizing the reading of the levels of various internal signals during chip testing. In this way, the signal is transmitted or received through the first pin during the chip testing process, thereby reducing the pins required for testing the internal modules of the chip.

[0068] A chip testing method according to an embodiment of the present invention comprises a parser, at least one processing module and a first pin, wherein the parser is connected to each processing module, the parser is connected to a signal codec through the first pin, the first pin is used to transmit a level data stream, the method is applied to the signal codec, receives character string data sent by a test terminal, and then sends a first level data stream to the parser through the first pin when the character string data is identified as a level data stream, so that the parser sends a first level signal to at least one processing module according to the first level data stream, and then receives a second level data stream sent by the parser, the second level data stream is obtained by encoding the signal codec according to the second level signal received from at least one processing module, and then sends a second level data stream to the test terminal. The signal codec sends the first level data stream received from the test terminal to the parser of the chip through the first pin, and then receives the second level data stream sent by the parser through the first pin, and sends the second level data stream to the test terminal, so that in the process of chip testing, the levels of various signals inside the chip are written and read through the first pin, thereby reducing the pins required for testing the internal modules of the chip, and chip testing can also be performed on chips with fewer external pins.

[0069] Reference Figure 2 , showing a schematic diagram of a chip testing method according to an embodiment of the present invention, the chip 10 further includes a second pin 32, the second pin 32 is used to output a clock signal, the signal codec 20 is connected to the parser 12 via the second pin 32, and the method further includes:

[0070] When the character string data is identified as a control command, the working state of the second pin 32 is controlled according to the control command.

[0071] Specifically, the first pin 31 is a Data pin, which is used to transmit a level data stream, and the second pin 32 is a Figure 2 The Clock pin in the chip 10 is used to output a clock signal. The signal codec 20 is connected to the parser 12 of the chip 10 through the first pin 31 and the second pin 32. The chip 10 includes the parser 12 and at least one processing module 11. The processing module 11 can be an IP module. At least one processing module 11 is connected to the parser 12 through a signal line. The number of processing modules 11 corresponds to the number of signal lines.

[0072] When the signal codec 20 identifies the string data as a control command, it controls the working state of the second pin 32 according to the control command. The control command may include a stop string data control command, a clock setting string data control command, and a start string data control command.

[0073] Exemplarily, the test terminal sends a "stop" string to the signal codec via USB, that is, a stop string data control command, and the codec stops the second pin output, stops all transmission and reception actions with the chip, and clears the cache.

[0074] The test terminal sends a string of "frequency" + "hz" (such as "10000hz") to the signal codec via USB, which is a clock setting string data control command. The codec configures the frequency output by the second pin. At this time, it only configures the clock frequency and does not output a clock signal.

[0075] The test terminal sends a "start" string to the signal codec through the USB, which is the start string data control command, and the codec outputs a clock through the second pin at the configured frequency. At the same time, the codec waits for string data containing a level data stream.

[0076] Reference Figure 3 , shows a flow chart of the steps of another chip testing method according to an embodiment of the present invention, the chip includes a parser, at least one processing module and a first pin, the parser is connected to each of the processing modules, the parser is connected to a signal codec through the first pin, the first pin is used to transmit a level data stream, the method is applied to the parser, and specifically may include the following steps:

[0077] Step 201: receiving a first level data stream sent by the signal codec through the first pin.

[0078] Specifically, the parser of the chip receives the first level data stream sent by the signal codec through the first pin.

[0079] Step 202: Send a first level signal to the at least one processing module according to the first level data stream.

[0080] Specifically, after receiving the first level data stream, the parser sends a first level signal to at least one processing module according to the first level data stream, thereby providing an excitation signal for the module during testing.

[0081] Step 203: Receive a second level signal sent by the at least one processing module.

[0082] Specifically, after sending the first level signal to at least one processing module, the analyzer receives the second level signal fed back by at least one processing module.

[0083] Step 204: Encode according to the second level signal to obtain a second level data stream.

[0084] Specifically, after receiving the second level signal fed back by at least one processing module, the parser performs encoding according to the second level signal to obtain a second level data stream.

[0085] Step 205: Send the second level data stream to the signal codec.

[0086] Specifically, after the parser encodes the second level signal to obtain the second level data stream, the parser sends the second level data stream to the test terminal through the first pin, so that the test terminal performs analysis according to the second level data stream.

[0087] The test terminal transmits the first level data stream to the codec in the form of a string through the USB device, and at the same time, the second level data stream fed back by the chip parser is fed back to the computer terminal in the form of a string through the codec, thereby testing the chip.

[0088] A chip testing method according to an embodiment of the present invention comprises a parser, at least one processing module and a first pin, wherein the parser is connected to each processing module, the parser is connected to a signal codec through the first pin, the first pin is used to transmit a level data stream, the method is applied to the parser, the parser receives a first level data stream sent by the signal codec through the first pin, sends a first level signal to at least one processing module according to the first level data stream, receives a second level signal sent by at least one processing module, encodes according to the second level signal, obtains a second level data stream, and sends the second level data stream to the signal codec. During the chip testing process, the levels of various signals inside the chip are written and read through the first pin, thereby reducing the pins required for testing the internal modules of the chip, and the chip testing can also be performed on a chip with fewer external pins.

[0089] In the embodiment of the present invention, the first level data stream includes at least one first data section and a first end section. Step 202, sending a first level signal to the at least one processing module according to the first level data stream may specifically include the following sub-steps:

[0090] Sub-step S11, after receiving the first data node, parsing the first data node to obtain first level signal information, and loading the first level signal information into a cache of a corresponding channel; one first data node corresponds to one channel.

[0091] Specifically, refer to Figure 4 , which shows a schematic diagram of a first level data stream format according to an embodiment of the present invention, Figure 4The data format of the level data stream sent by the signal codec to the internal parser of the chip is expressed in hexadecimal, and the sending order is 1-1, 1-2, 1-3...1-12, 2-1, 2-2...5-4, that is, it starts from the first bit of the first row, then the second bit of the first row to the twelfth bit of the first row, at this point the first row is sent, and then the first bit of the second row is sent, the second bit of the second row is sent, at this point the two rows are sent, and then the first bit of the third row is sent, and so on, until the last bit of the last row is sent.

[0092] Figure 4 There are two first data nodes, namely the first row and the second row. The first bit of the data node indicates the channel corresponding to the data in the node. After receiving the first data node, the parser parses the first data node to obtain first level signal information, and loads the first level signal information into the cache of the corresponding channel. Exemplarily, the channel corresponding to the first data node of the first row is channel 1, and the channel corresponding to the first data node of the second row is channel 2. The first level signal information obtained by parsing the first data node of the first row is loaded into the cache corresponding to channel 1, and the first level signal information obtained by parsing the first data node of the second row is loaded into the cache corresponding to channel 2.

[0093] Sub-step S12, after receiving the first end section, sending the first level signal to the corresponding processing module through the corresponding signal line according to the first level signal information in the cache of the channel; one processing module is connected to the parser through one signal line, and one channel corresponds to one signal line.

[0094] Specifically, Figure 4 The 5th line in is the end section. After receiving the first end section, the parser sends the first level signal to the corresponding processing module through the corresponding signal line according to the first level signal information in the buffer of the channel. Exemplarily, the first level signal information in the buffer of channel 1 is sent to the processing module connected to signal line 1 through signal line 1; and the first level signal information in the buffer of channel 2 is sent to the processing module connected to signal line 2 through signal line 2.

[0095] In the embodiment of the present invention, the first level data stream further includes at least one first receiving section; Step 203, receiving the second level signal sent by the at least one processing module, may specifically include the following sub-steps:

[0096] Sub-step S21, after receiving the first receiving node, configuring the channel corresponding to the first receiving node to a receiving state; one receiving node corresponds to one channel.

[0097] Specifically, Figure 4The third and fourth rows in the receive node are receive nodes. The first bit of the receive node indicates the channel to which the receive node corresponds. The first receive node in the third row corresponds to channel 3, and the first receive node in the fourth row corresponds to channel 4. After receiving the first receive node, the parser configures the channel corresponding to the first receive node to the receive state. Exemplarily, the parser configures channel 3 and channel 4 to the receive state.

[0098] Sub-step S22, after receiving the first end section, receiving a second level signal sent by the corresponding processing module through a signal line of a channel configured in a receiving state.

[0099] Exemplarily, after receiving the first end section of line 5, the parser receives the second level signal sent by the processing module connected to signal line 3 and the second level signal sent by the processing module connected to signal line 4 through signal line 3 of channel 3 and signal line 4 of channel 4 configured in the receiving state.

[0100] The function of the first data node in the first level data stream is to configure the channel's cache and wait for the end node to send a level signal. The function of the receiving node is to configure the channel to receive the feedback level in the receiving state. The end node, as a ready mark, sends the configured channel level to the signal line in parallel. At the same time, the configured receiving channel receives the level signal.

[0101] In an embodiment of the present invention, the first data section is in a preset format, and the preset format includes channel number information, bit width information of a level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of a starting level, information on the number of clock cycles required for level switching, and section end flag information; Sub-step S11, parsing the first data section to obtain first level signal information, and loading the first level signal information into a cache of a corresponding channel, may specifically include the following sub-steps:

[0102] Sub-step S111, determining the corresponding channel according to the channel number information of the first data node.

[0103] Specifically, Figure 4The data section is in hexadecimal format. Taking the data section of the first row as an example, the data section includes 12 bits in total. The first bit of the data section has a bit width of 8, which indicates the corresponding channel number, indicating that the level information of the data section will control signal line 1; the second bit of the data section has a bit width of 8, which indicates the bit width of the level change frame 6-11, and the bit width is 4 in the figure; the third bit of the data section has a bit width of 8, which indicates the high bit of the number of level change frames; the fourth bit of the data section has a bit width of 8, which indicates the low bit of the number of level change frames, and 3 and 4 in the figure are together represented as 0x0006, which means that there are 6 level changes, namely 6-11; the fifth bit of the data section has a bit width of 1, which indicates the high and low of the starting level on the transmission signal line, 1 represents a high level, and 0 represents a low level; the sixth to eleventh bits of the data section have a bit width determined according to the second bit, and the value of the level change is the clock cycle in which the level change occurs. 6-11 has 6 level changes, which means that the level changes from the initial high level to the low level after 4 clock cycles, then to the high level after 3 clock cycles, then to the low level after 1 clock cycle, then to the high level after 1 clock cycle, then to the low level after 3 clock cycles, and then to the high level after 1 clock cycle; the twelfth bit of the data node, the bit width is determined according to the second bit, and the value is fixed at 0, indicating the end of the node flag.

[0104] The first bit of the third column receiving section has a width of 8, indicating the corresponding channel number, indicating that the level information of the section data will control signal line 3; the second bit has a width of 8, indicating the bit width of the level change frame, and the above figure shows that the bit width is 4; the third bit has a width of 8, indicating the high bit of the number of level change frames; the fourth bit has a width of 8, indicating the low bit of the number of level change frames. In the above figure, the third and fourth bits are together represented as 0x0000, which means setting the level on channel 3 receiving signal line 3.

[0105] The first bit width of the end section is 8, indicating the corresponding channel number. Channel 0 represents that the channel configuration of the parser is completed, and the configured channel starts to send data in parallel; the second bit width is 8, indicating the bit width of the level change frame, and the above figure shows that the bit width is 4; the third bit width is 8, indicating the high bit of the number of level change frames; the fourth bit width is 8, indicating the low bit of the number of level change frames.

[0106] The first bit of the first data section indicates the channel number. The parser can determine the channel corresponding to the data section according to the channel number information of the first bit of the first data section.

[0107] Sub-step S112, determining the first level signal information according to the high-bit information of the level change frame number, the low-bit information of the level change frame number, the high and low information of the starting level and the number of clock cycles required for level switching.

[0108] Specifically, according to the third and fourth bits of the data section, the high-bit information of the number of level change frames and the low-bit information of the number of level change frames can be determined, and according to the high-bit and low-bit information of the number of level change frames, the bit where the level change frame is located can be determined, and according to the high and low information of the starting level and the number of clock cycles required for the level switching, the first level signal information is determined. Exemplarily, Figure 4 The third and fourth bits in the first line of data are expressed together as 0x0006, which means that there are 6 level changes, that is, the level change frame is in the sixth to eleventh bits, and the fifth bit 1 indicates that the starting level bit is high. The first level signal information is determined according to the sixth to eleventh bits, that is, the level changes from the starting high level to the low level after 4 clock cycles, and then to the high level after 3 clock cycles, and then to the low level after 1 clock cycle, and then to the high level after 1 clock cycle, and then to the low level after 3 clock cycles, and then to the high level after 1 clock cycle. Figure 5 The waveform of level change is shown, indicating the level change of the clock signal and the signal line 1 to the corresponding processing module.

[0109] Sub-step S113: loading the first level signal information into the buffer of the corresponding channel.

[0110] Specifically, after the first level signal information is determined, the first level signal information is loaded into a buffer of the corresponding channel according to the determined corresponding channel.

[0111] In the embodiment of the present invention, the second level data stream includes a second data section and a second end section. Step 204, encoding is performed according to the second level signal to obtain a second level data stream, which may specifically include the following sub-steps:

[0112] Sub-step S31, parse the second level signal to obtain the channel number information in a preset binary format, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information.

[0113] Specifically, refer to Figure 6 , shows a schematic diagram of a second level data stream format of an embodiment of the present invention, the second level data stream includes a second data section and a second end section, the first line and the second row are the second data section, and the third row is the second end section. The processing module sends a second level signal to the parser through the corresponding signal line, Figure 4The channels corresponding to the two receiving nodes are channel 3 and channel 4, that is, corresponding to signal line 3 and signal line 4, and channel 3 and channel 4 have been configured as receiving state. Here, the processing module corresponding to signal line 3 will send the second level signal to the parser through signal line 3, and the processing module corresponding to signal 4 will send the second level signal to the parser through signal line 4. After parsing the second level signal, according to the first level data stream format, the channel number corresponding to the second level signal, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information can be obtained, and the above information can be converted into hexadecimal.

[0114] Sub-step S31, determining the second data section according to the channel number information in the preset binary format, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information.

[0115] Specifically, according to the channel number information in hexadecimal format, the bit width information of the level change frame, the high bit information of the number of level change frames, the low bit information of the number of level change frames, the high and low bit information of the starting level, the number of clock cycles required for level switching, and the section end flag information, the twelve bits of data of the second data section are determined, thereby determining the second data section and converting it into a character string. Exemplarily, Figure 6 The converted string of the receiving section of the first line is "0304000614-3-1-1-3-1-0", where the first to fifth digits directly convert the hexadecimal into a string, and the characters in the sixth to eleventh digits are separated by "-". Because the width of the sixth to eleventh digits is determined by the second digit, that is, the sixth to eleventh digits are variable widths, a flag is required to distinguish and parse them to avoid confusion.

[0116] The function of the second data node in the second level data stream is to encode the level signal fed back by the receiving channel. The format and function of the frame are the same as the format of the first level data stream. The function of the second end node is to mark the end of the level signal fed back by the receiving channel. The format and function of the frame are the same as the format of the first level data stream.

[0117] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0118] In an embodiment of the present invention, a chip testing system is also disclosed. Figure 2 , the system comprises a chip and a signal codec, the chip comprises a parser, at least one processing module and a first pin, the parser is connected to each of the processing modules, the parser is connected to the signal codec via the first pin, and the first pin is used to transmit a level data stream;

[0119] The signal codec is used to receive character string data sent by the test terminal; when identifying the character string data as a level data stream, send a first level data stream to the parser through the first pin, so that the parser sends a first level signal to the at least one processing module according to the first level data stream; receive a second level data stream sent by the parser, the second level data stream is obtained by the parser encoding according to the second level signal received from the at least one processing module; and send the second level data stream to the test terminal;

[0120] The parser is used to receive the first level data stream sent by the signal codec through the first pin; send a first level signal to the at least one processing module according to the first level data stream; receive a second level signal sent by the at least one processing module; encode according to the second level signal to obtain a second level data stream; and send the second level data stream to the signal codec.

[0121] In an embodiment of the present invention, the chip further comprises a second pin, the second pin is used to output a clock signal, and the signal codec is connected to the parser via the second pin;

[0122] The signal codec is used to control the working state of the second pin according to the control command when recognizing that the character string data is a control command.

[0123] In the embodiment of the present invention, the first level data stream includes at least one first data section and a first end section;

[0124] The parser is used to parse the first data node to obtain first level signal information after receiving the first data node, and load the first level signal information into the cache of the corresponding channel; one first data node corresponds to one channel; after receiving the first end node, according to the first level signal information in the cache of the channel, send the first level signal to the corresponding processing module through the corresponding signal line; one processing module is connected to the parser through one signal line, and one channel corresponds to one signal line.

[0125] In the embodiment of the present invention, the first level data stream further includes at least one first receiving node;

[0126] The parser is used to configure the channel corresponding to the first receiving node to a receiving state after receiving the first receiving node; one receiving node corresponds to one channel; after receiving the first ending node, receive the second level signal sent by the corresponding processing module through the signal line of the channel configured to the receiving state.

[0127] In an embodiment of the present invention, the first data section is in a preset format, and the preset format includes channel number information, bit width information of a level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of a starting level, information on the number of clock cycles required for level switching, and section end flag bit information;

[0128] The parser is used to determine the corresponding channel according to the channel number information of the first data node; determine the first level signal information according to the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level and the number of clock cycles required for level switching; and load the first level signal information into the cache of the corresponding channel.

[0129] In the embodiment of the present invention, the second level data stream includes a second data section and a second end section;

[0130] The parser is used to parse the second level signal to obtain the channel number information in a preset base format, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information; determine the second data section according to the channel number information in the preset base format, the bit width information of the level change frame, the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, the number of clock cycles required for level switching, and the section end flag information.

[0131] An embodiment of the present invention further provides an electronic device, including:

[0132] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes of the test method embodiment of the above-mentioned chip are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0133] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned chip testing method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0134] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0135] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0136] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0137] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0138] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0139] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0140] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0141] The above is a detailed introduction to the chip testing method, system, electronic device and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A chip testing method, characterized in that: The chip comprises a parser, at least one processing module and a first pin, wherein the parser is connected to each of the processing modules, the parser is connected to a signal codec via the first pin, the first pin is used to transmit a level data stream, the method is applied to the signal codec, and the method comprises: Receive the string data sent by the test terminal; When the character string data is identified as a level data stream, sending a first level data stream to the parser through the first pin, so that the parser sends a first level signal to the at least one processing module according to the first level data stream; receiving a second level data stream sent by the parser, where the second level data stream is obtained by the parser through encoding according to a second level signal received from the at least one processing module; The second level data stream is sent to the test terminal.

2. The method according to claim 1, characterized in that The chip further includes a second pin, the second pin is used to output a clock signal, the signal codec is connected to the parser via the second pin, and the method further includes: When the character string data is identified as a control command, the working state of the second pin is controlled according to the control command.

3. A chip testing method, characterized in that: The chip comprises a parser, at least one processing module and a first pin, wherein the parser is connected to each of the processing modules, the parser is connected to a signal codec via the first pin, the first pin is used to transmit a level data stream, and the method is applied to the parser, and the method comprises: receiving a first level data stream sent by the signal codec through the first pin; Sending a first level signal to the at least one processing module according to the first level data stream; receiving a second level signal sent by the at least one processing module; Perform encoding according to the second level signal to obtain a second level data stream; The second level data stream is sent to the signal codec.

4. The method according to claim 3, characterized in that The first level data stream includes at least one first data section and a first end section, and sending a first level signal to the at least one processing module according to the first level data stream includes: After receiving the first data node, parsing the first data node to obtain first level signal information, and loading the first level signal information into a cache of a corresponding channel; one first data node corresponds to one channel; After receiving the first end section, a first level signal is sent to the corresponding processing module through a corresponding signal line according to the first level signal information in the buffer of the channel; one processing module is connected to the parser through one signal line, and one channel corresponds to one signal line.

5. The method according to claim 4, characterized in that The first level data stream also includes at least one first receiving node; The receiving the second level signal sent by the at least one processing module comprises: After receiving the first receiving node, configuring the channel corresponding to the first receiving node to a receiving state; one receiving node corresponds to one channel; After receiving the first end section, a second level signal sent by the corresponding processing module is received through a signal line of a channel configured in a receiving state.

6. The method according to claim 4, characterized in that The first data section is in a preset format, and the preset format includes channel number information, bit width information of the level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of the starting level, number of clock cycles required for level switching, and section end flag bit information; The step of parsing the first data node to obtain first level signal information, and loading the first level signal information into a cache of a corresponding channel includes: Determine the corresponding channel according to the channel number information of the first data node; Determine the first level signal information according to the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, and the number of clock cycles required for level switching; The first level signal information is loaded into the buffer of the corresponding channel.

7. The method according to claim 6, characterized in that The second level data stream includes a second data section and a second end section, and is encoded according to the second level signal to obtain a second level data stream including: Parse the second level signal to obtain channel number information in a preset binary format, bit width information of a level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of a starting level, information on the number of clock cycles required for level switching, and section end flag bit information; The second data section is determined according to the channel number information in the preset binary format, the bit width information of the level change frame, the high bit information of the number of level change frames, the low bit information of the number of level change frames, the high and low bit information of the starting level, the number of clock cycles required for level switching and the section end flag information.

8. A chip testing system, characterized in that: The system comprises a chip and a signal codec, wherein the chip comprises a parser, at least one processing module and a first pin, wherein the parser is connected to each of the processing modules, and the parser is connected to the signal codec via the first pin, and the first pin is used to transmit a level data stream; The signal codec is used to receive the string data sent by the test terminal; when identifying the string data as a level data stream, sending a first level data stream to the parser through the first pin, so that the parser sends a first level signal to the at least one processing module according to the first level data stream; receiving a second level data stream sent by the parser, where the second level data stream is obtained by the parser through encoding according to a second level signal received from the at least one processing module; Sending the second level data stream to the test terminal; The parser is used to receive a first level data stream sent by the signal codec through the first pin; Sending a first level signal to the at least one processing module according to the first level data stream; receiving a second level signal sent by the at least one processing module; Perform encoding according to the second level signal to obtain a second level data stream; The second level data stream is sent to the signal codec.

9. The system according to claim 8, characterized in that The chip further comprises a second pin, the second pin being used to output a clock signal, and the signal codec is connected to the parser via the second pin; The signal codec is used to control the working state of the second pin according to the control command when recognizing that the character string data is a control command.

10. The system according to claim 8, characterized in that The first level data stream includes at least one first data section and a first end section; The parser is used to parse the first data section to obtain first level signal information after receiving the first data section, and load the first level signal information into the cache of the corresponding channel; one first data section corresponds to one channel; after receiving the first end section, according to the first level signal information in the cache of the channel, send the first level signal to the corresponding processing module through the corresponding signal line; A processing module is connected to the analyzer via a signal line, and one channel corresponds to one signal line.

11. The system according to claim 10, characterized in that The first level data stream also includes at least one first receiving node; The parser is used to configure the channel corresponding to the first receiving node to a receiving state after receiving the first receiving node; One receiving section corresponds to one channel; after receiving the first ending section, the second level signal sent by the corresponding processing module is received through the signal line of the channel configured as the receiving state.

12. The system according to claim 10, characterized in that The first data section is in a preset format, and the preset format includes channel number information, bit width information of the level change frame, high bit information of the number of level change frames, low bit information of the number of level change frames, high and low bit information of the starting level, number of clock cycles required for level switching, and section end flag bit information; The parser is used to determine the corresponding channel according to the channel number information of the first data node; Determine the first level signal information according to the high-bit information of the number of level change frames, the low-bit information of the number of level change frames, the high and low information of the starting level, and the number of clock cycles required for level switching; The first level signal information is loaded into the buffer of the corresponding channel.

13. The system according to claim 12, characterized in that The second level data stream includes a second data section and a second end section; The parser is used to parse the second level signal to obtain the channel number information in a preset binary format, the bit width information of the level change frame, the high bit information of the number of level change frames, the low bit information of the number of level change frames, the high and low bit information of the starting level, the number of clock cycles required for level switching, and the section end flag bit information; The second data section is determined according to the channel number information in the preset binary format, the bit width information of the level change frame, the high bit information of the number of level change frames, the low bit information of the number of level change frames, the high and low bit information of the starting level, the number of clock cycles required for level switching and the section end flag information.

14. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the chip testing method as described in any one of claims 1-2 or 3-7 are implemented.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip testing method as described in any one of claims 1-2 or 3-7 are implemented.

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